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WO2019196316A1 - 一种用于nand flash的ldpc测试平台 - Google Patents

一种用于nand flash的ldpc测试平台 Download PDF

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Publication number
WO2019196316A1
WO2019196316A1 PCT/CN2018/103043 CN2018103043W WO2019196316A1 WO 2019196316 A1 WO2019196316 A1 WO 2019196316A1 CN 2018103043 W CN2018103043 W CN 2018103043W WO 2019196316 A1 WO2019196316 A1 WO 2019196316A1
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nand flash
module
information
ldpc
decoding
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PCT/CN2018/103043
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English (en)
French (fr)
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徐光明
后嘉伟
虞安华
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南京扬贺扬微电子科技有限公司
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Publication of WO2019196316A1 publication Critical patent/WO2019196316A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/20—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits using counters or linear-feedback shift registers [LFSR]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C29/56008—Error analysis, representation of errors

Definitions

  • the invention belongs to the field of integrated circuit design, in particular to a test platform for LDPC for NAND FLASH.
  • LDPC for NAND FLASH does not have a standard check matrix and its corresponding generator matrix, and there are many ways to construct check matrix. How to verify the performance of each matrix requires a test platform.
  • the object of the present invention is to solve the test problem of LDPC for NAND FLASH, and to provide a test platform for LDPC for NAND FLASH.
  • the present invention provides a test platform for LDPC for NAND FLASH, including
  • a random number generation module that generates a random number according to the required information length
  • the encoding module generates verification information according to the input information length and the matrix
  • NAND FLASH control module for data exchange with NAND FLASH
  • NAND FLASH controller writes information bits and check bits to FLASH
  • the decoding module sends the hard information and the soft information data read from the FLASH to the decoder for decoding, and the input is hard information and soft information, and the output is hard information, and
  • the error detection module is configured to collect error information, compare the decoded data and the data of the random generator, and calculate the error rate.
  • the random number generating module adopts an LFSR structure and includes a plurality of registers whose initial values are 0 or 1.
  • the random number generating module obtains a random number with a period of 128.
  • the encoding module adopts a SARR structure including a shift register and an accumulating circuit.
  • the NAND FLASH control module includes a read control portion that reads the hard information and soft information of the FLASH and sends it to the decoding module for decoding, and writes the information bits and check bits sent by the encoding module to the write control portion of the NAND FLASH. And an erase control portion that implements block erasure to NAND FLASH.
  • the decoding module adopts NMS decoding to include an input module, an output module, a storage unit, a variable node calculation unit and a check node calculation unit, the variable node calculation unit is responsible for updating the variable node, and the verification node calculation unit is responsible for verifying the update of the node.
  • the intermediate result of each iteration is stored in the storage unit.
  • the error detection module includes a comparator and a UART module, and the comparator is responsible for comparing the data of the random number generator with the decoded data, and counting the number of errors, and the UART is responsible for transmitting the information of the error number to the PC.
  • FIG. 1 is a block diagram of the present invention
  • Figure 2 is a structural diagram of the LFSR
  • Figure 3 is a SARR structure diagram
  • FIG. 4 is a schematic diagram of a NAND FLASH controller
  • Figure 5 is a block diagram of the decoder
  • Figure 6 is a schematic diagram of the error detection structure.
  • the invention provides an LDPC test platform for NAND FLASH, which first generates a random number of a certain length, writes the random number and the verification information into the FLASH, and then reads the FLASH and sends it to the decoder for decoding, and finally Statistics error information.
  • the implementation of the invention specifically includes the following steps:
  • Step 1 the generation of a random number.
  • the random number generation adopts the LFSR structure shown in FIG. 2, and generates a random number according to the required information length.
  • the initial value of each register may be 0 or 1, and a random number with a period of 128 is obtained.
  • Step 2 coding.
  • the encoder adopts the SARR (shift-register-adder-accumulator) structure shown in Figure 3.
  • the SARR circuit uses the shift register and the accumulating circuit as the core to realize the multiplication of the vector and the matrix, which greatly reduces the computational complexity and resource consumption.
  • the verification information is generated according to the input information length and the matrix.
  • Step 3 Data exchange with NAND FLASH.
  • the NAND FLASH controller writes the information bits and parity bits to the FLASH.
  • the controller of the NAND FLASH is divided into a read control portion, a write control portion, and an erase control portion as shown in FIG.
  • the characteristics of NAND FLASH determine that an erase operation must be performed before writing.
  • the read control part reads the hard information and soft information of the FLASH and sends it to the decoder for decoding.
  • the erase control section implements block erase of the NAND FLASH.
  • the write control part is to write the information bits and check bits sent by the encoder to the NAND FLASH.
  • Step 4 decoding.
  • the hard information and soft information data read from the FLASH are sent to the decoder for decoding.
  • the decoder uses the NMS decoding method.
  • the structure diagram of the decoding is shown in FIG. 5, and includes an input module, an output module, a storage unit, a variable node calculation unit, and a check node calculation unit.
  • the variable node calculation unit is responsible for updating the variable node
  • the check node calculation unit is responsible for verifying the update of the node.
  • the intermediate result of each iteration is stored in the storage unit.
  • the input is hard information and soft information
  • the output is hard information.
  • Step 5 statistics errors. Comparing the decoded data with the data of the random generator, and counting the bit error rate, the data can be sent to the PC through the UART.
  • the block diagram is shown in Figure 6, which includes a comparator and a UART module.
  • the comparator is responsible for comparing the data of the random number generator with the decoded data, and counting the number of errors.
  • the UART is responsible for sending the number of errors to the PC.

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  • Techniques For Improving Reliability Of Storages (AREA)
  • Read Only Memory (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

一种用于NAND FLASH的LDPC测试平台，该测试平台先产生一定长度的随机数，把随机数和校验信息写入FLASH，再读取FLASH送入译码器译码，最后统计错误信息。

Description

一种用于NAND FLASH的LDPC测试平台 技术领域
本发明属于集成电路设计领域，具体说是一种用于NAND FLASH的LDPC的测试平台。
背景技术
随着NAND FLASH工艺的进步，越来越多的NAND FLASH需要LDPC来进行纠错。然而用于NAND FLASH的LDPC没有标准的校验矩阵和其相对应的生成矩阵，而且校验矩阵的的构造方法有很多种，如何验证出每种矩阵的性能，就需要一个测试平台。
发明内容
本发明的目的是解决用于NAND FLASH的LDPC的测试问题，提供一种用于NAND FLASH的LDPC的测试平台。
为解决上述技术问题，本发明提供了一种用于NAND FLASH的LDPC的测试平台，包括
随机数产生模块，根据需要的信息长度产生随机数、
编码模块，根据输入的信息长度和矩阵产生校验信息、
NAND FLASH控制模块，用于和NAND FLASH进行数据交换，NAND FLASH控制器把信息位和校验位写入FLASH、
译码模块，把从FLASH读出的hard information和soft information数据送入译码器进行译码，输入的是hard information和soft information，输出的结果是hard information、和
误码检测模块，用于统计错误信息，比较译码后的数据和随机发生器的数据，统计误码率。
所述随机数产生模块采用LFSR结构，包括若干寄存器，所述寄存器的初始值为0或1。
所述随机数产生模块得到周期为128的随机数。
所述编码模块采用SARR结构包括位移寄存器和累加电路。
所述NAND FLASH控制模块包括把FLASH的hard information和soft information读出来送入译码模块进行译码的读控制部分、把编码模块送入的信息位和校验位写入NAND FLASH的写控制部分和实现对NAND FLASH的块擦除的擦除控制部分。
所述译码模块采用NMS解码包括输入模块、输出模块、存储单元、变量节点计算单元和校验节点计算单元，变量节点计算单元负责变量节点的更新，校验节点计算单元 负责校验节点的更新，每次迭代的中间结果保存在存贮单元中。
误码检测模块包括比较器和UART模块，该比较器负责比较随机数发生器的数据和解码后的数据，并统计出错误个数，UART负责把错误个数的信息发送到PC端。
附图说明
图1为本发明的模块图；
图2为LFSR结构图；
图3为SARR结构图；
图4为NAND FLASH控制器示意图；
图5为译码器结构图；
图6为误码检测结构示意图。
具体实施方式
下面结合附图对本发明作更进一步的说明。
本发明提供了一种用于NAND FLASH的LDPC测试平台，该测试平台先产生一定长度的随机数，把随机数和校验信息写入FLASH，再读取FLASH送入译码器译码，最后统计错误信息。
该发明的实施具体包括以下步骤：
步骤1，随机数的产生。随机数产生采用图二所示的LFSR结构，根据需要的信息长度产生随机数，每个寄存器的初始值可以是0或者1，得到周期为128的随机数。
步骤2，编码。编码器采用图三所示的SARR(shift-register-adder-accumulator)结构，SARR电路利用移位寄存器和累加电路为核心实现向量与矩阵的乘法，极大地减少了运算量和资源消耗，有利于编码器的硬件实现。根据输入的信息长度和矩阵产生校验信息。
步骤3，和NAND FLASH的数据交换。NAND FLASH控制器把信息位和校验位写入FLASH，NAND FLASH的控制器如图4所示，分为读控制部分、写控制部分和擦除控制部分。NAND FLASH的特性决定了在写之前必须进行擦除操作。读控制部分就是把FLASH的hard information和soft information读出来送入译码器进行译码。擦除控制部分实现对NAND FLASH的块擦除。写控制部分就是把编码器送入的信息位和校验位写入NAND FLASH。
步骤4，译码。把从FLASH读出的hard information和soft information数据送入译码器进行译码。译码器采用NMS的解码方法。译码的结构图如图5所示，包括输入模块，输出模块，存储单元，变量节点计算单元和校验节点计算单元。变量节点计算单元负责变量节点的更新，校验节点计算单元负责校验节点的更新。每次迭代的中间结果 保存在存贮单元中。输入的是hard information和soft information，输出的结果是hard information。
步骤5，统计错误。比较译码后的数据和随机发生器的数据，统计误码率，可以通过UART把数据送到PC端。结构图如图6所示，包括一个比较器和一个UART模块。比较器负责比较随机数发生器的数据和解码后的数据，并且统计出错误个数。UART负责把错误个数的信息发送到PC端。

Claims (7)

  1. 一种用于NAND FLASH的LDPC的测试平台，其特征在于：包括
    随机数产生模块，根据需要的信息长度产生随机数、
    编码模块，根据输入的信息长度和矩阵产生校验信息、
    NAND FLASH控制模块，用于和NAND FLASH进行数据交换，NAND FLASH控制器把信息位和校验位写入FLASH、
    译码模块，把从FLASH读出的hard information和soft information数据送入译码器进行译码，输入的是hard information和soft information，输出的结果是hard information、和
    误码检测模块，用于统计错误信息，比较译码后的数据和随机发生器的数据，统计误码率。
  2. 根据权利要求1所述的一种用于NAND FLASH的LDPC的测试平台，其特征在于：所述随机数产生模块采用LFSR结构，包括若干寄存器，所述寄存器的初始值为0或1。
  3. 根据权利要求1或2所述的一种用于NAND FLASH的LDPC的测试平台，其特征在于：所述随机数产生模块得到周期为128的随机数。
  4. 根据权利要求1所述的一种用于NAND FLASH的LDPC的测试平台，其特征在于：所述编码模块采用SARR结构包括位移寄存器和累加电路。
  5. 根据权利要求1所述的一种用于NAND FLASH的LDPC的测试平台，其特征在于：所述NAND FLASH控制模块包括把FLASH的hard information和soft information读出来送入译码模块进行译码的读控制部分、把编码模块送入的信息位和校验位写入NAND FLASH的写控制部分和实现对NAND FLASH的块擦除的擦除控制部分。
  6. 根据权利要求1所述的一种用于NAND FLASH的LDPC的测试平台，其特征在于：所述译码模块采用NMS解码包括输入模块、输出模块、存储单元、变量节点计算单元和校验节点计算单元，变量节点计算单元负责变量节点的更新，校验节点计算单元负责校验节点的更新，每次迭代的中间结果保存在存贮单元中。
  7. 根据权利要求1所述的一种用于NAND FLASH的LDPC的测试平台，其特征在于：误码检测模块包括比较器和UART模块，该比较器负责比较随机数发生器的数据和解码后的数据，并统计出错误个数，UART负责把错误个数的信息发送到PC端。
PCT/CN2018/103043 2018-04-10 2018-08-29 一种用于nand flash的ldpc测试平台 WO2019196316A1 (zh)

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