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WO2019029007A1 - 一种tft基板的制备方法、tft基板以及oled显示面板 - Google Patents

一种tft基板的制备方法、tft基板以及oled显示面板 Download PDF

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Publication number
WO2019029007A1
WO2019029007A1 PCT/CN2017/106969 CN2017106969W WO2019029007A1 WO 2019029007 A1 WO2019029007 A1 WO 2019029007A1 CN 2017106969 W CN2017106969 W CN 2017106969W WO 2019029007 A1 WO2019029007 A1 WO 2019029007A1
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Prior art keywords
layer
region
drain
source
barrier layer
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PCT/CN2017/106969
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English (en)
French (fr)
Inventor
卜呈浩
方宏
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武汉华星光电半导体显示技术有限公司
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US15/737,300 priority Critical patent/US10361261B2/en
Publication of WO2019029007A1 publication Critical patent/WO2019029007A1/zh

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    • HELECTRICITY
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    • H10K59/10OLED displays
    • H10K59/12Active-matrix OLED [AMOLED] displays
    • H10K59/121Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating a TFT substrate, a TFT substrate, and an OLED display panel.
  • a low-temperature polysilicon technology that is, a low-temperature polysilicon TFT substrate is often used in the display panel, but the TFT substrate currently used is generally a top-gate TFT substrate, that is, a TFT gate preparation.
  • the top gate type TFT substrate is excellent in electrical conductivity, but its reliability is low.
  • the top-gate TFT substrate When the top-gate TFT substrate is subjected to excimer laser annealing of amorphous silicon during the preparation process, inevitable protrusions are formed on the formed polysilicon layer, and these protrusions may affect the interface quality between the gate insulating layer and the polysilicon layer. Reducing the breakdown voltage of the gate insulating layer limits further reduction in the thickness of the gate insulating layer.
  • a bottom gate type TFT substrate is also used in some display panels.
  • the barrier layer above the polysilicon layer needs to be etched to expose the polar region.
  • the polysilicon layer of the drain region and then the ion implantation of the exposed polysilicon layer of the source region and the drain region, which usually causes damage to the underlying polysilicon layer when the barrier layer is etched, and introduces defects.
  • the polysilicon layer is completely etched, which affects the display quality of the display panel.
  • the present invention provides a method for fabricating a TFT substrate, a TFT substrate, and an OLED display panel.
  • the method for fabricating the TFT substrate solves the problem of reducing display quality due to etching of the polysilicon layer.
  • one technical solution proposed by the present invention is to provide an OLED display panel, and the OLED display panel includes:
  • the anode layer provides an anode driving signal for the organic light emitting device layer, and the anode layer and the TFT substrate are leaked Pole connection
  • the TFT substrate includes a substrate and a gate electrode, a gate insulating layer, a polysilicon layer, a barrier layer, a source and a drain formed on the substrate, wherein the polysilicon layer includes a source region and a drain region. And a channel region, the polysilicon layer of the source region and the drain region being ion implanted;
  • the source and the drain respectively pass through the barrier layer above the source and drain regions and the first type of connection holes on the ion implanted polysilicon layer and the source region and the drain
  • the polysilicon layer of the region is connected;
  • the thickness of the barrier layer above the source region and the drain region is a thickness through which ions can pass, and is not zero;
  • the TFT substrate further includes a second type of contact hole, a metal trace in the same layer as the gate electrode, and a metal trace in the same layer as the source and the drain, and the gate electrode is in the same layer of metal.
  • a line is located below the barrier layer disposed outside the polysilicon layer;
  • the second type of contact hole is disposed on the barrier layer outside the polysilicon layer, and the metal trace in the same layer as the gate electrode passes through the second type of contact hole and the The source and drain are connected to the same metal trace.
  • the present invention also provides a technical solution for providing a TFT substrate, the TFT substrate comprising:
  • the substrate and a gate electrode, a gate insulating layer, a polysilicon layer, a barrier layer, a source and a drain formed on the substrate, wherein the polysilicon layer includes a source region, a drain region, and a channel region,
  • the polysilicon layer of the source region and the drain region are ion implanted;
  • the source and the drain respectively pass through the barrier layer above the source and drain regions and the first type of connection holes on the ion implanted polysilicon layer and the source region and the drain
  • the polysilicon layer of the region is connected;
  • the thickness of the barrier layer above the source region and the drain region is a thickness through which ions can pass, and is not zero.
  • Another technical solution provided by the present invention provides a method for preparing a TFT substrate, the preparation method comprising:
  • a gate electrode Forming a gate electrode, a gate insulating layer, a polysilicon layer, and a barrier layer on a substrate, wherein the polysilicon layer includes a source region, a drain region, and a channel region;
  • a source and a drain are formed over the barrier layer, wherein the source and drain are respectively connected to the polysilicon layer of the source and drain regions through the first type of contact hole.
  • the flexible display panel of the embodiment of the present invention includes a flexible substrate and a functional layer, and the flexible substrate includes at least two non-bending regions and a bending region between the at least two non-bending regions. At least one of the at least two non-bending regions is used as a display region; the display region and the bending region of the flexible substrate are both provided with an organic light emitting device layer, wherein the display region of the flexible substrate is further provided for providing driving to the organic light emitting device layer At least one metal layer of the signal, and the bending zone is further provided with a buffer layer.
  • the driving portion for driving the organic light emitting device layer in the bending region is disposed in the non-bending region near the bending region while the organic device light emitting layer is disposed in the bending region of the flexible display panel. Satisfying the bending zone can also display the picture, and reduce the probability that the metal traces are damaged by the bending in the bending zone, thereby improving the service life of the display panel.
  • FIG. 1 is a schematic flow chart of an embodiment of a method for preparing a TFT substrate of the present invention
  • FIG. 2a to 2e are schematic cross-sectional views showing an application example of a TFT substrate in each step shown in Fig. 1;
  • 3a to 3c are schematic cross-sectional views showing another application example of the TFT substrate in each step shown in Fig. 1;
  • FIG. 4 is a schematic structural view of an embodiment of an OLED display panel of the present invention.
  • FIG. 1 is a schematic flow chart of an embodiment of a method for fabricating a TFT substrate of the present invention. As shown in FIG. 1, the preparation method of this embodiment may include the following steps:
  • the substrate 10 may be PEN (Polyethylene). Naphthalene, polyethylene naphthalate), PET (Polyethylene) Terephthalate, polyethylene terephthalate) or PI (Polyimide, polyimide) or glass.
  • PEN Polyethylene
  • Naphthalene polyethylene naphthalate
  • PET Polyethylene
  • Terephthalate polyethylene terephthalate
  • PI Polyimide, polyimide
  • the substrate 10 may also be a flexible substrate, that is, the TFT substrate of the embodiment is applied in a flexible display device. Since the bottom gate type TFT substrate, the gate insulating layer and the polysilicon layer are prepared together in a vacuum device. There is no need to expose the polysilicon layer to deposit the gate insulating layer first. Therefore, applying the bottom gate type TFT substrate to the flexible display panel can improve the display quality of the flexible display panel. Further, since the polysilicon layer in the bottom gate type TFT substrate is prepared over the gate insulating layer, the protrusion formed on the surface of the polysilicon layer does not affect the interface quality between the polysilicon layer and the gate insulating layer when the polysilicon layer is formed. When the flexible display panel is bent, cracks are not easily generated due to the protrusions on the surface of the polysilicon layer, and the stability of the flexible display panel can be improved.
  • a gate electrode 20, a gate insulating layer 30, a polysilicon layer, and a barrier layer 50 are sequentially formed on the substrate 10 by sputtering, chemical vapor deposition, or the like.
  • the polysilicon layer is prepared by depositing an amorphous silicon layer, and then performing an excimer laser annealing on the amorphous silicon layer to convert the amorphous silicon layer into a polysilicon layer, and then obtaining a polysilicon layer on the polysilicon layer.
  • the polysilicon layer needs to be exposed and etched, that is, the polysilicon layer is patterned, and then deposited on the patterned polysilicon layer.
  • the patterned polysilicon layer is divided into a source region 41, a drain region 42 and a channel region 43, and the source region 41 and the drain region 42 are respectively located on both sides of the channel region 43.
  • a buffer layer (not shown) is further formed on the substrate 10.
  • the buffer layer is a silicon nitride buffer layer and a silicon oxide buffer layer on the substrate 10.
  • the formed gate electrode 20, gate insulating layer 30, polysilicon layer, and barrier layer 50 are all formed on the buffer layer.
  • the barrier layer located above the source region and the drain region is etched by the first mask so that the thickness of the barrier layer above the source region and the drain region is a thickness through which ions can pass, and Zero.
  • the barrier layer 50 is etched through a mask, specifically, the barrier layer 50 over the source region 41 and the drain region 42 is etched, and the source region 41 and the drain region 42 are etched.
  • the thickness of the barrier layer 50 is reduced to reduce the thickness of the barrier layer 50 above the source region 41 and the drain region 42 to a thickness through which ions can pass, but not zero, that is, the source region 41 and the drain are not exposed.
  • the polysilicon layer of the polar region 42 is etched through a mask, specifically, the barrier layer 50 over the source region 41 and the drain region 42 is etched, and the source region 41 and the drain region 42 are etched.
  • the thickness of the barrier layer 50 is reduced to reduce the thickness of the barrier layer 50 above the source region 41 and the drain region 42 to a thickness through which ions can pass, but not zero, that is, the source region 41 and the drain are not exposed.
  • the polysilicon layer of the polar region 42 is etched through a mask, specifically, the barrier layer 50 over the source region 41 and the drain
  • the barrier layer 50 above the channel region 43 is protected by photoresist, the barrier layer 50 above the channel region 43 is not etched, and the barrier layer above the source region 41 and the drain region 42 50 without photoresist protection, it will be etched.
  • the thickness of the barrier layer 50 in the barrier layer 50 above the channel region 43 is greater than that in the source region 41 and The thickness of the barrier layer 50 above the drain region 42. It is to be noted that the thickness of the barrier layer 50 above the etched channel region 43 needs to be a thickness that does not allow ions to pass through.
  • the transmittance of the portion of the first reticle corresponding to the barrier layer 50 above the channel region 43 is zero, so that the barrier layer 50 above the channel region 43 can be prevented from being etched.
  • the barrier layer 50 above the source region 41 and the drain region 42 is etched away, that is, the thickness of the barrier layer 50 above the channel region 43 etched by the first mask is the same as the thickness before etching.
  • the thickness of the barrier layer 50 before the etching is between 2800 angstroms and 3200 angstroms.
  • the barrier layer 50 is The thickness before the etching is 3000 angstroms; the barrier layer 50 above the source region 41 and the drain region 42 is etched to between 450 angstroms and 550 angstroms by the first reticle, in this embodiment, the source region
  • the barrier layer 50 over 41 and drain region 42 has a thickness of 500 angstroms after etching.
  • the TFT substrate prepared in step S102 is ion implanted. Since the thickness of the barrier layer 50 above the polysilicon layer of the channel region 43 is large, ions cannot pass through the barrier layer 50 above the channel region 43, and the source is The thickness of the barrier layer 50 above the region 41 and the drain region 42 is such that ions can be allowed to pass therethrough, so ions can be implanted into the source region 41 and the drain through the barrier layer 50 above the source region 41 and the drain region 42. In the polysilicon layer of region 42.
  • the TFT substrate prepared in the whole step S102 is ion implanted, and is used in this embodiment.
  • the boron atoms are ion implanted. In other embodiments, other ions may be used for ion implantation, which is not specifically limited in the present invention. Since the thickness of the barrier layer 50 above the source region 41 and the drain region 42 is small, the thickness of the barrier layer 50 above the channel region 43 is large, utilizing the source region 41, the drain region 42, and the channel region 43.
  • the difference in thickness of the barrier layer 50 allows boron ions implanted over the source region 41 and the drain region 42 to be implanted into the polysilicon layer through the barrier layer 50, while the boron ions above the channel region 43 are blocked.
  • the layer 50 is blocked, thereby performing ion implantation on the polysilicon layer of the source region 41 and the drain region 42.
  • the polysilicon layer is not exposed by etching, and the source region 41 and the drain region 42 may be The polysilicon layer is ion implanted, which avoids the damage of the polysilicon layer during the etching exposure, and affects the display quality.
  • the blocking of the source region 41 and the drain region 42 by another reticle is blocked.
  • the layer 50 is patterned to form a first type of contact hole 61.
  • the barrier layer 50 above the source region 41 and the drain region 42 is etched by the second mask, the ion-coated polysilicon layer is also etched and etched.
  • the first type of contact hole 61 passes through the ion-implanted polysilicon layer, and the gate insulating layer 30 is exposed at the bottom of the first type of contact hole 61.
  • the depth of the first type of contact hole 61 is greater than or equal to the sum of the thickness of the barrier layer 50 above the source region 41 and the drain region 42 after etching and the thickness of the polysilicon layer of the source region 41 and the drain region 42.
  • a metal layer is deposited on the substrate 10 by sputtering or the like, and the metal layer is patterned by another photomask to form a source 71 and a drain 72.
  • the material of the metal layer includes But not limited to materials such as gold, silver, copper or iron.
  • the source 71 and the drain 72 formed in this step are located above the barrier layer 50, and the first type of contact holes 61 prepared by the step S104 are respectively connected to the polysilicon layers of the source region 41 and the drain region 42.
  • the TFT substrate 100 shown in Fig. 2e is a TFT substrate obtained by the above production method.
  • the prepared source 71 and the drain 72 are prepared.
  • Contact with the polysilicon layer is by side contact. It can be understood that, in the process of preparing the first type contact hole 61, when the polysilicon layer is etched, the side surface of the first type contact hole 61 is relatively smooth, so the source 71 and the drain 72 are respectively separated from the source region.
  • the contact faces of the polysilicon layer of 41 and the drain region 42 are also relatively smooth, and the contact properties of the source 71 and the drain 72 with the polysilicon layers of the source region 41 and the drain region 42, respectively, can be improved.
  • the method for preparing the TFT substrate of the present embodiment can pass ions of the source region and the drain region of the polysilicon through the source region and the drain by etching the barrier layer with different thicknesses and using the difference in thickness of the barrier layer.
  • the barrier layer above the polar region is implanted into the corresponding polysilicon layer, and the thickness of the barrier layer above the channel region is larger, which blocks the implanted ions from conducting the polysilicon layer in the channel region, thereby not exposing the polysilicon layer.
  • Ion implantation of the source region and the drain region of the polysilicon layer can be achieved to avoid damage to the polysilicon layer when the polysilicon layer is exposed, thereby affecting display quality.
  • the gate electrode 20 when the gate electrode 20, the gate insulating layer 30, the polysilicon layer and the barrier layer 50 are formed on the substrate 10 in step S101, the remaining region of the substrate 10 is formed with the gate electrode 20 according to actual needs.
  • a metal trace 21 of the same layer forms a gate insulating layer 30 and a barrier layer 50 over the metal trace 21 in the same layer as the gate electrode 20. It is noted that the metal trace 21 and the gate in the same layer as the gate electrode 20 The electrodes 20 are not necessarily connected, and the connection relationship between the two needs to be set according to actual needs.
  • the metal trace 21 in the same layer as the gate electrode 20 is formed simultaneously with the gate electrode 20, that is, when the conductive layer for forming the gate electrode 20 is patterned, a part of the conductive layer forms the gate electrode 20, and the other part The conductive layer forms a metal trace 21 in the same layer as the gate electrode 20.
  • the metal traces 21 of the same layer of the gate electrode 20 need to be connected to the metal traces 73 of the same layer of the source 71 and the drain 72 to achieve signal conduction. Therefore, as shown in FIG. 3b,
  • the barrier layer 50 disposed outside the polysilicon layer may be patterned by the same mask to form the barrier layer 50 outside the polysilicon layer.
  • a second type of contact hole 62 is formed thereon. It is noted that the barrier layer 50 disposed outside the polysilicon layer in this embodiment refers to the barrier layer 50 over the metal trace 21 in the same layer as the gate electrode 20.
  • the gate insulating layer 30 and the barrier layer 50 over the metal trace 21 in the same layer as the gate electrode 20 are etched by a second mask to form a second type of contact hole 62, and the second type of contact hole 62 is exposed and gated.
  • the electrode 20 is in the same layer as the metal trace 21.
  • first type of contact hole 61 and the second type of contact hole 62 are simultaneously performed by the second photomask, if the second reticle corresponds to the first type of contact hole 61 and the second type of contact hole
  • the transmittances at 62 are the same, and the depths of the first type of contact holes 61 and the second type of contact holes 62 are the same.
  • the first type of contact holes 61 pass through the etched source region 41 and the drain region 42.
  • the barrier layer 50 and the polysilicon layer, the second type of contact hole 62 passes through the barrier layer 50 and the gate insulating layer 30 over the metal trace 21 in the same layer as the gate electrode 20, due to the metal trace in the same layer as the gate electrode 20.
  • the thickness of the barrier layer 50 above 21 is the same as the thickness of the barrier layer 50 of the source region 41 and the drain region 42 after etching, so the thickness of the polysilicon layer needs to be less than or equal to the thickness of the gate insulating layer 30.
  • the first type of contact hole 61 and the second type of contact hole 62 can be simultaneously formed.
  • the thickness of the gate insulating layer 30 is 900 angstroms, and the thickness of the polysilicon layer is 450 angstroms, due to the etched source region 41 and drain region 42.
  • the barrier layer 50 has a thickness of 500 angstroms.
  • the barrier layer 50 of 500 angstroms, the polysilicon layer of 450 angstroms, and the gate insulating layer 30 of 450 angstroms are etched to form the second type of contact holes 62.
  • a barrier layer 50 of 500 angstroms and a gate insulating layer 30 of 900 angstroms are etched away.
  • the first type of contact hole 61 formed passes through the polysilicon layer.
  • the thickness setting described above is only a thickness setting in a specific embodiment. In other embodiments, the thickness of each hierarchical structure can be adjusted according to requirements, and only the contact hole 62 of the second type needs to be exposed. While the gate electrode 20 is in the same layer as the metal trace, the first type of contact hole 61 passes through the polysilicon layer, and the metal trace 21 in the same layer as the gate electrode 20 is not etched when the second type contact hole 62 is prepared.
  • metal traces 73 in the same layer as the source 71 and the drain 72 are formed over the metal traces 21 of the same layer as the gate electrode 20,
  • the metal traces 73 in the same layer as the source 71 and the drain 72 are connected to the metal traces 21 in the same layer as the gate electrode 20 through the second type of contact holes 62.
  • the metal traces 73 in the same layer as the source 71 and the drain 72 are not connected to the source 71 and the drain 72.
  • the present invention also discloses a TFT substrate embodiment.
  • the TFT substrate in this embodiment is prepared according to the method for preparing the TFT substrate shown in FIG. 1.
  • the structure of the obtained TFT substrate is as shown in FIG. 2e or FIG. 3c. , 200 is the same, and will not be described here.
  • FIG. 4 is a schematic structural diagram of an embodiment of an OLED display panel of the present invention.
  • the OLED display panel of the present embodiment includes the TFT substrate 200 shown in FIG. 3c, and further includes a flat layer, an anode layer, and an organic light emitting device layer above the TFT substrate 200.
  • the TFT substrate in the OLED display panel may also be the TFT substrate 100 shown in FIG. 2e.
  • a flat layer 80 is deposited on the TFT substrate 200, and another conductive layer is deposited on the flat layer 80.
  • the conductive layer is patterned to form an anode layer 90, which is an organic light emitting device (OLED).
  • OLED organic light emitting device
  • An organic light emitting device layer 110 is formed on the anode layer 90.
  • the organic light emitting device layer 110 is provided with a plurality of organic light emitting devices 1101. In the present embodiment, the organic light emitting device 1101 is an OLED device.
  • the flat layer 80 is an organic flat layer.

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Abstract

提供了一种TFT基板的制备方法、TFT基板以及OLED显示面板。该TFT基板的制备方法包括在基板(10)上依次形成栅电极(20)、栅极绝缘层(30)、多晶硅层和阻挡层(50),多晶硅层包括源极区(41)、漏极区(42)和沟道区(43);通过一道光罩对源极区(41)和漏极区(42)上方的阻挡层(50)进行刻蚀,使源极区(41)和漏极区(42)上方的阻挡层(50)的厚度为离子能够穿过的厚度,且不为零;再对多晶硅层进行离子布植;通过上述方式,可以不用暴露出源极区(41)和漏极区(42)的多晶硅层既能够对源极区(41)和漏极区(42)的多晶硅层进行离子布植,避免了多晶硅层在制备过程中受到损坏,提升TFT基板的稳定性,提高显示质量。

Description

一种TFT基板的制备方法、TFT基板以及OLED显示面板
【技术领域】
本发明涉及显示技术领域,具体而言涉及一种TFT基板的制备方法、TFT基板以及OLED显示面板。
【背景技术】
随着显示技术的发展,人们对显示面板的解析度要求越来越高。现有技术中,为了提高显示面板的解析度,常常在显示面板中采用低温多晶硅技术,即低温多晶硅的TFT基板,但目前采用的TFT基板一般为顶栅型TFT基板,即将TFT的栅极制备在TFT结构顶端,顶栅型TFT基板电性优异,但其可靠性较低。
顶栅型TFT基板在制备过程中对非晶硅进行准分子激光退火时,会在形成的多晶硅层上形成不可避免的突起,这些突起会影响栅极绝缘层与多晶硅层之间的界面质量,降低栅极绝缘层的击穿电压,限制了栅极绝缘层的厚度的进一步降低。
现有技术中,在某些显示面板中也使用底栅型TFT基板,但在现有技术中,制备底栅型TFT基板时,需要对多晶硅层上方的阻挡层进行刻蚀,暴露出极区和漏极区的多晶硅层,再对暴露的源极区和漏极区的多晶硅层进行离子布植,这种方式通常会在刻蚀阻挡层时,对下层的多晶硅层造成损坏,引入缺陷,严重时造成多晶硅层被完全蚀刻,影响显示面板的显示质量。
【发明内容】
有鉴于此,本发明提供一种TFT基板的制备方法、TFT基板以及OLED显示面板,该TFT基板的制备方法解决由于多晶硅层受到刻蚀影响而降低显示质量的问题。
为解决上述技术问题,本发明提出的一个技术方案是:提供一种OLED显示面板,该OLED显示面板包括:
TFT基板,以及形成于所述TFT基板上的平坦层、阳极层、有机发光器件层;所述阳极层为所述有机发光器件层提供阳极驱动信号,所述阳极层与所述TFT基板的漏极连接;
其中,所述TFT基板包括基板及形成在所述基板上的栅电极、栅极绝缘层、多晶硅层、阻挡层、源极和漏极,其中,所述多晶硅层包括源极区、漏极区和沟道区,所述源极区和漏极区的所述多晶硅层经过离子布植;
所述源极和漏极分别通过所述源极区和漏极区上方的所述阻挡层以及经过离子布植的所述多晶硅层上的第一类连接孔与所述源极区和漏极区的所述多晶硅层连接;
其中,所述源极区和所述漏极区上方的所述阻挡层的厚度为离子能够穿过的厚度,且不为零;
所述所述TFT基板还包括第二类接触孔、与所述栅电极同层的金属走线以及与所述源极和漏极同层的金属走线,所述栅电极同层的金属走线位于所述设置于所述多晶硅层之外的所述阻挡层下方;
其中,所述第二类接触孔设置在所述多晶硅层之外的所述阻挡层上,所述与所述栅电极同层的金属走线通过所述第二类接触孔与所述与所述源极和漏极同层的金属走线连接。
本发明还提出的一个技术方案:提供一种TFT基板,该TFT基板包括:
基板及形成在所述基板上的栅电极、栅极绝缘层、多晶硅层、阻挡层、源极和漏极,其中,所述多晶硅层包括源极区、漏极区和沟道区,所述源极区和漏极区的所述多晶硅层经过离子布植;
所述源极和漏极分别通过所述源极区和漏极区上方的所述阻挡层以及经过离子布植的所述多晶硅层上的第一类连接孔与所述源极区和漏极区的所述多晶硅层连接;
其中,所述源极区和所述漏极区上方的所述阻挡层的厚度为离子能够穿过的厚度,且不为零。
本发明还提出的另一个技术方案,提供一种TFT基板的制备方法,该制备方法包括:
在一基板上依次形成栅电极、栅极绝缘层、多晶硅层和阻挡层,其中,所述多晶硅层包括源极区、漏极区和沟道区;
通过第一道光罩对位于所述源极区和漏极区上方的所述阻挡层进行刻蚀,以使所述源极区和所述漏极区上方的所述阻挡层的厚度为离子能够穿过的厚度,且不为零;
对所述源极区和所述漏极区的所述多晶硅层进行离子布植;
通过第二道光罩对所述源极区和漏极区上方的所述阻挡层进行图案化处理,以分别在所述源极区和漏极区上方的所述阻挡层上形成第一类接触孔;
在所述阻挡层上方形成源极和漏极,其中,所述源极和漏极分别通过所述第一类接触孔与所述源极区和漏极区的所述多晶硅层连接。
有益效果:区别于现有技术,本发明实施例的柔性显示面板包括柔性基板和功能层,柔性基板包括至少两个非弯折区和位于至少两个非弯折区之间的弯折区,至少两个非弯折区中至少一个用作显示区;柔性基板的显示区和弯折区均设置有有机发光器件层,其中,柔性基板的显示区还设置有用于向有机发光器件层提供驱动信号的至少一金属层,弯折区还设置有缓冲层。本发明通过在柔性显示面板的弯折区内设置有机器件发光层的同时,将用于驱动弯折区内的有机发光器件层的驱动部分设置在弯折区附近的非弯折区内,在满足弯折区也能够显示画面的同时,减少弯折区内有金属走线受到弯折影响而损害的概率,提高显示面板的使用寿命。
【附图说明】
图1是本发明TFT基板的制备方法一实施例的流程示意图;
图2a至2e是图1所示的各个步骤中TFT基板的一应用例的截面示意图;
图3a至3c是图1所示的各个步骤中TFT基板的另一应用例的截面示意图;
图4是本发明OLED显示面板一实施例的结构示意图。
【具体实施方式】
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,说明书及说明书附图中,相同结构采用相同标号,显然,所描述的实施例仅是本发明的一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
参阅图1,图1是本发明TFT基板的制备方法一实施例的流程示意图。如图1所示,本实施例的制备方法可包括如下步骤:
S101、在一基板上依次形成栅电极、栅极绝缘层、多晶硅层和阻挡层。
本实施例中,基板10可以是PEN(Polyethylene naphthalene,聚萘二甲酸乙二醇酯)、PET(Polyethylene terephthalate,聚对苯二甲酸乙二醇酯)或PI(Polyimide,聚酰亚胺)或玻璃制成的。
此外,基板10还可以是柔性基板,即将本实施例的TFT基板应用在柔性显示装置中,由于底栅型TFT基板中,其栅极绝缘层和多晶硅层的制备是在真空设备中一起完成的,不需要先对多晶硅层进行曝光再沉积栅极绝缘层,因此,将底栅型TFT基板应用在柔性显示面板中能够提升柔性显示面板的显示质量。进一步,由于底栅型TFT基板中的多晶硅层是制备在栅极绝缘层上方,因此在形成多晶硅层时,在多晶硅层表面形成的突起不会影响多晶硅层与栅极绝缘层之间的界面质量,使得柔性显示面板发生弯折时,不容易因为多晶硅层表面的突起而产生裂纹,能够提升柔性显示面板的稳定性。
如图2a所示,通过溅镀、化学气相沉积等方式在基板10上依次形成栅电极20、栅极绝缘层30、多晶硅层和阻挡层50。可以理解的是,多晶硅层的制备是先沉积非晶硅层,再对非晶硅层进行准分子激光退火等方式使非晶硅层转变为多晶硅层,得到多晶硅层之后再在该多晶硅层上沉积阻挡层50,值得注意的是,在多晶硅层上沉积阻挡层50之前,需要对多晶硅层进行曝光刻蚀,即对多晶硅层进行图案化处理,再在图案化处理后的多晶硅层上沉积阻挡层50。其中,将图案化处理后的多晶硅层划分为源极区41、漏极区42和沟道区43,源极区41和漏极区42分别位于沟道区43两侧。
可以理解的是,在基板10上形成栅电极20之前,基板10上还制备有缓冲层(图中未画出),该缓冲层为氮化硅缓冲层和氧化硅缓冲层,在基板10上形成的栅电极20、栅极绝缘层30、多晶硅层和阻挡层50均是形成在缓冲层上的。
S102、通过第一道光罩对位于源极区和漏极区上方的阻挡层进行刻蚀,以使源极区和漏极区上方的阻挡层的厚度为离子能够穿过的厚度,且不为零。
通过一道光罩对阻挡层50进行刻蚀,具体的,对位于源极区41和漏极区42上方的阻挡层50进行刻蚀,通过刻蚀使源极区41和漏极区42上方的阻挡层50厚度减小,使源极区41和漏极区42上方的阻挡层50的厚度减小至能够让离子穿过的厚度,但不为零,即不暴露出源极区41和漏极区42的多晶硅层。
本实施例中,由于沟道区43上方的阻挡层50有光阻保护,因此沟道区43上方的阻挡层50不会被刻蚀,而源极区41和漏极区42上方的阻挡层50没有光阻保护,则会被刻蚀,如图2b所示通过第一道光罩刻蚀后,阻挡层50中位于沟道区43上方的阻挡层50的厚度大于位于源极区41和漏极区42上方的阻挡层50的厚度。值得注意的是,刻蚀后的沟道区43上方的阻挡层50的厚度需要为不能让离子穿过的厚度。可选的,令第一道光罩中对应与沟道区43上方的阻挡层50的部分的透光率为零,则能够使沟道区43上方的阻挡层50不被刻蚀,而刻蚀掉源极区41和漏极区42上方的阻挡层50,即经第一道光罩刻蚀后的沟道区43上方的阻挡层50的厚度与刻蚀前的厚度相同。
为了后续能够实现对源极区41和漏极区42的多晶硅层进行离子布植,阻挡层50在未刻蚀前的厚度为2800埃至3200埃之间,本实施例中,阻挡层50在未刻蚀前的厚度为3000埃;通过第一道光罩将源极区41和漏极区42上方的阻挡层50刻蚀至450埃至550埃之间,本实施例中,源极区41和漏极区42上方的阻挡层50刻蚀后的厚度为500埃。
S103、对源极区和漏极区的多晶硅层进行离子布植。
此时,对步骤S102制备得到TFT基板进行离子布植,由于沟道区43的多晶硅层上方的阻挡层50的厚度较大,离子不能穿过沟道区43上方的阻挡层50,而源极区41和漏极区42上方的阻挡层50的厚度是能够允许离子穿过的,因此离子能够通过源极区41和漏极区42上方的阻挡层50布植到源极区41和漏极区42的多晶硅层中。
如图2c所示,本实施例中对源极区41和漏极区42的多晶硅层进行离子布植时,是对整个步骤S102制备得到的TFT基板进行离子布植的,本实施例中利用硼原子进行离子布植,在其他实施例中,也可以使用其他离子进行离子布植,本发明不做具体限制。由于源极区41和漏极区42上方的阻挡层50的厚度较小,沟道区43上方的阻挡层50的厚度较大,利用源极区41、漏极区42和沟道区43上方的阻挡层50的厚度差异,使布植在源极区41和漏极区42上方的硼离子能够穿过阻挡层50布植入多晶硅层中,而沟道区43上方的硼离子则被阻挡层50阻挡,进而实现对源极区41和漏极区42的多晶硅层进行离子布植,本实施例中不需要通过刻蚀暴露出多晶硅层,即可对源极区41和漏极区42的多晶硅层进行离子布植,避免了多晶硅层在刻蚀暴露的过程中收到损坏,而影响显示质量。
S104、通过第二道光罩对源极区和漏极区上方的阻挡层进行图案化处理,以分别在源极区和漏极区上方的阻挡层上形成第一类接触孔。
为了使后续步骤中制备的源极71和漏极72能够分别与源极区41和漏极区42的多晶硅层连接,则通过另一道光罩对源极区41和漏极区42上方的阻挡层50进行图案化处理,以形成第一类接触孔61。如图2d所示,在利用第二道光罩对对源极区41和漏极区42上方的阻挡层50进行刻蚀时,对经过离子布植的多晶硅层也进行刻蚀,刻蚀得到的第一类接触孔61穿过经过离子布植的多晶硅层,且第一类接触孔61的底部会裸露出栅极绝缘层30。第一类接触孔61的深度大于或等于刻蚀后的源极区41和漏极区42上方的阻挡层50的厚度与源极区41和漏极区42的多晶硅层的厚度的总和。
S105、在阻挡层上方形成源极和漏极。
如图2e所示,通过溅镀等方式在基板10上沉积一金属层,通过另一道光罩对该金属层进行图案化处理,以形成源极71和漏极72,该金属层的材料包括但不限于金、银、铜或铁等材料。本步骤形成的源极71和漏极72位于阻挡层50上方,通过步骤S104制备得到的第一类接触孔61分别与源极区41和漏极区42的多晶硅层连接。图2e所示的TFT基板100即为根据上述制备方法得到的TFT基板。
本实施例中,由于第一类接触孔61穿过经过离子布植的多晶硅层,且第一类接触孔61的底部会裸露出栅极绝缘层30,因此制备的源极71和漏极72与多晶硅层的接触是通过侧面接触的。可以理解的是,在制备第一类接触孔61的过程中,对多晶硅层刻蚀时,第一类接触孔61的侧面是比较平滑的,因此源极71和漏极72分别与源极区41和漏极区42的多晶硅层的接触面也是比较平滑的,能够提高源极71和漏极72分别与源极区41和漏极区42的多晶硅层的接触性能。
本实施例的TFT基板的制备方法通过对阻挡层进行不同厚度的刻蚀,利用阻挡层的厚度差,使得布植在多晶硅的源极区和漏极区处的离子能够通过源极区和漏极区上方的阻挡层布植入相应的多晶硅层中,而沟道区上方的阻挡层的厚度较大,则阻挡了布植的离子进行沟道区的多晶硅层,进而不用暴露出多晶硅层即可实现对多晶硅层的源极区和漏极区进行离子布植,避免在暴露多晶硅层时对多晶硅层造成损坏,影响显示质量。
进一步,如图3a所示,在步骤S101中在基板10上形成栅电极20、栅极绝缘层30、多晶硅层和阻挡层50时,在基板10的剩余区域会根据实际需求形成与栅电极20同层的金属走线21,在与栅电极20同层的金属走线21上方形成栅极绝缘层30和阻挡层50,值得注意的是,与栅电极20同层的金属走线21与栅电极20不一定连接,两者之间的连接关系需要根据实际需求进行设置。其中,与栅电极20同层的金属走线21是与栅电极20同时形成的,即在对用于形成栅电极20的导电层进行图案化处理时,一部分导电层形成栅电极20,另一部分导电层形成与栅电极20同层的金属走线21。
在一些显示面板的应用中,栅电极20同层的金属走线21需要和源极71和漏极72同层的金属走线73连接,以实现信号导通,因此,如图3b所示,在步骤S104中利用第二道光罩制备第一类接触孔61时,可以通过该同一道光罩对设置于多晶硅层之外的阻挡层50进行图案化处理,以在多晶硅层之外的阻挡层50上形成第二类接触孔62,值得注意的是,本实施例中的设置于多晶硅层之外的阻挡层50指的是位于与栅电极20同层的金属走线21上方的阻挡层50。通过第二道光罩对与栅电极20同层的金属走线21上方的栅极绝缘层30和阻挡层50进行刻蚀,形成第二类接触孔62,第二类接触孔62暴露出与栅电极20同层的金属走线21。
值得注意的是,由于第一类接触孔61和第二类接触孔62均是通过第二道光罩同时执行的,若第二道光罩中对应于第一类接触孔61和第二类接触孔62处的透光率相同,则第一类接触孔61和第二类接触孔62的深度是相同,第一类接触孔61穿过了刻蚀后的源极区41与漏极区42的阻挡层50和多晶硅层,第二类接触孔62穿过了与栅电极20同层的金属走线21上方的阻挡层50和栅极绝缘层30,由于与栅电极20同层的金属走线21上方的阻挡层50的厚度与刻蚀后的源极区41与漏极区42的阻挡层50的厚度相同,因此多晶硅层的厚度需要小于或等于栅极绝缘层30的厚度,如此才能使第一类接触孔61和第二类接触孔62能够同时形成。
本实施例中,为了满足各个层级之间的厚度关系,令栅极绝缘层30的厚度为900埃,多晶硅层的厚度为450埃,由于刻蚀后的源极区41与漏极区42的阻挡层50的厚度为500埃,如此形成第一类接触孔61时刻蚀掉500埃的阻挡层50、450埃的多晶硅层和450埃的栅极绝缘层30,形成第二类接触孔62时刻蚀掉500埃的阻挡层50和900埃的栅极绝缘层30。通过上述的厚度设置,使第二类接触孔62暴露出与栅电极20同层的金属走线21时,形成的第一类接触孔61穿过多晶硅层。值得注意的是,上述的厚度设置仅是一个具体实施方式中的厚度设置,在其他实施方式中,每个层级结构的厚度可以根据需求进行调整,只需要满足第二类接触孔62暴露出与栅电极20同层的金属走线的同时,第一类接触孔61穿过多晶硅层,其中,制备第二类接触孔62时不刻蚀与栅电极20同层的金属走线21。
如图3c所示,在步骤S105中制备源极71和漏极72时,在与栅电极20同层的金属走线21上方形成与源极71和漏极72同层的金属走线73,其中,与源极71和漏极72同层的金属走线73通过第二类接触孔62连接与栅电极20同层的金属走线21。与源极71和漏极72同层的金属走线73与源极71和漏极72均不连接。
本发明还公开了TFT基板实施例,本实施例中的TFT基板是根据图1所示的TFT基板的制备方法制备得到,得到的TFT基板的结构如图2e或图3c所示的TFT基板100,200相同,此处不再赘述。
参阅图4,图4是本发明OLED显示面板一实施例的结构示意图。如图4所示,本实施例的OLED显示面板包括图3c所示的TFT基板200,在TFT基板200上方还包括平坦层、阳极层、有机发光器件层。在其他实施例中,OLED显示面板中的TFT基板也可以图2e所示的TFT基板100。
本实施例中,在TFT基板200上沉积平坦层80,并在平坦层80上沉积另一导电层,对该导电层进行图案化处理形成阳极层90,该阳极层90为有机发光器件(OLED器件)的阳极。在阳极层90上形成有机发光器件层110。有机发光器件层110中设置有若干个有机发光器件1101,本实施例中有机发光器件1101为OLED器件。其中,平坦层80为有机平坦层。
以上仅为本发明的实施例,并非因此限制本发明的专利范围,凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换,或直接或间接运用在其他相关的技术领域,均同理包括在本发明的专利保护范围。

Claims (15)

  1. 一种OLED显示面板,其中,包括:
    TFT基板,以及形成于所述TFT基板上的平坦层、阳极层、有机发光器件层;所述阳极层为所述有机发光器件层提供阳极驱动信号,所述阳极层与所述TFT基板的漏极连接;
    其中,所述TFT基板包括基板及形成在所述基板上的栅电极、栅极绝缘层、多晶硅层、阻挡层、源极和漏极,其中,所述多晶硅层包括源极区、漏极区和沟道区,所述源极区和漏极区的所述多晶硅层经过离子布植;
    所述源极和漏极分别通过所述源极区和漏极区上方的所述阻挡层以及经过离子布植的所述多晶硅层上的第一类连接孔与所述源极区和漏极区的所述多晶硅层连接;
    其中,所述源极区和所述漏极区上方的所述阻挡层的厚度为离子能够穿过的厚度,且不为零;
    所述所述TFT基板还包括第二类接触孔、与所述栅电极同层的金属走线以及与所述源极和漏极同层的金属走线,所述栅电极同层的金属走线位于所述设置于所述多晶硅层之外的所述阻挡层下方;
    其中,所述第二类接触孔设置在所述多晶硅层之外的所述阻挡层上,所述与所述栅电极同层的金属走线通过所述第二类接触孔与所述与所述源极和漏极同层的金属走线连接。
  2. 根据权利要求1所述的OLED显示面板,其中,所述多晶硅层的厚度小于或等于所述栅极绝缘层的厚度。
  3. 根据权利要求1所述的OLED显示面板,其中,所述源极区和漏极区上方的所述阻挡层的厚度为450埃至550埃之间,所述沟道区上方的所述阻挡层的厚度与刻蚀前的厚度相同。
  4. 一种TFT基板,其中,包括:
    基板及形成在所述基板上的栅电极、栅极绝缘层、多晶硅层、阻挡层、源极和漏极,其中,所述多晶硅层包括源极区、漏极区和沟道区,所述源极区和漏极区的所述多晶硅层经过离子布植;
    所述源极和漏极分别通过所述源极区和漏极区上方的所述阻挡层以及经过离子布植的所述多晶硅层上的第一类连接孔与所述源极区和漏极区的所述多晶硅层连接;
    其中,所述源极区和所述漏极区上方的所述阻挡层的厚度为离子能够穿过的厚度,且不为零。
  5. 根据权利要求4所述的低温多晶硅薄膜晶体管,其中,所述多晶硅层的厚度小于或等于所述栅极绝缘层的厚度。
  6. 根据权利要求4所述的低温多晶硅薄膜晶体管,其中,所述源极区和漏极区上方的所述阻挡层的厚度为450埃至550埃之间,所述沟道区上方的所述阻挡层的厚度与刻蚀前的厚度相同。
  7. 根据权利要求4所述的低温多晶硅薄膜晶体管,其中,所述所述TFT基板还包括第二类接触孔、与所述栅电极同层的金属走线以及与所述源极和漏极同层的金属走线,所述栅电极同层的金属走线位于所述设置于所述多晶硅层之外的所述阻挡层下方;
    其中,所述第二类接触孔设置在所述多晶硅层之外的所述阻挡层上,所述与所述栅电极同层的金属走线通过所述第二类接触孔与所述与所述源极和漏极同层的金属走线连接。
  8. 一种TFT基板的制备方法,其中,包括:
    在一基板上依次形成栅电极、栅极绝缘层、多晶硅层和阻挡层,其中,所述多晶硅层包括源极区、漏极区和沟道区;
    通过第一道光罩对位于所述源极区和漏极区上方的所述阻挡层进行刻蚀,以使所述源极区和所述漏极区上方的所述阻挡层的厚度为离子能够穿过的厚度,且不为零;
    对所述源极区和所述漏极区的所述多晶硅层进行离子布植;
    通过第二道光罩对所述源极区和漏极区上方的所述阻挡层进行图案化处理,以分别在所述源极区和漏极区上方的所述阻挡层上形成第一类接触孔;
    在所述阻挡层上方形成源极和漏极,其中,所述源极和漏极分别通过所述第一类接触孔与所述源极区和漏极区的所述多晶硅层连接。
  9. 根据权利要求8所述的制备方法,其中,所述通过第一道光罩对位于所述源极区和漏极区上方的所述阻挡层进行刻蚀,包括:
    通过所述第一道光罩,令刻蚀后的所述沟道区上方的所述阻挡层的厚度大于所述源极区和漏极区上方的所述阻挡层的厚度,且刻蚀后的所述沟道区上方的所述阻挡层的厚度为离子不能穿过的厚度。
  10. 根据权利要求9所述的制备方法,其中,所述对所述源极区和所述漏极区的所述多晶硅层进行离子布植,包括:
    对所述TFT基板进行离子布植,位于所述源极区和漏极区上方离子穿过所述源极区和漏极区上方所述阻挡层,掺入所述源极区和漏极区的多晶硅层,且位于所述沟道区上方的离子被所述沟道区上方的所述阻挡层阻挡。
  11. 根据权利要求8所述的制备方法,其中,所述通过第二道光罩对所述源极区和漏极区上方的所述阻挡层进行图案化处理,以分别在所述源极区和漏极区上方的所述阻挡层上形成第一类接触孔,包括:
    通过第二道光罩对所述源极区和漏极区上方的所述阻挡层以及经过离子布植的所述多晶硅层进行图案化处理,以使所述阻挡层和所述多晶硅层的图案化区域形成第一类接触孔。
  12. 根据权利要求8所述的制备方法,其中,所述通过第二道光罩对所述源极区和漏极区上方的所述阻挡层进行图案化处理,以分别在所述源极区和漏极区上方的所述阻挡层上形成第一类接触孔,还包括:
    通过所述第二道光罩对设置于所述多晶硅层之外的所述阻挡层进行图案化处理,以在所述设置于所述多晶硅层之外的所述阻挡层上形成第二类接触孔;
    其中,所述第二类接触孔用于连接所述栅电极同层的金属走线与所述源极和漏极同层的金属走线,所述栅电极同层的金属走线位于所述设置于所述多晶硅层之外的所述阻挡层下方。
  13. 根据权利要求8所述的制备方法,其中,所述多晶硅层的厚度小于或等于所述栅极绝缘层的厚度。
  14. 根据权利要求8所述的制备方法,其中,经所述第一道光罩刻蚀后的所述源极区和漏极区上方的所述阻挡层的厚度为450埃至550埃之间,经所述第一道光罩刻蚀后的所述沟道区上方的所述阻挡层的厚度与刻蚀前的厚度相同。
  15. 根据权利要求8所述的制备方法,其中,所述第一类接触孔的底部裸露出所述栅极绝缘层。
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