WO2019001090A1 - Information processing method, apparatus and communication device - Google Patents

Abstract

Disclosed in the present application are an encoding method and apparatus, a communication device and a communication system. The method comprises: using a low density parity check (LDPC) matrix to encode an input bit sequence; the LDPC matrix being obtained on the basis of a spreading factor Z and a basis matrix, the basis matrix comprising the 0th to 6th rows and the 0th to 16th columns in one of the matrices shown in figures 3b-1 to 3b-8, or the basis matrix comprising the 0th to 6th rows and some of the 0th to 16th columns in any one of the matrices shown in figures 3b-1 to 3b-8. The encoding method and apparatus, the communication device and the communication system of the present application are able to support encoding requirements of information bit sequences of various lengths.

Description

Information processing method, device and communication device Technical field

Embodiments of the present invention relate to the field of communications, and in particular, to a method for information processing and a communication device.

Background technique

Low density parity check (LDPC) code is a kind of linear block coding with sparse check matrix, which has the characteristics of flexible structure and low decoding complexity. Because it uses a partially parallel iterative decoding algorithm, it has a higher throughput than the traditional Turbo code. The LDPC code can be used for the error correction code of the communication system, thereby improving the reliability and power utilization of the channel transmission. LDPC codes can also be widely used in space communication, optical fiber communication, personal communication systems, ADSL, and magnetic recording devices. At present, LDPC codes have been considered as one of channel coding methods in the fifth generation mobile communication.

In actual use, an LDPC matrix with special structured features can be used. The LDPC matrix H with special structuring features can be obtained by extending the LDPC basis matrix of a quasi-cycle (QC) structure. QC-LDPC is suitable for hardware with high parallelism and provides higher throughput. The LDPC matrix can be designed to be applied to channel coding.

QC-LDPC is suitable for hardware with high parallelism and provides higher throughput. The LDPC matrix can be designed to be applied to channel coding.

Summary of the invention

Embodiments of the present invention provide a method, a communication device, and a system for information processing, which can support encoding and decoding of information bit sequences of various lengths.

In a first aspect, an encoding method and an encoder are provided that encode an input sequence using a low density parity check LDPC matrix.

In a second aspect, a decoding method and decoder are provided that decode an input sequence using a low density parity check LDPC matrix.

In the first aspect or the first implementation of the second aspect, the LDPC matrix is obtained based on the spreading factor Z and the base matrix.

Based on the above implementation manner, the base matrix of the base map 30a may include: 0th to 6th rows and 0th to 16th columns of one of the matrices in the matrix shown in FIG. 3b-1 to FIG. 3b-8, or the base matrix includes The 0th to 6th rows of one of the matrices in the matrix shown in FIGS. 3b-1 to 3b-8 and the partial columns in the 0th to 16th columns. Alternatively, the base matrix of the base map 30a may be the matrix of the 0th to 6th rows of the matrix in the matrix shown in FIG. 3b-1 to FIG. 3b-8 and the row/column transformed matrix of the 0th to 16th columns, or The matrix may be a row/column transformed matrix of the 0th to 6th rows of one of the matrices in the matrix shown in FIGS. 3b-1 to 3b-8 and the partial columns in the 0th to 16th columns.

In order to support different block lengths, the LDPC code requires different spreading factors Z. Based on the foregoing implementation manner, in a possible implementation manner, a base matrix corresponding thereto is adopted based on different spreading factors Z. For example, Z = a × 2 ^j , 0 ^≤ j < 7, a ∈ {2, 3, 5, 7, 9, 11, 13, 15}.

Further, optionally, based on the foregoing implementation manner, the LDPC matrix may be obtained based on the spreading factor Z and the matrix Hs compensated for each of the foregoing base matrices, or based on the spreading factor Z and the matrix after compensating the foregoing base matrices. The matrix after the row/column transformation of Hs is obtained. For the foregoing base matrix compensation, the offset value may be increased or decreased for an offset value greater than or equal to 0 in one or more of the columns.

The base map and the base matrix of the LDPC matrix in each of the foregoing implementation manners can satisfy the performance requirements of the code blocks of various block lengths.

Wherein, the spreading factor Z may be determined by the encoder or the decoder according to the length K of the input sequence, or may be determined by other devices and provided as an input parameter to the encoder or the decoder. Optionally, the LDPC matrix may be obtained according to the obtained spreading factor Z and the base matrix corresponding to the spreading factor Z.

In the above first aspect or the second implementation of the second aspect, the LDPC matrix is obtained based on parameters of the spreading factor Z and the LDPC matrix.

The parameters of the LDPC matrix may include: a row number, a column in which the non-zero element is located, and a non-zero element offset value, as in rows 0 to 6 of the table shown in Table 2, Table 3b-1 to Table 3b-8. Way to save. It can also include line weights. The offset values in the positions of the non-zero elements and the non-zero element offset values are one-to-one correspondence.

For the communication device at the transmitting end, encoding the input sequence by using the LDPC matrix may include: encoding the input sequence by using an LDPC matrix corresponding to the spreading factor Z; or the LDPC matrix corresponding to the spreading factor Z undergoes row/column conversion, The input sequence is encoded using a matrix whose row/column transformed matrix encodes the input sequence. The row/column transformation in this application refers to a row transformation, a column transformation, or a row transformation and a column transformation.

For the communication device at the receiving end, decoding the input sequence using the LDPC matrix includes: decoding the input sequence using the LDPC matrix corresponding to the spreading factor Z; or the LDPC matrix corresponding to the spreading factor Z undergoes row/column conversion, using the row/ The matrix after the column transformation encodes the input sequence to encode the input sequence. The row/column transformation in this application refers to a row transformation, a column transformation, or a row transformation and a column transformation.

In a possible implementation, the LDPC matrix may be saved, the input sequence is encoded using the LDPC matrix, or transformed (row/column transform) or extended based on the LDPC matrix to obtain an LDPC matrix usable for encoding.

In another possible implementation, parameters may be saved, and an LDPC matrix for encoding or decoding may be obtained according to the parameters, so that the input sequence may be encoded or decoded based on the LDPC matrix. The parameter includes at least one of: a base map, a base matrix, a transform matrix based on a base/column transformation of a base map or a base matrix, an extended matrix based on a base map or a base matrix, and an offset value of a non-zero element in the base matrix; Or any parameter related to obtaining an LDPC matrix.

In yet another possible implementation, the base matrix of the LDPC matrix can be stored in a memory.

In yet another possible implementation, the base map of the LDPC matrix is stored in a memory, and offset values of non-zero elements in the base matrix of the LDPC matrix may be stored in the memory.

In another possible implementation manner, the parameters of the LDPC matrix are stored in the memory in the manner shown in Table 2 or Table 3b-1 to Table 3b-8, and some of the element groups may also be saved.

Based on the foregoing possible implementation manners, in a possible design, at least one of the base map and the base matrix used for LDPC encoding or decoding is at least one of a base map and a base matrix of the foregoing LDPC matrix, or Column exchange, or row exchange and column exchange.

In a third aspect, a communication device is provided that can include corresponding modules for performing the above method design. The module can be software and/or hardware.

In one possible design, a communication device provided by the third aspect includes a processor and a transceiver component that can be used to implement the functions of various portions of the encoding or decoding method described above. In this design, if the communication device is a terminal, a base station or other network device, the transceiver component thereof may be a transceiver. If the communication device is a baseband chip or a baseband single board, the transceiver component may be a baseband chip or a baseband single board. Input/output circuits for receiving/transmitting input/output signals. The communication device can optionally also include a memory for storing data and/or instructions.

In one implementation, the processor may include the encoder and the determining unit as described in the first aspect above. The determining unit is operative to determine a spreading factor Z required to encode the input sequence. The encoder is configured to encode the input sequence using an LDPC matrix corresponding to the spreading factor Z.

In another implementation, the processor may include the decoder and the obtaining unit as described in the second aspect above. The obtaining unit is configured to acquire a soft value and an expansion factor Z of the LDPC code. The decoder is configured to decode the soft value of the LDPC code based on the base matrix H _B corresponding to the spreading factor Z to obtain an information bit sequence.

In a fourth aspect, a communication device is provided that includes one or more processors. In one possible design, one or more of the processors may implement the functions of the encoder of the first aspect, and in another possible design, the encoder of the first aspect may be the processor In part, the processor can implement other functions in addition to the functions of the encoder described in the first aspect. In one possible design, one or more of the processors may implement the functions of the decoder of the second aspect, and in another possible design, the decoder of the second aspect may be Part of the processor.

Optionally, the communication device may further include a transceiver and an antenna.

Optionally, the communication device may further include a device for generating a transport block CRC, a device for code block splitting and CRC check, an interleaver for interleaving, a modulator for modulation processing, and the like. In one possible design, the functionality of these devices can be implemented by one or more processors.

Optionally, the communication device may further include a demodulator for demodulation operation, a deinterleaver for deinterleaving, a device for de-rate matching, and the like. The functionality of these devices can be implemented by one or more processors.

In a fifth aspect, an embodiment of the present invention provides a communication system, where the system includes the communication device described in the foregoing third aspect.

In a sixth aspect, an embodiment of the present invention provides a communication system, where the system includes one or more communication devices according to the fourth aspect.

In still another aspect, an embodiment of the present invention provides a computer storage medium having stored thereon a program, and when executed, causes a computer to perform the method described in the above aspect.

Yet another aspect of the present application provides a computer program product comprising instructions which, when run on a computer, cause the computer to perform the methods described in the various aspects above.

The method, device, communication device and communication system of the information processing according to the embodiments of the present invention can adapt to the flexible code length code rate requirement of the system in coding performance and error leveling.

DRAWINGS

1 is a schematic diagram of a base map, a base matrix, and a cyclic permutation matrix of an LDPC code;

2 is a schematic structural diagram of a base diagram of an LDPC code;

3a is a schematic diagram of a base diagram of an LDPC code according to an embodiment of the present invention;

FIG. 3b-1 is a schematic diagram of a base matrix according to an embodiment of the present invention; FIG.

3b-2 is a schematic diagram of another base matrix according to an embodiment of the present invention;

3b-3 is a schematic diagram of another base matrix according to an embodiment of the present invention;

3b-4 is a schematic diagram of another base matrix according to an embodiment of the present invention;

FIG. 3b is a schematic diagram of another base matrix according to an embodiment of the present disclosure;

3b-6 is a schematic diagram of another base matrix according to an embodiment of the present invention;

3b-7 is a schematic diagram of another base matrix according to an embodiment of the present invention;

3b-8 is a schematic diagram of another base matrix according to an embodiment of the present invention;

4 is a schematic diagram of performance provided by an embodiment of the present invention;

FIG. 5 is a schematic flowchart of information processing according to an embodiment of the present disclosure;

FIG. 6 is a schematic flowchart of information processing according to an embodiment of the present disclosure;

FIG. 7 is a schematic structural diagram of a communication apparatus according to an embodiment of the present invention;

FIG. 8 is a schematic structural diagram of a system according to an embodiment of the present invention.

Detailed ways

To facilitate understanding, some of the terms related to this application are described below.

In the present application, the terms "network" and "system" are often used interchangeably, and "device" and "device" are often used interchangeably, and "information" and "data" are often used interchangeably, but those skilled in the art can understand the meaning. . The "communication device" may be a chip (such as a baseband chip, or a data signal processing chip, or a general purpose chip, etc.), a terminal, a base station, or other network device. A terminal is a device having a communication function, and may include a handheld device having a wireless communication function, an in-vehicle device, a wearable device, a computing device, or other processing device connected to a wireless modem. Terminals can be called different names in different networks, such as: user equipment, mobile stations, subscriber units, stations, cellular phones, personal digital assistants, wireless modems, wireless communication devices, handheld devices, laptops, cordless phones, Wireless local loop station, etc. For convenience of description, the present application is simply referred to as a terminal. A base station (BS), also referred to as a base station device, is a device deployed in a radio access network to provide wireless communication functions. The name of a base station may be different in different wireless access systems, for example, in a Universal Mobile Telecommunications System (UMTS) network, a base station is called a Node B, but in an LTE network. A base station is called an evolved Node B (eNB or eNodeB). A base station in a new radio (NR) network is called a transmission reception point (TRP) or a next generation node B (generation node B, gNB). Base stations in other various evolved networks may also adopt other names. The invention is not limited to this.

The technical solutions in the embodiments of the present invention will be described below with reference to the accompanying drawings in the embodiments of the present invention.

The LDPC code can usually be represented by a parity check matrix H. In an implementation manner, the check matrix of the LDPC code may be simplified by using a base graph, where each element represents a Z*Z extension matrix. Z is a positive integer, which can also be called a lifting factor, and sometimes called lifting size or lifting factor. The position of the zero element and the non-zero element can be indicated by the base map. The non-zero elements in the base map correspond to the offset values. The parity check matrix H of the LDPC code can be obtained by a base graph and a shift value. The base map can usually include m*n matrix elements, which can be represented by a matrix of m rows and n columns. The value of the matrix element is 0 or 1, and the element with a value of 0 is sometimes called a zero element. , indicating that the element can be replaced by Z*Z's zero matrix. An element with a value of 1, sometimes referred to as a non-zero element, indicates that the element can be a cyclic permutation matrix of Z*Z (circulant permutation) Matrix) replacement. That is, each matrix element represents an all-zero matrix or a cyclic permutation matrix. As shown by 10a in Fig. 1, an exemplary m=7, n=17 elements in the base map of the LDPC code having the QC structure. It should be noted that, in this paper, the row number and column number of the base map and the matrix are numbered from 0, for convenience of explanation, for example, the 0th column is represented as the base map and the first column of the matrix, the first The columns are represented as the base and the second column of the matrix, the 0th row represents the base map and the first row of the matrix, the first row is represented as the base map and the second row of the matrix, and so on.

It can be understood that the line number and column number can also be numbered from 1, and the corresponding line number and column number are incremented by 1 on the basis of the line number and column number shown in this article, for example, if the line number or column number is from 1 Starting with the number, the first column represents the base column and the first column of the matrix, the second column represents the base map and the second column of the matrix, the first row represents the first row representing the base map and the matrix, and the second row represents the base map. And the second line of the matrix, and so on.

In another implementation, a base matrix of m rows and n columns, sometimes referred to as a PCM (parity check matrix), may be defined. For example, a matrix defined by any of the matrices as shown in FIGS. 3b-1 to 3b-8, or a partial row and column in the matrix as shown in FIGS. 3b-1 to 3b-8 is defined. In the base matrix, each element corresponds to the position of each element in the base map, and the zero elements in the base map are unchanged in the base matrix. In the base matrix, -1 or a null value "null" may be used to represent a zero element, and a non-zero element having a value of the i-th row and the j-th column in the base map is unchanged in the base matrix, and is represented as V _i,j . Or a value defined by the system based matrix V _{i, j} predefined, non-zero elements may be offset by the group values in FIG P _{i, j} obtained by calculation, and spreading factor Z V _{i, j.} P _i,j may be an offset value defined relative to a predetermined or specific spreading factor Z. P _i,j can be obtained based on Z and V _i,j , and in one implementation P _i,j and V _i,j satisfy the following relationship: P _i,j =mod(V _i,j ,Z). i and j represent the row index (row number) and column index (column number) of the element to indicate the position of the element in the matrix.

In the embodiment of the present application, the base matrix is sometimes referred to as an offset matrix of the base map. The base matrix can be obtained from the base map and the offset values. If the element value of the i-th row and the j-th column in the base map is 1, and the offset value is P _i,j , P _i,j is an integer greater than or equal to 0, the value of the j-th column of the i-th row is 1 The elements of the element can be replaced by a cyclic permutation matrix of Z*Z corresponding to P _i,j . The cyclic permutation matrix may also sometimes be referred to as a shift matrix. The cyclic permutation matrix can be obtained by cyclically shifting the unit matrix of Z*Z by P _{i, j} times to the right or left. In one implementation, P _i,j = mod(V _i,j ,Z). V _i,j is the value of the base matrix corresponding to the non-zero element in the base map. Sometimes it can also be called an offset value, or a cyclic offset value, or an offset coefficient. For example, V _i,j may be an offset value corresponding to the maximum spreading factor Z _max . The Z _max pair is the maximum value in the set of values of Z. If the element value of the i-th row and the j-th column in the base map is 0, the element with a value of 0 can be replaced with the all-zero matrix of Z*Z. An element with a value of 0 in the base map is replaced by an all-zero matrix of Z*Z, and an element having a value of 1 is replaced with a cyclic permutation matrix of Z*Z corresponding to the offset value P _i,j , and an LDPC code can be obtained. The parity check matrix. Z is a positive integer, which can also be called a lifting factor, and sometimes called lifting size or lifting factor. It can be determined according to the code block size supported by the system and the size of the information data. It can be seen that the size of the parity check matrix H is (m*Z)*(n*Z). For example, if the spreading factor Z=4, then each zero element is replaced by a 4*4 size all-zero matrix 11a. If P _2,3 = 2, the non-zero elements of the second row and third column are 4*4. The cyclic permutation matrix 11d is replaced by a quadrature cyclic shift of the 4*4 unit matrix 11b. If P _2,4 =0, the non-zero elements of the second row and the fourth column are replaced by the unit matrix. 11b replacement. It should be noted that the description herein is merely illustrative and not limiting.

Since P _i,j can be obtained based on the spreading factor Z, for elements with a value of 1 at the same position, different spreading factors Z may have different P _i,j . As shown by 10b in Fig. 1, a base matrix corresponding to the base map 10a is shown. For example, the value of the first row and the third column in the base map 10a is 1, which corresponds to the offset value V _i,j of the first row and the third column in the base matrix 10b. The value of P _i,j can be known using the formula P _i,j = mod(V _i,j ,Z). Therefore, the elements of the first row and the third column can be replaced by a cyclic permutation matrix obtained by cyclically shifting the unit matrix of Z*Z by P _{i, j} times to the right or left.

Generally, the base map or the base matrix of the LDPC code may further include a p-column built-in puncture bit string, and p may be an integer of 0 to 2. These columns participate in encoding, but the system bits corresponding to the encoding are not When transmitted, the code rate of the LDPC code base matrix satisfies R=(nm)/(np). Taking the base map 10a as an example, if there are 2 columns of built-in punch bit columns, the code rate is (17-7) / (17-2) = 0.667, which is approximately 2/3.

The LDPC code used in the wireless communication system is a QC-LDPC code, and the check bit portion has a double diagonal structure or a raptor-like structure, which can simplify coding and support incremental redundant hybrid retransmission. In the decoder of the QC-LDPC code, a QC-LDPC shift network (QSN), a Banyan network or a Benes network is generally used to implement cyclic shift of information.

For a QC-LDPC code having a raptor-like structure, the matrix size of the base map is m rows and n columns, and may include five sub-matrices A, B, C, D, and E, wherein the weight of the matrix is determined by a non-zero element The number of rows (row weight) refers to the number of non-zero elements included in a row, and the weight of the column (column weight) refers to the number of non-zero elements included in a column. As shown in 200 in Figure 2, where:

Submatrix A is a matrix of m _A rows and n _A columns, which may be of size M _A *n _A , where each column corresponds to Z systematic bits in the LDPC code, and system bits are sometimes referred to as information bits.

The sub-matrix B is a square matrix of m _A rows and m _A columns, and its size may be m _A *m _A , and each column corresponds to Z parity bits in the LDPC code. The sub-matrix B includes a sub-matrix B' with a double-diagonal structure and a matrix column with a weight of 3 (referred to as a 3-column re-column), wherein the matrix column with a column weight of 3 may be located before the sub-matrix B', as shown in FIG. 20a; the sub-matrix B may further include one or more columns of columns having a column weight of 1 (referred to as a single column of re-columns). For example, one possible implementation is as shown by 20b or 20c in FIG.

A matrix that is typically generated based on sub-matrices A and B can be referred to as a core matrix and can be used to support high code rate encoding.

Submatrix C is an all-zero matrix with a size of m _A × m _D .

The sub-matrix E is an identity matrix having a size of m _D × m _D .

The submatrix D has a size of m _D × (n _A + m _A ) and can generally be used to generate a low bit rate check bit.

Since the structures of the sub-matrices C and E are relatively determined, the structure of the two sub-matrices A, B and D is one of the factors influencing the coding performance of the LDPC code.

It can be understood that the above description of the structure of the base/base matrix is described from the principle. It can be understood that the division of the sub-matrices A, B, C, D, E is only to help understand from a principle perspective. The division of the sub-matrices A, B, C, D, E may not be limited to the above division manner. In an implementation manner, since C is an all-zero matrix and E is a unit matrix, the LDPC matrix can be simplified, and it is not necessary to use the complete A, B, C, D, E to represent the LDPC. matrix. For example, the sub-matrices A, B, and D may be used to simplify the representation of the LDPC matrix, or the sub-matrices A, B, C, and D may be used to represent the LDPC matrix, or the sub-matrices A, B, D, and E may be used to represent the LDPC matrix. In another implementation manner, since the sub-matrix B includes one or more columns of single column weights, the structure is also relatively fixed for one column of the sub-matrix B or the column portion of the single column, so the column or single column re-column may not be used. To represent the LDPC matrix. For example, when used to represent an LDPC matrix, a sub-matrix A, a partial column in the sub-matrix B, and a corresponding column in the sub-matrix D may be used. When encoding by using the LDPC matrix of the raptor-like structure, a possible implementation manner is that the matrix of the sub-matrices A and B, that is, the core matrix, can be encoded to obtain the parity bits corresponding to the sub-matrix B. The entire matrix is then encoded to obtain parity bits corresponding to the E portion of the sub-matrix. Since the sub-matrix B can include the sub-matrix B' of the double-diagonal structure and a single-column re-column, the parity bits corresponding to the double-diagonal structure can be obtained first in the encoding, and the parity bits corresponding to the single-column re-column can be obtained.

An example way of encoding is given below. Suppose that the core matrix part composed of sub-matrices A and B is H _core , and the last row and the last column are removed from the H _core , that is, the single-column re-column and the row where the non-zero elements of the column are located are obtained, and the obtained matrix portion is H _core-dual , parity part H _core-dual expressed as _{H e = [H e1 H e2} ], H e1 is 3 restated, H _e2 dual diagonal structure. According to the LDPC code matrix definition, H _core-dual ·[S P _e ] ^T =0, where S is an input sequence, represented by a vector of information bits, P _e is a vector of check bits, and [S P _e ] ^T represents The matrix consists of input sequences S and P _e transposed. Can be calculated according to the input sequence S and the H _core-dual H _core-dual check bit corresponding to the input sequence S includes all information bits; then according to obtain H _core-dual check bit corresponding to an input sequence and calculates S Obtaining the parity bits corresponding to the single column re-column in the sub-matrix B, in this case, all the parity bits corresponding to the sub-matrix B can be obtained; and then according to the input sequence S and the parity bits corresponding to the sub-matrix B, the sub-matrix D is partially encoded. The check bits corresponding to the sub-matrix E, thus obtaining all information bits and all check bits, these bits constitute the encoded sequence, that is, an LDPC code sequence.

Alternatively, the LDPC code encoding may also include shortening and puncturing operations. Both truncated bits and punctured bits are not transmitted.

Among them, the truncation is generally truncated from the last bit of the information bit, and can be truncated in different ways. For example, the truncated number of bits s ₀ can be set to the last s ₀ bits in the input sequence S to obtain the input sequence S', such as set to 0 or null, or some other value, and then through the LDPC matrix pair The input sequence S' is encoded. For example, the last (s ₀ mod Z) bits in the input sequence S may be set to the known bits to obtain the input sequence S', if set to 0 or null, or some other value. Put the last in submatrix A

The column deletion results in the LDPC matrix H', the input sequence S' is encoded using the LDPC matrix H', or the last in the submatrix A

The column does not participate in the encoding of the input sequence S'. After the encoding is completed, the truncated bits are not sent.

The punching may be a punching bit built in the input sequence or a punching bit. When puncturing the parity bit, the last bit of the parity bit is usually punctured. Of course, the puncturing may be performed according to the preset puncturing order of the system. A possible implementation manner is that the input sequence is first encoded, and then the last p bits in the parity bit are selected according to the number of bits p to be punctured, or p bits are selected according to the system's preset puncturing order. p bits are not sent. In another possible implementation manner, the p columns of the matrix corresponding to the punctured bits and the p rows of the non-zero elements in the columns may also be determined, and the rows and columns do not participate in the coding, and the corresponding school is not generated. Check the bit.

It should be noted that the coding mode is only an example here, and other coding methods known to those skilled in the art may be used based on the present disclosure to provide a base map and/or a base matrix, which is not limited in this application. The decoding involved in the present application may be a plurality of decoding methods, for example, a min-sum (MS) decoding method or a belief propagation decoding method. The MS decoding method is sometimes also referred to as a Flood MS decoding method. For example, the input sequence is initialized and iteratively processed, the hard decision detection is performed after the iteration, and the hard decision result is verified. If the decoding result conforms to the check equation, the decoding is successful, the iteration is terminated, and the decision result is output. . If the check equation is not met, iterative processing is performed again within the maximum number of iterations. If the maximum number of iterations is reached and the verification fails, the decoding fails. It will be understood that those skilled in the art can understand the principle of MS decoding and will not be described in detail herein.

It should be noted that the decoding mode is only an example. For the base map and/or the base matrix provided by the present application, other decoding methods known to those skilled in the art may be used. The decoding method is not limited in this application.

The LDPC code can usually be obtained by designing a base map or a base matrix. For example, a density evolution method may be applied to the base map or the base matrix to determine an upper performance limit of the LDPC code, and an error leveling layer of the LDPC code is determined according to the offset value in the base matrix. By designing the base or base matrix, coding or decoding performance can be improved, and error leveling can be reduced. The code length in the wireless communication system is flexible, for example, it can be 2560 bits, 38400 bits, etc., FIG. 3a is an example of a base diagram of an LDPC code, and FIG. 3b-1 to FIG. 3b-8 are base matrixes of the base diagram of FIG. 3a. An example that meets the performance needs of multiple block lengths. For convenience of explanation and understanding, column numbers and line numbers are respectively shown on the uppermost side and the leftmost side in 3a and 3b-1 to 3b-8 in the drawing.

Figure 4 shows the performance of the LDPC code shown in Figure 3a. In the performance diagram shown in Figure 4, based on the performance curve of the matrix coding shown in Figure 3b-1 to Figure 3b-8, the abscissa represents the information bit sequence. The length is in bits, and the ordinate is the symbol-to-noise ratio (Es/N0) required to reach the corresponding BLER. The two lines of each code rate correspond to the BLER of 0.01 and 0.0001, respectively. At the same code rate, 0.01 corresponds to the upper curve and 0.0001 corresponds to the lower curve. Smooth curves, indicating that the matrix has superior performance over different block lengths

Fig. 3a shows an example of a base map of an LDPC code, in which the uppermost row 0 to 51 (i.e., columns 0 to 51) represents the column number, and the leftmost column 0 to 41 (i.e., rows 0 to 41) represents the row number. That is, the size of the base map is 42 rows and 52 columns.

In one implementation, portions of sub-matrix A and sub-matrix B can be viewed as the core matrix portion of the base map of the LDPC code, which can be used for high bit rate encoding. A matrix of 7 rows and 17 columns is constructed, and a matrix of 7 rows and 17 columns in the upper left corner of the base diagram shown in FIG. 3a can be regarded as a core matrix portion of the base map. The core matrix portion may include a sub-matrix A and a sub-matrix B. The sub-matrix A is a matrix of 7 rows and 10 columns composed of the 0th row to the 6th row in Fig. 3a, and the 0th column to the 9th column. The sub-matrix B is a matrix of 7 rows and 7 columns composed of the 0th row to the 6th row in Fig. 3a, and the 10th column to the 16th column.

In another implementation, a matrix consisting of 7 rows and 14 columns, or 7 rows and 15 columns, or 7 rows and 16 columns in the upper left corner of the base map shown in FIG. 3a can be regarded as a core portion, that is, the base shown in FIG. 3a. The 0th to 6th rows of the figure, the matrix of the 0th column to the 13th column, or the matrix of the 0th to 6th rows, the 0th column to the 14th column, or the 0th to 6th rows, the 0th column to the 15th A matrix of columns. Correspondingly, the corresponding position portion of the matrix shown in FIG. 3b-1 to FIG. 3b-8 and the base map can also be regarded as a core portion.

In an implementation manner, the sub-matrix A may include one or more columns of built-in punctured bit columns. For example, it may include two columns of built-in punctured bit columns. After puncturing, the core matrix can support a code rate of 2/. 3. The sub-matrix B may include one column and three columns of re-columns, that is, the first column of the sub-matrix B (the 10th column of the core matrix) has a column weight of 3, and the second column of the sub-matrix B (11 columns of the core matrix) The column weight is 5, the second to fourth columns of the sub-matrix B (12 to 13 columns of the core matrix), the 0th to 3rd behaviors are double-diagonal structures, and the third and fourth columns (12 to 13 columns of the core matrix) The column weight is 2, and the sub-matrix B also includes 3 columns of single column weights (14 to 16 columns of the core matrix).

In one implementation, the sub-matrix A may correspond to systematic bits, sometimes referred to as information bits, having a size of m _A rows and 10 columns, where m _A = 5, from the 0th row to the 4th in the base map 30a The elements of the rows and columns 0 through 9;

In one implementation, the sub-matrix B may correspond to a parity bit, which is m _A rows and m _A columns, and is composed of elements of the 0th row to the 6th row and the 10th column to the 16th column in the base map 30a. .

In order to obtain a flexible code rate, sub-matrices C, sub-matrices D, and sub-matrices E of corresponding sizes may be added based on the core matrix to obtain different code rates. Since the sub-matrix C is an all-zero matrix, the sub-matrix is an identity matrix, and its size is mainly determined according to the code rate, and the structure is relatively fixed. The main factors affecting the performance of the compiled code are the core matrix and the sub-matrix D part. Adding rows and columns on the basis of the core matrix to form corresponding C, D and E parts can obtain different code rates.

The number of columns m _D of the sub-matrix D is the sum of the number of columns of the sub-matrices A and B, and the number of rows thereof is mainly related to the code rate. Taking the base map 30a as an example, the number of columns of the sub-matrix D is 17 columns. If the code rate supported by the LDPC code is R _m , the size of the base or base matrix is m rows and n columns, where n=n _A /R _m +p,m=nn _A =n _A /R _m +pn _A. Where P is the built-in punch column. According to the formula, the code rate supported by the LDPC code can be known. If the lowest code rate R _m = 1/3, the number of built-in punch columns is p=2, taking the base map 30a as an example, then n=52, m=42, and the number of rows m _{D of the} sub-matrix D may be mm _A = 42-7=35, so 0≤m _D ≤35.

Taking the base map 30a as an example, the sub-matrix D may include the m _D rows in the 7th to 41st lines of the base map 30a.

In the present application, if there are at most one non-zero element in the same column of two adjacent rows in the base map, the two rows are orthogonal to each other. If there are only one non-zero element in the same column except for a partial column in the adjacent two rows in the base map, the adjacent two rows are quasi-orthogonal. For example, for two adjacent rows, except for the column other than the built-in punctured bit column, which has only one non-zero element, the adjacent two rows can be considered to be quasi-orthogonal.

Lines 7 to 41 of the base map 30a may include a plurality of rows of quasi-orthogonal structures and at least two rows of orthogonal structures. For example, the 32rd line and the 33rd line in the base map 30a are orthogonal, the 34th line is orthogonal to the 35th line, and the 36th, 37th, and 38th lines are orthogonal. For any of the adjacent columns except for the built-in punctured bit column, there is at most one non-zero element in the same column, which is quasi-orthogonal. If the built-in punctured bit column is included, and any one column has at most one non-zero element, it conforms to the orthogonal structure.

If m _D =15, the sub-matrix D in the LDPC code base map has a size of 15 rows and 17 columns, and may be composed of a matrix of the 7th to 21st rows and the 0th column to the 16th column of the base map 30a, corresponding to the LDPC code. The supported code rate can be obtained by referring to the above calculation formula.

The sub-matrix E is an element matrix of 15 rows and 15 columns, and the sub-matrix C is an all-zero matrix of 7 rows and 15 columns;

If m _D =19, the sub-matrix D in the LDPC code base map has a size of 19 rows and 17 columns, and may be composed of a matrix of the 7th to 25th rows and the 0th column to the 16th column of the base map 30a, corresponding to the LDPC code. The supported code rate can be obtained by referring to the above calculation formula. At this code rate, the base map of the LDPC code corresponds to the matrix portion of the 0th row to the 25th row, the 0th column to the 16th column of the base map 30a, wherein the sub-matrix E is an element matrix of 16 rows and 16 columns, Submatrix C is an all-zero matrix of 7 rows and 16 columns. And so on, not elaborated one by one.

In one design, row/column swapping may be performed on the base map and/or base matrix, that is, row swapping, or column swapping, or row swapping and column swapping. The row/column swap operation does not change the row weight and the column weight, and the number of non-zero elements does not change. Therefore, the base and/or base matrix after row/column swap has limited impact on system performance. That is to say, as a whole, the impact on system performance is acceptable, within tolerance, for example, performance may fall within the allowable range for certain scenarios or within certain ranges, but in some scenarios or certain ranges Within the performance, the performance has improved, and overall it has little effect on performance.

For example, the 34th row and the 36th row of the base map 30a can be exchanged, and the 44th column and the 45th column can be exchanged. For another example, the sub-matrix D includes m _D rows in the matrix F. The m _D rows may not be exchanged in rows, or one or more rows may be exchanged between rows, and the sub-matrix E is still a diagonal structure, and no row is performed. The column swap, for example, performs row swapping of the 27th and 29th rows of the matrix F, the submatrix D includes the m _D rows in the matrix F, and the submatrix E is still a diagonal structure. It can be understood that if the base map or the base matrix includes the sub-matrix D, when the columns of the core matrix are exchanged, the columns in the corresponding sub-matrix D also need to be exchanged.

The matrix shown in Fig. 3b-1 to Fig. 3b-8 is a design example of a plurality of base matrices of the base map 30a, respectively. Wherein, the non-zero elements of the i-th row and the j-th column in the base map 30a are invariant in the matrix shown in FIGS. 3b-1 to 3b-8, and the value is the offset value V _i,j , and the zero element is biased The shift matrix is represented by -1 or null. Wherein the sub-matrix D in the base portion corresponding matrix line 7 may include any of which to the matrix _D m in the row lines 41 may be different from the value selected in accordance with bit rate _D m. It can be understood that if the base map is a matrix after row/column transformation with respect to the base map 30a, the base matrix is also a matrix corresponding to any one of the row/column transforms.

In a possible design, since the structure of the sub-matrices C and E is relatively fixed, the sub-matrices A, B, and D can be used to represent the base/base matrix of the LDPC, that is, FIG. 3a or FIG. 3b-1 to FIG. 3b. The matrix of -8 shows 0 to 41 rows, 0 to 16 columns.

In one possible design, since the structures of columns 14 to 51 are relatively fixed, a matrix of 0 to 41 rows and 0 to 13 columns in the matrix shown in FIG. 3a or FIG. 3b-1 to FIG. 3b-8 may be used. Simplify the base/base matrix representing LDPC.

In one possible design, 0 to 41 rows, 0 to 13 columns, and partial columns of columns 14 to 51 in the matrix shown in FIG. 3a or FIG. 3b-1 to FIG. 3b-8 may be used to represent LDPC. Basemap/base matrix. For example, 0 to 41 rows, 0 to 15 columns in the matrix shown in FIG. 3a or FIG. 3b-1 to FIG. 3b-8 may be used to represent the base/base matrix of the LDPC, or 0 to 41 rows, 0 to 14 may be used. Columns represent the base/base matrix of the LDPC.

In a possible design, the base matrix of the LDPC code may include the 0th to 6th rows and the 0th to 16th columns of any of the matrixes shown in FIG. 3b-1 to FIG. 3b-8. In this case, FIG. 3b-1 A matrix composed of the 0th to 6th rows and the 0th to 16th columns of the matrix shown in FIGS. 3b-8 can be used as a core portion of the base matrix. In this design, the structure of the other part of the base matrix of the LDPC code, for example, the matrix C, D, E is not limited, for example, any of the structures shown in FIG. 3b-1 to FIG. 3b-8 may be used. Other matrix designs can be used.

In another possible design, the base matrix of the LDPC code may include the 0th to (m-1)th rows and the 0th to the (n-) in any of the matrixes shown in FIG. 3b-1 to FIG. 3b-8. 1) A matrix composed of columns, where 7 ≤ m ≤ 42, m is an integer, 18 ≤ n ≤ 52, and n is an integer.

In the present design, the structure of other parts of the base matrix of the LDPC code is not limited. For example, any of the structures shown in FIG. 3b-1 to FIG. 3b-8 may be employed, and other matrix designs may be employed.

In yet another possible design, the base matrix of the LDPC code may include the 0th to 6th rows and the 0th to 16th of any of the matrices 3b-1 to 3b-8 shown in FIGS. 3b-1 to 3b-8. A partial column in the column. For example, the core portions (lines 0 to 6 and columns 0 to 16) of the matrix shown in Figures 3b-1 through 3b-8 can be shortened and/or punctured. In one implementation, the base matrix of the LDPC code may not include columns corresponding to truncated and/or punctured bits.

In the present design, the other portions of the base matrix of the LDPC code are not limited. For example, the structure shown in FIG. 3b-1 to FIG. 3b-8 may be referred to, and other configurations may be employed.

In yet another possible design, the base matrix of the LDPC code may include the 0th to (m-1)th rows and the 0th to (n-) of any of the matrixes shown in FIG. 3b-1 to FIG. 3b-8. 1) A matrix composed of partial columns in a column, where 7 ≤ m ≤ 42, m is an integer, 18 ≤ n ≤ 52, and n is an integer. For example, the 0th to (m-1)th rows and the 0th to (n-1)th columns in any of the matrices shown in FIGS. 3b-1 to 3b-8 may be shortened and/or punctured. (puncturing). In one implementation, the base matrix of the LDPC code may not include columns corresponding to truncated and/or punctured bits. In the present design, the other portions of the base matrix of the LDPC code are not limited. For example, the structure shown in FIG. 3b-1 to FIG. 3b-8 may be referred to, and other configurations may be employed.

In one implementation, the truncating operation may be truncating the information bits. For example, taking any matrix shown in FIG. 3b-1 to FIG. 3b-8 as an example, for one or more columns of 0 to 9 columns, the base matrix of the LDPC code may not include FIG. 3b-1. One or more columns truncated in the matrix shown in Figures 3b-8. For example, if the ninth column is truncated, the base matrix of the LDPC code may include columns 0 to 8 and columns 10 to 16 of any of the matrixes of FIGS. 3b-1 to 3b-8. For lines 0 to 6, and columns 0 to 8 and columns 10 to 16.

In another implementation, the puncturing may be puncturing the parity bit. For example, one or more columns in the 10th to 16th columns are punched by taking any of the matrices shown in FIG. 3b-1 to FIG. 3b-8 as an example. Then, the base matrix of the LDPC code may not include one or more columns that are perforated in the matrix shown in FIGS. 3b-1 to 3b-8. For example, if the 16th column is punctured, the base matrix of the LDPC code may include columns 0 to 15 of any of the matrixes 3b-1 to 3b-8.

Different spreading factors Z are designed for the LDPC code, which can support information bit sequences of different lengths. In one possible design, different base factors can be used for different spreading factors to achieve better performance. For example, the expansion factor Z = a × 2 ^j , 0 ^≤ j < 7, a ∈ {2, 3, 5, 7, 9, 11, 13, 15}. Table 1 shows a set of extension factors that may be supported {2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,18,20,22,24, 26, 28, 30, 32, 36, 40, 44, 48, 52, 56, 60, 64, 72, 80, 88, 96, 104, 112, 120, 128, 144, 160, 176, 192, 208, 224, 240, 256, 288, 320, 352, 384}, wherein each cell represents, in addition to the top row and the leftmost column, respectively The values of a and j correspond to the value of Z, for example, a column of a=2, and the row of j=1, Z=4, and for example, a=11 and j=3, Z=88. And so on, no longer repeat them.

Table 1

Z	a=2	a=3	a=5	a=7	a=9	a=11	a=13	a=15
j=0	2	3	5	7	9	11	13	15
j=1	4	6	10	14	18	twenty two	26	30
j=2	8	12	20	28	36	44	52	60
j=3	16	twenty four	40	56	72	88	104	120
j=4	32	48	80	112	144	176	208	240
j=5	64	96	160	224	288	352
j=6	128	192	320
j=7	256	384

It can be understood that Table 1 is only a form of expressing the expansion factor. When the actual product is implemented, it is not limited to the form of Table 1, and can be expressed by other forms.

For example, for a value of each a, it corresponds to a set of expansion factors. The set of spreading factors can be identified by a group index, for example, Table 1' gives another representation of the spreading factor.

Table 1'

Since the set of spreading factors supported by the base map can be all of the spreading factors in Table 1 or Table 1', it can also be a part of the spreading factor. For example, it can be {24, 26, 28, 30, 32, 36, 40, 44, 48, 52, 56, 60, 64, 72, 80, 88, 96, 104, 112, 120, 128, 144, 160, 176, 192, 208, 224, 240, 256, 288, 320, 352, 384}, that is, Z is greater than or equal to 24. For another example, one or more of {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 18, 20, 22} The union of 24,26,28,30,32,36,40,44,48,52,56,60,64,72,80,88,96,104,112,120,128,144,160,176,192,208,224,240,256,288,320,352,384}. It should be noted that this is only an example. The set of spreading factors supported by the base map can be divided into different subsets according to the value of a. For example, a=2, the subset of the spreading factor Z may include one or more of {2, 4, 8, 16, 32, 64, 128, 256}, and for example, a=3, the subset of the spreading factor Z may include { One or more of 3, 6, 12, 24, 48, 96, 192, 384}, and so on.

The set of spreading factors supported by the base map can be divided according to different values of a to determine the corresponding base matrix:

If a=2, or the spreading factor Z takes one of {2, 4, 8, 16, 32, 64, 128, 256}, the base matrix may include the number in the matrix shown in FIG. 3b-1 to FIG. 0 to 6 rows and 0 to 16 columns, or the base matrix includes the 0th to (m-1)th rows and the 0th to (n-1)th columns in the matrix shown in FIG. 3b-1, where 7≤m≤ 42, m is an integer, 17 ≤ n ≤ 52, n is an integer; or, the base matrix includes the 0th to (m-1)th rows of the matrix shown in FIG. 3b-1 and the 0th to (n-1)th columns Part of the column, where 7 ≤ m ≤ 42, m is an integer, 17 ≤ n ≤ 52, and n is an integer. .

If a=3, or the spreading factor Z takes one of {3, 6, 12, 24, 48, 96, 192, 384}, the base matrix may include the 0th to 6th rows and the 0th to 16th of the matrix 3b-2. Column, or, the base matrix includes the 0th to (m-1)th rows and the 0th to (n-1)th columns in the matrix shown in FIG. 3b-2, where 7≤m≤42, m is an integer, 17≤n ≤ 52, n is an integer; or, the base matrix includes the 0th to (m-1)th rows of the matrix shown in FIG. 3b-2 and the partial columns in the 0th to (n-1)th columns, where 7≤m≤42 m is an integer, 17≤n≤52, and n is an integer.

For example, the base matrix PCM includes lines 0 to 41 in FIG. 3b-2, and columns 0 to 13, or columns 0 to 14, or columns 0 to 15.

If a=5, or the spreading factor Z takes one of {5, 10, 20, 40, 80, 160, 320}, the base matrix may include the 0th to 6th rows and the 0th to 16th columns in the matrix 3b-3, Alternatively, the base matrix includes the 0th to (m-1)th rows and the 0th to (n-1)th columns in the matrix shown in FIG. 3b-3, where 7≤m≤42, m is an integer, 17≤n≤52 , n is an integer; or, the base matrix includes the 0th to (m-1)th rows of the matrix shown in FIG. 3b-1 and the partial columns in the 0th to (n-1)th columns, where 7≤m≤42,m Is an integer, 17 ≤ n ≤ 52, and n is an integer.

If a=7, or the spreading factor Z takes one of {7, 14, 28, 56, 112, 224}, the base matrix may include the 0th to 6th rows and the 0th to 16th columns in the matrix 3b-4, or The base matrix includes the 0th to (m-1)th rows and the 0th to (n-1)th columns in the matrix shown in FIG. 3b-4, where 7≤m≤42, m is an integer, 17≤n≤52,n Is an integer; or, the base matrix includes the 0th to (m-1)th rows of the matrix shown in FIG. 3b-4 and the partial columns in the 0th to (n-1)th columns, where 7≤m≤42, m is an integer , 17 ≤ n ≤ 52, and n is an integer.

If a=9, or the spreading factor Z takes one of {9, 18, 36, 72, 144, 288}, the base matrix may include the 0th to 6th rows and the 0th to 16th columns in the matrix 3b-5, or The base matrix includes the 0th to (m-1)th rows and the 0th to (n-1)th columns in the matrix shown in FIG. 3b-5, where 7≤m≤42, m is an integer, 17≤n≤52,n An integer; or, the base matrix includes the 0th to (m-1)th rows of the matrix shown in FIG. 3b-5 and the partial columns in the 0th to (n-1)th columns, where 7≤m≤42, m is an integer , 17 ≤ n ≤ 52, and n is an integer.

If a=11, or the spreading factor Z takes one of {11, 22, 44, 88, 176, 352}, the base matrix may include the 0th to 6th rows and the 0th to 16th columns in the matrix 3b-6, or The base matrix includes the 0th to (m-1)th rows and the 0th to (n-1)th columns in the matrix shown in FIG. 3b-6, where 7≤m≤42, m is an integer, 17≤n≤52,n Is an integer; or, the base matrix includes the 0th to (m-1)th rows of the matrix shown in FIG. 3b-6 and the partial columns in the 0th to (n-1)th columns, where 7≤m≤42, m is an integer , 17 ≤ n ≤ 52, and n is an integer.

If a=13, or the spreading factor Z takes one of {13, 26, 52, 104, 208}, the base matrix may include the 0th to 6th rows and the 0th to 16th columns in the matrix 3b-7, or the base matrix Including the 0th to (m-1)th rows and the 0th to (n-1)th columns in the matrix shown in FIG. 3b-7, where 7≤m≤42, m is an integer, 17≤n≤52, n is an integer Or, the base matrix includes the 0th to (m-1)th rows of the matrix shown in FIG. 3b-7 and the partial columns in the 0th to (n-1)th columns, where 7≤m≤42, m is an integer, 17 ≤ n ≤ 52, where n is an integer.

If a=15, or the spreading factor Z takes one of {15, 30, 60, 120, 240}, the base matrix may include the 0th to 6th rows and the 0th to 16th columns in the matrix 3b-8, or the base matrix Including the 0th to (m-1)th rows and the 0th to (n-1)th columns in the matrix shown in Fig. 3b-8, where 7≤m≤42, m is an integer, 17≤n≤52, n is an integer Or, the base matrix includes the 0th to (m-1)th rows of the matrix shown in FIG. 3b-8 and the partial columns in the 0th to (n-1)th columns, where 7≤m≤42, m is an integer, 17 ≤ n ≤ 52, where n is an integer.

Optionally, for a given base matrix of an LDPC code, the offset value Offset _s may be increased or decreased for the offset value of one or more columns of non-zero elements in the matrix, and the system performance is not greatly affected. The compensation values of the non-zero elements in different columns may be the same or different. For example, one or more columns of the matrix may be compensated. The compensation values of different columns may be the same or different, and the application is not limited.

A small impact on system performance means that the impact on system performance is acceptable and within tolerance. For example, performance may be degraded within certain limits for certain scenarios or within certain ranges, but performance may improve over certain scenarios or within certain ranges, and overall has little impact on performance.

For example, increasing or decreasing the compensation value Offset _s for each offset value greater than or equal to 0 in the sth column of any of the matrices 3b-1 to 3b-8 can obtain the compensation matrix Hs of the matrix, where Offset _s is greater than Or an integer equal to 0, where S is an integer greater than or equal to 0 and less than 11. . The offset values Offsets of one or more columns may be the same or different. .

In the performance graph shown in FIG. 4, which is a performance curve based on the matrix coding shown in FIGS. 3b-1 to 3b-2, the abscissa indicates the length of the information bit sequence in units of bits, and the ordinate is a symbol letter required to reach the corresponding BLER. The noise ratio (Es/N0), the two lines of each code rate correspond to the BLER of 0.01 and 0.0001 respectively. At the same code rate, 0.01 corresponds to the upper curve and 0.0001 corresponds to the lower curve. Smooth curves, indicating that the matrix has superior performance over different block lengths

Figures 1 to 3a and Figures 3b-1 to 3b-8 show the base diagrams involved in the LDPC code and the structure of the base matrix. In order to fully illustrate the design of the base map and/or the base matrix in the embodiments of the present invention. The structure of the base matrix can be expressed in other ways that the system can recognize. For example, it can be done in the form of a table, or in other ways.

In one design, the base map of 10a in FIG. 1 is a matrix of 7 rows and 10 columns, and the parameters involved can be represented by Table 2.

Table 2

It can be understood that since the 14th to 16th columns in the base map 10a are columns of single column weight, the positions thereof are relatively fixed or easy to determine, and may not be recorded in Table 2, and the non-zero columns of 14 to 16 columns are recorded by other means. The location of the element.

In one design, taking the base matrix shown in FIG. 3b-1 to FIG. 3b-8 as an example, the parameters involved can be represented by Table 3b-1 to Table 3b-8, respectively.

Table 3b-1

Table 3b-2

Table 3b-3

Table 3b-4

Table 3b-5

Table 3b-6

Table 3b-7

Table 3b-8

It can be understood that the above FIG. 3a, FIG. 3b-1 to 3b-8 and Table 2, Table 3b-1 to Table 3b-8 are for the purpose of helping to understand the design of the base map and the matrix, and the expression thereof is not limited to this. Manifestations. Other possible variations may also be included. For example, Tables 3b-1, 3b-3 to 3b-8 can also be modified with reference to the form of 3b-2'. For columns with relatively fixed structures and offset values of 0, for example, information for elements of columns 14 through 51 may optionally be included or not included in the table to save storage space.

In one design, for a portion of the base or base matrix where the structure is relatively fixed, the position of the non-zero element can be calculated from the position of the row and column, and the positions of these non-zero elements may not be saved. Taking Figure 3b-2 and Table 3b-2 as an example, the 14th column to the 51st column in the matrix shown in Figure 3b-2 are relatively fixed in position, and the offset values V _{i, j} are all 0. The non-zero element calculates the position of its non-zero element. In the above Table 3b-2, the information of the 14th column to the 51st column may not be included. Or the information of the partial columns in the 14th to the 51st is not included. For example, non-zero elements in columns 16 through through 51 and their corresponding offset values are not included. For example, the matrix shown in Figure 3b-2 can also be represented as shown in Table 3b-2' below.

Table 3b-2’

For example, taking FIG. 3b-2 as an example, the offset value V _{i,j of} the 0th line is also 0, and may be obtained by calculation without saving the information of the 0th line.

In one implementation, the parameter "row weight" in Table 2, Table 3b-1 through Table 3b-8, and Table 3b-2' may also be omitted. You can know how many non-zero elements are in the row through a column with a non-zero element, so the row weight is known.

In an implementation manner, for the above Table 2, the parameter values in the column of "non-zero elements in Table 3b-1 to Table 3b-8 and Table 3b-2' may also not be from small to large. The order is as long as the parameter value is indexed to the column in which the non-zero element is located. In addition, for Table 2, the parameter values in the "non-zero element offset value" of Table 3b-1 to Table 3b-8 are not necessarily arranged in the order of the columns, as long as the parameters in the "non-zero element offset value" The value corresponds to the parameter value in the column of "non-zero element".

In one implementation, the different base matrices described above may be combined in one or more tables for representation. For example, the non-zero elements corresponding to different base matrices have the same position, and the row numbers are the same, except that the offset values V _{i, j are} different. Therefore, you can use a table to represent multiple base matrices by using the row number, the column where the non-zero element is located, and the offset values of multiple sets of non-zero elements. For example, two sets of non-zero element offset values can be listed in separate columns, indicated by an index.

In one implementation, the location of the non-zero element can be indicated by the base map, and the parameter "column where the non-zero element is located" in the above table can also be optional.

In one implementation, the parameters shown in FIG. 3a and FIGS. 3b-1 to 3b-8 may also be represented by a column number (column index), a row where the non-zero element is located, and an offset value of the non-zero element. matrix. Optional can include column weights.

In another implementation, the base or base matrix can be regarded as a binary number according to 1 and 0 of each row or column, and saving in a decimal or hexadecimal number can save storage space. For example, in any of the above base maps or base matrices, the positions of the first 14 columns or the first 17 columns of non-zero elements can be stored in hexadecimal numbers. For example, the first 14 columns of the 0th row are 11110010011100, and can be recorded as the 0th row. The position of the non-zero element is 0xF2, 0x70, that is, every 8 columns constitute a hexadecimal number. For the last 2 columns, the corresponding hexadecimal number can be obtained by padding 0 to an integer multiple of 8 bits. Of course, Filling 0 in front of it to reach an integer multiple of 8 bits to get the corresponding hexadecimal number, and so on, and so on.

Figure 5 shows the design of the process of processing data. The process of processing the data may be implemented by a communication device, which may be a base station, terminal or other entity, such as a communication chip, an encoder/decoder, and the like.

In Section 501, the input sequence is obtained. In one implementation, the encoded input sequence may be an information bit sequence, or a padded information bit sequence, or a CRC-added sequence. The information bit sequence is sometimes also referred to as a code block, and may be, for example, an output sequence after code block division of the transport block. In one implementation, the decoded input sequence may be a soft sequence of LDPC codes.

In Section 502, the input sequence is encoded/decoded based on an LDPC matrix; the base matrix of the LDPC matrix may be any of the base matrices in the foregoing examples.

In one implementation, the LDPC matrix can be derived based on the spreading factor Z and the base matrix.

In an implementation manner, related parameters of the LDPC matrix may be saved, and the parameters include one or more of the following:

a) for obtaining parameters in any of the base matrices enumerated in the above implementation manners, the base matrix may be obtained based on the parameters; for example, the parameters may include one or more of the following: row number, row weight, The column number, column weight, position of the non-zero element (such as the row where the non-zero element is located, or the column where the non-zero element is located), the offset value in the base matrix, the non-zero element offset value and the corresponding position, the compensation value , expansion factor Z, base map, code rate, etc.

b) any of the base matrices listed in each of the above implementations;

c) any of the base matrix enumerated in each of the above implementation modes passes through at least one column of compensated compensation matrix Hs;

d) a matrix based on the base matrix or its compensation matrix Hs;

e) A base matrix obtained by row/column transformation based on any of the base matrix or the compensation matrix Hs enumerated in each of the above embodiments.

f) a matrix based on the base matrix after the row/column transformation or the matrix after the compensation matrix Hs.

g) A truncated or punctured matrix based on any of the base matrices or compensation matrices Hs listed in each of the above implementations.

In a possible implementation manner, the input sequence is encoded/decoded based on the low density parity check LDPC matrix, which may be performed in one or more of the following manners in the encoding/decoding process:

i. obtaining a basis matrix based on the above a), based on the obtained base matrix encoding/decoding; or performing row/column exchange based on the obtained base matrix, base matrix encoding/decoding based on row/column transformation, or based on obtained The compensation matrix of the base matrix is encoded/decoded, or encoded/decoded based on the matrix of the matrix matrix obtained by the compensation matrix Hs. Here, based on the base matrix or the compensation matrix Hs encoding/decoding, optionally, it may further include an extended matrix encoding/decoding based on an extension matrix of the base matrix or the compensation matrix Hs, or truncating or playing based on a base matrix or a compensation matrix. Matrix coding/decoding after aperture;

Ii. Encoding/decoding based on b), c) d) or e) preserved basis matrix (save base matrix H or Hs, or saved base matrix H or Hs row/column transformed base matrix), or based on The saved base matrix performs row/column transform, based on base/column transform base matrix encoding/decoding. Here, based on the base matrix or the compensation matrix Hs encoding/decoding, optionally, it may further include an extended matrix encoding/decoding based on an extension matrix of the base matrix or the compensation matrix Hs, or truncating based on a base matrix or a compensation matrix or Matrix coding/decoding after puncturing;

Iii. Encoding/decoding based on d), f) or g).

In Section 503, the encoded/decoded bit sequence is output. In one design, the input sequence c={c ₀ , c ₁ , c ₂ , . . . , c _K-1 } may be encoded to obtain an output sequence d={d ₀ , d ₁ , d ₂ ,. .., d _N-1 }, where K and N are integers greater than 0; the output sequence d includes K ₀ bits in the input sequence c and parity bits in the check sequence w, K ₀ is an integer and ₀ <K 0 ≤K; the check sequence and the input sequence w satisfies the equation c

Where c ^T =[c ₀ , c ₁ , c ₂ , . . . , c _K-1 ] ^T , is a transpose vector of a vector composed of bits in the input sequence c,

a transpose vector of a vector composed of bits in the check sequence w, 0 ^T is a column vector, and all elements have a value of 0; H is a low density parity check LDPC matrix, and the base map of the H includes H _BG and H _{BG, EXT} , where

An all-zero matrix representing the size of m _c ×n _c ,

N _c × n _c represents the size of the matrix, H _BG comprising H _BG2 Kb columns corresponding to information bits in a column, and the H _BG2 to 10 + m _A -1 column 10, H _BG2 number of columns is 10 + m _A column , 4 ≤ m _A ≤ 7, where Kb ∈ {6, 8, 9, 10}; where m _c = 7, 0 ≤ n _c ≤ 35, the number of columns of H _BG2 is equal to 17, or, m _c = 6, 0 ≤n _c ≤36, the number of columns 16 is equal to H _BG2, or, m _c = 5,0≤n _c ≤37, the number of columns 15 is equal to H _BG2, or, m _c = 4,0≤n _c ≤38, The number of columns of H _BG2 is equal to 14.

Figure 6 shows a design for the process of obtaining processed data, which can be used in section 502 of Figure 5.

In Section 601, the expansion factor Z is obtained. In one possible design, the information bit sequence can be padded to obtain an input sequence, the length of the input sequence is K = K _b · Z, Z = K / K _b . In another possible design, the bits of the information bit sequence that need to be punctured or truncated can be padded, that is, the bits that need to be punctured or truncated are replaced with padding bits, so that after encoding, these are encoded. The padding bits can be identified and not sent. For example, Null can be used, or a value of 0, or a value agreed by the system, or a predetermined value can be used as the value of the padding bit. In a design, the bits that need to be punched do not need to be filled, and can be directly destroyed. The padding is done after the information bit sequence.

In one implementation, the spreading factor Z can be determined based on the length K of the input sequence. For example, it may be that in the set of supported extension factors, the smallest Z _{0 is} found as the size of the expansion factor Z, and Kb·Z ₀ ≥K is satisfied. In one possible design, Kb can be the number of columns of information bits in the base matrix of the LDPC code. For the base map 30a, where the number of columns of information bits Kb _max = 10, it is assumed that the set of spreading factors supported by the base map 30a is {24, 26, 28, 30, 32, 36, 40, 44, 48, 52, 56, 60 , 64, 72, 80, 88, 96, 104, 112, 120, 128, 144, 160, 176, 192, 208, 224, 240, 256, 288, 320, 352, 384}. If the length of the input sequence is K = 529 bits, Z is 26, and if the length of the input sequence is K = 5000 bits, Z is 240. It should be noted that the examples are merely examples and are not limited thereto.

For another example, the value of Kb may also vary according to the value of K, but does not exceed the number of information bit columns in the base matrix of the LDPC code. For example, different thresholds can be set for Kb.

In a design as follows: It should be noted that the thresholds 640, 560, 192 here are merely examples. It can also be designed to other values based on system design requirements.

If(K>640), Kb=10;

Elseif (K>560), Kb=9;

Elseif (K>192), Kb=8;

Else Kb=6;end

The spreading factor Z may be determined by the communication device based on the length K of the input sequence or may be obtained by the communication device from other entities such as a processor.

In Section 602, an LDPC matrix is obtained based on the spreading factor and the base matrix. The base matrix is any of the base matrices exemplified in the foregoing embodiments, or a compensation matrix obtained by compensating at least one of any of the base matrices exemplified above, or with respect to any of the base matrices exemplified above or In the compensation matrix, the row order is transformed, or the column order is transformed, or the base matrix in which the row order and the column order are transformed, and the base map includes at least the sub-matrix A and the sub-matrix B. Optionally, the sub-matrix C, the sub-matrix D, and the sub-matrix E are further included in the descriptions of the foregoing embodiments, and details are not described herein again. The base matrix may be obtained based on the base map and the offset value, or may be any one of the base matrices exemplified in the foregoing embodiments, or may be obtained by modifying any of the base matrices enumerated in the foregoing embodiments.

In a possible implementation manner, the corresponding base matrix is determined according to the spreading factor Z, and the base matrix is replaced according to the spreading factor Z to obtain an LDPC matrix.

In one implementation, the LDPC matrix H can be obtained based on the correspondence between the spreading factor and the base matrix. For example, based on the expansion factor Z obtained in Section 601, the corresponding base matrix is determined.

For example, Z is 26, a=13, and the base matrix may include the 0th to 6th rows and the 0th to 16th columns in the matrix shown in FIG. 3b-7, or the base matrix may include the matrix shown in FIG. 3b-7. The 0th to 6th rows and the partial columns in the 0th to 16th columns; further, the base matrix further includes the matrix 0 to m-1 rows and the 0th to n-1th columns, where 7≤m≤42, m is An integer, 17 ≤ n ≤ 52, n is an integer, or the base matrix includes the 0th to m-1th rows and the 0th to the n-1th columns of the matrix shown in FIG. 3b-7, where 7≤m≤42,m In the integer, 17 ≤ n ≤ 52, n is an integer, the rows in the 7th to 41st rows of the matrix shown in Fig. 3b-7, and the columns in the 17th column to the 61st column. The base matrix is replaced according to the spreading factor Z to obtain an LDPC matrix. It should be noted that, here, only the matrix shown by Z=26, a=13, and FIG. 3b-7 is taken as an example. This is merely an example, and the invention is not limited thereto. It can be understood that the base matrix is different when the expansion factors are different.

In a possible implementation manner, the correspondence between the spreading factor and the base matrix can be as shown in Table 4, and the base matrix index corresponding to the spreading factor is determined according to Table 4. A possible design, PCM1 may be a matrix as shown in Figure 3b-1; PCM2 may be a matrix as shown in Figure 3b-2; PCM3 may be a matrix as shown in Figure 3b-3; PCM4 may be as shown 3b-4 matrix; PCM5 may be a matrix as shown in Figure 3b-5; PCM6 may be a matrix as shown in Figure 3b-6; PCM7 may be a matrix as shown in Figure 3b-7; PCM8 may be The matrix shown in Figure 3b-8. This is for the sake of example only and is not intended to be limiting.

Table 4

In another design, the following can also be used:

Further, in a possible design, for the spreading factor Z, the i-th row and the j-th column element P _i,j in the base matrix can satisfy the following relationship:

Wherein, V _i,j may be an offset value of an element of the i-th row and the j-th column in the base matrix of the set of the expansion factor Z, or an i-th row of the base matrix of the largest spreading factor in the set of the expansion factor Z The offset value of the non-zero element of the column.

For example, taking Z as an example, the element P _i,j of the i-th row and the j-th column in the base matrix is satisfied.

Where V _i,j is the offset value of the non-zero element of the ith row j column in PCM7, matrix 3b-7. For Z=13, the offset value V _i,j of the non-zero element of the i-th row and the j-th column in the matrix 3b-7 needs to be modulo Z=13. It should be noted that the present invention is merely an example, and the present invention is not limited thereto.

In Section 603, the input sequence is encoded/decoded based on the LDPC matrix.

In one implementation, the encoded input sequence can be a sequence of information bits. In yet another implementation, the decoded input sequence may be a soft value sequence of the LDPC code, as described in the related description in FIG. When encoding/decoding an input sequence, the LDPC matrix H obtained by extending the Z-base matrix can be used. For each non-zero element P _i,j in the basis matrix, a cyclic permutation matrix h _{i,j of} Z*Z size is determined, where h _i,j is a cyclic permutation matrix obtained by cyclically shifting the unit matrix by P _i,j times Substituting h _i,j for the non-zero element P _i,j , replacing the zero-element in the base matrix H _B with the all-zero matrix of the Z*Z size, thereby obtaining the parity check matrix H;

In a possible implementation manner, the base matrix of the LDPC code may be stored in a memory, and the communication device acquires an LDPC matrix corresponding to the spreading factor Z, thereby encoding/decoding the input sequence.

In a possible implementation manner, since there are multiple base matrices of the LDPC code, the storage according to the matrix structure may occupy a large storage space, and the base map of the LDPC code may be stored in the memory, respectively, row by row or column by column. The offset values of the non-zero elements in each base matrix are saved, and then the LDPC matrix is obtained according to the offset values of the base matrix corresponding to the base map and the spreading factor Z.

In a possible implementation manner, the offset values of non-zero elements in each base matrix may also be saved according to Table 2, Table 3b-1 to Table 3b-8, as a parameter of the LDPC matrix, and the row weight is one column. Optional, that is, the "row weight" column can be optionally saved or not saved. By knowing the number of non-zero elements in a row, it is known how many non-zero elements are in the row. In a possible implementation manner, for the above Table 2, the parameter values in the “column of non-zero elements” in Table 3b-1 to Table 3b-8 may not be arranged in a small to large order. As long as the parameter value is indexed to the column where the non-zero element is located. In addition, for Table 2, the parameter values in the "non-zero element offset value" in Table 3b-1 to Table 3b-8 are not necessarily arranged in the order of the columns, as long as the "non-zero element offset value" The parameter value corresponds to the parameter value in the "column where the non-zero element is located", and the communication device can know that the non-zero element offset value is a non-zero element corresponding to which column. For example, in one implementation, you can pass the column number, the row where the non-zero element is located, or the row where the zero element is located. Similar to Table 2, the forms of Table 3b-1 to Table 3b-8 are not listed here.

In a possible implementation manner, relevant parameters of the LDPC matrix may be saved by referring to the related description in FIG. 5.

In a possible implementation manner, when the relevant parameters of the LDPC matrix are saved, all the rows of the matrix of FIG. 3a, 3b-1 to 3b-8 may not be saved, or Table 2, Table 3b-1 to Table 3b- All the rows of the matrix shown in Figure 8 can hold the parameters indicated by the corresponding rows in the table according to the rows included in the base matrix. For example, a matrix composed of rows and columns included in the base matrix of the LDPC matrix described in the above embodiments, or related parameters involved in the matrix formed by the rows and columns may be saved.

For example, if the 0th to 6th rows and the 0th to 16th columns in the matrix of FIG. 3b-1 to FIG. 3b-8, the matrix of the 0th to 6th rows and the 0th to 16th columns can be saved. And/or the related parameters of the matrix formed by the 0th to 6th rows and the 0th to 16th columns can be referred to the parameters shown in Tables 3b-1 to 3b-8, and the above description.

If the 0th to (m-1)th rows and the 0th to (n-1)th columns in any of the matrixes of FIG. 3b-1 to FIG. 3b-8, where 7≤m≤42, m is an integer, 17≤n≤ 52, where n is an integer, the matrix of the 0th to (m-1)th rows and the 0th to (n-1)th columns may be saved, and/or the 0th to (m-1)th may be saved. For the relevant parameters of the matrix and the matrix of the 0th to (n-1)th columns, reference may be made to the parameters shown in Tables 3b-1 to 3b-8 and the descriptions of the above sections.

In a possible implementation manner, each of the tables in Table 2, Table 3b-1 to Table 3b-8 may indicate a position greater than or equal to 0 indicated by a position s in at least one column of "non-zero elements" The shift value increases or decreases the offset value Offset _s . It should be noted that the examples herein are merely examples and are not intended to be limiting.

Taking FIG. 1 as an example, in an implementation manner, after determining the base matrix H _B , the input sequence and the 0th to 3th rows and the 0th to 9th columns of the base matrix, that is, the H _core-dual portion, may be first passed. Obtaining the check bits corresponding to the 10th to 15th columns; and obtaining the 16th column according to the input sequence and the check bit corresponding to the H _core-dual , that is, the parity bit corresponding to the single column re-column; then according to the input sequence and the 10th to The 16-column corresponding check bits and the partial code corresponding to the sub-matrix D obtain the parity bits corresponding to the E-matrix E portion, thereby completing the encoding. For the encoding process of the LDPC code, refer to the foregoing implementation manner, and details are not described herein again.

In one design, the above 502 parts and 603 parts encode/decode the input sequence based on the LDPC matrix, and the input sequence may be encoded using the LDPC matrix H corresponding to the spreading factor Z.

In a possible implementation, the encoding of the LDPC can be implemented in the following manner.

1) The input sequence to be encoded is represented as c={c ₀ , c ₁ , c ₂ ,..., c _K-1 }, the length of the input sequence c is K, and the output sequence obtained by the encoder c is encoded by the input sequence c , denoted as d={d ₀ , d ₁ , d ₂ , . . . , d _N-1 }, K is an integer greater than 0, K may be an integer multiple of the expansion factor Z, and the expansion factor of the input sequence c may represent For Z or Z _c , the subscript c is used to indicate for the input sequence c. Optionally, other parameters in this implementation manner may or may not be subscripted. It does not affect the substance of the parameters. Those skilled in the art can understand the meaning thereof. Where N=50Z, or N=(40+K _b )·Z. The length of the input sequence c is K, and the length of the output sequence d is N. The output sequence N may include K ₀ bits in the input sequence c and NK ₀ check bits in the check sequence w. K ₀ is an integer and 0 < K ₀ ≤ K. The check sequence w can be expressed as {W ₀ , W ₁ , W ₂ , . . . , W _N-K0-1 }, and has a length of NK ₀ . In one design, if the LDPC matrix H includes a p-column built-in punctured column, p is an integer greater than or equal to 0, and the p-column built-in punctured column does not participate in encoding, for example, p=2, then the check sequence w The length is N+2Z _c -K, and the check sequence w can be expressed as {W ₀ , W ₁ , W ₂ , . . . , W _N+2Zc-K-1 }. If the p-column built-in puncturing column participates in the encoding, the length of the check sequence w is NK, and the check sequence w can be expressed as {W ₀ , W ₁ , W ₂ , . . . , W _NK-1 }.

For the value of Kb, refer to the above design. E.g:

If(K>640), Kb=10;

Elseif (K>560), Kb=9;

Elseif (K>192), Kb=8;

Else Kb=6;

End

2) According to Z _c = K / K _b , the PCM index corresponding to the bit length K, or the expansion factor group index is determined. For example, the expansion factor Z _c can be determined by referring to Table 1 and Table 2.

3) Assign the first K-2Z _c bits in the encoded bit sequence d={d ₀ , d ₁ , d ₂ , . . . , d _N-1 }. Here, it is necessary to skip 2Z _c padding bits before the bit segment to be encoded, and it is necessary to consider that padding bits may be included in the bit segment to be encoded.

In one implementation, the assignment can be made as follows:

For k=2Z _c to K-1,

If c _k ≠<NULL>

Else

c _k =0;

End if

End for

Where k is an index value, and k is an integer, <NULL> represents a padding bit, which may take a value of 0, or other predetermined value. Alternatively, padding bits may not be sent.

4) Generate a check bit w so that the check bit satisfies the following formula:

In the formula (1), c = [c ₀ , c ₁ , c ₂ , ..., c _K-1 ] ^T , 0 represents a column vector in which the values of all the elements are 0. The matrix H represents an LDPC check matrix, which can be represented by two parts, H ₁ and H ₂ , such as H=[H ₁ H ₂ ]. Where c=[c ₀ , c ₁ , c ₂ , . . . , c _K-1 ] ^T is a transpose vector of a vector composed of bits in the input sequence. The check bit w in the formula (1) is a transposition vector of a vector composed of bits in the check sequence w. For example, N+2Z _{c -} K check bits w=[W ₀ , W ₁ , W ₂ , . . . , W _N+2Zc-K-1 ] ^T is a check sequence {W ₀ , W ₁ , W ₂ , ..., W _N+2Zc-K-1 } The transpose vector of the vector composed of bits. For another example, NK-1 check bits w=[w ₀ , w ₁ , w ₂ , . . . , w _NK-1 ] ^T are check sequences {W ₀ , W ₁ , W ₂ , . . . , W _NK A transpose vector of vectors consisting of bits in _-1 }. H in the formula (1) is based on any of the LDPC matrices exemplified in the foregoing embodiments.

In one implementation, H may be derived based on any of the base maps listed in the above embodiments and an extended matrix of Zc*Zc. Each 0 element in the base map is replaced by the all-zero matrix of Zc*Zc. The element with a value of 1 in the base map uses the Z*Z cyclic permutation matrix I corresponding to its offset value P _i,j (P _i,j Replace, where i, j represents the row index and column index of the element. The cyclic permutation matrix I(P _i,j ) is obtained by performing a P _i,j cyclic shift of the matrix of Zc*Zc to the right or left. Where P _i,j = mod(V _i,j ,Z _c ), V _i,j are offset values in the base matrix corresponding to non-zero elements in the base map.

In one implementation, the H ₁ portion may be the A, B, and D portions of the base map or base matrix enumerated in the above embodiments, that is, lines 0 to 41 in FIGS. 3a, 3b-1 to 3b-8, 0-16 columns.

In one implementation, the H ₁ portion may be a partial row portion column in the A, B, D portions of the base map or base matrix enumerated in the above embodiments. For example, lines 0 to 41, 0 to 13 columns, or 0 to 41 rows 0 to 14 columns, or 0 to 41 rows 0 to 15 columns, or 1 to 41 rows, 0 to 13 columns, and the like.

In one implementation, the H ₁ portion may be m rows and n columns of the base map or base matrix enumerated in the above embodiments, for example, m=7, n=35; or m=4, n=38; m=5, n=37; or m=6, n=36.

In an implementation manner, according to the value of Kb, the input length of the encoder is Kb*Z, and if Kb<9, the {K _b , K _b+1 , . . . , 9} column in the matrix H ₁ is deleted. And then encode.

In an implementation manner, H may be an M row (N+p·Z) column or an M row N column, and the size of the base matrix is m=M/Z.

Or n=N/Z.

In one implementation, the H ₂ portion can be expressed as

Where 0 _{m × n} represents an all-zero matrix of m × n (m rows, n columns), for example, may be 7 rows and 35 columns, or 4 rows and 38 columns, or 5 rows and 37 columns, or 6 rows and 36 columns, and the like. I _{n × n} represents a matrix of n × n (n rows, n columns), for example, 35 rows and 35 columns, or 36 rows and 36 columns, or 37 rows and 37 columns, or 38 rows and 38 columns, and the like.

In one implementation, when encoding using an H matrix, encoding may be based on a base or base matrix as described above. For example, it may be based on the matrix of the 0th to 41st rows, 0 to 16 columns in any of the matrix of FIG. 3a, or FIGS. 3b-1 to 3b-8, or may be based on FIG. 3a, or FIG. 3b-1 to 3b. Lines 0 to 41 in any of -8, a matrix of 0 to 13 columns, and the like.

In one design, for K _b ∈{6,8,9}, the H matrix can be removed from any of the aforementioned base or base matrices {K _b , K _b +1,...,9 The matrix after the column, for K _b = 10, can be any of the aforementioned base or base matrices.

The offset value V _i,j in the check matrix H can be obtained by the above-described Figures 3b-1 to 3b-8, or Tables 3b-1 to 3b-8 and 3b-2', or any of the above. Based on the check matrix index, it is sometimes considered that the group index of the spreading factor can know which check matrix corresponds to, so as to know the corresponding offset value V _i,j .

In one design, H includes a p-column built-in punctured column, p is an integer greater than or equal to 0, and the p-column built-in punctured column does not participate in encoding. For example, if p=2, the length of the check sequence w is N. +2Z _c -K. If the p-column built-in punch column participates in the encoding, the length of the check sequence w is NK.

In one design, 0 _m×n may be the submatrix C part in the foregoing embodiments, or the submatrix C part plus the last column of the submatrix B, or the submatrix C part plus the last of the submatrix B The second column, or the submatrix C portion, adds the last three columns of the submatrix B.

I _n×n may be the sub-matrix E in the foregoing embodiments, or the sub-matrix E plus the last column of the sub-matrices B and D, or the sub-matrix E plus the last two columns of the sub-matrices B and D, or Is the sub-matrix E plus the last three columns of the sub-matrices B and D.

5) Optional, for k=K to N+2Z _c -1,

In the above various implementation manners, the encoder can be encoded and output in various manners, and any of the base map or the base matrix shown in FIG. 3a, FIG. 3b-1 to FIG. For example, the number of base map rows is up to 42 rows, and the number of columns is up to 52 columns, including two columns of built-in punched columns. For convenience of description, in the present invention, the number of rows is the largest and the number of columns is also the largest. The graph/base matrix is called the complete base or base matrix. The base/base matrix that removes the two columns of built-in punctured columns from the complete base/base matrix is called the complete base/base matrix without the built-in punctured columns. .

method one:

Get as many check bits as possible based on the complete base/base matrix or complete base/base matrix encoding that does not include built-in punctured columns. At this time, m=42, if the built-in punched column participates in the encoding, then n=52, that is, the 0th to 41st rows and the 0th to the first of the matrix of any of the above-mentioned FIG. 3a, FIG. 3b-1 to FIG. 51 columns; if the built-in punch column does not participate in the encoding, then n=51, that is, rows 0 to 41 and columns 2 to 51. Accordingly, for the LDPC matrix H, M = 41Z, N = 52Z or N = 51Z. The information bits and check bits that need to be transmitted can be determined from the output sequence generated by the encoder in a subsequent processing step.

Method 2:

Partial row and column encoding based on the complete base map. The row and column encodings may be selected from a complete base map or a complete base map that does not include a built-in punctured column, depending on the code rate to be transmitted, or the number of information bits and check bits. For example, the code rate is 2/3, m=7, if the built-in puncturing column participates in the encoding, then n=17, that is, based on the 0th to 6th of any of the above-mentioned matrixes of FIG. 3a, FIG. 3b-1 to FIG. Line and partial encoding of columns 0 to 16; if the built-in puncturing column does not participate in encoding, then n=15, that is, lines 0 to 6 of any of the matrices of Figures 3a, 3b-1 to 3b-8, and Columns 2 to 16.

In a possible design, the 14th to 51st columns of the matrix of any of the above-mentioned examples of FIG. 3a and 3b-1 to 3b-8 are single-column re-columns, and one or more columns of single-column re-columns in the core matrix may be performed. Perform puncturing so that the core matrix corresponds to one or more columns, for example, m is 6. If the built-in punctured column participates in encoding, n=16, it may be based on any matrix matrix of FIG. 3a, FIG. 3b-1 to 3b-8 above. Partial coding in columns 0 to 6 and columns 0 to 15. In one implementation, the built-in punctured column may also not participate in the encoding, so that a higher code rate can be obtained.

It should be noted that the principle of the H matrix has been described above. When the solution provided by the embodiment of the present invention is adopted, multiple transformations may be performed on the H matrix, as long as the generated check bits satisfy the formula (1).

One possible implementation is that the H matrix performs a Quasi-Cycle (QC) expansion before use. Another possible implementation manner is that the H matrix performs a Quasi-Cycle (QC) expansion on the portion corresponding to the current element to be processed during use.

One possible implementation method is to (directly calculate the offset value), the H matrix is not directly expanded during use, and the expandable equivalent formula method is used to calculate the connection relationship between the matrix rows and columns.

A possible implementation manner is that the H matrix may not be expanded. In the encoding process, for each element to be processed, according to the offset value of the element, the corresponding bit segment to be encoded is shifted; afterwards, All bit segments after the shift operation are directly subjected to encoding operations.

As a possible implementation, the base matrix PCM can be defined by a predefined or system without obtaining a base matrix according to the base map. For example, a matrix of LDPCs may be obtained based on the basis matrix provided in FIGS. 3b-1 to 3b-8, or a matrix of LDPCs may be obtained based on the corresponding tables 3b-1 to 3b-8.

In the implementation process, the sender or receiver can store the complete matrix, that is, all parts of ABCDE. It is also possible to save storage space without storing a complete matrix. For example, you only need to store a part of it or its corresponding parameters to implement the compiled code. Compared to the method of storing the complete matrix, storing only a part of the matrix can reduce the overhead of the storage device in the codec. See the description in the above embodiments for details.

For example, in one implementation, the ABD portion of the matrix is stored, or the single column weight portion is not included in the ABD. In the actual compilation code process, the value of the C and E parts or the value of the single column weight part is calculated by the formula. That is, only the first 17 columns, or the first 14 columns, of the original complete matrix are saved. Since the C part is an all-zero matrix, it can be directly obtained. The E part is an identity matrix. The position of the non-zero element can be calculated according to the currently processed line number. For example, when the current processing behavior is on the 18th line, the E part Corresponding non-zero elements are located in 28 columns. When the current processing behavior is on the 19th line, the E-part corresponds to non-zero elements in the 29th column, and so on. When all the non-zero element positions of the E part are obtained by calculation, the calculation result may be saved, or may not be saved, and is calculated when the corresponding row and column are calculated in the encoding or decoding process.

In another embodiment, the first 14 columns of the original complete matrix are stored. In the unstored part of the right side of the matrix, the position of the non-zero element in the unstored part can be directly obtained by calculation. For example, when the current processing behavior is on the fourth line, the storage portion corresponds to a non-zero element located in 14 columns, and when the current processing behavior is on the fifth line, the storage portion corresponds to a non-zero element located in 15 columns, and so on. When all non-zero element positions in the unstored portion of the matrix are obtained by calculation, the calculation result may be saved or not, and may be calculated when the corresponding row and column are calculated in the encoding or decoding process.

In another implementation, the first 14+x columns in the original complete matrix are stored. In the unstored part of the right side of the matrix, the first 4 acts as a full 0 matrix, and the rest is a unit matrix. The position of the non-zero element in the unstored part can be directly obtained by calculation. For example, when the current processing behavior is (3+x), the bit storage portion corresponds to a non-zero element located in the (14+x)z column. When the current processing behavior is (3+x)+1 rows, the E portion corresponds to a non-zero element. Located in the (14+x)z+1 column, and so on. When all non-zero element positions in the unstored portion of the matrix are obtained by calculation, the calculation result may be saved or not, and may be calculated when the corresponding row and column are calculated in the encoding or decoding process.

In another implementation manner, when the offset value matrix is stored, the value recorded in the offset value matrix may be directly stored, or the value obtained by performing simple mathematical transformation on the offset value matrix value described in the present application may be stored. .

In one implementation, the value of the offset value matrix is transformed and stored. When transforming, starting from the first line in the current offset value matrix, the transform is performed row by row. If an element (such as -1) that represents an all-zero matrix is encountered, it is stored directly without transformation; if it is an element representing a non-zero matrix (non-negative element), and the element is in the column An element (non-negative element) representing a non-zero matrix is stored without direct transformation; if it is an element representing a non-zero matrix (non-negative element), and the element is not the first in the column An element representing a non-zero matrix (non-negative element) holds the difference between the non-negative element and the previous one of the same column representing the non-zero matrix element. The difference is positive for right shift, if the difference is negative Then it means to move left.

It should be noted that a similar transformation may not start from the first row in the offset value matrix, and may start from any row. After the similar transformation proceeds to the last row of the matrix, the return loop returns to the first row and continues downward. Transform. And this way of storing the difference may be different for different spreading factors Z, and it is necessary to calculate the actual offset value and calculate the difference by P _i,j = mod(V _i,j , Z _c ).

In the process of encoding and decoding, the value of the previous element in the same column can be recursively calculated to recover the offset value before the transformation; or the relative offset value can be directly used for encoding and decoding.

In one implementation, the values V _{i,j of the} offset matrix may be transformed and stored. During the transform operation, the positions and values of all the elements (such as -1) representing the all-zero matrix in the matrix are kept unchanged. For the elements representing non-all-zero matrices (non-negative elements), the original value is assumed to be Vij. , the transformed value is (z-Vij) mod z. In the actual encoding and decoding process, the normal encoding and decoding can be realized by performing a left shift operation (originally right shift) on the unit matrix based on the transformed offset value.

In one implementation, the value V _i,j of the offset value matrix is transformed and stored. During the transform operation, the original decimal offset value is converted to other binary forms, such as binary, octal, hexadecimal, and so on. During the process of encoding and decoding, you can choose to restore the transformed offset matrix and then compile the code. You can also directly use the transformed offset matrix to compile the code.

In one implementation, the encoding end does not save the check matrix, but saves the generator matrix that may be needed for encoding. Suppose that the bit segment to be encoded is c=c ₀ , c ₁ , c ₂ , c ₃ ,..., c _K-1 , and the bit segment after encoding is d=d ₀ , d ₁ , d ₂ ,...,d _N-1 , the generator matrix G satisfies: d=c·G

The generation matrix can be obtained by transforming the check matrix H. For the check matrix H, by the row and column transformation, the right side can be changed into a diagonal matrix form, which is expressed as:

H=[P I] (2)

Then, its corresponding generation matrix G satisfies:

G=[I P ^T ] (3)

The check matrix H may be any one of the check matrix or the base matrix described in the above embodiments, or an LDPC matrix. When encoding, the stored generation matrix G can be used to directly calculate the encoded bit segment d=d ₀ from the bit segment to be encoded c=c ₀ , c ₁ , c ₂ , c ₃ , . . . , c _K-1 . d ₁ , d ₂ ,...,d _N-1 .

In an implementation manner, when encoding, for the double diagonal portion of the matrix, the encoding may be performed by any of the above methods, or may be performed by a method of storing a multi-row superposition matrix.

In an implementation manner, for each expansion factor Z, the corresponding offset value matrix can be calculated according to P _i,j = mod(V _i,j , Z _c ), and then 51 matrices corresponding to the expansion factor are used. Both are stored for compilation.

Optionally, in the communication system, the LDPC code is obtained by using the above method. After obtaining the LDPC code, the communication device may perform one or more operations of performing rate matching on the LDPC code, interleaving the rate matched LDPC code according to the interleaving scheme, and modulating the interleaved LDPC code according to the modulation scheme. Bit sequence X; transmit bit sequence X.

Decoding is the inverse of encoding. The base matrix used in the decoding process has the same characteristics as the base matrix used in the encoding process. For the encoding process of the LDPC code, refer to the foregoing implementation manner, and details are not described herein again. In an implementation, before decoding, the communication device may perform one or more operations of: receiving a signal including LDPC-based coding, demodulating, deinterleaving, and de-rate matching the signal to obtain a soft value of the LDPC code. The sequence decodes the soft value sequence of the LDPC code. It is also possible to perform decoding based on a complete base map or a complete base map that does not include a built-in punctured column, or a partial row and column decoding based on a complete base map.

The preservation referred to in this application may be stored in one or more memories. The one or more memories may be separate settings, or may be integrated in an encoder or decoder, a processor, a chip, a communication device, or a terminal. The one or more memories may be separately provided in a part, and the part may be integrated in a decoder, a processor, a chip, a communication device, or a terminal. The type of the memory may be any form of storage medium, and the present application does not limited.

Corresponding to the design of the data processing procedure given in FIG. 5 and FIG. 6, the embodiment of the present invention further provides a corresponding communication device, and the communication device includes a module for executing each part of FIG. 5 or FIG. The module can be software, hardware, or a combination of software and hardware. For example, a module can include a memory, an electronic device, an electronic component, a logic circuit, etc., or any combination of the above. FIG. 7 is a schematic structural diagram of a communication device 700. The device 700 can be used to implement the method described in the foregoing method embodiments. For details, refer to the description in the foregoing method embodiments. The communication device 700 can be a chip, a base station, a terminal, or other network device.

The communication device 700 includes one or more processors 701. The processor 701 can be a general purpose processor or a dedicated processor or the like. For example, it can be a baseband processor, or a central processing unit. The baseband processor can be used to process communication protocols and communication data, and the central processor can be used to control communication devices (eg, base stations, terminals, or chips, etc.), execute software programs, and process data of the software programs.

In one possible involvement, such as 5, one or more of the modules of FIG. 6 may be implemented by one or more processors, or by one or more processors and memories.

In one possible design, the communication device 700 includes one or more of the processors 701, and the one or more processors 701 can implement the above-described encoding/decoding functions, for example, the communication device can be an encoder. Or decoder. In another possible design, the processor 701 can implement other functions in addition to the encoding/decoding functions.

The communication device 700 encodes/decodes an input sequence based on an LDPC matrix; the base matrix of the LDPC matrix may be any of the base matrix in the foregoing example or may be changed in a row order with respect to any of the base matrices exemplified above, Or a column matrix in which the column order is transformed, or a matrix matrix in which both the row order and the column order are transformed, or a base matrix based on the truncation or puncturing of any of the base matrix exemplified above, or based on any of the foregoing basic matrix extensions After the matrix. For the processing of encoding or / decoding, reference may be made to the description of the relevant parts of FIG. 5 and FIG. 6, and details are not described herein again.

Alternatively, in one design, the processor 701 can include instructions 703 (sometimes referred to as code or programs) that can be executed on the processor such that the communication device 700 performs the above-described implementation The method described in the example. In yet another possible design, communication device 700 can also include circuitry that can implement the encoding/decoding functions of the previous embodiments.

Optionally, in one design, the communication device 700 may include one or more memories 702 on which instructions 704 are stored, the instructions being executable on the processor such that the communication device 700 performs the method described in the above method embodiments.

Optionally, data may also be stored in the memory. Instructions and/or data can also be stored in the optional processor. The processor and the memory may be provided separately or integrated.

Optionally, the “storage” described in the above embodiments may be in the storage memory 702, or may be stored in a memory or a storage device of other peripherals.

For example, one or more of the stores 702 may store parameters related to the LDPC matrix enumerated above, eg, base matrix related parameters, such as offset values, base maps, extensions based on the base map to the matrix, rows in the base matrix, extensions The factor, the base matrix or the base matrix is extended to the matrix and so on. For details, refer to the related description in the above part of FIG. 5.

Optionally, the communication device 700 may further include a transceiver 705 and an antenna 706. The processor 701 may be referred to as a processing unit that controls a communication device (terminal or base station). The transceiver 505 can be referred to as a transceiver unit, a transceiver, a transceiver circuit, or a transceiver, etc., for implementing the transceiver function of the communication device through the antenna 506.

Optionally, the communication device 700 may further comprise a device for generating a transport block CRC, a device for code block splitting and CRC check, an interleaver for interleaving, a device for rate matching, or for Modulation of the modulator, etc. The functionality of these devices can be implemented by one or more processors 701.

Optionally, the communication device 700 may further include a demodulator for demodulation operation, a deinterleaver for deinterleaving, a device for de-rate matching, or a code block cascading and CRC calibration. Tested devices and so on. The functionality of these devices can be implemented by one or more processors 701.

8 shows a schematic diagram of a communication system 800 that includes a communication device 80 and a communication device 81, wherein the information data is received and transmitted between the communication device 80 and the communication device 81. The communication devices 80 and 81 may be the communication device 700, or the communication devices 80 and 81 respectively include a communication device 700 for receiving and/or transmitting information data. In one example, communication device 80 can be a terminal, and corresponding communication device 81 can be a base station; in another example, communication device 80 is a base station and corresponding communication device 81 can be a terminal.

It is also understood by those skilled in the art that the various illustrative logical blocks and steps listed in the embodiments of the present invention can be implemented by electronic hardware, computer software, or a combination of both. Whether such functionality is implemented by hardware or software depends on the design requirements of the particular application and the overall system. A person skilled in the art can implement the described functions using various methods for each specific application, but such implementation should not be construed as being beyond the scope of the embodiments of the present invention.

The techniques described herein can be implemented in a variety of ways. For example, these techniques can be implemented in a combination of hardware, software, or hardware. For hardware implementations, processing units for performing these techniques at a communication device (eg, a base station, terminal, network entity, or chip) may be implemented in one or more general purpose processors, digital signal processors (DSPs), digital Signal processing device (DSPD), application specific integrated circuit (ASIC), programmable logic device (PLD), field programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or In any combination. A general purpose processor may be a microprocessor. Alternatively, the general purpose processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented by a combination of computing devices, such as a digital signal processor and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a digital signal processor core, or any other similar configuration. achieve.

The steps of the method or algorithm described in the embodiments of the present invention may be directly embedded in hardware, instructions executed by a processor, or a combination of the two. The memory can be RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium in the art. For example, the memory can be coupled to the processor such that the processor can read information from the memory and can write information to the memory. Alternatively, the memory can also be integrated into the processor. The processor and the memory may be disposed in an ASIC, and the ASIC may be disposed in the UE. Alternatively, the processor and memory may also be located in different components in the UE.

Through the description of the above embodiments, those skilled in the art can clearly understand that the present invention can be implemented in hardware, firmware implementation, or a combination thereof. When implemented using a software program, it may be implemented in whole or in part in the form of a computer program product comprising one or more computer instructions. When the computer instructions are loaded and executed on a computer, the processes or functions described in accordance with embodiments of the present invention are generated in whole or in part. When implemented using a software program, the functions described above may also be stored in or transmitted as one or more instructions or code on a computer readable medium. The computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer readable storage medium or transferred from one computer readable storage medium to another computer readable storage medium. Computer readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one location to another. A storage medium may be any available media that can be accessed by a computer. By way of example and not limitation, computer readable media may comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, disk storage media or other magnetic storage device, or can be used for carrying or storing in the form of an instruction or data structure. The desired program code and any other medium that can be accessed by the computer. Also. Any connection may suitably be a computer readable medium. For example, if the software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable , fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, wireless, and microwave are included in the definition of the medium to which they belong. As used in the present invention, a disk and a disc include a compact disc (CD), a laser disc, a compact disc, a digital versatile disc (DVD), a floppy disk, and a Blu-ray disc, wherein the disc is usually magnetically copied, and the disc is The laser is used to optically replicate the data. Combinations of the above should also be included within the scope of the computer readable media.

It should be noted that “/” in the present application means and/or, for example, “encoding/decoding (encoding and/or decoding), refers to encoding, or decoding, or encoding and decoding.

In summary, the above description is only a preferred embodiment of the technical solution of the present invention, and is not intended to limit the scope of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and scope of the present invention are intended to be included within the scope of the present invention.

Claims (42)

1. An encoding method, the method comprising:

   The input sequence is encoded based on a low density parity check LDPC matrix;

   The LDPC matrix is obtained based on a spreading factor Z and a base matrix including: rows 0 to 6 and columns 0 to 16 of one of the matrices in the matrix shown in FIGS. 3b-1 to 3b-8. Alternatively, the base matrix includes the 0th to 6th rows and the partial columns in the 0th to 16th columns of one of the matrices in the matrix shown in FIGS. 3b-1 to 3b-8.
2. A decoding method, characterized in that the method comprises:

   Decoding the input sequence based on the low density parity check LDPC matrix;

   The LDPC matrix is obtained based on a spreading factor Z and a base matrix including rows 0 to 6 and columns 0 to 16 of one of the matrices in the matrix shown in FIGS. 3b-1 to 3b-8, or The base matrix includes the 0th to 6th rows and the partial columns in the 0th to 16th columns of one of the matrices in the matrix shown in FIGS. 3b-1 to 3b-8.
3. The method according to any one of claims 1 to 2, characterized in that said spreading factor Z = a × 2 ^j , 0 ^≤ j < 7, a ∈ {2, 3, 5, 7, 9, 11, 13,15}, among them,

   If a=2, or the spreading factor Z takes one of {2, 4, 8, 16, 32, 64, 128, 256}, the base matrix may include the number in the matrix shown in FIG. 3b-1 to FIG. 0 to 6 rows and 0 to 16 columns, or the base matrix includes the 0th to (m-1)th rows and the 0th to (n-1)th columns in the matrix shown in FIG. 3b-1, where 7≤m≤ 42, m is an integer, 17 ≤ n ≤ 52, n is an integer; or, the base matrix includes the 0th to (m-1)th rows of the matrix shown in FIG. 3b-1 and the 0th to (n-1)th columns Partial column, where 7 ≤ m ≤ 42, m is an integer, 17 ≤ n ≤ 52, and n is an integer;

   If a=3, or the spreading factor Z takes one of {3, 6, 12, 24, 48, 96, 192, 384}, the base matrix may include the 0th to 6th rows and the 0th to 16th of the matrix 3b-2. Column, or, the base matrix includes the 0th to (m-1)th rows and the 0th to (n-1)th columns in the matrix shown in FIG. 3b-2, where 7≤m≤42, m is an integer, 17≤n ≤ 52, n is an integer; or, the base matrix includes the 0th to (m-1)th rows of the matrix shown in FIG. 3b-2 and the partial columns in the 0th to (n-1)th columns, where 7≤m≤42 , m is an integer, 17≤n≤52, and n is an integer;

   If a=5, or the spreading factor Z takes one of {5, 10, 20, 40, 80, 160, 320}, the base matrix may include the 0th to 6th rows and the 0th to 16th columns in the matrix 3b-3, Alternatively, the base matrix includes the 0th to (m-1)th rows and the 0th to (n-1)th columns in the matrix shown in FIG. 3b-3, where 7≤m≤42, m is an integer, 17≤n≤52 , n is an integer; or, the base matrix includes the 0th to (m-1)th rows of the matrix shown in FIG. 3b-1 and the partial columns in the 0th to (n-1)th columns, where 7≤m≤42,m Is an integer, 17 ≤ n ≤ 52, where n is an integer;

   If a=7, or the spreading factor Z takes one of {7, 14, 28, 56, 112, 224}, the base matrix may include the 0th to 6th rows and the 0th to 16th columns in the matrix 3b-4, or The base matrix includes the 0th to (m-1)th rows and the 0th to (n-1)th columns in the matrix shown in FIG. 3b-4, where 7≤m≤42, m is an integer, 17≤n≤52,n Is an integer; or, the base matrix includes the 0th to (m-1)th rows of the matrix shown in FIG. 3b-4 and the partial columns in the 0th to (n-1)th columns, where 7≤m≤42, m is an integer , 17≤n≤52, n is an integer;

   If a=9, or the spreading factor Z takes one of {9, 18, 36, 72, 144, 288}, the base matrix may include the 0th to 6th rows and the 0th to 16th columns in the matrix 3b-5, or The base matrix includes the 0th to (m-1)th rows and the 0th to (n-1)th columns in the matrix shown in FIG. 3b-5, where 7≤m≤42, m is an integer, 17≤n≤52,n An integer; or, the base matrix includes the 0th to (m-1)th rows of the matrix shown in FIG. 3b-5 and the partial columns in the 0th to (n-1)th columns, where 7≤m≤42, m is an integer , 17≤n≤52, n is an integer;

   If a=11, or the spreading factor Z takes one of {11, 22, 44, 88, 176, 352}, the base matrix may include the 0th to 6th rows and the 0th to 16th columns in the matrix 3b-6, or The base matrix includes the 0th to (m-1)th rows and the 0th to (n-1)th columns in the matrix shown in FIG. 3b-6, where 7≤m≤42, m is an integer, 17≤n≤52,n Is an integer; or, the base matrix includes the 0th to (m-1)th rows of the matrix shown in FIG. 3b-6 and the partial columns in the 0th to (n-1)th columns, where 7≤m≤42, m is an integer , 17≤n≤52, n is an integer;

   If a=13, or the spreading factor Z takes one of {13, 26, 52, 104, 208}, the base matrix may include the 0th to 6th rows and the 0th to 16th columns in the matrix 3b-7, or the base matrix Including the 0th to (m-1)th rows and the 0th to (n-1)th columns in the matrix shown in FIG. 3b-7, where 7≤m≤42, m is an integer, 17≤n≤52, n is an integer Or, the base matrix includes the 0th to (m-1)th rows of the matrix shown in FIG. 3b-7 and the partial columns in the 0th to (n-1)th columns, where 7≤m≤42, m is an integer, 17 ≤ n ≤ 52, n is an integer; or

   If a=15, or the spreading factor Z takes one of {15, 30, 60, 120, 240}, the base matrix may include the 0th to 6th rows and the 0th to 16th columns in the matrix 3b-8, or the base matrix Including the 0th to (m-1)th rows and the 0th to (n-1)th columns in the matrix shown in Fig. 3b-8, where 7≤m≤42, m is an integer, 17≤n≤52, n is an integer Or, the base matrix includes the 0th to (m-1)th rows of the matrix shown in FIG. 3b-8 and the partial columns in the 0th to (n-1)th columns, where 7≤m≤42, m is an integer, 17 ≤ n ≤ 52, where n is an integer.
4. The method according to any one of claims 1 to 3, wherein the LDPC matrix is obtained based on the spreading factor Z and a matrix Hs compensated for the base matrix, wherein the matrix Hs is obtained by increasing or decreasing a compensation value Offset _s for each offset value greater than or equal to 0 in at least one column s of the base matrix, wherein the compensation value Offset _s is an integer greater than or equal to 0, where S is An integer greater than or equal to 0 and less than 11.
5. The method according to any one of claims 1 to 4, wherein the LDPC matrix is based on the spreading factor Z, and the compensation matrix Hs of the base matrix or the base matrix is subjected to row switching, or column switching, Or the matrix after row swapping and column swapping.
6. An encoding method, the method comprising:

   Encoding the input sequence according to the parameters of the spreading factor Z and the low density parity check LDPC matrix;

   The parameters of the LDPC matrix include the parameters corresponding to the row numbers 0 to 6 in the table shown in any of Table 2 and Table 3b-1 to Table 3b-8.
7. A decoding method, characterized in that the method comprises:

   Decoding the input sequence according to the parameters of the spreading factor Z and the low density parity check LDPC matrix;

   The parameters of the LDPC matrix include the parameters corresponding to the row numbers 0 to 6 in the table shown in any of Table 2 and Table 3b-1 to Table 3b-8.
8. The method according to claim 6 or 7, wherein the parameter of the LDPC matrix further comprises a row number of 7 to 41 corresponding to the table shown in any of the table 2, the table 3b-1 to the table 3b-8. Parameters.
9. The method according to any one of claims 6 to 8, wherein said spreading factor Z = a × 2 ^j , 0 ^≤ j < 7, a ∈ {2, 3, 5, 7, 9, 11, 13,15}, among them,

   a=2, the parameters of the LDPC matrix include the parameters corresponding to the row numbers 0 to 6 in Table 2 or Table 3b-1; or

   a=3, the parameters of the LDPC matrix include the parameters corresponding to the row numbers 0 to 6 in Table 2 or Table 3b-2; or

   a=5, the parameters of the LDPC matrix include the parameters corresponding to the row numbers 0 to 6 in Table 2 or Table 3b-3; or

   a=7, the parameters of the LDPC matrix include the parameters corresponding to the row numbers 0 to 6 in Table 2 or Table 3b-4; or

   a=9, the parameters of the LDPC matrix include the parameters corresponding to the row numbers 0 to 6 in Table 2 or Table 3b-5; or

   a=11, the parameters of the LDPC matrix include the parameters corresponding to the row numbers 0 to 6 in Table 2 or Table 3b-6; or

   a=13, the parameters of the LDPC matrix include the parameters corresponding to the row numbers 0 to 6 in Table 2 or Table 3b-7; or

   a=15, the parameters of the LDPC matrix include the parameters corresponding to the row numbers 0 to 6 in Table 2 or Table 3b-8.
10. The method of claim 9 wherein:

    a=2, the parameters of the LDPC matrix include the parameters corresponding to the row numbers 7 to 41 in Table 2 or Table 3b-1; or

    a=3, the parameters of the LDPC matrix include the parameters corresponding to the row numbers 7 to 41 in Table 2 or Table 3b-2; or

    a=5, the parameters of the LDPC matrix include the parameters corresponding to the row numbers 7 to 41 in Table 2 or Table 3b-3; or

    a=7, the parameters of the LDPC matrix include the parameters corresponding to the row numbers 7 to 41 in Table 2 or Table 3b-4; or

    a=9, the parameters of the LDPC matrix include the parameters corresponding to the row numbers 7 to 41 in Table 2 or Table 3b-5; or

    a=11, the parameters of the LDPC matrix include the parameters corresponding to the row numbers 7 to 41 in Table 2 or Table 3b-6; or

    a=13, the parameters of the LDPC matrix include the parameters corresponding to the row numbers 7 to 41 in Table 2 or Table 3b-7; or

    a=15, the parameters of the LDPC matrix include the parameters corresponding to the row numbers 7 to 41 in Table 2 or Table 3b-8.
11. The method according to any one of claims 6 to 10, wherein the encoding/decoding of the input sequence according to the parameters of the spreading factor Z and the low density parity check LDPC matrix comprises:

    Encoding/decoding the input sequence according to a spreading factor Z and a parameter compensated for parameters of the LDPC matrix;

    The compensated parameters include:

    An offset value greater than or equal to 0 in at least one column position s of the parameters of the LDPC matrix increases or decreases a compensation value Offset _s , wherein the compensation value Offset _s is an integer greater than or equal to 0, where s is greater than An integer equal to 0 and less than 11.
12. An information processing method includes:

    Encoding the input sequence c={c ₀ , c ₁ , c ₂ , . . . , c _K-1 } to obtain an output sequence d={d ₀ , d ₁ , d ₂ , . . . , d _N-1 } Where K and N are integers greater than 0;

    The output sequence d includes K ₀ bits in the input sequence c and parity bits in the check sequence w, K ₀ is an integer, and 0 < K ₀ ≤ K;

    The check sequence w and the input sequence c satisfy a formula

    

    Where c ^T =[c ₀ , c ₁ , c ₂ , . . . , c _K-1 ] ^T , is a transpose vector of a vector composed of bits in the input sequence c,

    

    a transpose vector of a vector composed of bits in the check sequence w, 0 ^T is a column vector, and the values of all elements thereof are 0;

    H is a low density parity check LDPC matrix, and the base map of H includes _HBG and _{HBG, EXT} , where

    

    An all-zero matrix representing the size of m _c ×n _c ,

    

    N _c × n _c represents the size of the matrix, H _BG comprising H _BG2 Kb columns corresponding to information bits in a column, and the H _BG2 to 10 + m _A -1 column 10, H _BG2 number of columns is 10 + m _A column , 4 ≤ m _A ≤ 7, where Kb ∈ {6, 8, 9, 10};

    m _c =7,0≤n _c ≤35, the number of columns of H _BG2 is equal to 17, or,

    m _c =6, 0 ≤ n _c ≤ 36, the number of columns of H _BG2 is equal to 16, or,

    m _c = 5,0≤n _c ≤37, the number of columns 15 is equal to H _BG2, or,

    m _c = 4,0≤n _c ≤38, the number of columns 14 is equal to H _BG2.
13. The method of claim 12 wherein:

    If the position of the element row of the respective rows of nonzero H _BG2 such as charts 3a, 3b-1 or 3b-8 to Table 3a, Table 3b-1 through Table 3b-8, Table 3b-2 'by any one.
14. An information processing method includes:

    Obtaining an input sequence c={c ₀ , c ₁ , c ₂ , . . . , c _K-1 }, the input sequence c has a length of K;

    Determine the expansion factor Z;

    Determining a check matrix H of the LDPC based on the spreading factor Z;

    Encoding the input sequence c to obtain the encoded bit sequence d={d ₀ , d ₁ , d ₂ , . . . , d _N-1 }, where d is of length N; wherein d contains the check bit w, The check bits satisfy:

    

    Where c = [c ₀ , c ₁ , c ₂ , ..., c _K-1 ] ^T represents a transpose vector of a vector composed of bits in the input sequence c,

    

    A transpose vector representing a vector of bits in a check sequence, 0 representing a column vector, where all elements have a value of zero. The matrix H represents an LDPC check matrix.
15. The method of claim 14 wherein the matrix H can be represented as H = [H ₁ H ₂ ] and H ₁ is in the A, B, D portions of any of the matrices of Figures 3b-1 through 3b-8 Partial row partial column, H _{2 is} expressed as

    

    Where 0 _{m × n} represents an all-zero matrix of m × n, and I _{n × n} represents an n × n matrix.
16. The method according to any one of claims 12 to 15, characterized in that the length of the check sequence w is N+2Z-K, or the length of the check sequence is N-K.
17. An encoding method comprising:

    Encoding the input sequence c based on the low density parity check LDPC matrix H;

    The base matrix of the LDPC matrix H includes a non-zero element (i, j), where i is a row number, j is a column number, and the non-zero element (i, j) represents a loop of the element by a Z*Z size Substitution matrix replacement, the cyclic permutation matrix corresponding to the rightward P _i of the unit matrix of the Z*Z size _{, j} times cyclic shift, P _i,j = mod(V _i,j ,Z), Z is an expansion factor, The non-zero element (i, j) and its corresponding value V _i,j are as follows:

    
18. The method of claim 17, wherein the encoding the input sequence c based on the low density parity check LDPC matrix H comprises:

    Encoding the input sequence c={c ₀ , c ₁ , c ₂ , . . . , c _K-1 } to obtain an output sequence d={d ₀ , d ₁ , d ₂ , . . . , d _N-1 } Where K and N are both positive integers, K is an integer multiple of Z, and N=50Z.
19. The method of claim 18 wherein said Z is one of {5, 10, 20, 40, 80, 160, 320}.
20. The method according to claim 18 or 19, characterized in that Z is a minimum value satisfying K _b · Z ≥ K, wherein K _b is one of {6, 8, 9, 10}.
21. The method of claim 19 wherein K _b satisfies:

    
22. The method according to any one of claims 18 to 21, wherein said output sequence d comprises K ₀ bits in said input sequence c and check bits in check sequence w, K ₀ being an integer, and 0<K ₀ ≤K, the length of the check sequence w is NK ₀ ;

    The check sequence w and the input sequence c satisfy a formula

    

    Where c ^T =[c ₀ , c ₁ , c ₂ , . . . , c _K-1 ] ^T , is a transpose vector of a vector composed of bits in the input sequence c,

    

    For the transpose vector of the vector composed of bits in the check sequence w, 0 ^T is a column vector, and the values of all the elements thereof are 0.
23. The method according to claim 22, wherein the check sequence w has a length of N + 2Z - K.
24. The method according to any one of claims 18 to 23, wherein the encoding of the input sequence c based on the low density parity check LDPC matrix H comprises:

    For k=2Z to K-1;

    If c _k ≠ <NULL>;

    

    Otherwise, c _k =0.
25. The method according to any one of claims 18 to 24, wherein the encoding of the input sequence c based on the low density parity check LDPC matrix H comprises: for k=K to N+2Z _c -1,

    
26. A decoding method comprising:

    Decoding the soft value sequence of the LDPC code based on the low density parity check LDPC matrix H to obtain an information sequence;

    Wherein the base matrix of H comprises a non-zero element (i, j), wherein i is a row number, j is a column number, and the non-zero element (i, j) represents a loop of the element being Z*Z size Substitution matrix replacement, the cyclic permutation matrix corresponding to the rightward P _i of the unit matrix of the Z*Z size _{, j} times cyclic shift, P _i,j = mod(V _i,j ,Z), Z is an expansion factor, The non-zero element (i, j) and its corresponding value V _i,j are as follows:

    
27. The method according to any one of claims 17 to 26, wherein the base matrix of H further comprises the following non-zero elements (i, j), the corresponding values V _{i,j being} as follows:

    
28. The method according to any one of claims 17 to 27, wherein the base matrix of H further comprises the following non-zero elements (i, j), the corresponding values V _{i,j being} as follows:

    

    
29. The method according to any one of claims 17 to 28, wherein the base matrix of H further comprises the following non-zero elements (i, j), the corresponding values V _{i,j being} as follows:

    
30. The method according to any one of claims 17 to 29, wherein the base matrix of H further comprises the following non-zero elements (i, j), the corresponding values V _{i,j being} as follows:

    
31. The method according to any one of claims 17 to 30, characterized in that the base matrix of H further comprises the following non-zero elements (i, j), the corresponding values V _{i,j being} as follows:

    
32. The method according to any one of claims 17 to 31, wherein the base matrix of H further comprises a non-zero element (i, j) of the i+1th row, wherein 9 ≤ i ≤ 41 said non- The value V _i,j corresponding to the zero element (i,j) satisfies the following:

    
33. The method according to any one of claims 17 to 32, wherein the base matrix of H is a matrix of m rows and n columns, m ≤ 42, n ≤ 52.
34. The method according to any one of claims 17 to 33, characterized in that said Z is one of {5, 10, 20, 40, 80, 160, 320}.
35. A method according to any one of claims 12 to 34, wherein K is an integer multiple of Z.
36. A device for performing the method of any one of claims 1 to 35.
37. A communication device, comprising: a processor, a memory, and instructions stored on the memory and operable on the processor, when the instructions are executed, causing the communication device to perform the claims The method of any one of 1 to 35.
38. A terminal comprising the apparatus of claim 36 or the communication apparatus of claim 37.
39. A base station comprising the apparatus of claim 36 or the communication apparatus of claim 37.
40. A communication system comprising the terminal of claim 38 and the base station of claim 39.
41. A computer readable storage medium comprising instructions which, when run on a computer, cause the computer to perform the method of any one of claims 1 to 35.
42. A computer program product, when run on a computer, causes the computer to perform the method of any one of claims 1 to 35.

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