WO2019047956A1 - 一种提高图像流畅度的方法及装置 - Google Patents
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Classifications
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Definitions
- the present disclosure relates to, but is not limited to, the field of terminal technology.
- electronic devices such as mobile phones basically use the mobile industry processor interface (MIPI) transmission protocol between the processing chip and the screen. According to the protocol, it can be divided into video mode. It is transmitted in two modes, the command mode (cmd mode), and the manner in which the vertical synchronization signals (VSync) are generated in these two modes is also different. If the video mode transmission mode is adopted, the VSync synchronization signal is sent by the processing chip of the electronic device. Calculated at a refresh rate of 60 fps, a VSync is generated in about 16.7 milliseconds, that is, the processing chip of the electronic device needs to process the image to be displayed within this time, and then send it to the screen for display.
- MIPI mobile industry processor interface
- a method for improving image fluency comprising: starting processing of current frame data when a VSync issued by a display arrives; if processing of current frame data is not completed in a VSync cycle, continuing Processing the current frame data in a predetermined predetermined duration; and if the processing of the current frame data is not completed in the predetermined duration of the delay, discarding the processing of the current frame data and continuing to display the previous one on the display Frame image.
- an apparatus for improving image fluency comprising: a triggering module configured to start processing current frame data when a VSync issued by the display arrives; and a delay module configured to If the processing of the current frame data is not completed in the VSync cycle, the current frame data continues to be processed in the predetermined duration of the delay; and the detection module is configured to not process the current frame data if the predetermined duration of the delay is not completed. , the processing of the current frame data is discarded, and the previous frame image is continuously displayed on the display.
- an electronic device comprising: a display; a memory storing a computer program; and a processor that performs an improvement according to the present disclosure when the processor executes the computer program The method of image fluency.
- a computer readable storage medium having stored thereon a computer program that, when executed by a processor, performs a method of improving image fluency in accordance with the present disclosure.
- FIG. 1 and FIG. 2 are diagrams showing an example of synchronization of image processing and VSync of a CPU and a GPU in the related art
- FIG. 3 is a schematic flow chart of a method for improving image fluency according to an embodiment of the present disclosure
- VSync delay 4 is an exemplary diagram of a VSync delay in accordance with an embodiment of the present disclosure
- FIG. 5 is a schematic structural diagram of an apparatus for improving image fluency according to an embodiment of the present disclosure
- FIG. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure.
- FIG. 7 is a flow chart showing an example of a method of improving image fluency according to an embodiment of the present disclosure.
- FIG. 1 and 2 are diagrams showing an example of synchronization of image processing and VSync of a CPU and a GPU in the related art.
- the present disclosure provides a technical solution for ensuring that the CPU and the GPU can process one frame of data in one cycle of the VSync by adjusting the cycle of the VSync in real time, thereby avoiding the jam and effectively improving the smoothness of the display.
- the synchronization period of the VSync is extended by 1 to 2 milliseconds, so that the CPU And the GPU can process the frame data of this picture in the synchronization cycle of VSync, so as to ensure that the screen can display normally, so as to improve the smoothness of the system.
- Embodiments of the present disclosure are applicable to scenes that are not very demanding in real-time but require high display effects, such as scenes in which video files are played.
- the technical solution of the present disclosure can be implemented by an electronic device supporting video playback or image display.
- the electronic device can be implemented in various forms.
- the electronic device can be, but is not limited to, a mobile phone, a tablet computer, a notebook computer, a palmtop computer, a personal digital assistant (PDA), a portable media player (PMP), a navigation device.
- PDA personal digital assistant
- PMP portable media player
- Mobile terminals such as wearable devices, smart bracelets, pedometers, and fixed terminals such as digital TVs and desktop computers.
- FIG. 3 is a flow chart of a method for improving image fluency according to an embodiment of the present disclosure.
- the method of improving image fluency according to an embodiment of the present disclosure may include steps 301 to 303.
- processing of the current frame data begins when the VSync issued by the display arrives.
- step 302 if the processing of the current frame data is not completed in the VSync cycle, the current frame data continues to be processed in the predetermined duration of the delay.
- step 303 if the processing of the current frame data has not been completed in the predetermined time period of the delay, the processing of the current frame data is discarded and the display of the previous frame image on the display continues.
- the display will issue a VSync after one frame of picture is drawn and before the next frame is prepared.
- the display is refreshed at a fixed frequency, which is the frequency at which VSync is generated.
- the VSync cycle can be delayed by setting a timer.
- a timer is set in the processor, and the duration set for the timer may be the sum of the VSync period and the predetermined duration (for example, the VSync period is 16.7 milliseconds, and the predetermined duration is 2 milliseconds. The set duration is 16.7 + 2 milliseconds).
- VSync arrives, the timer is triggered and starts timing. If the current frame data is still not processed when the timer reaches its set time, the processor will abandon the processing of the frame data and send an interrupt signal to the display. The display continues to display the previous frame. When the timer has not reached its set time, the processor will continue to process the current frame data until processing is complete.
- the predetermined duration of the delay may be 1 to 2 milliseconds.
- the predetermined duration may also be set to other values, which is not limited in the disclosure.
- VSync delay 4 is an exemplary diagram of a VSync delay in accordance with an embodiment of the present disclosure.
- the CPU and the GPU can be completed in the extended processing time by appropriately extending the processing time.
- the processing of the current frame data ensures that the screen can be displayed normally.
- the processing of the frame data may include: the CPU calculates the display content of the current frame data, and submits to the GPU after the calculation is completed; the GPU performs the transformation processing, the synthesis processing, the rendering processing, and submits the rendering result to the frame buffer; and the video controller The rendering result is read from the frame buffer and loaded on the display.
- FIG. 5 is a schematic structural diagram of an apparatus for improving image fluency according to an embodiment of the present disclosure.
- the apparatus for improving image fluency may include a trigger module 51, a delay module 52, and a detection module 53.
- the trigger module 51 is arranged to begin processing the current frame data when the VSync issued by the display arrives.
- the delay module 52 is arranged to continue processing the current frame data for a predetermined period of time delay if the processing of the current frame data is not completed in the VSync cycle.
- the detection module 53 is arranged to abandon the processing of the current frame data if the processing of the current frame data has not been completed in the predetermined duration of the delay, and to continue displaying the previous frame image on the display.
- the apparatus for improving image fluency may further include a timer.
- the set duration of the timer is the sum of the VSync period and the predetermined duration of the delay. The timer starts timing when the vertical sync signal arrives, and when the timing of the timer has not reached its set duration, the trigger module 51 or the delay module 52 continues to process the current frame data until the processing of the current frame data is completed.
- the detecting module 53 discards the processing of the current frame data and continues to display the previous frame image on the display. If the processing of the current frame data is completed before the timer's timing reaches its set duration, the display displays an image corresponding to the current frame data.
- the predetermined duration of the delay may be 1 to 2 milliseconds.
- the predetermined duration may also be set to other values, which is not limited in the disclosure.
- the apparatus for improving image fluency may further include a CPU, a GPU, a frame buffer, and a video controller.
- the CPU calculates the display content of the current frame data and submits it to the GPU after the calculation is completed.
- the GPU performs transform processing, compositing processing, and rendering processing, the rendering result is submitted to the frame buffer.
- the video controller reads the rendering result from the frame buffer and loads it on the display.
- each of the above modules in this embodiment may be software, hardware, or a combination of the two.
- each of the above modules may be implemented by a CPU in an electronic device (eg, a mobile phone).
- the above apparatus of the embodiment can be applied to an electronic device supporting video playback or image display.
- FIG. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure.
- an electronic device in accordance with an embodiment of the present disclosure may include a display, a memory, and a processor (eg, a CPU and a GPU).
- the memory stores a computer program that, when executed by the processor, performs a method of improving image fluency in accordance with various embodiments of the present disclosure.
- the electronic device may also include, but is not limited to, a video controller and a bus, as shown in FIG.
- the CPU, the GPU, and the memory are communicably connected to each other through a bus.
- the CPU is responsible for calculating the display content and submitting it to the GPU.
- the GPU is responsible for rendering and processing, and puts the rendering result into the frame buffer after the rendering is completed.
- the video controller is responsible for reading the data of the frame buffer line by line according to VSync under the control of the GPU. And through the possible digital-to-analog conversion to the display for display.
- Embodiments of the present disclosure also provide a computer readable storage medium having stored thereon a computer program that, when executed by a processor, performs a method of improving image fluency according to various embodiments of the present disclosure .
- the computer readable storage medium is applicable to an electronic device according to the present disclosure.
- FIG. 7 is a flow chart showing an example of a method of improving image fluency according to an embodiment of the present disclosure.
- the flow according to the present example may include steps 701 to 708.
- the display draws the Nth frame and displays it.
- the display issues VSync before preparing the N+1th frame.
- step 703 after the arrival of VSync, processing of the (N+1)th frame data is started.
- step 704 it is judged whether or not the processing of the (N+1)th frame data is completed in the VSync cycle (i.e., 16.7 ms). If the processing is completed, step 707 is performed; if the processing is not completed, step 705 is continued.
- the N+1th frame data continues to be processed in the delayed duration (e.g., 2 ms).
- step 706 it is judged whether or not the processing of the (N+1)th frame data is completed in the length of the delay (for example, 2 ms). If the processing is completed, step 707 is performed; if the processing is not completed, step 708 is performed.
- the display displays the N+1th frame.
- step 708 the processing of the N+1th frame data is discarded, and the Nth frame picture continues to be displayed.
- each module/unit in the above embodiment may be implemented in the form of hardware, for example, by implementing an integrated circuit to implement its corresponding function, or may be implemented in the form of a software function module, for example, executing a program stored in the memory by a processor. / instruction to achieve its corresponding function.
- the present disclosure is not limited to any specific form of combination of hardware and software.
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Abstract
Description
Claims (12)
- 一种提高图像流畅度的方法,包括:在显示器发出的垂直同步信号到来时,开始对当前帧数据进行处理;如果在垂直同步信号周期中没有完成当前帧数据的处理,则继续在延迟的预定时长中对当前帧数据进行处理;以及如果在所述延迟的预定时长中仍没有完成当前帧数据的处理,则放弃当前帧数据的处理,并继续在所述显示器上显示上一帧图像。
- 根据权利要求1所述的方法,其中,设置定时器,所述定时器的设定时长为所述垂直同步信号周期与所述延迟的预定时长之和,所述定时器在垂直同步信号到来时开始计时,并且在所述定时器的计时未达到其设定时长时持续对当前帧数据进行处理,直到完成当前帧数据的处理。
- 根据权利要求2所述的方法,其中,如果在所述定时器的计时达到其设定时长时仍没有完成当前帧数据的处理,则放弃当前帧数据的处理,并继续在所述显示器上显示上一帧图像,如果在所述定时器的计时达到其设定时长之前完成了当前帧数据的处理,则所述显示器显示与当前帧数据对应的图像。
- 根据权利要求1至3任一项所述的方法,其中,所述延迟的预定时长为1至2毫秒。
- 根据权利要求1所述的方法,其中,对当前帧数据进行处理的步骤包括:中央处理单元计算当前帧数据的显示内容,并在计算完成后提交至图形处理单元;图形处理单元执行变换处理、合成处理、渲染处理之后,将渲染结果提交至帧缓冲区;以及视频控制器从所述帧缓冲区读取所述渲染结果并加载所述显示器上。
- 一种提高图像流畅度的装置,包括:触发模块,其设置为在显示器发出的垂直同步信号到来时,开始当前帧数据的处理;延时模块,其设置为如果在垂直同步信号周期中没有完成当前帧数据的处理,则继续在延迟的预定时长中对当前帧数据进行处理;以及检测模块,其设置为如果在所述延迟的预定时长中仍没有完成当前帧数据的处理,则放弃当前帧数据的处理,并继续在所述显示器上显示上一帧图像。
- 根据权利要求6所述的装置,还包括:定时器,所述定时器的设定时长为所述垂直同步信号周期与所述延迟的预定时长之和,所述定时器在垂直同步信号到来时开始计时,并且在所述定时器的计时未达到其设定时长时,使得所述触发模块或所述延时模块持续对当前帧数据进行处理,直到完成当前帧数据的处理。
- 根据权利要求7所述的装置,其中,如果在所述定时器的计时达到其设定时长时仍没有完成当前帧数据的处理,则所述检测模块放弃当前帧数据的处理,并继续在所述显示器上显示上一帧图像,如果在所述定时器的计时达到其设定时长之前完成了当前帧数据的处理,则所述显示器显示与当前帧数据对应的图像。
- 根据权利要求6至8任一项所述的装置,其中,所述延迟的 预定时长为1至2毫秒。
- 根据权利要求6所述的装置,还包括中央处理单元、图形处理单元、帧缓冲区和视频控制器,其中,所述中央处理单元计算当前帧数据的显示内容,并在计算完成后提交至所述图形处理单元,所述图形处理单元执行变换处理、合成处理、渲染处理之后,将渲染结果提交至所述帧缓冲区,并且所述视频控制器从所述帧缓冲区读取所述渲染结果并加载所述显示器上。
- 一种电子设备,包括显示器、存储器和处理器,其中,所述存储器存储有计算机程序,当所述处理器执行所述计算机程序时,所述处理器执行根据权利要求1至5任一项所述的提高图像流畅度的方法。
- 一种计算机可读存储介质,其上存储有计算机程序,当所述计算机程序被处理器执行时,所述处理器执行根据权利要求1至5中任一项所述的提高图像流畅度的方法。
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EP18854949.7A EP3681143A4 (en) | 2017-09-08 | 2018-09-10 | METHOD AND DEVICE FOR IMPROVING IMAGE FLOW |
JP2019536838A JP6894976B2 (ja) | 2017-09-08 | 2018-09-10 | 画像円滑性向上方法および装置 |
KR1020197026750A KR20190117635A (ko) | 2017-09-08 | 2018-09-10 | 이미지 유창성을 향상하는 방법 및 장치 |
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WO2024098871A1 (zh) * | 2022-11-07 | 2024-05-16 | 荣耀终端有限公司 | 数据处理方法、设备及存储介质 |
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CN110018874B (zh) * | 2019-04-09 | 2021-07-13 | Oppo广东移动通信有限公司 | 垂直同步方法、装置、终端及存储介质 |
CN111656797A (zh) * | 2019-06-25 | 2020-09-11 | 深圳市大疆创新科技有限公司 | 控制方法、图像传输系统、显示装置及无人机系统 |
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EP3681143A4 (en) | 2021-04-07 |
CN109474768A (zh) | 2019-03-15 |
JP2020507244A (ja) | 2020-03-05 |
JP6894976B2 (ja) | 2021-06-30 |
EP3681143A1 (en) | 2020-07-15 |
KR20190117635A (ko) | 2019-10-16 |
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