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WO2019047956A1 - 一种提高图像流畅度的方法及装置 - Google Patents

一种提高图像流畅度的方法及装置 Download PDF

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Publication number
WO2019047956A1
WO2019047956A1 PCT/CN2018/104884 CN2018104884W WO2019047956A1 WO 2019047956 A1 WO2019047956 A1 WO 2019047956A1 CN 2018104884 W CN2018104884 W CN 2018104884W WO 2019047956 A1 WO2019047956 A1 WO 2019047956A1
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WO
WIPO (PCT)
Prior art keywords
processing
frame data
current frame
display
completed
Prior art date
Application number
PCT/CN2018/104884
Other languages
English (en)
French (fr)
Inventor
潘明东
Original Assignee
中兴通讯股份有限公司
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Filing date
Publication date
Application filed by 中兴通讯股份有限公司 filed Critical 中兴通讯股份有限公司
Priority to EP18854949.7A priority Critical patent/EP3681143A4/en
Priority to JP2019536838A priority patent/JP6894976B2/ja
Priority to KR1020197026750A priority patent/KR20190117635A/ko
Publication of WO2019047956A1 publication Critical patent/WO2019047956A1/zh

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Classifications

    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/001Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/60Network structure or processes for video distribution between server and client or between remote clients; Control signalling between clients, server and network components; Transmission of management data between server and client, e.g. sending from server to client commands for recording incoming content stream; Communication details between server and client 
    • H04N21/63Control signaling related to video distribution between client, server and network components; Network processes for video distribution between server and clients or between remote clients, e.g. transmitting basic layer and enhancement layers over different transmission paths, setting up a peer-to-peer communication via Internet between remote STB's; Communication protocols; Addressing
    • H04N21/647Control signaling between network components and server or clients; Network processes for video distribution between server and clients, e.g. controlling the quality of the video stream, by dropping packets, protecting content from unauthorised alteration within the network, monitoring of network load, bridging between two different networks, e.g. between IP and wireless
    • H04N21/64784Data processing by the network
    • H04N21/64792Controlling the complexity of the content stream, e.g. by dropping packets
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/14Picture signal circuitry for video frequency region
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/12Synchronisation between the display unit and other units, e.g. other display units, video-disc players
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/44Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
    • H04N21/44004Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving video buffer management, e.g. video decoder buffer or video display buffer
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/44Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
    • H04N21/4402Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display
    • H04N21/440263Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display by altering the spatial resolution, e.g. for displaying on a connected PDA
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00Aspects of display data processing
    • G09G2340/04Changes in size, position or resolution of an image
    • G09G2340/0407Resolution change, inclusive of the use of different resolutions for different screen areas
    • G09G2340/0435Change or adaptation of the frame rate of the video stream
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00Aspects of the architecture of display systems
    • G09G2360/18Use of a frame buffer in a display terminal, inclusive of the display panel
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/18Timing circuits for raster scan displays
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/04Synchronising

Definitions

  • the present disclosure relates to, but is not limited to, the field of terminal technology.
  • electronic devices such as mobile phones basically use the mobile industry processor interface (MIPI) transmission protocol between the processing chip and the screen. According to the protocol, it can be divided into video mode. It is transmitted in two modes, the command mode (cmd mode), and the manner in which the vertical synchronization signals (VSync) are generated in these two modes is also different. If the video mode transmission mode is adopted, the VSync synchronization signal is sent by the processing chip of the electronic device. Calculated at a refresh rate of 60 fps, a VSync is generated in about 16.7 milliseconds, that is, the processing chip of the electronic device needs to process the image to be displayed within this time, and then send it to the screen for display.
  • MIPI mobile industry processor interface
  • a method for improving image fluency comprising: starting processing of current frame data when a VSync issued by a display arrives; if processing of current frame data is not completed in a VSync cycle, continuing Processing the current frame data in a predetermined predetermined duration; and if the processing of the current frame data is not completed in the predetermined duration of the delay, discarding the processing of the current frame data and continuing to display the previous one on the display Frame image.
  • an apparatus for improving image fluency comprising: a triggering module configured to start processing current frame data when a VSync issued by the display arrives; and a delay module configured to If the processing of the current frame data is not completed in the VSync cycle, the current frame data continues to be processed in the predetermined duration of the delay; and the detection module is configured to not process the current frame data if the predetermined duration of the delay is not completed. , the processing of the current frame data is discarded, and the previous frame image is continuously displayed on the display.
  • an electronic device comprising: a display; a memory storing a computer program; and a processor that performs an improvement according to the present disclosure when the processor executes the computer program The method of image fluency.
  • a computer readable storage medium having stored thereon a computer program that, when executed by a processor, performs a method of improving image fluency in accordance with the present disclosure.
  • FIG. 1 and FIG. 2 are diagrams showing an example of synchronization of image processing and VSync of a CPU and a GPU in the related art
  • FIG. 3 is a schematic flow chart of a method for improving image fluency according to an embodiment of the present disclosure
  • VSync delay 4 is an exemplary diagram of a VSync delay in accordance with an embodiment of the present disclosure
  • FIG. 5 is a schematic structural diagram of an apparatus for improving image fluency according to an embodiment of the present disclosure
  • FIG. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure.
  • FIG. 7 is a flow chart showing an example of a method of improving image fluency according to an embodiment of the present disclosure.
  • FIG. 1 and 2 are diagrams showing an example of synchronization of image processing and VSync of a CPU and a GPU in the related art.
  • the present disclosure provides a technical solution for ensuring that the CPU and the GPU can process one frame of data in one cycle of the VSync by adjusting the cycle of the VSync in real time, thereby avoiding the jam and effectively improving the smoothness of the display.
  • the synchronization period of the VSync is extended by 1 to 2 milliseconds, so that the CPU And the GPU can process the frame data of this picture in the synchronization cycle of VSync, so as to ensure that the screen can display normally, so as to improve the smoothness of the system.
  • Embodiments of the present disclosure are applicable to scenes that are not very demanding in real-time but require high display effects, such as scenes in which video files are played.
  • the technical solution of the present disclosure can be implemented by an electronic device supporting video playback or image display.
  • the electronic device can be implemented in various forms.
  • the electronic device can be, but is not limited to, a mobile phone, a tablet computer, a notebook computer, a palmtop computer, a personal digital assistant (PDA), a portable media player (PMP), a navigation device.
  • PDA personal digital assistant
  • PMP portable media player
  • Mobile terminals such as wearable devices, smart bracelets, pedometers, and fixed terminals such as digital TVs and desktop computers.
  • FIG. 3 is a flow chart of a method for improving image fluency according to an embodiment of the present disclosure.
  • the method of improving image fluency according to an embodiment of the present disclosure may include steps 301 to 303.
  • processing of the current frame data begins when the VSync issued by the display arrives.
  • step 302 if the processing of the current frame data is not completed in the VSync cycle, the current frame data continues to be processed in the predetermined duration of the delay.
  • step 303 if the processing of the current frame data has not been completed in the predetermined time period of the delay, the processing of the current frame data is discarded and the display of the previous frame image on the display continues.
  • the display will issue a VSync after one frame of picture is drawn and before the next frame is prepared.
  • the display is refreshed at a fixed frequency, which is the frequency at which VSync is generated.
  • the VSync cycle can be delayed by setting a timer.
  • a timer is set in the processor, and the duration set for the timer may be the sum of the VSync period and the predetermined duration (for example, the VSync period is 16.7 milliseconds, and the predetermined duration is 2 milliseconds. The set duration is 16.7 + 2 milliseconds).
  • VSync arrives, the timer is triggered and starts timing. If the current frame data is still not processed when the timer reaches its set time, the processor will abandon the processing of the frame data and send an interrupt signal to the display. The display continues to display the previous frame. When the timer has not reached its set time, the processor will continue to process the current frame data until processing is complete.
  • the predetermined duration of the delay may be 1 to 2 milliseconds.
  • the predetermined duration may also be set to other values, which is not limited in the disclosure.
  • VSync delay 4 is an exemplary diagram of a VSync delay in accordance with an embodiment of the present disclosure.
  • the CPU and the GPU can be completed in the extended processing time by appropriately extending the processing time.
  • the processing of the current frame data ensures that the screen can be displayed normally.
  • the processing of the frame data may include: the CPU calculates the display content of the current frame data, and submits to the GPU after the calculation is completed; the GPU performs the transformation processing, the synthesis processing, the rendering processing, and submits the rendering result to the frame buffer; and the video controller The rendering result is read from the frame buffer and loaded on the display.
  • FIG. 5 is a schematic structural diagram of an apparatus for improving image fluency according to an embodiment of the present disclosure.
  • the apparatus for improving image fluency may include a trigger module 51, a delay module 52, and a detection module 53.
  • the trigger module 51 is arranged to begin processing the current frame data when the VSync issued by the display arrives.
  • the delay module 52 is arranged to continue processing the current frame data for a predetermined period of time delay if the processing of the current frame data is not completed in the VSync cycle.
  • the detection module 53 is arranged to abandon the processing of the current frame data if the processing of the current frame data has not been completed in the predetermined duration of the delay, and to continue displaying the previous frame image on the display.
  • the apparatus for improving image fluency may further include a timer.
  • the set duration of the timer is the sum of the VSync period and the predetermined duration of the delay. The timer starts timing when the vertical sync signal arrives, and when the timing of the timer has not reached its set duration, the trigger module 51 or the delay module 52 continues to process the current frame data until the processing of the current frame data is completed.
  • the detecting module 53 discards the processing of the current frame data and continues to display the previous frame image on the display. If the processing of the current frame data is completed before the timer's timing reaches its set duration, the display displays an image corresponding to the current frame data.
  • the predetermined duration of the delay may be 1 to 2 milliseconds.
  • the predetermined duration may also be set to other values, which is not limited in the disclosure.
  • the apparatus for improving image fluency may further include a CPU, a GPU, a frame buffer, and a video controller.
  • the CPU calculates the display content of the current frame data and submits it to the GPU after the calculation is completed.
  • the GPU performs transform processing, compositing processing, and rendering processing, the rendering result is submitted to the frame buffer.
  • the video controller reads the rendering result from the frame buffer and loads it on the display.
  • each of the above modules in this embodiment may be software, hardware, or a combination of the two.
  • each of the above modules may be implemented by a CPU in an electronic device (eg, a mobile phone).
  • the above apparatus of the embodiment can be applied to an electronic device supporting video playback or image display.
  • FIG. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure.
  • an electronic device in accordance with an embodiment of the present disclosure may include a display, a memory, and a processor (eg, a CPU and a GPU).
  • the memory stores a computer program that, when executed by the processor, performs a method of improving image fluency in accordance with various embodiments of the present disclosure.
  • the electronic device may also include, but is not limited to, a video controller and a bus, as shown in FIG.
  • the CPU, the GPU, and the memory are communicably connected to each other through a bus.
  • the CPU is responsible for calculating the display content and submitting it to the GPU.
  • the GPU is responsible for rendering and processing, and puts the rendering result into the frame buffer after the rendering is completed.
  • the video controller is responsible for reading the data of the frame buffer line by line according to VSync under the control of the GPU. And through the possible digital-to-analog conversion to the display for display.
  • Embodiments of the present disclosure also provide a computer readable storage medium having stored thereon a computer program that, when executed by a processor, performs a method of improving image fluency according to various embodiments of the present disclosure .
  • the computer readable storage medium is applicable to an electronic device according to the present disclosure.
  • FIG. 7 is a flow chart showing an example of a method of improving image fluency according to an embodiment of the present disclosure.
  • the flow according to the present example may include steps 701 to 708.
  • the display draws the Nth frame and displays it.
  • the display issues VSync before preparing the N+1th frame.
  • step 703 after the arrival of VSync, processing of the (N+1)th frame data is started.
  • step 704 it is judged whether or not the processing of the (N+1)th frame data is completed in the VSync cycle (i.e., 16.7 ms). If the processing is completed, step 707 is performed; if the processing is not completed, step 705 is continued.
  • the N+1th frame data continues to be processed in the delayed duration (e.g., 2 ms).
  • step 706 it is judged whether or not the processing of the (N+1)th frame data is completed in the length of the delay (for example, 2 ms). If the processing is completed, step 707 is performed; if the processing is not completed, step 708 is performed.
  • the display displays the N+1th frame.
  • step 708 the processing of the N+1th frame data is discarded, and the Nth frame picture continues to be displayed.
  • each module/unit in the above embodiment may be implemented in the form of hardware, for example, by implementing an integrated circuit to implement its corresponding function, or may be implemented in the form of a software function module, for example, executing a program stored in the memory by a processor. / instruction to achieve its corresponding function.
  • the present disclosure is not limited to any specific form of combination of hardware and software.

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Abstract

本公开提供了一种提高图像流畅度的方法及装置。所述方法包括:在显示器发出的垂直同步信号到来时,开始对当前帧数据进行处理;如果在垂直同步信号周期中没有完成当前帧数据的处理,则继续在延迟的预定时长中对当前帧数据进行处理;以及在所述延迟的预定时长中仍没有完成当前帧数据的处理,则放弃当前帧数据的处理,并继续在所述显示器上显示上一帧图像。

Description

一种提高图像流畅度的方法及装置 技术领域
本公开涉及(但不限于)终端技术领域。
背景技术
目前,电子设备(如手机)在处理芯片和屏幕之间基本都采用了移动产业处理器接口(Mobile Industry Processor Interface,MIPI)的传输协议,根据协议规定,又可以分为视频模式(video mode)和命令模式(cmd mode)两种方式传输,这两种模式下产生垂直同步信号(vertical synchronization,VSync)的方式也不同。如果采用video mode传输方式,则VSync同步信号是由电子设备的处理芯片发出的。以60fps的刷新率来计算,大约16.7毫秒产生一个VSync,也就是说,电子设备的处理芯片需要在这个时间内处理好要显示的图像,然后送至屏幕进行显示。但是由于芯片性能问题,以及多任务时资源竞争问题,有可能存在不能在16.7毫秒内处理完一帧图像的情况,这时处理芯片就要把上一帧图像再次发送给屏幕进行显示,也就是重复显示上一帧图像,这时用户就会明显感觉到卡顿现象。而针对此类卡顿问题,目前还未提出有效的解决方案。
发明内容
根据本公开实施例,提供了一种提高图像流畅度的方法,包括:在显示器发出的VSync到来时,开始对当前帧数据进行处理;如果在VSync周期中没有完成当前帧数据的处理,则继续在延迟的预定时长中对当前帧数据进行处理;以及如果在所述延迟的预定时长中仍没有完成当前帧数据的处理,则放弃当前帧数据的处理,并继续在所述显示器上显示上一帧图像。
根据本公开实施例,还提供一种提高图像流畅度的装置,包括:触发模块,其设置为在显示器发出的VSync到来时,开始对当前帧数据进行处理;延时模块,其设置为如果在VSync周期中没有完成当前 帧数据的处理,则继续在延迟的预定时长中对当前帧数据进行处理;以及检测模块,其设置为如果在所述延迟的预定时长中仍没有完成当前帧数据的处理,则放弃当前帧数据的处理,并继续在所述显示器上显示上一帧图像。
根据本公开实施例,还提供一种电子设备,包括:显示器;存储有计算机程序的存储器;以及处理器,当所述处理器执行所述计算机程序时,所述处理器执行根据本公开的提高图像流畅度的方法。
一种计算机可读存储介质,其上存储有计算机程序,当所述计算机程序被处理器执行时,所述处理器执行根据本公开的提高图像流畅度的方法。
本公开的其它特征和优点将在随后的说明书中阐述,并且,部分地从说明书中变得显而易见,或者通过实施本公开而了解。本公开的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本公开技术方案的进一步理解,并且构成说明书的一部分,与本公开的实施例一起用于解释本公开的技术方案,并不构成对本公开技术方案的限制。
图1和图2为相关技术中CPU、GPU的图像处理与VSync的同步示例图;
图3为根据本公开实施例的提高图像流畅度的方法流程示意图;
图4为根据本公开实施例的VSync延时的示例图;
图5为根据本公开实施例的提高图像流畅度的装置的结构示意图;
图6为根据本公开实施例的电子设备的示例性结构示意图;以及
图7为根据本公开实施例的提高图像流畅度方法的示例的流程示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白,下文中将结合附图对本公开的实施例进行详细说明。需要说明的是,在不冲突的情况下,本公开中的实施例及实施例中的特征可以相互任意组合。
在附图的流程图示出的步骤可以在诸如一组计算机可执行指令的计算机系统中执行。并且,虽然在流程图中示出了逻辑顺序,但是在某些情况下,可以以不同于此处的顺序执行所示出或描述的步骤。
图1和图2为相关技术中CPU、GPU的图像处理与VSync的同步示例图。
如图1所示,如果中央处理单元(Central Processing Unit,CPU)、图形处理单元(Graphics Processing Unit,GPU)在VSync的一个周期内处理完成一帧数据,那么该帧图像将在屏幕上正常显示,不会出现卡顿现象。如图2所示,如果CPU、GPU在VSync的一个周期内未能处理完成一帧数据,那么该帧图像将无法在屏幕上正常显示,将会出现卡顿现象。
针对此卡顿问题,本公开提供一种技术方案,通过实时调整VSync的周期来确保CPU、GPU在VSync的一个周期内能够处理完成一帧数据,从而避免卡顿,有效提高显示的流畅度。
根据本公开实施例,在某一次处理图像时,如果在VSync的同步周期(例如,16.7毫秒)内CPU和GPU的帧数据没有处理完,则将VSync的同步周期延长1至2毫秒,使CPU和GPU能够在VSync的同步周期内处理完此画面的帧数据,从而确保屏幕可正常显示画面,以提高系统的流畅度。本公开的实施例适用于对于实时性要求不是很高但对显示效果要求较高的场景,比如播放视频文件的场景。
本公开的技术方案可通过支持视频播放或图像显示的电子设备实现。该电子设备可以以各种形式来实施。例如,该电子设备可以为(但不限于)诸如手机、平板电脑、笔记本电脑、掌上电脑、个人数字助理(Personal Digital Assistant,PDA)、便捷式媒体播放器(Portable Media Player,PMP)、导航装置、可穿戴设备、智能手环、计步器等移动终端,以及诸如数字TV、台式计算机等固定终端。
下面对本公开技术方案的实现方式进行详细说明。
图3为根据本公开实施例的提高图像流畅度的方法流程示意图。
如图3所示,根据本公开实施例的提高图像流畅度的方法可以包括步骤301至303。
在步骤301,在显示器发出的VSync到来时,开始对当前帧数据进行处理。
在步骤302,如果在VSync周期中没有完成当前帧数据的处理,则继续在延迟的预定时长中对当前帧数据进行处理。
在步骤303,如果在延迟的预定时长中仍没有完成当前帧数据的处理,则放弃当前帧数据的处理,并继续在所述显示器上显示上一帧图像。
实际应用中,为了把显示器的显示过程和电子设备系统的视频控制器进行同步,当一帧画面绘制完成后,并且准备画下一帧前,显示器会发出一个VSync。通常,显示器以固定频率进行刷新,而这个刷新率就是产生VSync的频率。
根据本公开实施例,将VSync周期延迟预定时长可以有多种方式。在一种实现方式中,可以通过设置定时器的方式延迟VSync周期。例如,可以在开始处理每帧数据时,在处理器设置定时器,为定时器设定的时长可以为VSync周期与预定时长之和(比如,VSync周期是16.7毫秒是,预定时长是2毫秒,则设定的时长为16.7+2毫秒)。在VSync到来时定时器被触发并开始计时,如果在定时器计时达到其设定时长时当前帧数据仍没有处理完,则处理器将放弃该帧数据的处理,并向显示器发出中断信号,使得显示器继续显示上一帧画面,在定时器的计时未达到其设定时长,处理器将继续处理当前帧数据直到处理完成。
根据本公开实施例,延迟的预定时长可以为1至2毫秒。当然,所述预定时长也可以设置为其他值,本公开对此不作限制。
图4为根据本公开实施例的VSync延时的示例图。
如图4所示,采用本实施例的上述处理之后,可在某一帧数据的处理无法与VSync周期同步时,通过将处理时间适当延长,使CPU 和GPU能够在延长后的处理时间内完成当前帧数据的处理,从而确保屏幕可正常显示画面。
帧数据的处理可以包括:CPU计算当前帧数据的显示内容,并在计算完成后提交至GPU;GPU执行变换处理、合成处理、渲染处理之后,将渲染结果提交至帧缓冲区;以及视频控制器从所述帧缓冲区读取所述渲染结果并加载所述显示器上。
图5为根据本公开实施例的提高图像流畅度的装置的结构示意图。
如图5所示,根据本公开的提高图像流畅度的装置可以包括触发模块51、延时模块52和检测模块53。
触发模块51设置为在显示器发出的VSync到来时,开始对当前帧数据进行处理。
延时模块52设置为如果在VSync周期中没有完成当前帧数据的处理,则继续在延迟的预定时长中对当前帧数据进行处理。
检测模块53设置为如果在所述延迟的预定时长中仍没有完成当前帧数据的处理,则放弃当前帧数据的处理,并继续在所述显示器上显示上一帧图像。
根据本公开实施例的提高图像流畅度的装置还可以包括定时器。定时器的设定时长为VSync周期与所述延迟的预定时长之和。定时器在垂直同步信号到来时开始计时,并且在定时器的计时未达到其设定时长时,使得触发模块51或延时模块52持续对当前帧数据进行处理,直到完成当前帧数据的处理。
根据本公开实施例,如果在定时器的计时达到其设定时长时仍没有完成当前帧数据的处理,则检测模块53放弃当前帧数据的处理,并继续在所述显示器上显示上一帧图像;如果在定时器的计时达到其设定时长之前完成了当前帧数据的处理,则显示器显示与当前帧数据对应的图像。
根据本公开实施例,延迟的预定时长可以为1至2毫秒。。当然,所述预定时长也可以设置为其他值,本公开对此不作限制。
根据本公开实施例的提高图像流畅度的装置还可以包括CPU、 GPU、帧缓冲区和视频控制器。CPU计算当前帧数据的显示内容,并在计算完成后提交至GPU。GPU执行变换处理、合成处理、渲染处理之后,将渲染结果提交至帧缓冲区。视频控制器从帧缓冲区读取所述渲染结果并加载显示器上。
实际应用中,本实施例的上述中各模块分别可以是软件、硬件或两者的结合。比如,上述各模块可以由电子设备(比如,手机)中的CPU实现。实际应用中,本实施例的上述装置可以应用于支持视频播放或图像显示的电子设备。
图6为根据本公开实施例的电子设备的示例性结构示意图。
如图6所示,根据本公开实施例的电子设备可以包括显示器、存储器和处理器(例如,CPU和GPU)。存储器存储有计算机程序,当处理器执行所述计算机程序时,处理器执行根据本公开各实施例的提高图像流畅度的方法。
在一种实现方式中,电子设备还可以包括(但不限于)视频控制器以及总线,如图6所示。CPU、GPU、存储器通过总线彼此通信地连接。CPU负责计算显示内容并提交到GPU,GPU负责渲染等处理并在渲染完成后将渲染结果放入帧缓冲区,视频控制器负责在GPU的控制下按照VSync逐行读取帧缓冲区的数据,并经过可能的数模转换传递给显示器进行显示。
本公开实施例还提供一种计算机可读存储介质,其上存储有计算机程序,当所述计算机程序被处理器执行时,所述处理器执行根据本公开各实施例的提高图像流畅度的方法。
实际应用中,该计算机可读存储介质可应用于根据本公开的电子设备。
下面对上述各实施例的示例性实现方式进行详细说明。需要说明的是,下文各示例可任意结合。并且,在实际应用中,上述各实施例还可以有其他的实现方式,下文示例中各流程、执行过程等也可以根据实际应用的需要进行调整。
在本示例中,以显示器刷新频率为60fps为例来详细说明提高图像流畅度的实现流程。
图7为根据本公开实施例的提高图像流畅度方法的示例的流程示意图。
如图7所示,根据本示例的流程可以包括步骤701至708。
在步骤701,显示器绘制完成第N帧画面并进行显示。
在步骤702,准备第N+1帧画面前,显示器发出VSync。
在步骤703,在VSync到来后,开始处理第N+1帧数据。
在步骤704,判断在VSync周期(即,16.7ms)中是否完成第N+1帧数据的处理。如果完成处理,则执行步骤707;如果未完成处理,则继续执行步骤705。
在步骤705,在延迟的时长(例如,2ms)中继续处理第N+1帧数据。
在步骤706,判断在延迟的时长(例如,2ms)中是否完成第N+1帧数据的处理。如果完成处理,则执行步骤707;如果未完成处理,则执行步骤708。
在步骤707,显示器显示第N+1帧画面。
在步骤708,放弃第N+1帧数据的处理,并继续显示第N帧画面。
本领域普通技术人员可以理解上述方法中的全部或部分步骤可通过程序来指令相关硬件(例如处理器)完成,所述程序可以存储于计算机可读存储介质中,如只读存储器、磁盘或光盘等。可选地,上述实施例的全部或部分步骤也可以使用一个或多个集成电路来实现。相应地,上述实施例中的各模块/单元可以采用硬件的形式实现,例如通过集成电路来实现其相应功能,也可以采用软件功能模块的形式实现,例如通过处理器执行存储于存储器中的程序/指令来实现其相应功能。本公开不限制于任何特定形式的硬件和软件的结合。
以上显示和描述了本公开的基本原理和主要特征和本公开的优点。本公开不受上述实施例的限制,上述实施例和说明书中描述的只是说明本公开的原理,在不脱离本公开精神和范围的前提下,本公开还会有各种变化和改进,这些变化和改进都落入要求保护的本公开范围内。

Claims (12)

  1. 一种提高图像流畅度的方法,包括:
    在显示器发出的垂直同步信号到来时,开始对当前帧数据进行处理;
    如果在垂直同步信号周期中没有完成当前帧数据的处理,则继续在延迟的预定时长中对当前帧数据进行处理;以及
    如果在所述延迟的预定时长中仍没有完成当前帧数据的处理,则放弃当前帧数据的处理,并继续在所述显示器上显示上一帧图像。
  2. 根据权利要求1所述的方法,其中,设置定时器,所述定时器的设定时长为所述垂直同步信号周期与所述延迟的预定时长之和,所述定时器在垂直同步信号到来时开始计时,并且在所述定时器的计时未达到其设定时长时持续对当前帧数据进行处理,直到完成当前帧数据的处理。
  3. 根据权利要求2所述的方法,其中,
    如果在所述定时器的计时达到其设定时长时仍没有完成当前帧数据的处理,则放弃当前帧数据的处理,并继续在所述显示器上显示上一帧图像,
    如果在所述定时器的计时达到其设定时长之前完成了当前帧数据的处理,则所述显示器显示与当前帧数据对应的图像。
  4. 根据权利要求1至3任一项所述的方法,其中,所述延迟的预定时长为1至2毫秒。
  5. 根据权利要求1所述的方法,其中,对当前帧数据进行处理的步骤包括:
    中央处理单元计算当前帧数据的显示内容,并在计算完成后提交至图形处理单元;
    图形处理单元执行变换处理、合成处理、渲染处理之后,将渲染结果提交至帧缓冲区;以及
    视频控制器从所述帧缓冲区读取所述渲染结果并加载所述显示器上。
  6. 一种提高图像流畅度的装置,包括:
    触发模块,其设置为在显示器发出的垂直同步信号到来时,开始当前帧数据的处理;
    延时模块,其设置为如果在垂直同步信号周期中没有完成当前帧数据的处理,则继续在延迟的预定时长中对当前帧数据进行处理;以及
    检测模块,其设置为如果在所述延迟的预定时长中仍没有完成当前帧数据的处理,则放弃当前帧数据的处理,并继续在所述显示器上显示上一帧图像。
  7. 根据权利要求6所述的装置,还包括:
    定时器,所述定时器的设定时长为所述垂直同步信号周期与所述延迟的预定时长之和,所述定时器在垂直同步信号到来时开始计时,并且在所述定时器的计时未达到其设定时长时,使得所述触发模块或所述延时模块持续对当前帧数据进行处理,直到完成当前帧数据的处理。
  8. 根据权利要求7所述的装置,其中,
    如果在所述定时器的计时达到其设定时长时仍没有完成当前帧数据的处理,则所述检测模块放弃当前帧数据的处理,并继续在所述显示器上显示上一帧图像,
    如果在所述定时器的计时达到其设定时长之前完成了当前帧数据的处理,则所述显示器显示与当前帧数据对应的图像。
  9. 根据权利要求6至8任一项所述的装置,其中,所述延迟的 预定时长为1至2毫秒。
  10. 根据权利要求6所述的装置,还包括中央处理单元、图形处理单元、帧缓冲区和视频控制器,其中,
    所述中央处理单元计算当前帧数据的显示内容,并在计算完成后提交至所述图形处理单元,
    所述图形处理单元执行变换处理、合成处理、渲染处理之后,将渲染结果提交至所述帧缓冲区,并且
    所述视频控制器从所述帧缓冲区读取所述渲染结果并加载所述显示器上。
  11. 一种电子设备,包括显示器、存储器和处理器,其中,
    所述存储器存储有计算机程序,
    当所述处理器执行所述计算机程序时,所述处理器执行根据权利要求1至5任一项所述的提高图像流畅度的方法。
  12. 一种计算机可读存储介质,其上存储有计算机程序,当所述计算机程序被处理器执行时,所述处理器执行根据权利要求1至5中任一项所述的提高图像流畅度的方法。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113805831A (zh) * 2021-09-15 2021-12-17 Oppo广东移动通信有限公司 图像数据传输方法、装置、终端及介质
WO2024098871A1 (zh) * 2022-11-07 2024-05-16 荣耀终端有限公司 数据处理方法、设备及存储介质

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110018874B (zh) * 2019-04-09 2021-07-13 Oppo广东移动通信有限公司 垂直同步方法、装置、终端及存储介质
CN111656797A (zh) * 2019-06-25 2020-09-11 深圳市大疆创新科技有限公司 控制方法、图像传输系统、显示装置及无人机系统
CN110609645B (zh) * 2019-06-25 2021-01-29 华为技术有限公司 一种基于垂直同步信号的控制方法及电子设备
CN113140173B (zh) * 2020-01-17 2023-01-13 华为技术有限公司 显示驱动器及控制方法、显示控制电路系统、电子设备
WO2021142780A1 (en) * 2020-01-17 2021-07-22 Qualcomm Incorporated Methods and apparatus for reducing frame latency
CN113327554B (zh) 2020-02-28 2022-07-08 北京小米移动软件有限公司 显示控制方法和装置、驱动模组、电子设备
CN111752520A (zh) * 2020-06-28 2020-10-09 Oppo广东移动通信有限公司 图像显示方法、装置、电子设备和计算机可读存储介质
CN116847039A (zh) * 2020-09-30 2023-10-03 华为技术有限公司 一种基于垂直同步信号的图像处理方法及电子设备
CN112422873B (zh) * 2020-11-30 2022-09-16 Oppo(重庆)智能科技有限公司 插帧方法、装置、电子设备及存储介质
CN113225600B (zh) * 2021-04-30 2022-08-26 卡莱特云科技股份有限公司 一种防止led显示屏出现闪屏问题的方法及装置
CN113364767B (zh) * 2021-06-03 2022-07-12 北京字节跳动网络技术有限公司 一种流媒体数据显示方法、装置、电子设备及存储介质
CN113781949B (zh) * 2021-09-26 2023-10-27 Oppo广东移动通信有限公司 图像显示方法、显示驱动芯片、显示屏模组及终端

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1143331A2 (en) * 2000-04-07 2001-10-10 Sony Corporation Image procesing apparatus and method of the same, and display apparatus using the image processing apparatus
CN1697483A (zh) * 2004-05-13 2005-11-16 索尼公司 图像显示装置
CN101039442A (zh) * 2006-03-13 2007-09-19 硕颉科技股份有限公司 影像处理方法及装置
CN102291529A (zh) * 2010-06-16 2011-12-21 精工爱普生株式会社 摄影装置以及定时控制电路

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI314017B (en) * 2006-07-12 2009-08-21 Quanta Comp Inc System and method for synchronizing video frames and audio frames
US8754904B2 (en) * 2011-04-03 2014-06-17 Lucidlogix Software Solutions, Ltd. Virtualization method of vertical-synchronization in graphics systems
US8797340B2 (en) * 2012-10-02 2014-08-05 Nvidia Corporation System, method, and computer program product for modifying a pixel value as a function of a display duration estimate
JP6515455B2 (ja) * 2014-07-22 2019-05-22 セイコーエプソン株式会社 撮像装置及び撮像表示装置
US9679345B2 (en) * 2014-08-08 2017-06-13 Advanced Micro Devices, Inc. Method and system for frame pacing
US9811388B2 (en) * 2015-05-14 2017-11-07 Qualcomm Innovation Center, Inc. VSync aligned CPU frequency governor sampling
US9728166B2 (en) * 2015-08-20 2017-08-08 Qualcomm Incorporated Refresh rate matching with predictive time-shift compensation
US10019968B2 (en) * 2015-12-31 2018-07-10 Apple Inc. Variable refresh rate display synchronization
US10462336B2 (en) * 2017-03-15 2019-10-29 Microsoft Licensing Technology, LLC Low latency tearing without user perception

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1143331A2 (en) * 2000-04-07 2001-10-10 Sony Corporation Image procesing apparatus and method of the same, and display apparatus using the image processing apparatus
CN1697483A (zh) * 2004-05-13 2005-11-16 索尼公司 图像显示装置
US20050253878A1 (en) * 2004-05-13 2005-11-17 Sony Corporation Image display device
CN101039442A (zh) * 2006-03-13 2007-09-19 硕颉科技股份有限公司 影像处理方法及装置
CN102291529A (zh) * 2010-06-16 2011-12-21 精工爱普生株式会社 摄影装置以及定时控制电路

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3681143A4 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113805831A (zh) * 2021-09-15 2021-12-17 Oppo广东移动通信有限公司 图像数据传输方法、装置、终端及介质
CN113805831B (zh) * 2021-09-15 2024-01-30 Oppo广东移动通信有限公司 图像数据传输方法、装置、终端及介质
WO2024098871A1 (zh) * 2022-11-07 2024-05-16 荣耀终端有限公司 数据处理方法、设备及存储介质

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