WO2018220675A1 - Relay device and error correction method - Google Patents

Abstract

A relay device (20) relays data between a transmission station (10) and a reception station (30), and is characterized by being provided with an error-correction decoding unit (22) that carries out error-correction decoding on data transmitted by the transmission station (10), the error-correction decoding unit using an error correction decoding method which differs from the error-correction decoding method used by the reception unit (30).

Description

Relay device and error correction method

The present invention relates to a relay apparatus and an error correction method for performing error correction processing on data transmitted between a transmitting station and a receiving station.

In the field of data communication, a technique is generally used in which data is subjected to error correction coding at a transmitting station, error correction decoding is performed at a receiving station, and errors occurring during data transmission are corrected. As the data transmission distance increases, errors that occur during transmission increase and transmission quality often decreases. For this reason, a technique for error correction decoding has been proposed not only at a receiving station but also at a relay device that relays data between a transmitting station and a receiving station. In addition, in data transmission by satellite, it is conceivable to install a relay device on a geostationary satellite when transmitting observation satellite data traveling in a low orbit to a fixed station on the ground in real time. Similarly, it is possible to apply an error correction technique to a relay device mounted on a geostationary satellite.

The relay device described in Patent Document 1 performs error correction decoding on the received data, and transmits the decoded data again after error correction encoding. In the technique described in Patent Document 1, the relay apparatus performs error correction coding using the same method as that used for error correction decoding. That is, the error correction decoding method used by the relay apparatus and the error correction decoding method used by the receiving terminal station are the same.

JP 2008-258701 A

However, in the technique described in Patent Document 1, there is a high possibility that the error rate in the transmission path between the transmission station and the relay apparatus is different from the error rate in the transmission path between the relay apparatus and the reception station. Regardless, the error correction method used is the same. For this reason, in the transmission path on the side where the error rate is low, the error correction processing becomes overspec, the calculation amount increases, and power is wasted.

The present invention has been made in view of the above, and an object of the present invention is to obtain a relay device capable of correcting an error occurring during transmission while reducing power consumption for error correction.

In order to solve the above-described problems and achieve the object, the present invention is a relay device that relays data between a transmitting station and a receiving station, and is different from an error correction decoding method used by the receiving station. An error correction decoding unit that performs error correction decoding on the data transmitted by the transmitting station using the method is provided.

The relay apparatus according to the present invention has an effect that it is possible to correct errors that occur during transmission while reducing power consumption for error correction.

The figure which shows the structure of the error correction system concerning Embodiment 1 of this invention. The figure which shows the structural example of the data concatenatedly encoded by the transmitting station concerning Embodiment 2 of this invention. The figure which shows the structural example of the error correction encoding part which produces | generates the coding data of the structural example shown in FIG. The figure which shows the modification of the structure of the data concatenatedly encoded by the transmitting station concerning Embodiment 2 of this invention. The figure which shows the structure of the error correction system concerning Embodiment 3 of this invention. The figure which shows the structure of the comparative example of the error correction series which the error correction system shown in FIG. 5 uses. The figure which shows the hardware constitutions which implement | achieve the function of the error correction apparatus concerning Embodiment 1 to Embodiment 4.

Hereinafter, a relay device and an error correction method according to an embodiment of the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

Embodiment 1 FIG.
FIG. 1 is a diagram showing a configuration of an error correction system 1 according to the first exemplary embodiment of the present invention. The error correction system 1 according to the first embodiment includes an error correction device 11 provided in the transmission station 10, an error correction device 21 provided in the relay device 20, and an error correction device 31 provided in the reception station 30. . The error correction device 11 of the transmission station 10 has an error correction encoding unit 12. The error correction device 21 of the relay device 20 has a first error correction decoding unit 22. The error correction device 31 of the receiving station 30 has a second error correction decoding unit 32.

The error correction encoding unit 12 of the transmitting station 10 is an encoder that generates an error correction sequence 40 in which the information bits 41 are encoded and the error correction code 42 is added, and transmits the generated error correction sequence 40. The error correction sequence 40 transmitted from the error correction encoding unit 12 is sent to the first error correction decoding unit 22 of the relay device 20.

The first error correction decoding unit 22 of the relay apparatus 20 receives the error correction sequence 40 transmitted from the transmission station 10, performs error correction decoding processing on the received error correction sequence 40, and the error correction sequence 40 is transmitted to the transmission station 10. This is a decoder that corrects errors that occur during transmission between the relay device 20 and the relay device 20. The first error correction decoding unit 22 transmits the error correction sequence 40 after correcting the error as an error correction sequence 43. When it is detected that error correction is impossible, the first error correction decoding unit 22 transmits the received error correction sequence 40 as it is as the error correction sequence 43 without performing error correction decoding processing. Here, the first error correction decoding unit 22 performs an error correction decoding process using an error correction decoding method different from that of the second error correction decoding unit 32 of the receiving station 30.

The second error correction decoding unit 32 of the receiving station 30 is a decoder that receives the error correction sequence 43 transmitted from the first error correction decoding unit 22 and performs error correction decoding processing on the received error correction sequence 43. An information bit 41 in which an error occurring therein is corrected is obtained. As described above, the second error correction decoding unit 32 performs error correction decoding processing using an error correction decoding method different from that of the first error correction decoding unit 22 of the relay device 20.

The error correction decoding method used by the first error correction decoding unit 22 is determined based on the magnitude of the error rate that occurs in the transmission path between the transmission station 10 and the relay device 20. The error correction decoding method used by the second error correction decoding unit 32 is determined based on the magnitude of the error rate that occurs in the transmission path between the relay device 20 and the receiving station 30. When the error rate between the transmission station 10 and the relay device 20 is smaller than the error rate between the relay device 20 and the reception station 30, the error correction decoding method used by the first error correction decoding unit 22 of the relay device 20 The correction capability may be lower than the correction capability of the error correction decoding method used by the second error correction decoding unit 32 of the receiving station 30.

Generally, the higher the correction capability of the error correction decoding method, the larger the circuit scale and power consumption for error correction. For this reason, it becomes possible for the relay apparatus 20 and the receiving station 30 to optimize the power consumption for error correction by using an error correction decoding method having a correction capability according to the error rate. It is possible to suppress the use of an overspec error correction decoding method. Therefore, it is possible to correct errors that occur during transmission while reducing power consumption for error correction.

For example, the error correction decoding method used by the first error correction decoding unit 22 may be a hard decision decoding method, and the error correction decoding method used by the second error correction decoding unit 32 may be a soft decision decoding method. The hard-decision decoding method is a method of performing decoding processing after determining received data to be 0 or 1 before decoding processing. The soft decision decoding method calculates a log-likelihood ratio (LLR) indicating the degree of likelihood of 0 or 1 of received data by a plurality of bits and performs decoding using the log likelihood ratio. This is a method of processing. The hard decision process has a lower correction capability than the soft decision process, but the circuit scale for executing the hard decision process is smaller than that of the soft decision process, and power consumption can be reduced.

For example, the transmitting station 10 may be mounted on a low-orbit observation satellite, the relay device 20 may be mounted on a geostationary satellite that relays observation satellite data, and the receiving station 30 may be a ground station. In such an error correction system 1, since it is required to reduce the power consumption of the relay device 20 mounted on the geostationary satellite, it is desirable to change the error correction decoding method between the relay device 20 and the receiving station 30.

In the above description, the first error correction decoding unit 22 and the second error correction decoding unit 32 use different types of error correction decoding methods. However, the present invention is not limited to this example. The error correction decoding method used by the first error correction decoding unit 22 and the error correction decoding method used by the second error correction decoding unit 32 may be different in power consumption for the error correction decoding process. The error correction decoding method used by the first error correction decoding unit 22 and the error correction decoding method used by the second error correction decoding unit 32 are error correction decoding methods having different correction capabilities.

The error correction decoding method used by the first error correction decoding unit 22 and the error correction decoding method used by the second error correction decoding unit 32 are the same type of error correction decoding methods, and the error correction decoding methods having different processing contents It may be. For example, when an algebraic code such as BCH (Bose Chaudhuri Hocquenghem) code or Reed-Solomon code is used, the maximum number of corrections in error correction decoding processing is limited to a value smaller than the number of corrections that can be corrected. Electric power can be reduced. In addition, when iterative decoding such as LDPC (Low-Density Parity-check Code) code or turbo code is used, power consumption can be reduced by limiting the number of repetitions.

Further, in the error correction system 1 according to the first embodiment, the coding rate of data to be transmitted does not change during transmission from the transmitting station 10 to the receiving station 30, so it is necessary to adjust the transmission rate in the relay device 20. There is no. For this reason, an additional circuit for speed adjustment processing including retiming is not required, and an increase in circuit scale can be suppressed.

Embodiment 2. FIG.
In the first embodiment, the transmission station 10 transmits the error correction sequence 40 encoded using a single error correction code. However, in the second embodiment, the transmission station 10 transmits information bits to information bits. A concatenated code protected by a plurality of error correction code sequences is used.

FIG. 2 is a diagram illustrating a configuration example of data that is concatenatedly encoded by the transmitting station 10 according to the second embodiment of the present invention. Since the configuration of the error correction system 1 according to the second exemplary embodiment is the same as the configuration of the first exemplary embodiment illustrated in FIG. 1, the description thereof is omitted here.

The error correction encoding unit 12 of the transmitting station 10 divides the information bit sequence to be transmitted into a plurality of blocks 50 including an information bit area 51 and a parity bit area 52. In the following description, when each of the plurality of blocks 50 is distinguished, a hyphen and a number are added after the block 50 to indicate a block 50-1, a block 50-2, and the like. Similarly, for the information bit area 51 and the parity bit area 52, when distinguishing each of the plurality of information bit areas 51 and the plurality of parity bit areas 52, a hyphen and a number are added to the information bit area 51-1, the parity bit area 52, and the parity bit area 52. The bit area 52-1 is shown.

Each block 50 is a square of N bits in the vertical direction and N bits in the horizontal direction, and the information bit area 51 is arranged from the head of the block 50 in N bits in the vertical direction and K bits in the horizontal direction. The parity bit area 52 is arranged in the vertical direction N bits and the horizontal direction NK bits following the information bit area 51 of the block 50.

The concatenated encoded data is an error correction code sequence extending over a plurality of blocks 50, and bit replacement is performed using different rules for each block 50. For example, the code length is 2N bits, and the BCH code having an information length of N + K bits is configured in N series in parallel in the vertical direction. The BCH code sequence is encoded from the beginning for each block 50. As will be described later, the encoding in units of two blocks is performed by shifting the leading block one block at a time, so that each block has BCH encoding as the latter block, BCH encoding as the leading block, Are encoded by both BCH encodings. Thereby, one information bit is included in two BCH code sequences. The parity bit area 52 of the BCH code in the first block of the two blocks is an information bit series, and the parity bits of the BCH code series are arranged in the parity bit area 52 of the second block.

For example, in a sequence in which BCH encoding is performed with block 50-2 as the first block, a codeword generated in BCH encoding with block 50-1 as the first block is stored in the parity bit area 52-2 of block 50-2. Parity bits are arranged. When BCH encoding is performed with the block 50-2 as the first block, the data in the parity bit region 52-2 is treated as information bits, and the parity bits of the codeword obtained by this BCH encoding are stored in the parity bit region 52- 3 is arranged. Further, when BCH encoding is performed with the block 50-3 as the head block, the data in the parity bit area 52-3 is treated as information bits, and the parity bits of the codeword obtained by this BCH encoding are stored in the parity bit area. 52-4. In each BCH encoding, as described above, bit replacement using a different rule for each block 50 is performed, so that the position in the horizontal direction of each encoded sequence is shifted for each BCH encoding. In addition, the arrow line shown in FIG. 2 has shown the encoding direction of one of N code words in parallel.

In block 50, data is input in parallel in N bits every clock for N series in parallel. That is, one bit is input to each series every clock. Then, parallel N-bit bit replacement is performed for each clock, and bits whose positions in the parallel direction are switched are input to each series. Encoding in units of two blocks is performed by shifting the leading block one block at a time, so that each block has both BCH coding as the latter half block and BCH coding as the leading block. It is encoded by encoding. In the first block and the second half block, the direction of bit replacement in the parallel direction is opposite. As a result, an error correction code sequence over a plurality of blocks is configured, information bits indicating the same content information are included in two different BCH code sequences, and a concatenated code configuration in which different encoding processes are performed for each block Become.

FIG. 3 is a diagram illustrating a configuration example of the error correction encoding unit 12 that generates encoded data having the configuration illustrated in FIG. The error correction coding unit 12 includes a selector 121a and a selector 121b, a bit switching circuit 122a and a bit switching circuit 122b, a plurality of BCH coding circuits 123a and a plurality of BCH coding circuits 123b, a bit reverse switching circuit 124a and bits. A reverse switching circuit 124b and a selector 125 are included.

The information bit is input to both the selector 121a and the selector 121b. The selector 121a inputs information bits or N bits selected from the output of the bit reverse switching circuit 124b described later to the bit switching circuit 122a every clock. The selector 121b inputs N bits selected from the information bits or the output of the bit reverse switching circuit 124a described later to the bit switching circuit 122b every clock. In the configuration shown in FIG. 3, the encoding process is performed in parallel with two systems. A BCH code sequence starting at the odd-numbered block 50 from the head is generated from the N bits output from the selector 121a, and a BCH code sequence starting at the even-numbered block 50 from the N-bit output from the selector 121b. Is generated.

Bit exchange circuit 122a and bit exchange circuit 122b barrel-shift the input from selector 121a and selector 121b downward or upward for each input, and exchange the bit positions in the parallel direction for output. Here, the direction in which the bit switching circuit 122a performs the barrel shift is opposite to the direction in which the bit switching circuit 122b performs the barrel shift. That is, when the bit swapping circuit 122a performs a barrel shift upward, the bit swapping circuit 122b performs a barrel shift downward, and when the bit swapping circuit 122a performs a barrel shift downward, the bit swapping circuit 122b performs a barrel shift upward.

Bits output from the bit exchange circuit 122a are input bit by bit from the BCH encoding circuit 123a-1 to the BCH encoding circuit 123a-N. The bits output from the bit switching circuit 122b are input bit by bit to the BCH encoding circuit 123b-1 to the BCH encoding circuit 123b-N, respectively. The BCH encoding circuit 123a generates parity bits of the BCH code sequence of the odd-numbered block 50 from the beginning, that is, the block 50-1 and the block 50-3, and the BCH code sequence, and simultaneously inputs the information bit sequence. Is output. The BCH encoding circuit 123b generates parity bits of a BCH code sequence of an even-numbered block 50 from the head, that is, a block 50-2 and a block 50-4, and a BCH code sequence as a head block, and simultaneously inputs the information bit sequence Is output. Each of the BCH encoding circuit 123a and the BCH encoding circuit 123b outputs a parity bit of the generated BCH code following the N + K-bit information bit sequence.

The output of the BCH encoding circuit 123a is input to the bit reverse switching circuit 124a, and the output of the BCH encoding circuit 123b is input to the bit reverse switching circuit 124b. The bit reverse exchange circuit 124a performs a barrel shift opposite to that of the bit exchange circuit 122a, and the bit reverse exchange circuit 124b performs a barrel shift opposite to that of the bit exchange circuit 122b. The output of N bits output from the bit reverse switching circuit 124a and the bit reverse switching circuit 124b is input to the selector 125, and the output of the bit reverse switching circuit 124a is input to the selector 121b, and the output of the bit reverse switching circuit 124b. Is input to the selector 121a.

The selector 125 selects either the output of the bit reverse switching circuit 124a or the output of the bit reverse switching circuit 124b and outputs it as an N-bit code bit sequence. The selector 125 selects and outputs the side with the new BCH parity sequence. It should be noted that information bits are input to the selector 121a and the selector 121b as follows: the selector 121a, the selector 121b, the bit switching circuit 122a, the bit switching circuit 122b, the BCH encoding circuit 123a, the BCH encoding circuit 123b, the bit reverse switching circuit 124a and the bit. Considering the processing delay of the reverse switching circuit 124b, the parity bit sequence and the information bit sequence are input so as to be continuous.

FIG. 4 is a diagram showing a modification of the configuration of data that is concatenatedly encoded by the transmitting station 10 according to the second embodiment of the present invention. In the configuration shown in FIG. 2, a plurality of blocks are continuously encoded without termination, but in the modification shown in FIG. 4, concatenated encoding is performed within a finite number of blocks.

In the present modification, each of the plurality of blocks 53 includes an information bit area 54 and a parity bit area 55. Each block 53 is a square of N bits in the vertical direction and N bits in the horizontal direction, and the information bit area 54 is arranged from the head of the block 53 in N bits in the vertical direction and K bits in the horizontal direction. The parity bit area 55 is arranged in the vertical direction N bits and the horizontal direction NK bits following the information bit area 54 of the block 53.

The error correction encoding unit 12 encodes the parity bit region 55-1 as all zeros for the BCH encoding starting from the block 53-1. Subsequently, the error correction encoding unit 12 performs encoding while performing bit replacement including the information bit area 54-2 of the block 53-2, and converts the parity bit generated by the encoding into the parity bit area 55 of the block 53-2. -2. Thereafter, the processing up to block 53-3 is the same as the example shown in FIG.

In the BCH encoding starting from the block 53-4 which is the terminal block, the error correction encoding unit 12 is the head block following the information bit area 54-4 and the parity bit area 55-4 of the block 53-4. The information bits arranged in the information bit area 54-1 of the block 53-1 are encoded. Then, the error correction encoding unit 12 arranges the generated parity bits in the parity bit area 56 arranged subsequent to the block 53-4.

In the above description, the generated parity bit is arranged in the parity bit area 56 arranged after the block 53-4. However, the present invention is not limited to such an example. Instead of the parity bit area 56, parity bits may be arranged in the parity bit area 55-1 of the block 53-1, which is the head block.

In order to realize this modification, the error correction encoding unit 12 arranges a bit having a value of 0 in the parity bit area 55-1 of the block 53-1, which is the first block, in addition to the configuration shown in FIG. And means for holding the result of parity generation processing up to the middle of the block 53-1 which is the head block in the BCH encoding circuit 123b. In addition, the error correction encoding unit 12 generates a parity bit by combining the result of the parity generation processing up to the middle of the block 53-1, which is the first block, and the result of the parity generation processing in the block 53-4; Means for causing the bit reverse switching circuit 124 to output a parity bit area 56.

In the second embodiment, the example using the BCH code has been described. However, the present invention is not limited to such an example. For example, other codes such as a Reed-Solomon code may be used. When using a Reed-Solomon code, it is desirable to perform the bit replacement process for each symbol of the Reed-Solomon code.

In the second embodiment, an example of forming a square block has been described. However, rectangular blocks having different numbers of bits in the vertical direction and the horizontal direction may be used.

When the transmitting station 10 transmits a code bit sequence as shown in FIG. 2 as the error correction sequence 40, the relay device 20 performs error correction decoding by partially correcting the error without decoding the entire code sequence. The circuit scale required for processing, that is, power consumption can be reduced. For example, the first error correction decoding unit 22 of the relay device 20 can perform the correction process only on the BCH code sequence starting from the odd-numbered block 50.

Alternatively, the first error correction decoding unit 22 may perform error correction processing on all BCH code sequences. In this case, power consumption can be reduced by limiting the number of repetitions of the error correction process to a small number.

The first error correction decoding unit 22 transmits the error correction sequence 43 after performing the error correction processing to the receiving station 30. The error correction sequence 43 is obtained by correcting the error of the error correction sequence 40, and the error correction code 42 does not change.

The second error correction decoding unit 32 of the receiving station 30 corrects errors that occur between the relay device 20 and the receiving station 30. The second error correction decoding unit 32 can also correct this error when an error generated between the transmitting station 10 and the relay device 20 remains in the received error correction sequence 43. When the error rate between the relay device 20 and the receiving station 30 is higher than the error rate between the transmission station 10 and the relay device 20, the second error correction decoding unit 32 is more than the first error correction decoding unit 22. High correction capability is desirable. For example, the correction capability can be increased by increasing the number of iterative correction processes of the second error correction decoding unit 32 to be greater than the number of iterative correction processes of the first error correction decoding unit 22. In decoding, it is also conceivable to improve the correction capability by using the soft decision decoding method rather than using the hard decision decoding method.

Note that the concatenated encoding method shown in the second embodiment can also be used for communication between a transmitting station and a receiving station without using a relay device.

Also, the concatenated encoding method shown in the second embodiment is an example, and other code configurations such as a product code may be used.

Embodiment 3 FIG.
FIG. 5 is a diagram showing a configuration of the error correction system 2 according to the third exemplary embodiment of the present invention. The error correction system 2 includes an error correction device 11 provided in the transmission station 10, an error correction device 21 provided in the relay device 20, and an error correction device 31 provided in the reception station 30. The error correction device 11 of the transmission station 10 has a first error correction encoding unit 13. The error correction device 21 of the relay device 20 includes a first error correction decoding unit 23 and a second error correction encoding unit 24. The error correction device 31 of the receiving station 30 has a second error correction decoding unit 33.

In the first and second embodiments, the error correction code 42 added by the transmitting station 10 is transmitted to the receiving station 30 as it is. In the third embodiment, the second error correction encoding unit 24 of the relay device 20 performs the encoding process again, and the first error correction code 62 included in the first error correction sequence 60 is changed to the second error correction code 60. A second error correction sequence 63 that is replaced with the correction code 65 is generated. It is desirable to apply the configuration of the third embodiment when the relay device 20 has sufficient capability for performing the encoding process.

Note that the second error correction coding unit 24 performs coding so that the coding rate of the data transmitted by the relay device 20 is equal to the coding rate of the data received by the relay device 20. The information bits 61 included in the second error correction sequence 63 are the same as the information bits 61 included in the first error correction sequence 60, and the number of bits of the first error correction code 62 is the second error correction code 65. Is equal to the number of bits. For this reason, the first error correction sequence 60 and the second error correction sequence 63 have the same coding rate and frame structure, and have different error correction code configurations.

The configuration of the error correction system 2 is the same as the configuration of the error correction system 1 except that the relay device 20 includes the second error correction encoding unit 24. That is, the first error correction encoding unit 13 of the transmitting station 10 is the same as the error correction encoding unit 12 except for the functions described below. The first error correction decoding unit 23 of the relay apparatus 20 is the same as the first error correction decoding unit 22 except that the data is output to the second error correction encoding unit 24 instead of the receiving station 30. The second error correction decoding unit 33 of the receiving station 30 is the same as the second error correction decoding unit 32.

FIG. 6 is a diagram showing a configuration of a comparative example of error correction sequences used by the error correction system 2 shown in FIG. An error correction sequence 70 shown in FIG. 5 is an error correction sequence 70 in accordance with DVB (Digital Video Broadcasting) -S2, which is a standard for digital television broadcasting. BBHEADER is an area where control information is stored, DATA FIELD is an area where user data is stored, and PADDING is an area for adjusting the sequence length. BCH FEC is an area in which parity bits obtained by BCH encoding using DATA FIELD and PADDING as information bits are stored. LDPCFEC is an area for storing parity bits that are LDPC-encoded using BBFRAME as information bits when BBHEADER, DATA FIELD, PADDING, and BCH FEC are BBFRAME. The error correction sequence 70 is a concatenated code in which the BCH code is an outer code and the LDPC code is an inner code. The code length of the LDPC code is 16200 bits or 64800 bits, and the BBFRAME length is variable depending on the coding rate of the LDPC code.

When the error rate between the transmitting station 10 and the relay device 20 is relatively small, when the LDPC code is used, the relay device 20 must decode 64800 bits at a time, which increases the circuit scale and power consumption. Will increase.

For this reason, the first error correction coding unit 13 of the transmitting station 10 according to the third embodiment uses an algebraic block code such as a BCH code and a Reed-Solomon code or a concatenated code instead of the LDPC code. The first error correction encoding unit 13 includes a first error correction sequence 60 in which encoded parity bits obtained by an encoding process using a code other than the LDPC code are arranged at a parity length of 32400 bits of the LDPC code. Generate and send.

When the encoding configuration shown in FIGS. 2 and 4 is used, the first error correction encoding unit 13 can divide 64,800 bits into 8 blocks and code length 2N = 180 bits, where N = 90 bits, information length A BCH code having a length of N + K = 135 bits and a 5-bit correction can be configured. When N = 180 bits, 64800 bits can be divided into two blocks. A 10-bit corrected BCH code can be configured with a code length of 2N = 360 bits and an information length of N + K = 270 bits. The remainder of the parity bit area in the block is adjusted using padding.

According to the third embodiment, it is possible to improve the correction capability by changing the error correction code in the relay device 20. At this time, since the coding rate of the data received by the relay device 20 and the data to be transmitted does not change, it is not necessary to adjust the transmission rate in the relay device 20. For this reason, it is not necessary to provide an additional circuit for retiming processing in transmission rate adjustment processing, and it is possible to suppress an increase in power consumption by suppressing an increase in circuit scale.

Embodiment 4 FIG.
In the first to third embodiments, the number of apparatuses that relay data between the transmitting station 10 and the receiving station 30 is one. However, the present invention is not limited to such an example. There may be a plurality of relay apparatuses 20 that transmit data between the transmitting station 10 and the receiving station 30. For example, when the data transmitted by the transmission station 10 is transmitted to the reception station 30 via the relay device 20-1 and the relay device 20-2, the relay device 20-1 transmits the transmission station 10 and the relay device 20-1 to each other. It is preferable that the relay apparatus 20-2 use an error correction method according to the error rate between the relay apparatus 20-1 and the relay apparatus 20-2. .

In Embodiments 1 to 3, the case where the error rate between the transmission station 10 and the relay device 20 is mainly lower than the error rate between the relay device 20 and the reception station 30 has been described. However, when the error rate between the transmission station 10 and the relay device 20 is higher than the error rate between the relay device 20 and the reception station 30, the relay device 20 has a correction capability higher than that of the reception station 30. A high error correction method may be used.

It should be noted that the functions of the error correction apparatuses 11, 21, 31 can be realized using an encoder and a decoder which are dedicated processing circuits. For example, the error correction encoding unit 12 is an encoder, and the first error correction decoding unit 22 and the second error correction decoding unit 32 are decoders.

Alternatively, the functions of the error correction apparatuses 11, 21, 31 may be realized using software. FIG. 7 is a diagram illustrating a hardware configuration that implements the functions of the error correction apparatuses 11, 21, and 31 according to the first to fourth embodiments. The functions of the error correction apparatuses 11, 21, and 31 can be realized using a processing circuit including a processor 201 and a memory 202.

The processor 201 is a CPU (Central Processing Unit) and is also called a central processing unit, a processing unit, an arithmetic unit, a microprocessor, a microcomputer, a DSP (Digital Signal Processor), or the like. The memory 202 is, for example, a non-volatile or volatile semiconductor memory such as RAM (Random Access Memory), ROM (Read Only Memory), flash memory, EPROM (Erasable Programmable ROM), EEPROM (Electrically EPROM), magnetic disk, flexible Disks, optical disks, compact disks, mini disks, DVDs (Digital Versatile Disks), etc.

The processor 201 reads out the computer program stored in the memory 202 and executes the read computer program, whereby the functions of the error correction encoding unit 12, the first error correction decoding unit 22, and the second error correction decoding unit 32 are performed. Can be realized.

The configuration described in the above embodiment shows an example of the contents of the present invention, and can be combined with another known technique, and can be combined with other configurations without departing from the gist of the present invention. It is also possible to omit or change the part.

1, 2 error correction system, 10 transmission station, 11, 21, 31 error correction device, 12 error correction coding unit, 13 first error correction coding unit, 20 relay device, 22, 23 first error correction decoding unit, 24, second error correction coding unit, 30 receiving station, 32, 33 second error correction decoding unit, 40, 43, 70 error correction series, 41 information bits, 42 error correction code, 50, 50-1, 50-2 , 50-3, 50-4, 53, 53-1, 53-2, 53-3, 53-4 block, 51, 51-1, 54, 54-1, 54-2, 54-4 information bit area , 52, 52-1, 55, 55-1, 55-2, 55-4, 56 parity bit area, 60 first error correction sequence, 61 information bits, 62 first error correction code, 63 second error Correction series, 65 2 error correction code, 121a, 121b, 125 selector, 122a, 122b bit exchange circuit, 123a, 123b, 123a-1, 123b-1, 123b-N BCH encoding circuit, 124, 124a, 124b bit reverse exchange circuit, 201 Processor, 202 memory.

Claims (9)

1. A relay device that relays data between a transmitting station and a receiving station,
   Using an error correction decoding method different from the error correction decoding method used by the receiving station, an error correction decoding unit that performs error correction decoding of the data transmitted by the transmitting station;
   A relay device comprising:
2. The relay apparatus according to claim 1, wherein the error correction decoding unit uses an error correction decoding method having a correction capability different from that of the error correction decoding method used by the receiving station.
3. 3. The relay apparatus according to claim 1, wherein the error correction decoding unit performs error correction decoding on the data encoded using a plurality of error correction encoding methods.
4. The data is an error correction code sequence over a plurality of blocks composed of an information bit region and a parity bit region, and information bits indicating information of the same content are arranged in a plurality of error correction code sequences, 4. The relay apparatus according to claim 3, wherein the information bits are subjected to different encoding processes for each error correction code sequence.
5. 5. The relay apparatus according to claim 4, wherein the block size is a common divisor or common multiple of 64800 bits or 16200 bits.
6. An error correction encoding unit that performs error correction encoding on the data that has been subjected to error correction decoding by the error correction decoding unit;
   The relay apparatus according to claim 1, further comprising:
7. The coding rate of the data transmitted by the relay device is equal to the coding rate of the data received by the relay device,
   The relay apparatus according to any one of claims 1 to 6, wherein a configuration of an error correction code of data transmitted by the relay apparatus is different from a configuration of an error correction code of data received by the relay apparatus. .
8. The relay apparatus according to any one of claims 1 to 7, wherein the relay apparatus is mounted on a geostationary satellite, and the receiving station is a ground station.
9. A transmitting station transmitting error correction encoded data; and
   A relay device performing error correction decoding on the data transmitted by the transmitting station;
   The relay device transmitting the data after the error correction decoding; and
   A receiving station performing error correction decoding on the data transmitted by the relay device using an error correction decoding method different from an error correction decoding method used by the relay device;
   An error correction method comprising:

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