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WO2018210186A1 - 薄膜晶体管及其制作方法、阵列基板和显示面板 - Google Patents

薄膜晶体管及其制作方法、阵列基板和显示面板 Download PDF

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Publication number
WO2018210186A1
WO2018210186A1 PCT/CN2018/086513 CN2018086513W WO2018210186A1 WO 2018210186 A1 WO2018210186 A1 WO 2018210186A1 CN 2018086513 W CN2018086513 W CN 2018086513W WO 2018210186 A1 WO2018210186 A1 WO 2018210186A1
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Prior art keywords
layer
thin film
film transistor
light shielding
substrate
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PCT/CN2018/086513
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English (en)
French (fr)
Inventor
王铖铖
李贺飞
宫奎
董必良
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京东方科技集团股份有限公司
合肥京东方光电科技有限公司
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Priority to US16/326,775 priority Critical patent/US20190207037A1/en
Publication of WO2018210186A1 publication Critical patent/WO2018210186A1/zh

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    • H01L29/78609—
    • H01L29/78633—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H01L27/1214—
    • H01L29/42384—
    • H01L29/66742—
    • H01L29/78696—

Definitions

  • the present disclosure relates to the field of semiconductor technologies, and in particular, to a thin film transistor and a method of fabricating the same, an array substrate, and a display panel.
  • flat panel displays have become mainstream products on the market, and there are more and more types of flat panel displays, such as liquid crystal displays (LCDs) and organic light emitting diodes (Organic Light Emitting Diodes). OLED) display, plasma display panel (PDP) and Field Emission Display (FED).
  • LCDs liquid crystal displays
  • OLED organic light emitting diodes
  • PDP plasma display panel
  • FED Field Emission Display
  • TFT Thin Film Transistor
  • An aspect of the present disclosure provides a thin film transistor including: a light shielding layer disposed over a base substrate; and an active layer disposed over the light shielding layer.
  • the light shielding layer is provided with a groove on one side facing the active layer, and the orthographic projection of the active layer on the base substrate is located in the orthographic projection on the base substrate on the bottom surface of the groove.
  • the light shielding layer is a gate
  • the thin film transistor further includes: a gate insulating layer disposed between the light shielding layer and the active layer; and a source and a drain disposed over the active layer .
  • the thin film transistor further includes: a passivation layer disposed between the light shielding layer and the active layer; a gate insulating layer disposed over the active layer; disposed on the gate insulating layer a gate electrode; an interlayer insulating layer disposed over the gate; and a source and a drain disposed over the interlayer insulating layer.
  • the source is connected to the active layer through the first via
  • the drain is connected to the active layer through the second via.
  • the groove has an opening depth of from 1000 angstroms to 10,000 angstroms.
  • the light shielding layer is metal and the opening depth of the groove is 1700 angstroms.
  • the light shielding layer is a black matrix material
  • the opening depth of the groove is 5000 ⁇ to 7500 ⁇ .
  • the angle between the inner sidewall of the groove and the bottom of the groove is greater than or equal to 90°.
  • Another aspect of the present disclosure provides an array substrate including any of the above thin film transistors.
  • a further aspect of the present disclosure provides a display panel including a backlight, and any of the above array substrates, wherein the array substrate is disposed on a light exiting side of the backlight.
  • Yet another aspect of the present disclosure provides a method of fabricating a thin film transistor, comprising: forming a light shielding layer having a groove over a base substrate; and forming an active layer over the light shielding layer.
  • the orthographic projection of the active layer on the substrate is within the orthographic projection of the bottom surface of the recess on the substrate.
  • forming a light shielding layer having a groove over a base substrate includes: forming a first film layer over the substrate substrate; forming a first film layer through the halftone mask A patterned photoresist layer having regions of different thicknesses.
  • the patterned photoresist layer includes a first region and a second region, the second region having a thickness less than a thickness of the first region.
  • the orthographic projection of the bottom surface of the recess on the base substrate completely overlaps the orthographic projection of the second region on the base substrate.
  • Forming a light shielding layer having a groove on the base substrate further comprising: removing a portion of the first film layer not covered by the patterned photoresist layer; removing the photoresist layer of the second region; thinning and A portion of the first film layer corresponding to the two regions; removing the remaining photoresist layer.
  • thinning a portion of the first film layer corresponding to the second region includes: etching a portion of the first film layer corresponding to the second region by a preset duration to make the second region The thickness of the portion of the corresponding first film layer is halved.
  • FIG. 1 is a schematic structural view of a typical thin film transistor
  • FIG. 2 is a schematic structural diagram of a bottom gate thin film transistor according to an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of a top gate thin film transistor according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of a bottom gate type thin film transistor in which a top area of a recess is larger than a bottom area according to an embodiment of the present disclosure
  • FIG. 5 is a flow chart of fabricating a bottom gate thin film transistor according to an embodiment of the present disclosure
  • FIG. 6 is a schematic view of a photoresist layer being formed and illuminated when illuminated according to an embodiment of the present disclosure
  • FIG. 7 is a schematic structural view of a bottom gate thin film transistor after forming a patterned photoresist layer according to an embodiment of the present disclosure
  • FIG. 8 is a schematic structural diagram of a bottom gate thin film transistor after removing a photoresist layer of a second region according to an embodiment of the present disclosure
  • FIG. 9 is a schematic structural diagram of a bottom gate thin film transistor after removing a gate metal thin film layer corresponding to a second region according to an embodiment of the present disclosure
  • FIG. 10 is a schematic structural diagram of a bottom gate thin film transistor after halving the thickness of a gate metal film corresponding to a second region according to an embodiment of the present disclosure
  • FIG. 11 is a schematic structural diagram of a bottom gate thin film transistor after removing a remaining photoresist layer according to an embodiment of the present disclosure
  • FIG. 12 is a schematic structural diagram of a bottom gate type thin film transistor after forming a gate electrode according to an embodiment of the present disclosure
  • FIG. 13 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.
  • the thin film transistor includes a gate electrode 12 disposed over a substrate substrate 11, and a gate insulating layer 13 disposed over the gate electrode 12.
  • An active layer 14 disposed over the gate insulating layer 13 and a source 15 and a drain 16 disposed on the active layer 14 are provided.
  • the thin film transistor is typically designed as a bottom gate structure in which the active layer 14 is blocked by the gate 12 to avoid photo-induced leakage current. But this design does not completely block all of the light from the backlight.
  • light from a backlight may still be incident on the active layer after being reflected and refracted, thereby increasing the probability of generation of electron-hole pairs by illumination, thereby generating photo-generated leakage current.
  • the structure of the thin film transistor cannot effectively reduce the leakage current, and therefore the thin film transistor still has a large leakage current, which in turn causes the display panel formed thereof to easily cause crosstalk and splash screen problems.
  • FIG. 2 schematically illustrates a thin film transistor in accordance with an embodiment of the present disclosure.
  • the thin film transistor includes: a light shielding layer 22 disposed over the substrate substrate 21; and an active layer 24 disposed over the light shielding layer 22.
  • the light shielding layer 22 is provided with a recess 20 on a side facing the active layer 24, wherein the orthographic projection of the active layer 24 on the base substrate 21 is located in the orthographic projection of the bottom surface of the recess 20 on the base substrate 21.
  • the groove 20 is disposed on one side of the light shielding layer facing the active layer, and the orthographic projection of the active layer 24 on the substrate substrate 21 is located in the orthographic projection of the bottom surface of the groove 20 on the substrate substrate 21.
  • the light shielding layer 22 can be made to have a mask-like effect, thereby preventing the light generated by the backlight from being reflected or refracted to the active layer 24, thereby minimizing the leakage current generated by the illumination and greatly improving the thin film transistor.
  • the characteristic is to avoid the crosstalk caused by the excessive leakage current of the thin film transistor and the malfunction of the splash screen, thereby improving the display quality.
  • the thin film transistor provided by the embodiment of the present disclosure may be a bottom gate thin film transistor or a top gate thin film transistor.
  • the light shielding layer in the embodiment of the present disclosure may be a light shielding or light absorbing material such as a dark resin, or may be directly used by the gate, that is, on the side of the gate facing the active layer. Groove.
  • the light shielding layer may be a separate film layer different from the gate electrode. Specifically, a groove may be provided on a side of the light shielding layer facing the active layer to effectively block illumination of light from the backlight.
  • the thin film transistor is a bottom gate type thin film transistor, and the gate serves as a light shielding layer 22.
  • the bottom gate thin film transistor further includes a gate insulating layer 23 disposed between the light shielding layer 22 and the active layer 24, and a source 25 and a drain electrode 26 disposed over the active layer 24.
  • the gate when used as the light shielding layer, it is required that the gate itself includes a light shielding material.
  • the material of the gate electrode may specifically be Mo/Al, Mo/Nd or Al/Nd.
  • the thin film transistor is a top gate type thin film transistor as shown in FIG.
  • the top gate thin film transistor further includes a passivation layer 210 disposed between the light shielding layer 22 and the active layer 24; a gate insulating layer 23 disposed over the active layer 24; disposed above the gate insulating layer 23. a gate electrode 29; an interlayer insulating layer 213 disposed over the gate electrode 29; and a source electrode 25 and a drain electrode 26 disposed over the interlayer insulating layer 213.
  • the source 25 is connected to the active layer 24 through the first via 211, and the drain 26 is connected to the active layer 24 through the second via 212.
  • the material of the light shielding layer may be a black resin.
  • the opening depth of the groove is from 1000 angstroms to 10,000 angstroms in order to enable the light shielding layer to more effectively block light from the backlight. If the light shielding layer is metal, in particular, the opening depth of the groove may be 1700 angstroms. If the light shielding layer is made of a black matrix material, the opening depth of the groove may be 5000 ⁇ to 7500 ⁇ .
  • the angle between the inner sidewall of the groove and the bottom of the groove is greater than or equal to 90°.
  • the cross-sectional pattern of the opening of the groove 20 in the direction perpendicular to the surface of the substrate may be rectangular or inverted trapezoidal as shown in FIGS. 2 and 4, respectively.
  • An embodiment of the present disclosure further provides an array substrate including any of the above thin film transistors.
  • the embodiment of the present disclosure further provides a display panel including a backlight, and any one of the above array substrates, wherein the array substrate is disposed on a light exiting side of the backlight.
  • the embodiment of the present disclosure further provides a method of fabricating a thin film transistor.
  • the manufacturing method includes: at step 101, forming a light shielding layer having a groove on a base substrate; and at step 102, An active layer is formed over the light shielding layer, wherein the orthographic projection of the active layer on the substrate substrate is within an orthographic projection of the bottom surface of the recess on the substrate substrate.
  • forming a light shielding layer having a groove over a base substrate specifically comprising: forming a first film layer over the substrate substrate; forming a first color layer through the halftone mask a patterned photoresist layer having regions of different thicknesses, wherein the patterned photoresist layer comprises a first region and a second region, the thickness of the second region being less than the thickness of the first region, and the bottom surface of the recess is
  • the orthographic projection on the substrate substrate completely overlaps with the orthographic projection of the second region on the substrate; removing portions of the first film layer that are not covered by the patterned photoresist layer; removing the photoresist layer of the second region Thinning a portion of the first film layer corresponding to the second region; and removing the remaining photoresist layer.
  • the grooves can be formed by a half mask process.
  • the thinning of the portion of the first film layer corresponding to the second region includes: etching a predetermined duration of the first film layer corresponding to the second region to make the first film layer corresponding to the second region The thickness is halved.
  • a thin film transistor is used as the bottom gate type thin film transistor and the gate serves as a light shielding layer as an example, and will be described with reference to FIGS. 6 to 12 . It should be noted that the concepts of the present disclosure are equally applicable to top gate type thin film transistors.
  • a gate metal film 220 is deposited on the base substrate 21 by, for example, a magnetron sputtering method, and a photoresist layer 4 is coated on the gate metal film 220 as shown in FIG.
  • a photoresist is used as a positive photoresist as an example. It should be noted, however, that a negative photoresist can be employed in other embodiments of the present disclosure.
  • the base substrate may be a glass substrate.
  • the photoresist layer 4 is exposed and developed using a half-tone mask.
  • the AB area and the EF area in the mask 5 are all transparent areas, the BC area and the DE area are opaque areas, and the CD area is a semi-transmissive area, as shown in FIG.
  • the photoresist corresponding to the all-transmissive region of the mask 5 is removed, the photoresist corresponding to the semi-transmissive region of the mask 5 is partially retained, and corresponds to the opaque of the mask 5.
  • the photoresist of the region is completely retained, and a patterned photoresist layer 4 having a thickness smaller than that in the first region 41 in the second region 42 is formed as shown in FIG.
  • the light shielding material layer 220' is as shown in FIG.
  • the photoresist layer 4 at the second region 42 is removed by a dry etching process as shown in FIG.
  • the etching time is controlled by a dry or wet etching process to thin the thickness of the light shielding material layer 220' corresponding to the second region 42, as shown in FIG.
  • the thickness of the light shielding material layer 220' corresponding to the second region 42 can be halved.
  • the remaining photoresist layer 4 is removed using a lift-off process to obtain the final light-shielding layer 22, as shown in FIG.
  • the above manufacturing method may further include: obtaining a gate insulating layer 23 and an active material layer by a gas deposition method, and patterning the active material layer to obtain the active layer 24 such that the active layer 24 is on the base substrate 21.
  • the orthographic projection is located in the orthographic projection of the bottom surface of the recess on the base substrate 21, as shown in FIG.
  • the above fabrication method may further include forming a source 25 and a drain 26 over the active layer 24, and forming an insulating protective layer 27 and a pixel electrode 28 over the source 25 and the drain 26 to obtain a final array.
  • the substrate is as shown in FIG.
  • a recess is provided on a side of the light shielding layer facing the active layer, and an orthographic projection of the active layer on the base substrate is located in an orthographic projection on a base substrate of the bottom surface of the recess,
  • the light shielding layer can be made to have a mask-like effect, thereby preventing the light generated by the backlight from being reflected or refracted to the active layer, thereby minimizing the leakage current generated by the illumination, greatly improving the characteristics of the TFT device, and thereby avoiding
  • the display panel has improved crosstalk due to excessive leakage current of the thin film transistor and a splash screen, thereby improving display quality.

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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

一种薄膜晶体管及其制作方法、阵列基板和显示面板。薄膜晶体管包括：设置在衬底基板（21）之上的遮光层（22）；以及设置在遮光层（22）之上的有源层（24）。遮光层（22）在面向有源层（24）的一面设置有凹槽（20），并且有源层（24）在衬底基板（21）上的正投影位于凹槽（20）的底面在衬底基板（21）上的正投影内。

Description

薄膜晶体管及其制作方法、阵列基板和显示面板
相关申请
本申请要求享有2017年5月15日提交的中国专利申请No.201710338853.X的优先权，其全部公开内容通过引用并入本文。
技术领域
本公开涉及半导体技术领域，尤其涉及一种薄膜晶体管及其制作方法、阵列基板和显示面板。
背景技术
目前，平面显示器(Flat Panel Display，FPD)己成为市场上的主流产品，并且平面显示器的种类也越来越多，如液晶显示器(Liquid Crystal Display，LCD)、有机发光二极管(Organic Light Emitting Diode，OLED)显示器、等离子体显示面板(Plasma Display Panel，PDP)及场发射显示器(Field Emission Display，FED)等。
与此同时，作为FPD产业核心技术的薄膜晶体管(Thin Film Transistor，TFT)背板技术，也在经历着深刻的变革。然而，串扰和闪屏不良一直是伴随平面显示器的顽固不良，其中一个主要的原因是薄膜晶体管关态时漏电流太大。漏电流主要来自于沟道中的空穴电流和光照产生的漏电流。
发明内容
本公开的一方面提供了一种薄膜晶体管，包括：设置在衬底基板之上的遮光层；以及设置在遮光层之上的有源层。遮光层在面向有源层的一面设置有凹槽，并且有源层在衬底基板上的正投影位于凹槽的底面在衬底基板上的正投影内。
根据本公开的一些实施例，遮光层为栅极，并且薄膜晶体管还包括：设置在遮光层与有源层之间的栅极绝缘层；以及设置在有源层之上的源极和漏极。
根据本公开的一些实施例，上述薄膜晶体管还包括：设置在遮光层与有源层之间的钝化层；设置在有源层之上的栅极绝缘层；设置在 栅极绝缘层之上的栅极；设置在栅极之上的层间绝缘层；以及设置在层间绝缘层之上的源极和漏极。源极通过第一过孔与有源层连接，并且漏极通过第二过孔与有源层连接。
根据本公开的一些实施例，凹槽的开口深度为1000埃～10000埃。
根据本公开的一些实施例，遮光层为金属，并且凹槽的开口深度为1700埃。
根据本公开的一些实施例，遮光层为黑矩阵材质，并且凹槽的开口深度为5000埃～7500埃。
根据本公开的一些实施例，凹槽的内部侧壁与凹槽的底部之间的夹角大于或等于90°。
本公开的另一方面提供了一种阵列基板，包括上述任一种薄膜晶体管。
本公开另外的方面提供了一种显示面板，包括背光源，以及上述任一种阵列基板，其中阵列基板设置在背光源的出光侧。
本公开的又一方面提供了一种薄膜晶体管的制作方法，包括：在衬底基板之上形成具有凹槽的遮光层；以及在遮光层之上形成有源层。有源层在衬底基板上的正投影在凹槽的底面在衬底基板上的正投影内。
根据本公开的一些实施例，在衬底基板之上形成具有凹槽的遮光层，包括：在衬底基板之上形成第一膜层；通过半色调掩模板，在第一膜层之上形成具有不同厚度区域的图案化的光刻胶层。图案化的光刻胶层包括第一区域和第二区域，第二区域的厚度小于第一区域的厚度。凹槽的底面在衬底基板上的正投影与第二区域在衬底基板上的正投影完全重叠。在衬底基板之上形成具有凹槽的遮光层，还包括：去除未被图案化的光刻胶层覆盖的第一膜层的部分；去除第二区域的光刻胶层；减薄与第二区域对应的第一膜层的部分；去除剩余的光刻胶层。
根据本公开的一些实施例，减薄与第二区域对应的第一膜层的部分，包括：对与第二区域对应的第一膜层的部分刻蚀预设时长，以使与第二区域对应的第一膜层的部分的厚度减半。
附图说明
图1为典型的薄膜晶体管的结构示意图；
图2为本公开实施例提供的一种底栅型薄膜晶体管的结构示意图；
图3为本公开实施例提供的一种顶栅型薄膜晶体管的结构示意图；
图4为本公开实施例提供的一种其中凹槽的顶部面积大于底部面积的底栅型薄膜晶体管的结构示意图；
图5为本公开实施例提供的一种底栅型薄膜晶体管的制作流程图；
图6为根据本公开实施例，在制作完成光刻胶层并进行光照时的示意图；
图7为根据本公开实施例，在形成图案化的光刻胶层后的底栅型薄膜晶体管的结构示意图；
图8为根据本公开实施例，在去除第二区域的光刻胶层后的底栅型薄膜晶体管的结构示意图；
图9为根据本公开实施例，在去除与第二区域对应的栅极金属薄膜层后的底栅型薄膜晶体管的结构示意图；
图10为根据本公开实施例，在将与第二区域对应的栅极金属薄膜的厚度减半后的底栅型薄膜晶体管的结构示意图；
图11为根据本公开实施例，在去除剩余光刻胶层后的底栅型薄膜晶体管的结构示意图；
图12为根据本公开实施例，在形成栅极后的底栅型薄膜晶体管的结构示意图；以及
图13为本公开实施例提供的一种阵列基板的结构示意图。
具体实施方式
下面结合说明书附图对本公开实施例的实现过程进行详细说明。需要注意的是，自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本公开，而不能理解为对本公开的限制。
图1图示了一种典型的薄膜晶体管，如图1所示，该薄膜晶体管包括：设置在衬底基板11之上的栅极12，设置在栅极12之上的栅极绝缘层13，设置在栅极绝缘层13之上的有源层14，设置在有源层14上的源极15和漏极16。为了防止薄膜晶体管在背光源的照射下产生过大的漏电流，典型地将该薄膜晶体管设计成其中有源层14被栅极12遮挡的底栅结构，来避免光生漏电流。但是这种设计不能完全地遮挡 来自背光源的全部光线。例如，来自背光源的光线在经过反射和折射后仍旧可能入射到有源层，从而通过光照来增加电子空穴对的产生概率，进而产生光生漏电流。由此可见，该薄膜晶体管的结构并不能有效地降低漏电流，因此该薄膜晶体管仍旧具有较大的漏电流，进而导致由其形成的显示面板容易产生串扰和闪屏的问题。
图2示意性地图示了根据本公开实施例的薄膜晶体管。参见图2，该薄膜晶体管包括：设置在衬底基板21之上的遮光层22；设置在遮光层22之上的有源层24。遮光层22在面向有源层24的一面设置有凹槽20，其中，有源层24在衬底基板21上的正投影位于凹槽20的底面在衬底基板21上的正投影内。
本公开实施例通过在遮光层面向有源层的一面设置凹槽20，并使有源层24在衬底基板21上的正投影位于凹槽20的底面在衬底基板21上的正投影内，可以使遮光层22起到类似遮罩的效果，从而避免背光源产生的光线经反射或折射后照射到有源层24，因而可以将光照产生的漏电流降到最低，极大地改善薄膜晶体管的特性，避免显示面板由于薄膜晶体管的漏电流过大而产生的串扰和闪屏的不良，提高显示品质。
在具体实施时，本公开实施例提供的薄膜晶体管可以为底栅型薄膜晶体管，也可以为顶栅型薄膜晶体管。对于底栅型薄膜晶体管，本公开实施例中的遮光层可以为如深色树脂之类的遮光或者吸光材料，或者可直接由栅极充当，即在栅极的面向有源层的一侧设置凹槽。而对于顶栅型薄膜晶体管，其遮光层可以为不同于栅极的独立膜层。具体地，可以在遮光层的面向有源层的一侧设置凹槽，以便有效遮挡来自背光源的光的照射。以下通过具体实施例对两种结构的薄膜晶体管进行举例说明。
在示例实施例中，如图2所示，薄膜晶体管为底栅型薄膜晶体管，并且栅极充当遮光层22。该底栅型薄膜晶体管还包括设置在遮光层22与有源层24之间的栅极绝缘层23，以及设置在有源层24之上的源极25和漏极26。
需要说明的是，在这样的实施例中，当将栅极作为遮光层时，需要栅极本身包括遮光材料。例如，栅极的材质具体可以是Mo/Al、Mo/Nd或Al/Nd。
在另一示例实施例中，薄膜晶体管为顶栅型薄膜晶体管，如图3所示。该顶栅型薄膜晶体管还包括设置在遮光层22与有源层24之间的钝化层210；设置在有源层24之上的栅极绝缘层23；设置在栅极绝缘层23之上的栅极29；设置在栅极29之上的层间绝缘层213；以及设置在层间绝缘层213之上的源极25和漏极26。源极25通过第一过孔211与有源层24连接，并且漏极26通过第二过孔212与有源层24连接。
对于顶栅型薄膜晶体管，遮光层的材质可以为黑色树脂。
在示例性实施例中，为了使遮光层能够更加有效地遮挡来自背光源的光，凹槽的开口深度为1000埃～10000埃。如果遮光层为金属，具体地，凹槽的开口深度可以为1700埃。如果遮光层为黑矩阵材质，凹槽的开口深度可以为5000埃～7500埃。
在示例性实施例中，凹槽的内部侧壁与凹槽的底部之间的夹角大于或等于90°。具体地，例如，凹槽20的开口在垂直于衬底基板的面方向上的截面图形可以为矩形或倒梯形，分别如图2和图4所示。
本公开实施例还提供一种阵列基板，包括上述任一种薄膜晶体管。
本公开实施例还提供一种显示面板，包括背光源，以及上述任一种阵列基板，其中阵列基板设置在背光源的出光侧。
本公开实施例还提供一种薄膜晶体管的制作方法，如图5所示，该制作方法包括：在步骤101处，在衬底基板之上形成具有凹槽的遮光层；以及在步骤102处，在遮光层之上形成有源层，其中，有源层在衬底基板上的正投影位于凹槽的底面在衬底基板上的正投影内。
在示例性实施例中，在衬底基板之上形成具有凹槽的遮光层，具体包括：在衬底基板之上形成第一膜层；通过半色调掩模板，在第一膜层之上形成具有不同厚度区域的图案化的光刻胶层，其中，所述图案化的光刻胶层包括第一区域和第二区域，第二区域的厚度小于第一区域的厚度，凹槽的底面在衬底基板上的正投影与第二区域在衬底基板上的正投影完全重叠；去除未被图案化的光刻胶层覆盖的第一膜层的部分；去除第二区域的光刻胶层；减薄与第二区域对应的第一膜层的部分；以及去除剩余的光刻胶层。
为了简化工艺制作，可以通过半掩模工艺形成凹槽。以上的减薄与第二区域对应的第一膜层的部分，具体包括：对与第二区域对应的 第一膜层刻蚀预设时长，以使与第二区域对应的第一膜层的厚度减半。
为了更详细地对本公开实施例提供的薄膜晶体管的制作方法进行说明，以下以薄膜晶体管为底栅型薄膜晶体管并且栅极充当遮光层为例，结合图6至图12进行说明。应当指出的是，本公开的概念同样适用于顶栅型薄膜晶体管。
首先，在衬底基板21上采用例如磁控溅射方法沉积栅极金属膜220，并且在栅极金属膜220之上涂覆光刻胶层4，如图6所示。以下以光刻胶为正性光刻胶为例进行说明。但是应当指出的是，在本公开的其它实施例中可以采用负性光刻胶。衬底基板可以为玻璃基板。
然后，采用半阶调掩模板对光刻胶层4进行曝光和显影。掩模板5中的AB区、EF区为全透光区，BC区、DE区为不透光区，并且CD区为半透光区，如图6所示。在显影之后，对应于掩模板5的全透光区的光刻胶被去除，对应于掩模板5的半透光区的光刻胶被部分保留下来，并且对应于掩模板5的不透光区的光刻胶被全部保留下来，形成在第二区域42中的厚度小于在第一区域41中的厚度的图案化的光刻胶层4，如图7所示。
接着，采用湿法刻蚀工艺，将未被光刻胶覆盖的栅极金属膜220的部分去除，并且对应于图案化的光刻胶层4的栅极金属膜220的部分被保留下来，形成遮光材料层220’，如图8所示。
然后，采用干法刻蚀工艺将第二区域42处的光刻胶层4去除，如图9所示。
接着，采用干法或湿法刻蚀工艺，控制刻蚀时间以减薄与第二区域42对应的遮光材料层220’的厚度，如图10所示。特别地，与第二区域42对应的遮光材料层220’的厚度可以减半。
最后，采用剥离工艺将剩余的光刻胶层4除去，得到最后的遮光层22，如图11所示。
进一步地，上述制作方法还可以包括：采用气体沉积法得到栅极绝缘层23及有源材料层，图案化有源材料层以得到有源层24，使得有源层24在衬底基板21上的正投影位于凹槽的底面在衬底基板21上的正投影内，如图12所示。
另外，上述制作方法还可以包括在有源层24之上形成源极25和漏极26，并且在源极25和漏极26之上形成绝缘保护层27和像素电极 28，以便得到最终的阵列基板，如图13所示。
在本公开的实施例中，通过在遮光层面向有源层的一面设置凹槽，并使有源层在衬底基板上的正投影位于凹槽的底面在衬底基板上的正投影内，可以使遮光层起到类似遮罩的效果，从而避免背光源产生的光线被反射或折射到有源层，因而可以将光照产生的漏电流降到最低，极大地改进TFT器件的特性，进而避免显示面板由于薄膜晶体管的漏电流过大而产生的串扰和闪屏的不良，提高显示品质。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (12)

  1. 一种薄膜晶体管，包括：
    设置在衬底基板之上的遮光层；以及
    设置在所述遮光层之上的有源层，
    其中，所述遮光层在面向所述有源层的一面设置有凹槽，并且所述有源层在所述衬底基板上的正投影位于所述凹槽的底面在所述衬底基板上的正投影内。
  2. 如权利要求1所述的薄膜晶体管，其中，所述遮光层为栅极，并且所述薄膜晶体管还包括：
    设置在所述遮光层与所述有源层之间的栅极绝缘层；以及
    设置在所述有源层之上的源极和漏极。
  3. 如权利要求1所述的薄膜晶体管，还包括：
    设置在所述遮光层与所述有源层之间的钝化层；
    设置在所述有源层之上的栅极绝缘层；
    设置在所述栅极绝缘层之上的栅极；
    设置在所述栅极之上的层间绝缘层；以及
    设置在所述层间绝缘层之上的源极和漏极，
    其中，所述源极通过第一过孔与所述有源层连接，并且所述漏极通过第二过孔与所述有源层连接。
  4. 如权利要求2或3所述的薄膜晶体管，其中，所述凹槽的开口深度为1000埃～10000埃。
  5. 如权利要求1-3中任一项所述的薄膜晶体管，其中，所述遮光层为金属，并且所述凹槽的开口深度为1700埃。
  6. 如权利要求1-3中任一项所述的薄膜晶体管，其中，所述遮光层为黑矩阵材质，并且所述凹槽的开口深度为5000埃～7500埃。
  7. 如权利要求1所述的薄膜晶体管，其中，所述凹槽的内部侧壁与所述凹槽的底部之间的夹角大于或等于90°。
  8. 一种阵列基板，包括如权利要求1-7任一项所述的薄膜晶体管。
  9. 一种显示面板，包括背光源，以及如权利要求8所述的阵列基板，其中所述阵列基板设置在所述背光源的出光侧。
  10. 一种薄膜晶体管的制作方法，包括：
    在衬底基板之上形成具有凹槽的遮光层；以及
    在所述遮光层之上形成有源层，
    其中，所述有源层在所述衬底基板上的正投影在所述凹槽的底面在衬底基板上的正投影内。
  11. 如权利要求10所述的制作方法，其中，所述在衬底基板之上形成具有凹槽的遮光层，包括：
    在衬底基板之上形成第一膜层；
    通过半色调掩模板，在所述第一膜层之上形成具有不同厚度区域的图案化的光刻胶层，其中，所述图案化的光刻胶层包括第一区域和第二区域，所述第二区域的厚度小于所述第一区域的厚度，所述凹槽的底面在所述衬底基板上的正投影与所述第二区域在所述衬底基板上的正投影完全重叠；
    去除未被所述图案化的光刻胶层覆盖的所述第一膜层的部分；
    去除所述第二区域的光刻胶层；
    减薄与所述第二区域对应的所述第一膜层的部分；
    去除剩余的光刻胶层。
  12. 如权利要求11所述的制作方法，其中，所述减薄与所述第二区域对应的所述第一膜层的部分，包括：对与所述第二区域对应的所述第一膜层的部分刻蚀预设时长，以使与所述第二区域对应的所述第一膜层的部分的厚度减半。
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