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WO2018205753A1 - 过孔的制作方法、显示基板及其制作方法 - Google Patents

过孔的制作方法、显示基板及其制作方法 Download PDF

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Publication number
WO2018205753A1
WO2018205753A1 PCT/CN2018/080001 CN2018080001W WO2018205753A1 WO 2018205753 A1 WO2018205753 A1 WO 2018205753A1 CN 2018080001 W CN2018080001 W CN 2018080001W WO 2018205753 A1 WO2018205753 A1 WO 2018205753A1
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WO
WIPO (PCT)
Prior art keywords
insulating layer
layer
organic insulating
via hole
forming
Prior art date
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PCT/CN2018/080001
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English (en)
French (fr)
Inventor
万云海
杨成绍
王文龙
曹可
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/315,406 priority Critical patent/US10872807B2/en
Publication of WO2018205753A1 publication Critical patent/WO2018205753A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0212—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or coating of substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H10D86/443—Interconnections, e.g. scanning lines adapted for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

Definitions

  • Embodiments of the present disclosure relate to a method of fabricating a via, a display substrate, and a method of fabricating the same.
  • the display device is a device for displaying a character, a number, a symbol, a picture, or a picture formed by at least two combinations of characters, numbers, symbols, and pictures.
  • the display device generally includes a display substrate, and the display substrate generally includes a plurality of pixel units arranged in an array on the base substrate, each of the pixel units generally including a thin film transistor and a pixel electrode on a side of the thin film transistor away from the substrate.
  • the pixel electrode is connected to a drain in the source and drain layers of the thin film transistor.
  • An embodiment of the present disclosure provides a method for fabricating a via hole, including: forming a passivation protective layer on a conductive layer; forming a first via hole penetrating the passivation protective layer, wherein the first via hole is Forming a first sidewall of the passivation protective layer; forming an organic insulating layer on the passivation protective layer; and forming a second via extending through the organic insulating layer, wherein the second via is a second sidewall of the organic insulating layer is defined; wherein, in a cross-sectional view, a bottom of the second via is located in the first via and is in direct contact with the conductive layer, the organic insulating layer The second sidewall is separated from the first sidewall of the passivation protective layer.
  • the material of the organic insulating layer is a photoresist material.
  • the forming the second via hole through the passivation protective layer includes: exposing the organic insulating layer with a first mask; developing the exposed organic insulating layer Forming the second via.
  • the forming the first via hole through the passivation protective layer includes: coating a photoresist on the passivation protective layer; using the second mask, the photoresist Exposing; developing the exposed photoresist; etching the passivation protective layer to form the first via; removing residual portions of the photoresist.
  • the first reticle and the second reticle are the same reticle.
  • the exposure amount used when exposing the organic insulating layer is 80% to 90% of the exposure amount used when exposing the photoresist.
  • the conductive layer is a drain of a thin film transistor of a display substrate.
  • Another embodiment of the present disclosure provides a method of fabricating a display substrate, including a method of fabricating any of the above vias.
  • the conductive layer is a source drain layer
  • the method for fabricating the display substrate further comprises: sequentially forming a gate on the substrate a gate insulating layer, an active layer, and the source and drain layers.
  • the method for fabricating the display substrate further includes: Forming a pixel electrode on the insulating layer, the pixel electrode being connected to a drain of the source and drain layers through a second via; forming a passivation insulating layer on the pixel electrode; and forming on the passivation insulating layer Common electrode.
  • a further embodiment of the present disclosure provides a display substrate including: a substrate substrate, and a source and drain layer, a passivation protective layer, an organic insulating layer, and a pixel electrode over the substrate, the source and drain layers
  • the drain includes a first via extending through the passivation protective layer, the first via being defined by a first sidewall of the passivation protective layer; a portion of the organic insulating layer filling the first a via hole penetrating the organic insulating layer, the second via hole being defined by a second sidewall of the organic insulating layer; wherein, in a cross-sectional view, a bottom of the second via hole Located in the first via hole and in direct contact with the conductive layer, the second sidewall of the organic insulating layer and the first sidewall of the passivation protective layer are separated from each other.
  • the display substrate further includes: a gate electrode, a gate insulating layer, and an active layer between the substrate substrate and the source and drain electrodes and sequentially stacked thereon, and located on the pixel electrode A passivation insulating layer and a common electrode are sequentially laminated.
  • FIG. 1 is a flow chart of a method for fabricating a via hole according to an embodiment of the present disclosure
  • FIG. 2 is a flow chart of a method for fabricating a via hole according to an embodiment of the present disclosure
  • FIG. 3 to FIG. 11 are schematic cross-sectional structural diagrams of different stages in a manufacturing process of a via hole according to an embodiment of the present disclosure
  • FIG. 12 is a flowchart of a method for fabricating a display substrate according to an embodiment of the present disclosure
  • FIG. 13 is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure.
  • an insulating layer is usually provided between the pixel electrode and the source/drain layer.
  • the pixel electrode is usually connected to the drain through a via provided in the insulating layer.
  • the insulating layer generally includes a passivation protective layer and an organic insulating layer which are sequentially laminated on the source and drain layers. Therefore, the hole walls of the via holes in the insulating layer include a portion corresponding to the passivation protective layer and a portion corresponding to the organic insulating layer.
  • the hole wall of the via hole corresponds to the interface between the passivation protective layer and the organic insulating layer, and usually breaks.
  • the phenomenon of the line causes the pixel electrode and the drain to be not well connected, thereby causing the display quality of the display device to be degraded, for example, causing a dark line on the display device.
  • a method for fabricating a via hole provided by an embodiment of the present disclosure includes:
  • Step S100 forming a passivation protective layer on the source and drain layers.
  • Step S200 forming a first via hole at a portion of the passivation protective layer corresponding to the drain of the source/drain layer.
  • Step S300 forming an organic insulating layer on the passivation protective layer.
  • Step S400 forming a second via hole at a portion of the organic insulating layer corresponding to the first via hole, the second via hole exposing the drain, and a portion of the second via hole corresponding to the first via hole has a smaller aperture than the first via hole The aperture.
  • FIG. 3 when a via hole for connecting a pixel electrode and a drain is formed by using a via hole manufacturing method according to an embodiment of the present disclosure, refer to FIG. 3 , first on the source/drain layer.
  • the passivation protective layer 7 is, for example, an inorganic material layer, such as a metal oxide layer; then, referring to FIG. 4 to FIG. 8, the passivation of the passivation protective layer 7 and the source and drain layers
  • the corresponding portion of the 6 forms a first via 71, and the first via 71 exposes the drain 6.
  • FIG. 4 an inorganic material layer
  • an organic insulating layer 8 is formed on the passivation protective layer 7, and the organic insulating layer 8 covers the passivation protection.
  • the layer 7 covers the drain 6 exposed through the first via 71.
  • a second via 81 is formed at a portion of the organic insulating layer 8 corresponding to the first via 71.
  • the second via 81 exposes the drain 6.
  • the diameter of the portion of the second via 81 corresponding to the first via 71 is smaller than the aperture of the first via 71.
  • the first via 71 is sleeved outside the second via 81.
  • the hole wall of the first via hole 71 and the hole wall of the second via hole 81 are filled with an organic insulating layer 8.
  • the hole walls of the second via hole 81 correspond to the organic insulating layer 8, and the hole wall of the second via hole 81 does not have a portion corresponding to the passivation protective layer 7, and the hole wall of the via hole in the insulating layer in the related art includes The portion of the passivation protective layer is compared with the portion corresponding to the organic insulating layer.
  • the pixel electrode 9 is formed on the organic insulating layer 8. When the pixel electrode 9 is connected to the drain 6 through the second via 81, There is a phenomenon of disconnection, and the pixel electrode 9 and the drain electrode 6 can be well connected, so that the picture display quality of the display device can be improved.
  • the first via 71 penetrates the passivation protective layer 7, and the first via 71 is completely defined by the first sidewall W1 of the passivation protective layer; a part of the organic insulating layer 8 is filled in The first via 71 is formed; the second via 81 extends through the organic insulating layer 8, and the second via 81 is completely defined by the second sidewall of the organic insulating layer.
  • the bottom of the second via 81 is located in the first via 71 and is in direct contact with the drain 6.
  • the second side wall W2 of the organic insulating layer 8 and the first side wall W1 of the passivation protective layer 7 are separated from each other.
  • the first through hole and the second through hole each have, for example, a closed shape, such as a circular shape.
  • the fabrication of the via hole is completed without using a special step, and the method for fabricating the via hole is simple and easy, and can be applied to mass production.
  • the material of the organic insulating layer may be selected according to actual needs.
  • the material of the organic insulating layer may be selected from materials having good dielectric properties, for example, the material of the organic insulating layer may be combined with the material of the photoresist. the same.
  • the material of the organic insulating layer may be selected as a material of a negative photoresist.
  • step S400 can include:
  • Step S410 exposing the organic insulating layer by using the first mask.
  • Step S420 developing the exposed organic insulating layer to form a second via hole.
  • the second via is formed in the portion of the organic insulating layer corresponding to the first via
  • the first insulating layer 14 is used to face the organic insulating layer 8.
  • Exposure is performed; then, referring to FIG. 11, the exposed organic insulating layer 8 is developed to form a second via 81.
  • the photoresist is not coated on the organic insulating layer, and the first insulating layer can be directly used to the organic insulating layer.
  • a second via hole can be formed, which avoids coating another photoresist, etching the organic insulating layer, and removing another photoresist that is not exposed.
  • the step, thus forming the second via is simple, reducing the time required to form the second via, increasing the efficiency in forming the second via, and reducing the cost of forming the second via.
  • the step S200, forming the first via hole in the portion corresponding to the drain of the passivation protective layer and the source/drain layer may include:
  • Step S210 coating a photoresist on the passivation protective layer.
  • step S220 the photoresist is exposed by using a second mask.
  • Step S230 developing the exposed photoresist.
  • Step S240 etching the passivation protective layer to form a first via hole.
  • Step S250 removing residual photoresist.
  • a photoresist 12 is coated on the passivation protective layer 7, and the material of the photoresist 12 and the material of the organic insulating layer 8 may be the same.
  • the photoresist 12 is exposed by using the second mask 13; then, referring to FIG. 6, the exposed photoresist 12 is developed; after development, the passivation protective layer 7 is cured.
  • the area where the first via hole is to be formed is exposed; then, referring to FIG. 7, the passivation protective layer 7 is etched, and the exposed passivation protective layer 7 is etched away to form the first via hole 71; then, Referring to FIG. 8, the photoresist 12 remaining on the passivation protective layer 7 is removed.
  • the material of the organic insulating layer may be different from the material of the photoresist used in forming the first via.
  • the material of the organic insulating layer is a material of a negative photoresist
  • the material of the photoresist used to form the first via hole is a material of a positive photoresist; or the material of the organic insulating layer is positive light.
  • the material of the photoresist, the material of the photoresist used to form the first via is a material of a negative photoresist.
  • the second mask used in forming the first via is different from the first mask used in forming the second via.
  • the material of the organic insulating layer may be the same as the material of the photoresist used in forming the first via.
  • the material of the organic insulating layer and the material of the photoresist used in forming the first via hole are made of a material of a negative photoresist or a material of a positive photoresist.
  • the second mask used in forming the first via hole and the first mask used in forming the second via hole may share one mask. Therefore, the number of use of the reticle can be controlled, so that the cost at the time of fabricating the via hole can be reduced, and the cost at the time of manufacturing the display substrate can be reduced.
  • the exposure amount when the organic insulating layer 8 is exposed may be the same as the exposure amount when the photoresist 12 is exposed.
  • the material of the organic insulating layer 8 is made of the material of the photoresist 12, when the second via hole is formed, it is not necessary to additionally etch the organic insulating layer 8, so that the second via hole corresponds to the first pass.
  • the aperture of the portion of the aperture is smaller than the aperture of the first via.
  • the exposure amount when the organic insulating layer is exposed may be different from the exposure amount when the photoresist is exposed.
  • the exposure amount when the organic insulating layer 8 is exposed may be smaller than the exposure amount when the photoresist 12 is exposed, for example, when the exposure amount of the organic insulating layer 8 is exposed, when the photoresist 8 is exposed.
  • the exposure amount is 80% to 90%, so that the aperture of the portion corresponding to the first via hole and the first via hole is further smaller than the aperture of the first via hole.
  • an embodiment of the present disclosure further provides a method for fabricating a display substrate, and the method for fabricating the display substrate includes the method for fabricating a via hole as described in the above embodiments.
  • the method for fabricating the display substrate has the same advantages as the method for fabricating the via hole described above, and details are not described herein again.
  • the method for manufacturing the display substrate further includes:
  • Step S10 sequentially forming a gate electrode, a gate insulating layer, an active layer, and a source/drain layer on the base substrate.
  • the method for manufacturing the display substrate further includes:
  • Step S500 forming a pixel electrode on the organic insulating layer, and the pixel electrode is connected to the drain of the source/drain layer through the second via.
  • step S500 after the pixel electrode is formed on the organic insulating layer, the method for manufacturing the display substrate further includes:
  • Step S600 forming a passivation insulating layer on the pixel electrode.
  • Step S700 forming a common electrode on the passivation insulating layer.
  • the substrate includes a substrate substrate 1, and a thin film transistor, a passivation protective layer 7, an organic insulating layer 8, a pixel electrode 9, a passivation insulating layer 10, and a common electrode sequentially disposed on the substrate substrate 1.
  • the thin film transistor includes a gate electrode 2, a gate insulating layer 3, an active layer 4, and a source/drain layer sequentially disposed on the base substrate 1.
  • the material of the active layer 4 may be monocrystalline silicon, polycrystalline silicon or metal.
  • the oxide, source drain layer includes a source 5 and a drain 6.
  • the pixel electrode 9 is in direct contact with, for example, the second side wall of the organic insulating layer 8 without being in contact with the passivation protective layer 7 at all.
  • the step of fabricating the display substrate may be as follows: first, forming a thin film transistor on the substrate, that is, performing step S10, for example, first forming a gate on the substrate, and then covering the substrate and the gate with a gate insulating a layer, then forming an active layer on the gate insulating layer, then forming a source and drain layer on the active layer, the source and drain layers including a source and a drain; and then forming a blunt on the source and drain layers of the thin film transistor a protective layer, that is, performing step S100; then, forming a first via hole at a portion of the passivation protective layer corresponding to the drain of the source/drain layer, that is, performing step S200; then, forming an organic insulating layer on the passivation protective layer Step S300; then, forming a second via hole at a portion of the organic insulating layer corresponding to the first via hole, the second via hole exposing the drain, and a portion of the second via hole corresponding to the first via hole
  • an embodiment of the present disclosure further provides a display substrate including: a substrate substrate 1 , a source and drain layer over the substrate substrate 1 , a passivation protective layer 7 , an organic insulating layer 8 , and a pixel electrode 9 .
  • the source drain layer includes a drain electrode 6; the passivation protective layer 7 is provided with a first via hole at a portion corresponding to the drain electrode 6; the organic insulating layer 8 covers the passivation protective layer 7 and fills the first via hole, and the organic insulating layer a portion corresponding to the first via hole is provided with a second via hole, the second via hole exposing the drain electrode 6, and a portion of the second via hole corresponding to the first via hole has a smaller aperture than the aperture of the first via hole; the pixel electrode 9 is connected to the drain 6 through the second via.
  • the display substrate has the same advantages as the method for manufacturing the display substrate, and details are not described herein again.
  • the display substrate provided by the embodiment of the present disclosure further includes: a gate electrode 2 , a gate insulating layer 3 , and an active layer 4 , which are sequentially stacked between the substrate substrate 1 and the source and drain electrodes, and are located at the pixel.
  • the passivation insulating layer 10 and the common electrode 11 on the electrode 9 and sequentially stacked, the gate electrode 2, the gate insulating layer 3, the active layer 4, and the source and drain layers constitute a thin film transistor, and the source and drain layers include the source of the thin film transistor 5 and drain 6.

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Abstract

一种过孔的制作方法、显示基板及其制作方法。所述过孔的制作方法：在导电层(6)上形成钝化保护层(7)；形成贯穿所述钝化保护层(7)的第一过孔(71)，其中，所述第一过孔(71)由所述钝化保护层(7)的第一侧壁(W1)限定；在所述钝化保护层(7)上形成有机绝缘层(8)；以及形成贯穿所述有机绝缘层(8)的第二过孔(81)，其中，所述第二过孔(81)由所述有机绝缘层(8)的第二侧壁(W2)限定，其中，在一截面图中，所述第二过孔(81)的底部位于所述第一过孔(71)内且与所述导电层(6)直接接触，所述有机绝缘层(8)的所述第二侧壁(W2)与所述钝化保护层(7)的所述第一侧壁(W1)彼此分离。这样，能够避免填入第二过孔(81)中的电极层(9)出现断线。

Description

过孔的制作方法、显示基板及其制作方法
本申请要求于2017年5月12日递交的中国专利申请第201710335236.4号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种过孔的制作方法、显示基板及其制作方法。
背景技术
显示装置是一种用于显示文字、数字、符号、图片，或者由文字、数字、符号和图片中至少两种组合形成的图像等画面的装置。显示装置通常包括显示基板，显示基板通常包括形成在衬底基板上、呈阵列排布的多个像素单元，每个像素单元通常包括薄膜晶体管和位于薄膜晶体管远离衬底基板一侧的像素电极，像素电极与薄膜晶体管的源漏极层中的漏极连接。
发明内容
本公开一实施例提供一种过孔的制作方法，包括：在导电层上形成钝化保护层；形成贯穿所述钝化保护层的第一过孔，其中，所述第一过孔由所述钝化保护层的第一侧壁限定；在所述钝化保护层上形成有机绝缘层；以及形成贯穿所述有机绝缘层的第二过孔，其中，所述第二过孔由所述有机绝缘层的第二侧壁限定；其中，在一截面图中，所述第二过孔的底部位于所述第一过孔内且与所述导电层直接接触，所述有机绝缘层的所述第二侧壁与所述钝化保护层的所述第一侧壁彼此分离。
在一个示例中，所述有机绝缘层的材料为光刻胶材料。
在一个示例中，所述形成贯穿所述钝化保护层的所述第二过孔包括：利用第一掩模板，对所述有机绝缘层进行曝光；对曝光后的所述有机绝缘层进行显影，形成所述第二过孔。
在一个示例中，所述形成贯穿所述钝化保护层的所述第一过孔包括：在 所述钝化保护层上涂覆光刻胶；利用第二掩模板，对所述光刻胶进行曝光；对曝光后的所述光刻胶进行显影；对所述钝化保护层进行刻蚀，形成所述第一过孔；去除所述光刻胶的残留部分。
在一个示例中，所述第一掩模板和所述第二掩模板为同一个掩模板。
在一个示例中，对所述有机绝缘层进行曝光时采用的曝光量为对所述光刻胶进行曝光时采用的曝光量的80％～90％。
在一个示例中，所述导电层为显示基板的薄膜晶体管的漏极。
本公开另一实施例提供一种显示基板的制作方法，包括上述任一过孔的制作方法。
在一个示例中，所述导电层为一源漏极层，所述在导电层上形成所述钝化保护层之前，所述显示基板的制作方法还包括：在衬底基板上依次形成栅极、栅极绝缘层、有源层和所述源漏极层，在所述形成贯穿所述有机绝缘层的所述第二过孔之后，所述显示基板的制作方法还包括：在所述有机绝缘层上形成像素电极，所述像素电极通过第二过孔与所述源漏极层的漏极连接；在所述像素电极上形成钝化绝缘层；以及在所述钝化绝缘层上形成公共电极。
本公开又一实施例提供一种显示基板，包括：衬底基板，以及位于所述衬底基板上方的源漏极层、钝化保护层、有机绝缘层和像素电极，所述源漏极层包括漏极；其中，第一过孔贯穿所述钝化保护层，所述第一过孔由所述钝化保护层的第一侧壁限定；所述有机绝缘层的一部分填入所述第一过孔；第二过孔贯穿所述有机绝缘层，所述第二过孔由所述有机绝缘层的第二侧壁限定；其中，在一截面图中，所述第二过孔的底部位于所述第一过孔内且与所述导电层直接接触，所述有机绝缘层的所述第二侧壁与所述钝化保护层的所述第一侧壁彼此分离。
在一个示例中，所述显示基板还包括：位于所述衬底基板与所述源漏极之间且依次层叠的栅极、栅极绝缘层和有源层，以及位于所述像素电极上且依次层叠的钝化绝缘层和公共电极。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例， 而非对本公开的限制。
图1为本公开实施例提供的过孔的制作方法的流程图；
图2为本公开实施例提供的过孔的制作方法的流程图；
图3至图11为本公开实施例提供的过孔的制作工艺中不同阶段的截面结构示意图；
图12为本公开实施例提供的显示基板的制作方法的流程图；
图13为本公开实施例提供的显示基板的结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
为了进一步说明本公开实施例提供的过孔的制作方法及显示基板的制作方法、显示基板，下面结合说明书附图进行详细描述。
显示基板中，像素电极与源漏极层之间通常设置有绝缘层，像素电极与源漏极层中的漏极连接时，像素电极通常通过设置在绝缘层内的过孔与漏极连接。然而，在现有的显示基板中，绝缘层通常包括依次层叠在源漏极层上的钝化保护层和有机绝缘层。因此，绝缘层内的过孔的孔壁包括对应于钝化保护层的部分和对应于有机绝缘层的部分。在有机绝缘层上形成像素电极，并使像素电极通过绝缘层内的过孔与漏极连接时，在过孔的孔壁对应于钝化保护层与有机绝缘层的界面处，通常会出现断线的现象，造成像素电极与漏极不能良好连接，进而造成显示装置的画面显示质量降低，例如，造成显示装置出现暗线的现象。
请参阅图1，本公开实施例提供的过孔的制作方法包括：
步骤S100、在源漏极层上形成钝化保护层。
步骤S200、在钝化保护层与源漏极层的漏极对应的部位形成第一过孔。
步骤S300、在钝化保护层上形成有机绝缘层。
步骤S400、在有机绝缘层与第一过孔对应的部位形成第二过孔，第二过 孔暴露出漏极，且第二过孔与第一过孔对应的部分的孔径小于第一过孔的孔径。
请参阅图1以及图3至图11，采用本公开实施例提供的过孔的制作方法制作用于使像素电极与漏极连接的过孔时，请参阅图3，先在源漏极层上形成钝化保护层7，这里，钝化保护层7例如为无机材料层，例如金属氧化物层；然后，请参阅图4至图8，在钝化保护层7与源漏极层的漏极6对应的部位形成第一过孔71，第一过孔71暴露出漏极6；然后，请参阅图9，在钝化保护层7上形成有机绝缘层8，有机绝缘层8覆盖钝化保护层7，并覆盖经第一过孔71暴露出来的漏极6；然后，请参阅图10和图11，在有机绝缘层8与第一过孔71对应的部位形成第二过孔81。第二过孔81暴露出漏极6。第二过孔81与第一过孔71对应的部分的孔径小于第一过孔71的孔径。第一过孔71套在第二过孔81外部。第一过孔71的孔壁与第二过孔81的孔壁之间由有机绝缘层8填充。第二过孔81的孔壁均与有机绝缘层8对应，第二过孔81的孔壁不存在与钝化保护层7对应的部分，与相关技术中绝缘层内的过孔的孔壁包括对应于钝化保护层的部分和对应于有机绝缘层的部分相比，请参阅图13，在有机绝缘层8上形成像素电极9，像素电极9通过第二过孔81与漏极6连接时，不会存在断线的现象，像素电极9与漏极6可以良好连接，从而可以改善显示装置的画面显示质量。
这里，第一过孔71贯穿所述钝化保护层7，所述第一过孔71完全由所述钝化保护层的第一侧壁W1限定；所述有机绝缘层8的一部分填入所述第一过孔71；第二过孔81贯穿所述有机绝缘层8，所述第二过孔81完全由所述有机绝缘层的第二侧壁限定。在图11和13所示的截面图中，所述第二过孔81的底部位于所述第一过孔71内且与所述漏极6直接接触。所述有机绝缘层8的所述第二侧壁W2与所述钝化保护层7的所述第一侧壁W1彼此分离。
在一平面图中，所述第一通孔和所述第二通孔例如均具有封闭的形状，例如圆形。
另外，在本公开实施例提供的过孔的制作方法中，在不采用特殊步骤的情况下，完成过孔的制作，过孔的制作方法简单易行，可以适用于大规模量产。
在上述实施例中，有机绝缘层的材料可以根据实际需要进行选择，例如有机绝缘层的材料可以选择具有较好的介电性能的材料，例如，有机绝缘层的材料可以与光刻胶的材料相同。例如，有机绝缘层的材料可以选择为负性光刻胶的材料。
有机绝缘层的材料与光刻胶的材料相同时，则有机绝缘层本身可以作为光刻胶使用，当形成第二过孔时，请参阅图2，步骤S400可以包括：
步骤S410、利用第一掩模板，对有机绝缘层进行曝光。
步骤S420、对曝光后的有机绝缘层进行显影，形成第二过孔。
例如，在有机绝缘层与第一过孔对应的部位形成第二过孔时，在完成有机绝缘层的形成后，首先，请参阅图10，利用个第一掩模板14，对有机绝缘层8进行曝光；然后，请参阅图11，对曝光后的有机绝缘层8进行显影，形成第二过孔81。在本公开实施例中，在形成第二过孔时，在钝化保护层上形成有机绝缘层后，无需在有机绝缘层上涂覆光刻胶，可以直接利用第一掩模板对有机绝缘层进行曝光，并对曝光后的有机绝缘层进行显影后，即可形成第二过孔，避免了涂覆另一光刻胶、刻蚀有机绝缘层、去除未被曝光的另一光刻胶等步骤，因而第二过孔的形成步骤简单，减少了形成第二过孔所需要的时间，提高了形成第二过孔时的效率，并降低了形成第二过孔的成本。
请继续参阅图2，在本公开实施例中，步骤S200、在钝化保护层与源漏极层的漏极对应的部位形成第一过孔可以包括：
步骤S210、在钝化保护层上涂覆光刻胶。
步骤S220、利用第二掩模板，对光刻胶进行曝光。
步骤S230、对曝光后的光刻胶进行显影。
步骤S240、对钝化保护层进行刻蚀，形成第一过孔。
步骤S250、去除残留的光刻胶。
例如，在源漏极层上形成钝化保护层后，请参阅图4，在钝化保护层7上涂覆光刻胶12，该光刻胶12的材料与有机绝缘层8的材料可以相同；然后，请参阅图5，利用第二掩模板13，对光刻胶12进行曝光；然后，请参阅图6，对曝光后的光刻胶12进行显影；显影后，将钝化保护层7待形成第一过孔的区域暴露出来；然后，请参阅图7，对钝化保护层7进行刻蚀，即将暴露出来的钝化保护层7刻蚀掉，形成第一过孔71；然后，请参阅图8，将 残留在钝化保护层7上的光刻胶12去除。
在本公开实施例中，有机绝缘层的材料与形成第一过孔时所采用的光刻胶的材料可以不同。例如，有机绝缘层的材料为负性光刻胶的材料，形成第一过孔时所采用的光刻胶的材料为正性光刻胶的材料；或者，有机绝缘层的材料为正性光刻胶的材料，形成第一过孔时所采用的光刻胶的材料为负性光刻胶的材料。此时，形成第一过孔时所采用的第二掩模板和形成第二过孔时所采用的第一掩模板不同。
在本公开实施例中，有机绝缘层的材料与形成第一过孔时所采用的光刻胶的材料还可以相同。例如，有机绝缘层的材料与形成第一过孔时所采用的光刻胶的材料均采用负性光刻胶的材料或正性光刻胶的材料。此时，形成第一过孔时所采用的第二掩模板和形成第二过孔时所采用的第一掩模板可以共用一个掩模板。因此，可以控制掩模板的使用数量，从而可以降低制作过孔时的成本，进而降低制作显示基板时的成本。
在本公开实施例中，对有机绝缘层8进行曝光时的曝光量可以与对光刻胶12进行曝光时的曝光量相同。此时，由于有机绝缘层8的材料采用光刻胶12的材料，在形成第二过孔时，无需对有机绝缘层8进行额外的刻蚀，因而可以保证第二过孔对应于第一过孔的部分的孔径小于第一过孔的孔径。
例如，对有机绝缘层进行曝光时的曝光量可以与对光刻胶进行曝光时的曝光量不同。例如，对有机绝缘层8进行曝光时的曝光量可以小于对光刻胶12进行曝光时的曝光量，例如，对有机绝缘层8进行曝光时的曝光量为对光刻胶8进行曝光时的曝光量的80％～90％，从而进一步使得第二过孔与第一过孔对应的部分的孔径小于第一过孔的孔径。
请参阅图12，本公开实施例还提供一种显示基板的制作方法，所述显示基板的制作方法包括如上述实施例所述的过孔的制作方法。
所述显示基板的制作方法与上述过孔的制作方法所具有的优势相同，在此不再赘述。
请继续参阅图12，在制作过孔之前，即步骤S100、在源漏极层上形成钝化保护层之前，所述显示基板的制作方法还包括：
步骤S10、在衬底基板上依次形成栅极、栅极绝缘层、有源层和源漏极层。
请继续参阅图12，在完成过孔的制作后，即步骤S400、在有机绝缘层与第一过孔对应的部位形成第二过孔之后，所述显示基板的制作方法还包括：
步骤S500、在有机绝缘层上形成像素电极，像素电极通过第二过孔与源漏极层的漏极连接。
请继续参阅图12，步骤S500、在有机绝缘层上形成像素电极之后，所述显示基板的制作方法还包括：
步骤S600、在像素电极上形成钝化绝缘层。
步骤S700、在钝化绝缘层上形成公共电极。
例如，请参阅图13，显示基板包括衬底基板1、以及依次位于衬底基板1上的薄膜晶体管、钝化保护层7、有机绝缘层8、像素电极9、钝化绝缘层10和公共电极11，薄膜晶体管包括依次位于衬底基板1上的栅极2、栅极绝缘层3、有源层4、源漏极层，其中，有源层4的材料可以为单晶硅、多晶硅或金属氧化物，源漏极层包括源极5和漏极6。像素电极9例如与有机绝缘层8的第二侧壁直接接触，而完全不与钝化保护层7接触。
制作上述显示基板的步骤可以为：首先，在衬底基板上形成薄膜晶体管，即执行步骤S10，例如，先在衬底基板上形成栅极，然后在衬底基板和栅极上覆盖栅极绝缘层，然后在栅极绝缘层上形成有源层，然后在有源层上形成源漏极层，源漏极层包括源极和漏极；然后，在薄膜晶体管的源漏极层上形成钝化保护层，即执行步骤S100；然后，在钝化保护层与源漏极层的漏极对应的部位形成第一过孔，即执行步骤S200；然后，在钝化保护层上形成有机绝缘层，即执行步骤S300；然后，在有机绝缘层与第一过孔对应的部位形成第二过孔，第二过孔暴露出漏极，且第二过孔与第一过孔对应的部分的孔径小于第一过孔的孔径，即执行步骤S400；然后，在有机绝缘层上形成像素电极，像素电极通过第二过孔与源漏极层的漏极连接，即执行步骤S500；然后，在像素电极上形成钝化绝缘层，即执行步骤S600；然后，在钝化绝缘层上形成公共电极，即执行步骤S700。
请参阅图13，本公开实施例还提供一种显示基板，包括：衬底基板1，以及位于衬底基板1上方的源漏极层、钝化保护层7、有机绝缘层8和像素电极9，源漏极层包括漏极6；钝化保护层7与漏极6对应的部位设置有第一过孔；有机绝缘层8覆盖钝化保护层7，并填充第一过孔，有机绝缘层8与 第一过孔对应的部位设置有第二过孔，第二过孔暴露出漏极6，第二过孔与第一过孔对应的部分的孔径小于第一过孔的孔径；像素电极9通过第二过孔与漏极6连接。
所述显示基板与上述显示基板的制作方法所具有的优势相同，在此不再赘述。
请继续参阅图13，本公开实施例提供的显示基板还包括：位于衬底基板1与源漏极之间且依次层叠的栅极2、栅极绝缘层3和有源层4，以及位于像素电极9上且依次层叠的钝化绝缘层10和公共电极11，栅极2、栅极绝缘层3、有源层4和源漏极层构成薄膜晶体管，源漏极层包括薄膜晶体管的源极5和漏极6。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (11)

  1. 一种过孔的制作方法，包括：
    在导电层上形成钝化保护层；
    形成贯穿所述钝化保护层的第一过孔，其中，所述第一过孔由所述钝化保护层的第一侧壁限定；
    在所述钝化保护层上形成有机绝缘层；以及
    形成贯穿所述有机绝缘层的第二过孔，其中，所述第二过孔由所述有机绝缘层的第二侧壁限定；
    其中，在一截面图中，所述第二过孔的底部位于所述第一过孔内且与所述导电层直接接触，所述有机绝缘层的所述第二侧壁与所述钝化保护层的所述第一侧壁彼此分离。
  2. 根据权利要求1所述的过孔的制作方法，其中，所述有机绝缘层的材料为光刻胶材料。
  3. 根据权利要求2所述的过孔的制作方法，其中，所述形成贯穿所述钝化保护层的所述第二过孔包括：
    利用第一掩模板，对所述有机绝缘层进行曝光；
    对曝光后的所述有机绝缘层进行显影，形成所述第二过孔。
  4. 根据权利要求3所述的过孔的制作方法，其中，所述形成贯穿所述钝化保护层的所述第一过孔包括：
    在所述钝化保护层上涂覆光刻胶；
    利用第二掩模板，对所述光刻胶进行曝光；
    对曝光后的所述光刻胶进行显影；
    对所述钝化保护层进行刻蚀，形成所述第一过孔；
    去除所述光刻胶的残留部分。
  5. 根据权利要求4所述的过孔制作方法，其中，所述第一掩模板和所述第二掩模板为同一个掩模板。
  6. 根据权利要求4或5所述的过孔制作方法，其中，对所述有机绝缘层进行曝光时采用的曝光量为对所述光刻胶进行曝光时采用的曝光量的80％～90％。
  7. 根据权利要求1至6中任一项所述的过孔制作方法，其中，所述导电层为显示基板的薄膜晶体管的漏极。
  8. 一种显示基板的制作方法，其中，所述显示基板的制作方法包括如权利要求1～6任一所述的过孔的制作方法。
  9. 根据权利要求8所述的显示基板的制作方法，其中，所述导电层为一源漏极层，所述在导电层上形成所述钝化保护层之前，所述显示基板的制作方法还包括：
    在衬底基板上依次形成栅极、栅极绝缘层、有源层和所述源漏极层，
    在所述形成贯穿所述有机绝缘层的所述第二过孔之后，所述显示基板的制作方法还包括：
    在所述有机绝缘层上形成像素电极，所述像素电极通过第二过孔与所述源漏极层的漏极连接；
    在所述像素电极上形成钝化绝缘层；以及
    在所述钝化绝缘层上形成公共电极。
  10. 一种显示基板，包括：衬底基板，以及位于所述衬底基板上方的源漏极层、钝化保护层、有机绝缘层和像素电极，所述源漏极层包括漏极；其中，第一过孔贯穿所述钝化保护层，所述第一过孔由所述钝化保护层的第一侧壁限定；所述有机绝缘层的一部分填入所述第一过孔；第二过孔贯穿所述有机绝缘层，所述第二过孔由所述有机绝缘层的第二侧壁限定，其中，在一截面图中，所述第二过孔的底部位于所述第一过孔内且与所述导电层直接接触，所述有机绝缘层的所述第二侧壁与所述钝化保护层的所述第一侧壁彼此分离。
  11. 根据权利要求10所述的显示基板，其中，所述显示基板还包括：位于所述衬底基板与所述源漏极之间且依次层叠的栅极、栅极绝缘层和有源层，以及位于所述像素电极上且依次层叠的钝化绝缘层和公共电极。
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