WO2018170949A1

WO2018170949A1 - Liquid crystal display panel and manufacturing method thereof, and array substrate

Info

Publication number: WO2018170949A1
Application number: PCT/CN2017/079407
Authority: WO
Inventors: 李安石
Original assignee: 武汉华星光电技术有限公司
Priority date: 2017-03-20
Filing date: 2017-04-05
Publication date: 2018-09-27
Also published as: CN106909001B; CN106909001A

Abstract

A liquid crystal display panel (20) and a manufacturing method thereof, and an array substrate (21). A common electrode (224) is disposed at one side of a color filter substrate (22). A pixel electrode (214) is formed in a contact hole of a flat layer (213) of the array substrate (21), and is electrically connected to a drain (D1) of a thin film transistor (212) by means of the contact hole (220). In addition, the pixel electrode (214) has a columnar structure, and a top surface thereof is higher than a top surface of the flat layer (213). The pixel electrodes (214) and the common electrodes (224) are disposed alternately in a direction parallel to the array substrate (21). Based on this method the manufacturing process of the liquid crystal display panel (20) can be simplified, light transmittance thereof can be improved, and the influence of electrical fields on adjacent pixel electrodes (214) can be reduced.

Description

Liquid crystal display panel, manufacturing method thereof, and array substrate

[Technical Field]

The present invention relates to the field of liquid crystal display technology, and in particular to a liquid crystal display panel, a method of manufacturing the same, and an array substrate.

【Background technique】

LTPS (Low Temperature Poly-silicon) liquid crystal display panel has stood out in the display field due to its high electron mobility and high brightness. However, the number of structural layers is large and the process is complicated. As shown in FIG. 1 , in the structural design of the conventional LTPS liquid crystal display panel 10 , a PS (Photo Space) 121 is disposed on a side of the color filter substrate 12 facing the array substrate 11 , and the array substrate 11 includes a substrate substrate. 111 and each layer structure on the substrate substrate 111, such as a thin film transistor 112, a planarization layer (PLN) 113, a pixel electrode 114, a passivation layer (abbreviation layer) 115, and a common electrode 116. These layer structures generally require a 9-14 process, which not only makes the manufacturing cost high, but also reduces the light transmittance of the liquid crystal display panel 10 in each process.

[Summary of the Invention]

In view of the above, the present invention provides a liquid crystal display panel, a method of fabricating the same, and an array substrate, which can simplify the process of the liquid crystal display panel, improve the light transmittance thereof, and reduce the influence of the electric field between adjacent pixel electrodes.

A liquid crystal display panel according to an embodiment of the present invention includes a relatively spaced color filter substrate and an array substrate. The color filter substrate includes a common electrode, and the array substrate includes a thin film transistor, a flat layer covering the thin film transistor, and a pixel electrode, wherein the flat layer is opened. a contact hole exposing a drain of the thin film transistor, the pixel electrode being formed in the contact hole and electrically connected to the drain of the thin film transistor through the contact hole, and the pixel electrode is a columnar structure and a top surface thereof is higher than a top surface of the flat layer, The pixel electrode is spaced apart from the common electrode in a direction parallel to the array substrate.

A method of manufacturing a liquid crystal display panel according to an embodiment of the present invention includes: providing a first substrate substrate; sequentially forming a color filter, a protective layer, and a common electrode on the first substrate; and providing a second substrate a thin film transistor and a thin film transistor are sequentially formed on the second substrate a flat layer having a contact hole exposing a drain of the thin film transistor; a pixel electrode being formed in the contact hole such that the pixel electrode is electrically connected to a drain of the thin film transistor through the contact hole, and the pixel electrode is a columnar structure and The top surface is higher than the top surface of the flat layer, and the pixel electrode is spaced apart from the common electrode in a direction parallel to the second substrate substrate; the first substrate substrate and the second substrate substrate are subjected to a card forming process.

An array substrate according to an embodiment of the invention includes a thin film transistor, a flat layer covering the thin film transistor, and a pixel electrode, the flat layer is provided with a first contact hole exposing a drain of the thin film transistor, and the pixel electrode is formed in the first contact hole The first contact hole is electrically connected to the drain of the thin film transistor, and the pixel electrode has a columnar structure and a top surface thereof is higher than a top surface of the flat layer.

Through the above solution, in the embodiment of the present invention, the common electrode is disposed on one side of the color film substrate, the pixel electrode is designed as a columnar structure, and the PS electrode is used instead of the PS, and the PS process can be omitted, and the passivation layer can be omitted after forming the flat layer. The process can simplify the process of the liquid crystal display panel and improve the light transmittance thereof, and the columnar structure of the pixel electrode can increase the distance between adjacent pixel electrodes, thereby reducing the influence of the electric field between adjacent pixel electrodes. .

[Description of the Drawings]

1 is a cross-sectional view showing the structure of an embodiment of a liquid crystal display panel of the prior art;

2 is a cross-sectional view showing the structure of a liquid crystal display panel according to a first embodiment of the present invention;

3 is a schematic flow chart of an embodiment of a method for manufacturing a liquid crystal display panel shown in FIG. 2;

4 is a cross-sectional view showing the structure of a liquid crystal display panel according to a second embodiment of the present invention;

Fig. 5 is a cross-sectional view showing the structure of a liquid crystal display panel according to a third embodiment of the present invention.

【detailed description】

The technical solutions of the various exemplary embodiments provided by the present invention are clearly and completely described in the following with reference to the accompanying drawings. The various embodiments described below and the features in the embodiments can be combined with each other without conflict.

Please refer to FIG. 2, which is a liquid crystal display panel according to a first embodiment of the present invention. The liquid crystal display panel 20 includes a film substrate (Thin Film Transistor Substrate, which is also referred to as a thin film transistor substrate or an Array substrate) 21 and a color filter substrate (Color Filter Substrate, also referred to as a color filter). Sheet substrate 22) and liquid crystal filled between the two substrates (liquid Crystal molecule) 23. The liquid crystal 23 is located in a liquid crystal cell in which the array substrate 21 and the color filter substrate 22 are stacked and sealed.

The color filter substrate 22 includes a first substrate substrate 221 and color filters (also referred to as color resists) 222, a protective layer 223, and a common electrode 224 which are sequentially formed on the first substrate substrate 221. The color filter 222 may include a red color resist, a green color resist, and a blue color resist.

The array substrate 21 includes a second substrate substrate 210 and a light shielding layer 211, a buffer layer 215, a thin film transistor 212, a flat layer 213, and a pixel electrode 214 which are sequentially formed on the second substrate substrate 210. The material of the light shielding layer 211 includes, but is not limited to, a light shielding metal material such as copper or molybdenum. The thin film transistor 212 includes a polycrystalline silicon (P-Si) 216, a Gate Insulation Layer (GI, also referred to as a gate insulating layer) 217, a gate G ₁ , and a dielectric isolation formed on the buffer layer 215 in this order. An interlayer dielectric isolation (ILD), and a source/drain electrode layer formed by the source S ₁ and the drain D ₁ , wherein the dielectric isolation layer may include silicon sequentially formed on the gate G ₁ Oxide layer 218 and silicon nitride layer 219. In view of the fact that the gate G ₁ is located above the polysilicon semiconductor layer 216, the array substrate 21 of the present embodiment can be considered to have a top gate type pixel design. Planarization layer 213 defines the drain D 212 exposing the thin film transistor ₁ of the contact hole 220, the pixel electrode 214 formed in the contact hole 220, the pixel electrode 214 may be electrically connected through a contact hole 220 and the drain D 212 of the thin film transistor _1. In addition, the pixel electrode 214 has a columnar structure, for example, a trapezoidal or rectangular columnar structure. When the cross section of the pixel electrode 214 is a trapezoidal columnar structure, the length of the trapezoid upper side may be smaller than the length of the bottom side. The top surface of the pixel electrode 214 is higher than the top surface of the flat layer 213, and the pixel electrode 214 is spaced apart from the common electrode 224 in a direction parallel to the array substrate 21.

Of course, the color film substrate 22 and the array substrate 21 further include other structures, such as a polarizer, a black matrix, etc., wherein the black matrix may be disposed between the first substrate substrate 221 and the color filter 222, and the color filter 222 is formed on a side of the black matrix facing the array substrate 21, and a protective layer 223 is formed on a side of the color filter 222 facing the array substrate 21. The other structures can be referred to the prior art, and the present embodiment is not shown in the drawings.

Different from the conventional liquid crystal display panel 10 shown in FIG. 1 , in the structural design of the liquid crystal display panel 20 of the present embodiment, the common electrode 224 is disposed on the side of the color filter substrate 22 and the pixel electrode 214 . Designed as a columnar structure, the columnar pixel electrode 214 can abut against the protective layer 223 of the color filter substrate 21 for controlling the thickness and uniformity of the liquid crystal cell, thereby passing through the pixel electrode 214, in place of the PS 121 shown in FIG. 1, the PS process can be omitted, and the process of the passivation (PV) layer 115 can be omitted after the formation of the planar layer 213. Since the layer structure of the array substrate 21 is reduced in this embodiment, Therefore, the light transmittance can be improved and the process of the liquid crystal display panel 20 can be simplified. In addition, designing the pixel electrode 214 as a columnar structure can increase the distance between adjacent two pixel electrodes 214, thereby reducing the influence of an electric field between adjacent two pixel electrodes 214.

Further, the pixel electrode 214 can cover the region where the thin film transistor 212 is located, that is, the orthographic projection of the pixel electrode 214 on the array substrate 21 overlaps with the orthographic projection of the thin film transistor 212 on the array substrate 21, and the pixel electrode 214 is made of a light shielding material. In the obtained columnar structure, the pixel electrode 214 can prevent light leakage in the region where the thin film transistor 212 is covered, and thus the liquid crystal display panel 20 does not need to separately form a black matrix. Specifically, the light shielding material includes, but is not limited to, carbon, titanium oxide, and an organic material that absorbs light.

FIG. 3 is a flow chart showing a method of manufacturing the liquid crystal display panel 20 according to an embodiment of the present invention. This method can be used to manufacture the LTPS liquid crystal display panel 20 shown in FIG. 2. As shown in FIG. 3, the manufacturing method may include steps S31 to S36.

S31: providing a first substrate substrate.

The first substrate substrate 221 may be a light transmissive substrate such as a glass substrate, a plastic substrate, or a flexible substrate.

S32: sequentially forming a color filter, a protective layer, and a common electrode on the first substrate.

In this embodiment, a color filter having a predetermined pattern can be formed on the first substrate substrate 221 by a process such as coating photoresist, vacuum drying, removing edge photoresist, prebaking and cooling, exposure developing, and re-baking. 222. Then, a protective layer 223 and a common electrode 224 are sequentially formed on the color filter 222. Based on this, the color film substrate 22 having the common electrode 224 can be formed in this embodiment.

S33: providing a second substrate substrate.

The second substrate substrate 210 may be a light transmissive substrate such as a glass substrate, a plastic substrate or a flexible substrate.

S34: sequentially forming a thin film transistor and a flat layer covering the thin film transistor on the second substrate, and the flat layer is provided with a contact hole exposing a drain of the thin film transistor.

The thin film transistor 212 and the flat layer 213 formed on the second substrate substrate 210 may be the same as the prior art, and the manufacturing method thereof can be referred to the prior art, and details are not described herein again.

S35: forming a pixel electrode in the contact hole, so that the pixel electrode is electrically connected to the drain of the thin film transistor through the contact hole, the pixel electrode has a columnar structure and a top surface thereof is higher than a top surface of the flat layer, and the edge is parallel to the second substrate The pixel electrode is spaced apart from the common electrode in the direction of the substrate.

In this embodiment, the columnar pixel electrode 214 can be formed in the contact hole 220 by etching or deposition. The pixel electrode 214 can also be made of a conductive material such as ITO (Indium Tin Oxide).

S36: performing a cell process on the first substrate substrate and the second substrate substrate.

Since the method of the present embodiment can be used to obtain the liquid crystal display panel 20 shown in Fig. 2, it has the same advantageous effects as the embodiment shown in Fig. 2.

Please refer to FIG. 4, which is a liquid crystal display panel according to a second embodiment of the present invention. On the basis of the description of the embodiment shown in FIG. 2, the array substrate 41 of the present embodiment is not provided with a light shielding layer 211 and a buffer layer 215, and the thin film transistor 412 is sequentially formed on the second substrate substrate 410. A gate G ₂ , an insulating layer 417 , a polysilicon semiconductor layer 416 , a dielectric isolation layer, and a source/drain electrode layer formed of a source S ₂ and a drain D ₂ . In view of the fact that the gate G ₂ is located below the polysilicon semiconductor layer 416, the array substrate 41 of the present embodiment can be considered to have a bottom gate type pixel design. That is to say, the present invention is also applicable to a bottom gate type pixel design.

The liquid crystal display panel of this embodiment can also be fabricated by the method shown in FIG. 3, except that the manufacturing methods of the thin film transistors of the two embodiments are different. in particular:

In the embodiment shown in FIG. 3, before the thin film transistor 212 is formed on the second substrate substrate 210, the method further requires sequentially forming the light shielding layer 211 and the buffer layer 215 on the second substrate substrate 210, and then sequentially forming a polysilicon semiconductor layer 216, the insulating layer 217, a gate G _1, the dielectric spacer layer on the buffer layer 215 and the source and drain electrode layer.

In this embodiment, the gate G ₂ , the insulating layer 417 , the polysilicon semiconductor layer 416 , the dielectric isolation layer, and the source/drain electrode layer may be sequentially formed on the second substrate substrate 410 .

The present invention also provides a liquid crystal display panel 50 as shown in FIG. Referring to FIG. 5 , the array substrate 51 of the liquid crystal display panel 50 includes a thin film transistor 512 , a flat layer 513 , and a pixel electrode 514 . Planarization layer 513 is exposed to a thin film transistor is defined in the drain D 512 of the first contact hole ₃ 520a. The pixel electrode 514 is formed in the first contact hole 520a and electrically connected to the drain D _{3 of the} thin film transistor 512 through the first contact hole 520a, and the pixel electrode 514 has a columnar structure and its top surface is higher than the top surface of the flat layer 513. .

On the basis of the description of the array substrate 21 of the embodiment shown in FIG. 2, the common electrode of the liquid crystal display panel 50 is not disposed on the side of the color filter substrate 52 but on the array substrate 51. . Specifically, the array substrate 51 further includes a common electrode 524 and a passivation layer 525 which are sequentially formed on the flat layer 513. The passivation layer 525 is provided with a second contact hole 520b that is electrically connected to the first contact hole 520a. The pixel electrode 514 is further formed in the second contact hole 520b and has a top surface higher than a surface of the passivation layer 525. Also, the pixel electrode 514 is spaced apart from the common electrode 524 in a direction parallel to the array substrate 51.

Compared with the prior art shown in FIG. 1, this embodiment replaces the PS 121 shown in FIG. 1 by the pixel electrode 514, and the PS process can be omitted, thereby simplifying the process of the liquid crystal display panel 50. Also, designing the pixel electrode 514 as a columnar structure can increase the distance between adjacent two pixel electrodes 514, thereby reducing the influence of an electric field between adjacent two pixel electrodes 514.

Of course, in the bottom-gate pixel design of the embodiment shown in FIG. 4, the common electrode may be disposed on the side of the array substrate 41. The pixel electrode of the array substrate is the same as the structure of the embodiment, and the embodiment can also be implemented. Beneficial effect.

The above is only the embodiment of the present invention, and is not intended to limit the scope of the invention, and the equivalent structure or equivalent flow transformation made by the description of the present invention and the contents of the drawings, for example, the mutual technical features between the embodiments. Combinations, or direct or indirect use in other related technical fields, are included within the scope of the patent protection of the present invention.

Claims

A liquid crystal display panel comprising a relatively spaced color filter substrate and an array substrate, wherein the color film substrate comprises a common electrode, the array substrate comprises a thin film transistor, a flat layer covering the thin film transistor, and a pixel electrode, wherein The flat layer is provided with a contact hole exposing a drain of the thin film transistor, and the pixel electrode is formed in the contact hole and electrically connected to a drain of the thin film transistor through the contact hole, and The pixel electrode is a columnar structure and has a top surface higher than a top surface of the flat layer, and the pixel electrode is spaced apart from the common electrode in a direction parallel to the array substrate.
The liquid crystal display panel according to claim 1, wherein the pixel electrode comprises a columnar structure made of a light shielding material.
The liquid crystal display panel according to claim 1, wherein an orthographic projection of the pixel electrode on the array substrate overlaps with an orthographic projection of the thin film transistor on the array substrate.
The liquid crystal display panel according to claim 1, wherein a sectional shape of the pixel electrode includes one of a trapezoid and a rectangle.
The liquid crystal display panel according to claim 1, wherein the array substrate further comprises a substrate substrate and a light shielding layer and a buffer layer sequentially formed on the substrate substrate, wherein the thin film transistor comprises a layer formed in order a polysilicon semiconductor layer, an insulating layer, a gate electrode, a dielectric spacer layer, and a source/drain electrode layer formed of a source and a drain formed on the buffer layer, the flat layer being formed on the source/drain electrode layer.
The liquid crystal display panel according to claim 1, wherein the thin film transistor comprises a gate electrode, an insulating layer, a polysilicon semiconductor layer, a dielectric isolation layer, and a source and a gate, which are sequentially formed on a substrate of the array substrate A source/drain electrode layer formed by a drain formed on the source/drain electrode layer.
A method of manufacturing a liquid crystal display panel, wherein the method comprises:

Providing a first substrate substrate;

Forming a color filter, a protective layer and a common electrode on the first substrate substrate;

Providing a second substrate substrate;

Forming a thin film transistor and a flat layer covering the thin film transistor on the second substrate substrate, the flat layer opening a contact hole exposing a drain of the thin film transistor;

Forming a pixel electrode in the contact hole such that the pixel electrode is electrically connected to a drain of the thin film transistor through the contact hole, and the pixel electrode is a columnar structure and a top surface thereof is higher than the flat layer a top surface of the pixel electrode spaced apart from the common electrode in a direction parallel to the second substrate substrate;

The first substrate substrate and the second substrate substrate are subjected to a card forming process.
The method according to claim 7, wherein said pixel electrode is formed using a light shielding material.
The method of claim 7, wherein an orthographic projection of the pixel electrode on the array substrate overlaps with an orthographic projection of the thin film transistor on the array substrate.
The method of claim 7, wherein the sectional shape of the pixel electrode comprises one of a trapezoid and a rectangle.
The method according to claim 7, wherein the array substrate further comprises a substrate substrate and a light shielding layer and a buffer layer sequentially formed on the substrate substrate, the thin film transistor including the buffer layer formed in this order a polysilicon semiconductor layer, an insulating layer, a gate electrode, a dielectric isolation layer, and a source/drain electrode layer formed of a source and a drain formed on the layer, and the planarization layer is formed on the source/drain electrode layer.
The method according to claim 7, wherein said thin film transistor comprises a gate electrode, an insulating layer, a polysilicon semiconductor layer, a dielectric spacer layer, and a source and a drain, which are sequentially formed on a substrate substrate of said array substrate A source/drain electrode layer is formed, and the flat layer is formed on the source/drain electrode layer.
An array substrate comprising a thin film transistor, a flat layer covering the thin film transistor, and a pixel electrode, wherein the flat layer is provided with a first contact hole exposing a drain of the thin film transistor, and the pixel electrode is formed on The first contact hole is electrically connected to the drain of the thin film transistor through the first contact hole, and the pixel electrode has a columnar structure and a top surface thereof is higher than a top surface of the flat layer.
The array substrate according to claim 13, wherein the array substrate further comprises a common electrode and a passivation layer sequentially formed on the flat layer, and the passivation layer is opened to be electrically connected to the first contact hole a second contact hole, the pixel electrode is further formed in the second contact hole and a top surface thereof is higher than a surface of the passivation layer, and the pixel electrode is in a direction parallel to the array substrate It is spaced apart from the common electrode.
The array substrate according to claim 13, wherein the pixel electrode comprises a columnar structure made of a light shielding material.
The array substrate according to claim 13, wherein an orthographic projection of the pixel electrode on the array substrate overlaps with an orthographic projection of the thin film transistor on the array substrate.
The array substrate according to claim 13, wherein a sectional shape of the pixel electrode includes one of a trapezoid and a rectangle.
The array substrate according to claim 13, wherein the array substrate further comprises a substrate substrate and a light shielding layer and a buffer layer sequentially formed on the substrate substrate, wherein the thin film transistor comprises sequentially formed in the a polysilicon semiconductor layer, an insulating layer, a gate electrode, a dielectric spacer layer, and a source/drain electrode layer formed of a source and a drain on the buffer layer, the flat layer being formed on the source/drain electrode layer.
The array substrate according to claim 13, wherein the thin film transistor comprises a gate electrode, an insulating layer, a polysilicon semiconductor layer, a dielectric isolation layer, and a source and a drain, which are sequentially formed on a substrate substrate of the array substrate A source/drain electrode layer formed of a pole, the flat layer being formed on the source/drain electrode layer.