WO2018083797A1

WO2018083797A1 - Differential amplification circuit and voltage buffer circuit

Info

Publication number: WO2018083797A1
Application number: PCT/JP2016/082966
Authority: WO
Inventors: 隆也丸山; 恒次堤; 下沢　充弘
Original assignee: 三菱電機株式会社
Priority date: 2016-11-07
Filing date: 2016-11-07
Publication date: 2018-05-11
Also published as: JPWO2018083797A1

Abstract

A differential amplification circuit (11) is provided with: differential input terminals (INa, INb); first and second amplification transistors (M₁, M₂); a common connection node (21c) electrically connected to source electrodes of the first and second amplification transistors; a constant current source (22) connected between the common connection node (21c) and a second power supply line; a voltage detector (30) which detects a common mode input voltage (V_c) from input voltages (V_inp, V_inn) applied to the differential input terminals (INa, INb); and a shunt circuit (40) which forms a current path having a conductance value corresponding to the common mode input voltage (V_c) between a first power supply line (10D) and the common connection node (21c).

Description

Differential amplifier circuit and voltage buffer circuit

The present invention relates to a differential amplifier circuit and a voltage buffer circuit including the differential amplifier circuit.

In an analog integrated circuit, it is desirable to employ a differential circuit having a common-mode rejection ratio (CMRR) with a signal path differentiated and a high common-mode rejection ratio (CMRR). The differential circuit suppresses the superimposition of noise such as unnecessary radiation or disturbance signal on the output signal, so that it is possible to prevent the signal quality from being deteriorated due to the noise or the malfunction of the subsequent circuit. The common-mode rejection ratio (hereinafter also referred to as “CMRR”) is the ability to suppress the influence of the common-mode signal on the circuit when the common-mode signal is applied to the two input terminals of the differential circuit. (For example, Non-Patent Document 1). If the value of CMRR is large, the noise component that appears in the output signal can be reduced even if noise is applied to the differential circuit as an in-phase signal component. Therefore, it is evaluated that the higher the value of CMRR, the higher the performance of the differential circuit.

By the way, as a typical voltage buffer circuit operating in a radio frequency (RF) band, a source follower can be cited. However, since this type of source follower is not a fully-differential circuit, there is a problem that noise such as unwanted radiation or a disturbance signal is superimposed on the output signal as described above. In order to solve this problem, it is possible to effectively form a voltage buffer circuit having fully differential characteristics by disposing a differential amplifier in front of the source follower (for example, Non-Patent Document 2). ). This type of voltage buffer circuit can improve the driving capability for the next-stage circuit by lowering the output impedance, and can reduce the amount of superimposed noise.

As described above, in order to improve noise resistance, it is desirable to employ a differential circuit having a high CMRR. However, as the miniaturization of integrated circuits progresses, there is a problem that it is difficult to increase the value of CMRR. For example, in the case of a fine CMOS device, it is difficult to increase the value of CMRR because the size of the gate length of the field effect transistor is small and the output resistance of the tail current source constituting the differential amplifier portion is small. According to Non-Patent Document 1, the CMRR of a typical differential amplifier is given by the following approximate expression, for example.
CMRR = 2 × r _s × g _m

Here, g _m is the transconductance, r _s of the MOS transistor which is a component of the differential amplifier is the output resistance of the tail current source is a component of the differential amplifier. In general, the more the size of the gate width to the gate length of the MOS transistor is small, the value of the transconductance g _m is small.

In view of the above, an object of the present invention is to provide a differential amplifier circuit and a voltage buffer circuit capable of improving CMRR.

A differential amplifier circuit according to one aspect of the present invention includes: first and second differential input terminals; a first power supply line that supplies a predetermined first power supply voltage; and the first power supply voltage. A second power supply line for supplying a different second power supply voltage, a gate electrode electrically connected to the first differential input terminal, and a drain electrode electrically connected to the first power supply line A first amplifying transistor comprising a field effect transistor having a gate electrode electrically connected to the second differential input terminal, and a drain electrode electrically connected to the first power supply line A second amplifying transistor comprising a field effect transistor, a common connection node electrically connected to a source electrode of each of the first and second amplifying transistors, and the common connection node. The common-mode input voltage is detected from the constant current source connected between the power supply line and the second power supply line, and the input voltages applied to the first and second differential input terminals, respectively. An output voltage detector; a shunt circuit disposed between the common connection node and the first power supply line; and a current path having a conductance value corresponding to the common-mode input voltage; and the first amplification transistor And the first and second differential output terminals electrically connected to the drain electrode and the drain electrode of the second amplification transistor, respectively.

According to the present invention, the shunt circuit has a high CMRR by forming a current path having a conductance value according to the common-mode input voltage detected by the voltage detector between the first power supply line and the common connection node. Can be realized.

It is a figure which shows schematically the circuit structure of the voltage buffer circuit which is Embodiment 1 which concerns on this invention. It is a figure which shows schematically the circuit structure of the voltage buffer circuit which is Embodiment 2 which concerns on this invention. It is a figure which shows schematically the circuit structure of the voltage buffer circuit which is Embodiment 3 which concerns on this invention. It is a figure which shows schematically the circuit structure of the voltage buffer circuit which is Embodiment 4 which concerns on this invention. It is a figure which shows schematically the circuit structure of the voltage buffer circuit which is Embodiment 5 which concerns on this invention. 6A is a schematic diagram illustrating a circuit configuration example of the variable resistor of the fifth embodiment, and FIG. 6B is a schematic diagram illustrating another circuit configuration example of the variable resistor of the fifth embodiment. It is a figure which shows schematically the circuit structure of the voltage buffer circuit which is Embodiment 6 which concerns on this invention.

Hereinafter, various embodiments according to the present invention will be described in detail with reference to the drawings. In addition, the component to which the same code | symbol was attached | subjected in the whole drawing shall have the same structure and the same function.

Embodiment 1 FIG.
FIG. 1 is a diagram schematically showing a circuit configuration of a voltage buffer circuit 1 according to the first embodiment of the present invention. The voltage buffer circuit 1 includes a differential amplifier circuit 11 and a source follower circuit 51. The differential amplifier circuit 11 has differential input terminals INa and INb (first and second differential input terminals), a power supply voltage V _DD supplied from the first power supply line 10D, and a second power supply line 10S. The signals input to the differential input terminals INa and INb can be differentially amplified using the power supply voltage V _SS (V _SS <V _DD ) supplied from the input terminal. For example, a positive voltage as the power supply voltage V _DD, the power supply voltage V _SS is a negative voltage may be employed to supply, respectively.

The differential amplifier circuit 11 is a combination of a differential pair unit 21 and a constant current source 22 constituting a differential amplifier unit that amplifies a difference between input voltages V _inp and V _inn applied to the differential input terminals INa and INb, respectively. A voltage detector 30 that detects the common-mode input voltage V _C from these input voltages V _inp and V _inn , a shunt circuit 40 that operates by receiving the supply of the common-mode input voltage V _C from the voltage detector 30, a differential Output terminals OTa, OTb (first and second differential output terminals).

The differential pair unit 21 has a differential transistor pair including a pair of amplification transistors M ₁ and M ₂ . Each of these amplifying transistors M ₁ and M ₂ is composed of an n-channel field effect transistor (Field-Effect Transistor, FET). A MOS (Metal-Oxide-Semiconductor) FET may be used as the n-channel FET. As shown in FIG. 1, one of the amplification transistor M ₁ has a gate electrode connected differential input terminals INa and electrically, and a drain electrode connected a first power supply line 10D and electrically, The source electrode is electrically connected to the common connection node 21c. The other amplifying transistor M ₂ includes a gate electrode connected differential input terminal INb and electrically, the first power supply line 10D electrically the connected drain electrodes, the common connection node 21c and electrically And a connected source electrode.

The load resistor R ₁ is provided between the one of the drain electrode of the amplifying transistor M ₁ and the first power supply line 10D, the load resistance between the other of the drain electrode and the first power supply line 10D of the amplifying transistor M ₂ R ₂ is provided. Furthermore, one of the drain electrode of the amplifying transistor M ₁ is one of the differential output terminals OTa electrically connected, the drain electrode of the other amplifying transistor M _2, electrically connected to the differential output terminal OTb Has been.

At the design stage of the differential amplifier circuit 11, the amplification transistors M ₁ and M ₂ are designed to have the same transistor size ratio α and the same electrical characteristics, and load resistors R ₁ and R _2. Are set to have the same resistance _RL . Here, the transistor size ratio α is the ratio _W a / _{L a} gate width _{W a} to the gate length _{L a.}

The constant current source 22 is a tail current source having a constant current transistors M ₃ consisting of n-channel type FET. A constant bias voltage V _b is applied to the gate electrode of the constant current transistor M _3, constant power supply voltage V _SS is applied to the source electrode of constant current transistor M _3. Therefore, constant-current transistor M ₃ are, functions as a constant current element. The drain electrode of constant current transistor M ₃ are, are commonly connected node 21c and electrically connected.

The voltage detector 30 includes

resistance elements

31 and 32 connected in series with each other. That is, one end of the resistance element 31 and one end of the resistance element 32 are connected to each other via the intermediate node 30c. The other end of the resistance element 31 is electrically connected to the differential input terminal INa, and the other end of the resistance element 32 is electrically connected to the differential input terminal INb. These

resistance elements

31 and 32 have the same resistance value. Such a voltage detector 30 can detect the common-mode input voltage V _C which is a common-mode component of the input voltages V _inp and V _inn and output the common-mode input voltage V _C from the intermediate node 30c. The common-mode input voltage V _C is detected as an average of the input voltages V _inp and V _inn .

Shunt circuit 40 has a frequency reuse transistor M ₄ consisting of a common connection node 21c and connected n-channel FET between the first power supply line 10D. The partial diversion transistor M ₄ has a gate electrode which is the voltage detector 30 intermediate node 30c electrically connected, the first power supply line 10D electrically the attached drain electrode, and the common connection node 21c A source electrode which is electrically connected. Load resistor R ₃ is provided between the drain electrode of the minute diverting transistor M ₄ and the first power supply line 10D.

The source follower circuit 51 has a function of reducing the output impedance of the voltage buffer circuit 1. As shown in FIG. 1, the source follower circuit 51 includes

input terminals

51a and 51b connected to the differential output terminals OTa and OTb of the differential amplifier circuit 11, respectively, and

output terminals

51c and 51d. The source follower circuit 51 outputs output voltages V _outp and V _outn corresponding to the output voltages V _mp and V _mn input to the

input terminals

51a and 51b from the

output terminals

51c and 51d. More specifically, the source follower circuit 51 includes transistors M ₁₁ and M ₁₂ made of n-channel FETs and load transistors M ₁₃ and M _{14 made of} n-channel FETs. Transistor M ₁₁ includes a gate electrode connected to the input terminal 51a, a drain electrode connected to the first power supply line 10D, a source electrode connected to the second power supply line 10S via the load transistor M ₁₃ And have. Load the drain electrode of the transistor M ₁₃ is the source electrode electrically connected to the transistor M _11. The gate electrode of the load transistor M ₁₃ is applied constant bias voltage V _b, a constant power supply voltage V _SS and the source electrode of the load transistor M ₁₃ is applied. Output terminal 51c of the source follower circuit 51 is electrically with the source electrodes of the transistor M ₁₁ connected.

Other transistor M ₁₂ includes a gate electrode connected to the input terminal 51b, and a drain electrode connected to the first power supply line 10D, and is connected to the second power supply line 10S via the load transistor M ₁₄ A source electrode. A drain electrode of the load transistor M ₁₄ is electrically with the source electrodes of the transistor M ₁₂ connected. The load constant bias voltage V _b to the gate electrode of the transistor M ₁₄ is applied, a constant power supply voltage V _SS and the source electrode of the load transistor M ₁₄ is applied. Output terminal 51d of the source follower circuit 51 is electrically with the source electrodes of the transistor M ₁₂ connected.

The source follower circuit 51 is configured using a plurality of n-channel FETs, but is not limited to this. Instead of the source follower circuit 51, a source follower circuit configured using a plurality of p-channel FETs may be employed.

Next, the operation of the differential amplifier circuit 11 will be described in detail. The differential input signal to the differential amplifier circuit 11 can be divided into an in-phase input component and a differential input component. Phase with the input voltage V _C is the common mode input component, the differential input voltage V _D is a differential input component, the following equations (1), is given by (2).

As a response to the differential input component, a current corresponding to the amplitude of the differential input component flows through the differential pair 21 and the constant current source 22. On the other hand, as a response to the in-phase input component, a current corresponding to the amplitude of the in-phase input component flows through both the differential pair 21 and the shunt circuit 40. Therefore, compared with the case where the shunt circuit 40 is not provided, The amount of current corresponding to the in-phase input component in the moving pair 21 is small. Therefore, the shunt circuit 40 can reduce the ratio of the in-phase output component to the differential output component, and can improve the CMRR. The amount of current flowing through the shunt circuit 40 depends on the transistor size ratio α (= W _a / L _a ) of each of the amplification transistors M ₁ and M ₂ and the transistor size ratio β of the shunt transistor M ₄ . Here, the transistor size ratio of the frequency reuse transistor _{M 4} beta is given by the ratio _W b / _{L b} of the gate width _{W b} of the partial diversion transistor _{M 4} to the gate length _{L b.} The larger the dimensional ratio M _C (= β / α) indicating the ratio of the transistor size ratio β to the transistor size ratio α, the smaller the amount of current corresponding to the in-phase input component in the differential pair 21.

Here, if the partial diverting transistor M ₄ is configured to operate in a linear region with respect to common-mode input voltage V _C, shunt circuit 40, a variable having a conductance value corresponding to the value of the common-mode input voltage V _C Can function as a resistor. In this case, the larger the value of the common-mode input voltage V _C, the conductance value increases.

Next, it is assumed that the common source potential at the common connection node 21c is represented by V ₀ , the transconductance of each of the amplification transistors M ₁ and M ₂ is represented by g _m , and the output resistance of the tail current source 22 is represented by r _O. As described above, the transistor size ratio β min diverting transistor M _4, an M _C times the amplification transistor M _1, M ₂ each transistor size ratio alpha. At this time, the following equation (3) is established.

From this equation (3), the common source potential V ₀ can be obtained. That is, the common source potential V ₀ is given by the following equation (4).

The output voltages V _mp and V _mn of the differential amplifier circuit 11 can be expressed by the following equations (5) and (6), respectively.

Here, the load resistances R ₁ and R ₂ in the differential pair 21 are both the same resistance _RL .

Therefore, the output voltages V _mp and V _mn can be obtained by substituting the right side of the equation (4) into the common source potential V ₀ of the equations (5) and (6). That is, the output voltages V _mp and V _mn are given by the following expressions (7) and (8).

Thus, the differential gain _{A D} and phase gain _{A C} of the differential amplifier circuit 11 is expressed by the following equation (9) is given by (10).

Therefore, the CMRR of the differential amplifier circuit 11 is approximately as shown in the following equation (11).

As shown in the equation (11), the CMRR of the differential amplifier circuit 11 is about (1 + M _C / 2) times as compared with the CMRR value (= 2r _O g _m ) when the shunt circuit 40 is not present. It can be seen that it has a value.

In the differential amplifier circuit 11 of Embodiment 1 As described above, the shunt circuit 40, a current path having a conductance value corresponding to the value of the detected common-mode input voltage V _C by the voltage detector 30 first Since it is formed between the power supply line 10D and the common connection node 21c, CMRR can be improved. Therefore, it is possible to provide the differential amplifier circuit 11 and the voltage buffer circuit 1 having excellent noise resistance. Further, when the voltage buffer circuit 1 is configured as an integrated circuit, high CMRR can be realized even if the integrated circuit is miniaturized.

Embodiment 2. FIG.
The differential amplifier circuit 11 and the source follower circuit 51 in the voltage buffer circuit 1 of the first embodiment are configured using a plurality of FETs. Instead of these FETs, it is possible to configure a voltage buffer circuit using bipolar transistors. FIG. 2 is a diagram schematically showing a circuit configuration of the voltage buffer circuit 2 according to the second embodiment of the present invention. The voltage buffer circuit 2 includes a differential amplifier circuit 12 and an emitter follower circuit 52.

As shown in FIG. 2, the differential amplifier circuit 12 has differential input terminals INa and INb (first and second differential input terminals), and the power supply voltage V supplied from the first power supply line 10C. _{Using the CC} and the power supply voltage V _EE (V _EE <V _CC ) supplied from the second power supply line 10E, the signals input to the differential input terminals INa and INb are differentially amplified. For example, a positive voltage as the power supply voltage V _CC is, as the power supply voltage V _EE is a negative voltage may be employed to supply, respectively.

The differential amplifier circuit 12 includes a combination of a differential pair 23 and a constant current source 24 for amplifying a difference between input voltages V _inp and V _inn applied to the differential input terminals INa and INb, and the input voltage V _inp. , a voltage detector 30 for detecting the common mode input voltage _{V C} from _{V inn,} the shunt circuit 41 that operates by being supplied with the common-mode input voltage _{V C} from the voltage detector 30, the differential output terminals OTa, OTB (a 1 and a second differential output terminal).

The differential pair section 23 has a differential transistor pair composed of a pair of amplification transistors Q ₁ and Q ₂ . Each of these amplification transistors Q ₁ and Q ₂ is formed of an npn-type bipolar transistor. As shown in FIG. 2, one amplifying transistor Q ₁ is a base electrode connected differential input terminals INa and electrically, the first power line 10C electrically connected to it are collector electrodes, The emitter electrode is electrically connected to the common connection node 23c. The other amplifying transistor Q ₂ is a base electrode connected differential input terminal INb and electrically, the first power line 10C electrically connected to it are collector electrodes, the common connection node 23c and electrically And an emitter electrode connected thereto.

The load resistor r ₁ is provided between the one and the collector electrode of the amplifying transistor Q ₁ and the first power supply line 10C, the load resistance between the collector electrode of the other of the amplifying transistor Q ₂ and the first power supply line 10C r ₂ is provided. Further, the collector electrode of one of the amplifying transistor Q ₁ is are connected differential output terminals OTa electrically, the collector electrode of the other amplifying transistors Q _2, is electrically connected to the differential output terminal OTb Yes. At the design stage of the differential amplifier circuit 12, the amplification transistors Q ₁ and Q ₂ are designed to have the same electrical characteristics, and the load resistances r ₁ and r ₂ also have the same resistance r _L. Is set. The constant current source 24 is a tail current source connected between the common connection node 23c and the second power supply line 10E. The constant current source 24 may be composed using at least one bipolar transistor Q ₃ as shown schematically in Figure 2.

Shunt circuit 41 has a frequency reuse transistor Q ₄ consisting of a common connection node 23c and connected npn-type bipolar transistor between a first power supply line 10C. The partial diversion transistor Q ₄ are a base electrode which is the voltage detector 30 intermediate node 30c electrically connected, the first power supply line 10C electrically connected to it are collector electrodes, and the common connection node 23c And an emitter electrode which is electrically connected. The load resistor r ₃ is provided between the collector electrode of the minute diverting transistor Q ₄ and the first power supply line 10C.

The emitter follower circuit 52 has a function of reducing the output impedance of the entire voltage buffer circuit 2. As shown in FIG. 2, the emitter follower circuit 52 includes

input terminals

52a and 52b respectively connected to the differential output terminals OTa and OTb of the differential amplifier circuit 12, and

output terminals

52c and 52d. The emitter follower circuit 52 outputs output voltages V _outp and V _outn corresponding to the output voltages V _mp and V _mn input to these

input terminals

52a and 52b from the

output terminals

52c and 52d, respectively. More specifically, the emitter follower circuit 52 includes npn-type bipolar transistors Q ₁₁ and Q ₁₂ and constant

current sources

53 and 54. npn-type bipolar transistor Q ₁₁ has a base electrode connected to the input terminal 52a, a collector electrode connected to the first power supply line 10C, is connected to the second power supply line 10E via a constant current source 53 And an emitter electrode. Emitter output terminal 52c of the follower circuit 52 is npn-type bipolar transistors electrically connected to the emitter electrode of _{Q 11.}

On the other hand, npn-type bipolar transistor Q ₁₂ is connected to a base electrode connected to the input terminal 52 b, and a collector electrode connected to the first power supply line 10C, the second power supply line 10E via a constant current source 54 And an emitter electrode. Emitter output terminal 52d of the follower circuit 52 is npn-type bipolar transistor connected emitter electrode and electrically in _{Q 12.}

The emitter follower circuit 52 is configured using a plurality of npn-type bipolar transistors, but is not limited to this. Instead of the emitter follower circuit 52, an emitter follower circuit configured using a plurality of pnp bipolar transistors may be employed.

Also in the differential amplifier circuit 12 of the second embodiment as described above, the shunt circuit 41, a first power supply current path having a conductance value corresponding to the common mode input voltage V _C which is detected by the voltage detector 30 Since it can be formed between the line 10C and the common connection node 23c, CMRR can be improved. Therefore, it is possible to provide the differential amplifier circuit 12 and the voltage buffer circuit 2 having excellent noise resistance. Further, when the voltage buffer circuit 12 is configured as an integrated circuit, a high CMRR can be realized even if the integrated circuit is miniaturized.

Embodiment 3 FIG.
Next, a third embodiment which is a modification of the first embodiment will be described. FIG. 3 is a diagram schematically showing a circuit configuration of the voltage buffer circuit 3 according to the third embodiment of the present invention. As shown in FIG. 3, the voltage buffer circuit 3 includes a differential amplifier circuit 13 and a source follower circuit 51. The differential amplifier circuit 13 and the source follower circuit 51 operates using a power supply voltage _{V DD} supplied from the first power supply line 10D, and a power supply voltage _{V SS} supplied from the second power supply line 10S.

The differential amplifier circuit 13 includes a differential pair 21 and a constant amplifier for amplifying the difference between the input voltages V _inp and V _inn applied to the differential input terminals INa and INb (first and second differential input terminals), respectively. A combination of the current sources 22, a voltage detector 30 that detects the common-mode input voltage V _C from these input voltages V _inp and V _inn , and an amplifier 44 that amplifies the common-mode input voltage V _C with a gain _Av and outputs an amplified voltage. And a shunt circuit 40 that operates in response to the supply of the amplified voltage output from the amplifier 44, and differential output terminals OTa, OTb (first and second differential output terminals).

The configuration of the voltage buffer circuit 3 of the present embodiment is the same as the configuration of the voltage buffer circuit 1 of the first embodiment except that the differential amplifier circuit 13 includes an amplifier 44. The gate electrode of the minute diverting transistor M ₄ of the shunt circuit 40 amplifies the voltage supplied from the amplifier 44 is applied. Thereby, the amount of current flowing through the shunt circuit 40 can be increased corresponding to the in-phase input component. The CMRR of the differential amplifier circuit 13 is approximately given by the following equation (12).

As described above, in the differential amplifier circuit 13 of the third embodiment, the shunt circuit 40 commonly connects the current path having the conductance value corresponding to the common-mode input voltage amplified by the amplifier 44 with the first power supply line 10D. Since it can be formed with the node 21c, further improvement of CMRR can be realized as compared with the case of the first embodiment. Therefore, it is possible to provide the differential amplifier circuit 13 and the voltage buffer circuit 3 having excellent noise resistance. Further, when the voltage buffer circuit 3 is configured as an integrated circuit, a high CMRR can be realized even if the integrated circuit is miniaturized.

Embodiment 4 FIG.
The differential amplifier circuit 13 and the source follower circuit 51 in the voltage buffer circuit 3 of the third embodiment are configured using a plurality of FETs. Instead of these FETs, it is possible to configure a voltage buffer circuit using bipolar transistors. FIG. 4 schematically shows a circuit configuration of voltage buffer circuit 4 according to the fourth embodiment of the present invention. The voltage buffer circuit 4 includes a differential amplifier circuit 14 and an emitter follower circuit 52. The differential amplifier circuit 14 and an emitter follower circuit 52 operates using a power supply voltage _{V CC} supplied from the first power supply line 10C, and a power supply voltage _{V EE} supplied from the second power supply line 10E.

The differential amplifier circuit 14 includes a differential pair 23 and a constant amplifier for amplifying the difference between the input voltages V _inp and V _inn applied to the differential input terminals INa and INb (first and second differential input terminals), respectively. From the combination of the current sources 24, the voltage detector 30 for detecting the common-mode input voltage V _C from the input voltages V _inp and V _inn , the amplifier 45 for amplifying the common-mode input voltage V _C and outputting the amplified voltage, and the amplifier 45 A shunt circuit 41 that operates in response to the supplied amplified voltage and differential output terminals OTa, OTb (first and second differential output terminals) are provided.

The configuration of the voltage buffer circuit 4 of the present embodiment is the same as the configuration of the voltage buffer circuit 2 (FIG. 2) of the second embodiment except that the differential amplifier circuit 14 includes an amplifier 45. The base electrode of the minute diverting transistor Q ₄ of the shunt circuit 41 amplifies the voltage supplied from the amplifier 45 is applied. Thereby, the amount of current flowing through the shunt circuit 40 can be increased corresponding to the in-phase input component.

As described above, in the differential amplifier circuit 14 of the fourth embodiment, the shunt circuit 41 commonly connects the current path having the conductance value corresponding to the common-mode input voltage amplified by the amplifier 45 with the first power supply line 10C. Since it can be formed between the node 23c and the second embodiment, the CMRR can be further improved as compared with the second embodiment. Therefore, it is possible to provide the differential amplifier circuit 14 and the voltage buffer circuit 4 having excellent noise tolerance. Further, when the voltage buffer circuit 4 is configured as an integrated circuit, a high CMRR can be realized even if the integrated circuit is miniaturized.

Embodiment 5 FIG.
Next, a fifth embodiment which is another modification of the first embodiment will be described. FIG. 5 schematically shows a circuit configuration of voltage buffer circuit 5 according to the fifth embodiment of the present invention. As shown in FIG. 5, the voltage buffer circuit 5 includes a differential amplifier circuit 15 and a source follower circuit 51. The differential amplifier circuit 15 and the source follower circuit 51 operates using a power supply voltage _{V DD} supplied from the first power supply line 10D, and a power supply voltage _{V SS} supplied from the second power supply line 10S.

The differential amplifier circuit 15 includes a differential pair 21 that amplifies a difference between input voltages V _inp and V _inn applied to the differential input terminals INa and INb (first and second differential input terminals), and a constant pair. A combination of the current sources 22, a voltage detector 30 that detects the common-mode input voltage V _C from the input voltages V _inp and V _inn , and a shunt circuit 42 that operates by receiving the supply of the common-mode input voltage V _C from the voltage detector 30. And differential output terminals OTa and OTb (first and second differential output terminals).

The configuration of the voltage buffer circuit 5 of the present embodiment is the same as that of the first embodiment except that the differential amplifier circuit 15 has the shunt circuit 42 of FIG. 5 instead of the shunt circuit 40 of the first embodiment. The configuration of the buffer circuit 1 is the same.

The shunt circuit 42 according to the present embodiment includes a variable resistor 46 connected between the first power supply line 10D and the common connection node 21c. The variable resistor 46 may be formed between the current path having a conductance value corresponding to the value of the common-mode input voltage V _C and the first power supply line 10D and the common connection node 21c. Variable resistor 46, the larger the value of the common-mode input voltage V _C, it is possible to increase the conductance. Therefore, CMRR can be improved as in the case of the first embodiment. 6A and 6B are schematic diagrams showing

variable resistance circuits

46A and 46B, which are circuit configuration examples of such a variable resistor 46. FIG. 6A includes a resistance element 46a having one end connected to the first power supply line 10D and the other end connected to the common connection node 21c, and an n-channel type connected in parallel to the resistance element 46a. configured to include a control transistor _{M 5} consisting of FET. In the control transistor M _5, a drain electrode is electrically connected to the first power supply line 10D, a source electrode common connection node 21c and is electrically connected to the common mode input voltage V _C is applied to the gate electrode. On the other hand, the variable resistance circuit 46B of FIG. 6B includes a control element M including a resistance element 46b having one end connected to the first power supply line 10D and an n-channel FET connected in series to the other end of the resistance element 46b. ₆ . In the control transistor M ₆ has a drain electrode electrically connected to the other end of the resistance element 46b, a source electrode connected to the common connection node 21c and electrically, the common mode input voltage V _C is applied to the gate electrode. The circuit configuration of the variable resistor 46 is not limited to the

variable resistance circuits

46A and 46B of FIGS. 6A and 6B, and a circuit configuration other than the

variable resistance circuits

46A and 46B may be used.

As described above, in the fifth embodiment, it is possible to provide the differential amplifier circuit 15 and the voltage buffer circuit 5 that achieve an improvement in CMRR and have excellent noise resistance. Further, when the voltage buffer circuit 5 is configured as an integrated circuit, high CMRR can be realized even if the integrated circuit is miniaturized.

Embodiment 6 FIG.
The differential amplifier circuit 15 and the source follower circuit 51 in the voltage buffer circuit 5 of the fifth embodiment are configured using a plurality of FETs. Instead of these FETs, it is possible to configure a voltage buffer circuit using bipolar transistors. FIG. 7 schematically shows a circuit configuration of voltage buffer circuit 6 according to the sixth embodiment of the present invention. The voltage buffer circuit 6 includes a differential amplifier circuit 16 and an emitter follower circuit 52. The differential amplifier circuit 16 and an emitter follower circuit 52 operates using a power supply voltage _{V CC} supplied from the first power supply line 10C, and a power supply voltage _{V EE} supplied from the second power supply line 10E.

The differential amplifier circuit 16 includes a differential pair 23 and a constant amplifier that amplify the difference between the input voltages V _inp and V _inn applied to the differential input terminals INa and INb (first and second differential input terminals), respectively. A combination of the current sources 24, a voltage detector 30 that detects the common-mode input voltage V _C from the input voltages V _inp and V _inn , and a shunt circuit 43 that operates by receiving the supply of the common-mode input voltage V _C from the voltage detector 30 And differential output terminals OTa and OTb (first and second differential output terminals).

The configuration of the voltage buffer circuit 6 of the present embodiment is the same as that of the second embodiment except that the differential amplifier circuit 16 has the shunt circuit 43 of FIG. 7 instead of the shunt circuit 41 of the second embodiment. The configuration is the same as that of the buffer circuit 2.

The shunt circuit 43 of the present embodiment includes a variable resistor 47 connected between the first power supply line 10C and the common connection node 23c. The variable resistor 47 can form a current path having a conductance value corresponding to the value of the common-mode input voltage V _C between the first power supply line 10C and the common connection node 23c. The variable resistor 47 can increase the conductance value as the value of the common-mode input voltage V _C increases. Therefore, as in the case of the second embodiment, CMRR can be improved. Further, when the voltage buffer circuit 6 is configured as an integrated circuit, a high CMRR can be realized even if the integrated circuit is miniaturized.

Although various embodiments according to the present invention have been described above with reference to the drawings, these embodiments are examples of the present invention, and various forms other than these embodiments can be adopted. For example, a voltage buffer circuit may be configured by combining any of

differential amplifier circuits

11, 13, and 15 of the first, third, and fifth embodiments and emitter follower circuit 52 of the second embodiment. Alternatively, the voltage buffer circuit may be configured by combining any of the

differential amplifier circuits

12, 14, and 16 of the second, fourth, and sixth embodiments and the source follower circuit 51 of the first embodiment.

It should be noted that within the scope of the present invention, the above-described first to sixth embodiments can be freely combined, any constituent element of each embodiment can be modified, or any constituent element of each embodiment can be omitted.

The differential amplifier circuit and the voltage buffer circuit according to the present invention are suitable for use in, for example, an analog integrated circuit that operates in a high frequency region.

1 to 6 voltage buffer circuit, 11 to 16 differential amplifier circuit, 21 and 23 differential pair, 21c and 23c common connection node, 22 and 24 constant current source, 30 voltage detector, 40 to 43 shunt circuit, 44, 45 amplifier, 46, 47 variable resistor, 46A, 46B variable resistance circuit, 51 source follower circuit, 52 emitter follower circuit, 53, 54 constant current source, M ₁ , M ₂ , Q ₁ , Q ₂ amplification transistor, M ₃ constant current transistor, _{M 4} minutes diverting _{_transistor, M} _11, M ₁₂ field effect _{_transistor, M} _13, M ₁₄ load transistor, _{Q 3} bipolar transistors, _{Q 4} minutes diverted _{_transistors, Q} _11, Q ₁₂ bipolar transistors, INa, INb difference Dynamic input terminal, OTa, OTb differential output terminal.

Claims

First and second differential input terminals;
A first power supply line for supplying a predetermined first power supply voltage;
A second power supply line for supplying a second power supply voltage different from the first power supply voltage;
A first amplifying transistor comprising a field effect transistor having a gate electrode electrically connected to the first differential input terminal and having a drain electrode electrically connected to the first power supply line;
A second amplification transistor comprising a field effect transistor having a gate electrode electrically connected to the second differential input terminal and having a drain electrode electrically connected to the first power supply line;
A common connection node electrically connected to respective source electrodes of the first and second amplification transistors;
A constant current source connected between the common connection node and the second power supply line;
A voltage detector that detects a common-mode input voltage from input voltages applied to the first and second differential input terminals and outputs the common-mode input voltage;
A shunt circuit disposed between the common connection node and the first power supply line and forming a current path having a conductance value corresponding to the common-mode input voltage;
A differential amplifier comprising: a first differential output terminal electrically connected to the drain electrode of the first amplification transistor and the drain electrode of the second amplification transistor, respectively. circuit.
The differential amplifier circuit according to claim 1,
The shunt circuit includes a shunt transistor;
The shunt transistor includes a gate electrode to which the common-mode input voltage is applied, a source electrode electrically connected to the common connection node, and a drain electrode electrically connected to the first power supply line. A differential amplifier circuit comprising a field effect transistor.
3. The differential amplifier circuit according to claim 2, wherein the shunting transistor is a variable resistor that increases the conductance value as the value of the common-mode input voltage increases.
The differential amplifier circuit according to claim 1, further comprising an amplifier that amplifies the common-mode input voltage and outputs an amplified voltage,
The shunt circuit includes a shunt transistor connected between the common connection node and the first power supply line,
The shunt transistor has an electric field having a gate electrode to which the amplified voltage is applied, a source electrode electrically connected to the common connection node, and a drain electrode electrically connected to the first power supply line. A differential amplifier circuit comprising an effect transistor.
2. The differential amplifier circuit according to claim 1, wherein the shunt circuit includes a variable resistor that increases the conductance value as the value of the common-mode input voltage increases.
First and second differential input terminals;
A first power supply line for supplying a predetermined first power supply voltage;
A second power supply line for supplying a second power supply voltage different from the first power supply voltage;
A first amplifying transistor comprising a bipolar transistor having a base electrode electrically connected to the first differential input terminal and having a collector electrode electrically connected to the first power supply line;
A second amplification transistor comprising a bipolar transistor having a base electrode electrically connected to the second differential input terminal and having a collector electrode electrically connected to the first power supply line;
A common connection node electrically connected to the respective emitter electrodes of the first and second amplification transistors;
A constant current source connected between the common connection node and the second power supply line;
A voltage detector that detects a common-mode input voltage from input voltages applied to the first and second differential input terminals and outputs the common-mode input voltage;
A shunt circuit connected between the common connection node and the first power supply line and having a conductance value corresponding to the common-mode input voltage;
A differential amplifier comprising first and second differential output terminals electrically connected to the collector electrode of the first amplification transistor and the collector electrode of the second amplification transistor, respectively. circuit.
The differential amplifier circuit according to claim 6,
The shunt circuit includes a shunt transistor;
The shunt transistor includes a base electrode to which the common-mode input voltage is applied, an emitter electrode electrically connected to the common connection node, and a collector electrode electrically connected to the first power supply line. A differential amplifier circuit comprising a bipolar transistor.
8. The differential amplifier circuit according to claim 7, wherein the shunting transistor is a variable resistor that increases the conductance value as the value of the common-mode input voltage increases.
The differential amplifier circuit according to claim 6, further comprising an amplifier that amplifies the common-mode input voltage and outputs an amplified voltage,
The shunt circuit includes a shunt transistor connected between the common connection node and the first power supply line,
The shunting transistor is a bipolar transistor having a base electrode to which the amplified voltage is applied, an emitter electrode electrically connected to the common connection node, and a collector electrode electrically connected to the first power supply line. A differential amplifier circuit comprising a transistor.
7. The differential amplifier circuit according to claim 6, wherein the shunt circuit includes a variable resistor that increases the conductance value as the value of the common-mode input voltage increases.
A differential amplifier circuit according to claim 1;
A voltage buffer circuit comprising: a source follower circuit that outputs a signal corresponding to an output of the differential amplifier circuit.
A differential amplifier circuit according to claim 6;
A voltage buffer circuit comprising: an emitter follower circuit that outputs a signal corresponding to the output of the differential amplifier circuit.