WO2018055671A1

WO2018055671A1 - Inverter device, compressor drive device, and air conditioner

Info

Publication number: WO2018055671A1
Application number: PCT/JP2016/077684
Authority: WO
Inventors: 鹿嶋　美津夫
Original assignee: 三菱電機株式会社
Priority date: 2016-09-20
Filing date: 2016-09-20
Publication date: 2018-03-29
Also published as: JPWO2018055671A1; JP6591081B2

Abstract

An inverter device (100) is characterized by being provided with: an inverter main circuit (3); a direct current detection circuit (5) that detects a direct current flowing in a direct current bus bar; and an inverter control unit (7) that outputs a pulse width modulation drive signal for controlling a plurality of semiconductor switching elements on the basis of the direct current detected by the direct current detection circuit (5). The inverter device is also characterized in that, when an operation frequency for operating the pulse width modulation drive signal is represented by Ts, an operation time of the pulse width modulation drive signal is represented by Tx, and a control carrier period of the pulse width modulation drive signal is represented by Tc, the inverter control unit (7) sets, as Tc, a value satisfying formula of Tx<(Ts-Tc/2).

Description

Inverter device, compressor drive device and air conditioner

The present invention relates to an inverter device, a compressor driving device, and an air conditioner that convert DC power supplied from a DC bus into three-phase AC power by driving a plurality of switching elements in an inverter main circuit.

The conventional inverter device shown in Patent Document 1 includes an inverter main circuit including an upper arm switching element group connected to the positive side of a DC power source and a lower arm switching element group connected to the negative side of the DC power source, Generates a current sensor that detects the direct current flowing between the power supply and the inverter main circuit, and a pulse width modulation (PWM) drive signal that controls on / off of each of the upper arm switching element group and the lower arm switching element group A control circuit. The control circuit detects the phase current with the current sensor at the timing near the end of the ON period of the upper arm switching element group after the half cycle within the carrier cycle, and uses the phase current detected with the current sensor in the next carrier cycle And it is comprised so that the control which calculates the PWM modulation | alteration in the following next carrier period may be performed.

Japanese Patent No. 5200395

However, since the conventional inverter device shown in Patent Document 1 uses the detected current in the next carrier cycle and performs control to calculate PWM modulation in the next carrier cycle, the detected current value is Since it is based on the PWM modulation generated by the previous calculation, there is a problem that the control responsiveness is low and the step-out or overcurrent interruption occurs without being able to follow the load fluctuation at the time of high-speed rotation.

The present invention has been made in view of the above, and obtains an inverter device that improves control responsiveness by making a detected current value based on PWM modulation generated by the immediately preceding calculation. With the goal.

In order to solve the above-described problems and achieve the object, an inverter device according to the present invention is an inverter main circuit that converts DC power supplied from a DC bus into three-phase AC power using a plurality of semiconductor switching elements. A DC current detection circuit that detects a DC current flowing in the DC bus, and an inverter control unit that outputs a pulse width modulation drive signal that controls a plurality of semiconductor switching elements based on the DC current detected by the DC current detection circuit; Is provided. When the calculation cycle for calculating the pulse width modulation drive signal is Ts, the calculation processing time of the pulse width modulation drive signal is Tx, and the control carrier cycle of the pulse width modulation drive signal is Tc, A value satisfying “Tx <(Ts−Tc / 2)” is set.

The inverter device according to the present invention has an effect of improving control responsiveness by making the detected current value based on the PWM modulation generated by the immediately preceding calculation.

The block diagram of the inverter apparatus which concerns on Embodiment 1 of this invention FIG. 1 is a timing chart showing an operation from when a PWM drive signal is calculated based on a DC current detected by the DC current detection circuit shown in FIG. 1 until the calculated PWM drive signal is reflected. Output voltage vector Vs per calculation cycle calculated by the inverter control unit according to Embodiment 1 of the present invention, and output voltage vector Vsc per half carrier cycle of control carrier 1 before correction by the output voltage vector correction unit Diagram showing the relationship The figure which shows the correspondence of the switching state of the switching element of the inverter main circuit with respect to a basic voltage vector, and the phase current information reproduced from DC current Idc Timing chart of PWM drive signal corresponding to output voltage vector Vsc shown in FIG. The figure which shows the relationship between the output voltage vector Vs per calculation period calculated by the inverter control part which concerns on Embodiment 1 of this invention, and the output voltage vectors Vsa and Vsb after correction | amendment by an output voltage vector correction | amendment part. First timing chart of the PWM drive signal corrected by the output voltage vector correction unit corresponding to the output voltage vectors Vsa and Vsb shown in FIG. Second timing chart of PWM drive signal corrected by output voltage vector correction unit corresponding to output voltage vectors Vsa and Vsb shown in FIG. The figure which shows the relationship between the control carrier period and total efficiency in modulation factor Vk1, Vk2, Vk3 (Vk1 <Vk2 <Vk3). The figure which shows the example of a setting of the control carrier period with respect to a modulation rate The block diagram of the compressor drive device and air conditioner concerning Embodiment 3 of this invention

Hereinafter, an inverter device, a compressor driving device, and an air conditioner according to an embodiment of the present invention will be described in detail based on the drawings. Note that the present invention is not limited to the embodiments.

Embodiment 1 FIG.
FIG. 1 is a configuration diagram of an inverter device according to Embodiment 1 of the present invention. In the first embodiment, an example in which the inverter device 100 is applied as a drive device for a compressor mounted on an air conditioner (not shown) will be described.

The inverter device 100 includes a converter circuit 2 that converts AC power supplied from the AC power source 1 into DC power, an inverter main circuit 3 that converts DC power output from the converter circuit 2 into three-phase AC power, and a converter circuit. 2 and a DC current detection circuit 5 for detecting a DC current Idc flowing in a negative DC bus N provided between the inverter main circuit 3 and a positive DC bus P provided between the converter circuit 2 and the inverter main circuit 3. A DC voltage detection circuit 6 that detects a DC voltage Vdc applied to the negative DC bus N and an inverter control unit 7 are provided. The inverter device 100 is connected to a three-phase permanent magnet synchronous motor 4 driven by the three-phase AC power output from the inverter main circuit 3.

The converter circuit 2 is configured such that the value of the DC voltage Vdc output from the converter circuit 2 changes from 250V to 450V. For example, when the AC power supply 1 is AC100V, a voltage doubler rectifier circuit is applied to the compressor driving converter circuit 2 provided in the air conditioner. When the AC power supply is AC200V, the compressor drive provided in the air conditioner is applied. A full-wave rectifier circuit is applied to the converter circuit 2 for use.

In addition, the compressor driving converter circuit 2 provided in the air conditioner may be configured to increase the pressure by short-circuiting and opening a reactor (not shown) disposed between the AC power source 1 and the converter circuit 2. A configuration may be adopted in which a reactor (not shown) arranged in a subsequent stage of a rectifier circuit that rectifies AC power supplied from the AC power supply 1 is boosted by short-circuiting and opening. As described above, many methods are applied to the converter circuit 2, and any method can be applied to the converter circuit 2 as long as the DC voltage Vdc output from the converter circuit 2 is in the range of 250V to 450V. May be used. The AC power source 1 shown in FIG. 1 is a single-phase AC power source, but may be a three-phase AC power source.

The inverter main circuit 3 includes switching elements SW1, SW2, SW3, SW4, SW5, which are a plurality of semiconductor switching elements composed of SiC-MOSFETs (SiC: Silicon Carbide, MOSFETs: Metal-Oxide-Semiconductor Field-Effect Transistors). SW6, a plurality of free-wheeling diodes D1, D2, D3, D4, D5, D6 connected in reverse parallel to each of the plurality of switching elements SW1, SW2, SW3, SW4, SW5, SW6, and a plurality of switching elements It comprises a plurality of

drive circuits

3a, 3b, 3c, 3d, 3e, 3f for driving each of SW1, SW2, SW3, SW4, SW5, SW6.

The switching elements SW1, SW2, SW3, SW4, SW5, and SW6 for driving the compressor provided in the air conditioner take into account the DC voltage Vdc output from the converter circuit 2 and the surge voltage generated by the wiring impedance. An element of around 600V is used. A SiC-MOSFET parasitic diode is used for the diodes D1, D2, D3, D4, D5, and D6 that are a plurality of freewheeling diodes. The drains of the switching elements SW1, SW2, SW3 are connected to the positive DC bus P. The sources of the switching elements SW4, SW5, SW6 are connected to the negative DC bus N. The source of the switching element SW1 is connected to the drain of the switching element SW4. The source of the switching element SW2 is connected to the drain of the switching element SW5. The source of the switching element SW3 is connected to the drain of the switching element SW6. Three switching elements SW1, SW2, SW3 connected to the positive DC bus P constitute an upper arm switching element group, and three switching elements SW4, SW5, SW6 arranged on the negative DC bus N are lower arms. A side switching element group is configured.

The drive circuit 3a receives the PWM drive signal UP output from the inverter control unit 7, converts the PWM drive signal UP into a voltage capable of driving the switching element SW1, and outputs the voltage to the gate of the switching element SW1. The drive circuit 3b receives the PWM drive signal VP output from the inverter control unit 7, converts the PWM drive signal VP into a voltage that can drive the switching element SW2, and outputs the voltage to the gate of the switching element SW2. The drive circuit 3c receives the PWM drive signal WP output from the inverter control unit 7, converts the PWM drive signal WP into a voltage that can drive the switching element SW3, and outputs the voltage to the gate of the switching element SW3. The drive circuit 3d receives the PWM drive signal UN output from the inverter control unit 7, converts the PWM drive signal UN into a voltage that can drive the switching element SW4, and outputs the voltage to the gate of the switching element SW4. The drive circuit 3e receives the PWM drive signal VN output from the inverter control unit 7, converts the PWM drive signal VN into a voltage that can drive the switching element SW5, and outputs the voltage to the gate of the switching element SW5. The drive circuit 3f receives the PWM drive signal WN output from the inverter control unit 7, converts the PWM drive signal WN into a voltage that can drive the switching element SW6, and outputs the voltage to the gate of the switching element SW6.

Hereinafter, the plurality of switching elements SW1, SW2, SW3, SW4, SW5, and SW6 are simply referred to as switching elements SW1 to SW6, and the plurality of diodes D1, D2, D3, D4, D5, and D6 are simply referred to as diodes D1 to D6. The plurality of

drive circuits

3a, 3b, 3c, 3d, 3e, and 3f may be simply referred to as drive circuits 3a to 3f.

The permanent magnet synchronous motor 4 includes a stator 4a in which a three-phase Y-shaped connection composed of a U-phase winding 41, a V-phase winding 42, and a W-phase winding 43 is provided on a stator core (not shown), The permanent magnet rotor 4b provided inside the child 4a, the terminal U connected to the U-phase winding 41, the terminal V connected to the V-phase winding 42, and the W-phase winding 43 are connected. And a terminal W.

The connection point 3-1 of the switching element SW1 and the switching element SW4 of the inverter main circuit 3 is connected to the terminal U of the permanent magnet synchronous motor 4. A connection point 3-2 between the switching element SW2 and the switching element SW5 of the inverter main circuit 3 is connected to the terminal V of the permanent magnet synchronous motor 4. A connection point 3-3 between the switching element SW3 and the switching element SW6 of the inverter main circuit 3 is connected to a terminal W of the permanent magnet synchronous motor 4. In the first embodiment, the current flowing between the connection point 3-1 of the switching element SW1 and the switching element SW4 and the terminal U is referred to as a U-phase current Iu, and the connection point 3-2 of the switching element SW2 and the switching element SW5 A current flowing between the terminal V and the terminal W is referred to as a V-phase current Iv, and a current flowing between the connection point 3-3 of the switching element SW3 and the switching element SW6 and the terminal W is referred to as a W-phase current Iw.

The U-phase current Iu, the V-phase current Iv, and the W-phase current Iw are supplied to the stator 4a of the permanent magnet synchronous motor 4, and the permanent magnet rotor 4b is rotated by the magnetic field generated by the stator 4a, and the permanent magnet rotor 4b. As the compressor (not shown) connected to the motor rotates, the refrigerant circulates in the air conditioner. In the first embodiment, an example in which the stator 4a provided with the three-phase Y-type connection is used for the permanent magnet synchronous motor 4 is described. However, the permanent magnet synchronous motor 4 is provided with the three-phase Y-type connection. Instead of the fixed stator 4a, a stator 4a provided with a three-phase Δ-shaped connection may be used.

The DC current detection circuit 5 includes a shunt resistor 5a and an amplifier 5b provided on the negative DC bus N. The amplifier 5b amplifies the voltage drop between both ends of the shunt resistor 5a caused by the direct current flowing through the shunt resistor 5a, and outputs the amplified voltage to the inverter control unit 7 as current information corresponding to the direct current Idc. In FIG. 1, the current information output from the amplifier 5b is expressed as a direct current Idc. As the amplifier 5b, a circuit using an operational amplifier can be exemplified. In the first embodiment, a configuration example of a DC current detection circuit 5 that detects a DC current by amplifying a voltage drop across the shunt resistor 5a is shown. The DC current detection circuit 5 detects a DC current. A possible DCCT (DC Current Transformer) may be used.

The DC voltage detection circuit 6 divides the DC voltage Vdc applied between the positive DC bus P and the negative DC bus N connected to the output side of the converter circuit 2 and supplies the divided voltage to the inverter control unit 7.

The inverter control unit 7 configures the inverter main circuit 3 based on the DC current detected by the DC current detection circuit 5, the voltage detected by the DC voltage detection circuit 6, and the frequency command value f * given from the outside. PWM drive signals UP, UN, VP, VN, WP, and WN for controlling each of the switching elements SW1 to SW6 to be output are output. Hereinafter, the frequency command value f * may be simply represented by f *, and the PWM drive signals UP, UN, VP, VN, WP, and WN may be simply referred to as PWM drive signals UP to WN.

PWM drive signals UP, VP, and WP are PWM drive signals of the upper arm side switching element group of the inverter main circuit 3, and are signals for driving the switching elements SW1, SW2, and SW3, respectively. The PWM drive signals UN, VN, WN are PWM drive signals for the lower arm side switching element group of the inverter main circuit 3, and are signals for driving the switching elements SW4, SW5, SW6, respectively.

The inverter control unit 7 can be realized by a microprocessor. The inverter control unit 7 includes an AD (Analog to Digital) converter 8, an AD converter 9, and an output voltage vector correction unit 10. The output of the direct current detection circuit 5 is input to the AD converter 8, and the AD converter 8 converts the analog voltage output from the direct current detection circuit 5 into a digital value that can be used for calculation in the inverter control unit 7. Convert. The output of the DC voltage detection circuit 6 is input to the AD converter 9, and the AD converter 9 converts the analog voltage output from the DC voltage detection circuit 6 into a digital value that can be used for calculation in the inverter control unit 7. Convert.

The output voltage vector correction unit 10 corrects the output voltage vector in order to reproduce the phase current for two phases from the direct current Idc during one calculation cycle for calculating the PWM drive signal. The output voltage vector will be described later.

Next, the operation of the inverter device 100 will be described. FIG. 2 is a timing chart showing the operation from the calculation of the PWM drive signal based on the value of the DC current detected by the DC current detection circuit shown in FIG. 1 to the reflection of the calculated PWM drive signal. is there. Hereinafter, the calculation of the PWM drive signal may be simply referred to as PWM calculation.

In FIG. 2, (a) shows the reference carrier of the PWM signal. The reference carrier cycle Tc_std is the same as the calculation cycle Ts for calculating the PWM drive signal, and “Tc_std = Ts” is displayed in FIG. In (b), the start timing of the PWM calculation is indicated by an arrow.

(C) shows a control carrier 1 for generating a PWM drive signal. The control carrier 1 is an example of the control carrier when the calculation processing time Tx of the PWM calculation is set to “Ts / 2 ≦ Tx <2Ts / 3”, and the carrier cycle Tc1 of the control carrier 1 is “Tc1 = 2Ts / 3 ". Hereinafter, the carrier period Tc1 of the control carrier 1 may be simply referred to as a control carrier period Tc1. (D) shows a processing interval of PWM calculation when the calculation processing time Tx is set to “Ts / 2 ≦ Tx <2Ts / 3”.

(E) shows a control carrier 2 for generating a PWM drive signal. The control carrier 2 is an example of the control carrier when the calculation processing time Tx of the PWM calculation is set to “2Ts / 3 ≦ Tx <3Ts / 4”, and the carrier period Tc2 of the control carrier 2 is “Tc2 = Ts / 2 ". Hereinafter, the carrier period Tc2 of the control carrier 2 may be simply referred to as a control carrier period Tc2. (F) shows a PWM calculation processing section when the calculation processing time Tx is set to “2Ts / 3 ≦ Tx <3Ts / 4”.

(G) shows a control carrier 3 for generating a PWM drive signal. The control carrier 3 is an example of the control carrier when the calculation processing time Tx of the PWM calculation is set to “3Ts / 4 ≦ Tx <4Ts / 5”, and the carrier period Tc3 of the control carrier 3 is “Tc3 = 2Ts / 5 ". Hereinafter, the carrier period Tc3 of the control carrier 3 may be simply referred to as a control carrier period Tc3. (H) shows a processing section of PWM calculation when the calculation processing time Tx is set to “3Ts / 4 ≦ Tx <4Ts / 5”.

FIG. 2 illustrates a reference carrier and a control carrier that are symmetrical triangular wave carriers. In FIG. 2, the valley timing of the reference carrier coincides with the valley timing or peak timing of the control carrier. In the

control carriers

1, 2, and 3 shown in (c), (e), and (g), sections reflecting the output voltage vector are overlaid. In (c), (e), and (g), the output voltage vector is represented in the form of “Vsxy_z” for convenience. That is, (c) represents the output voltage vector Vsxy_z calculated by the PWM calculation shown in (d), (e) shows the output voltage vector Vsxy_z calculated by the PWM calculation shown in (f), (G) shows an output voltage vector Vsxy_z calculated by the PWM calculation shown in (h).

“X” portion of the output voltage vector Vsxy_z includes “a” and “b”, and the output voltage vector of “x = a” is obtained from the DC current Idc detected by the DC current detection circuit 5. 4 indicates that the vector can reproduce the phase current information for two phases flowing through 4. The output voltage vector of “x = b” indicates a vector that becomes an output voltage vector per calculation cycle, which will be described later, when combined with the output voltage vector of “x = a”. However, as will be described later, when the modulation rate is 1 or more, there is a possibility that even if two vectors are combined, they do not match the output voltage vector per calculation cycle.

An integer is entered in the “y” portion of Vsxy_z, and the output voltage vector of “y = 1” is an output calculated by “calculation processing 1” shown in each of (d), (f), and (h). Indicates the voltage vector. The output voltage vector of “y = 2” indicates the output voltage vector calculated in “calculation process 2” shown in each of (d), (f), and (h).

The number of the corresponding control carrier is entered in the “z” portion of Vsxy_z, and the output voltage vector of “z = 1” indicates an output voltage vector of the control carrier 1 by PWM calculation. The output voltage vector of “z = 2” indicates an output voltage vector obtained by PWM calculation of the control carrier 2. The output voltage vector of “z = 3” indicates an output voltage vector obtained by PWM calculation of the control carrier 3.

Subsequently, the operation from when the DC current Idc is detected until the PWM drive signal is calculated and the calculated PWM drive signal is reflected will be described by taking the timing of the calculation process 1 of (d) PWM calculation as an example. To do.

The calculation start timing of the calculation process 1 is the valley timing D of the reference carrier. Timing D is also the valley timing of the control carrier 1. The direct current Idc used in the calculation process 1 is detected in a section A to D that is a half carrier period of the control carrier 1 immediately before the calculation start timing D. Since the PWM drive signal corresponding to the output voltage vector “Vsa0_1” is output in the half-carrier cycle period from A to D, the inverter control unit 7 outputs the current flowing through the permanent magnet synchronous motor 4 based on the direct current Idc. Phase current information for the phase can be detected.

Based on the direct current Idc, the inverter control unit 7 obtains an output voltage vector at the center phase from the timing F before the next carrier start timing I to the timing K after one calculation cycle from the timing F before the half carrier cycle of the control carrier 1. . The inverter control unit 7 performs this calculation within a section from the calculation start timing D to the timing F. The PWM drive signal for the calculated output voltage vector is reflected in the interval from timing F to timing K. Hereinafter, a section in which the PWM drive signal for the calculated output voltage vector is reflected, such as a section from F to K, may be referred to as a “PWM drive signal reflection section”.

The inverter control unit 7 outputs a PWM drive signal corresponding to the output voltage vector “Vsa1_1” in a section from F to I which is a half carrier period of the control carrier 1 immediately before the calculation start timing I of the next calculation process 2. The PWM drive signal corresponding to the output voltage vector “Vsb1_1” is output in the remaining I to K intervals.

Similarly, in the inverter control unit 7, the calculation after the calculation process 2 of (d) is performed every calculation cycle Ts. Here, the calculation start timing does not necessarily need to be the valley timing or peak timing of the triangular wave carrier, and if it can be ensured that the calculation is completed by the timing at which the PWM drive signal is to be reflected, the calculation start timing is higher than the above timing. You can be late. In the inverter control unit 7, the operations (f) and (h) are performed in the same manner as (d).

Next, the output voltage vector will be described. The magnitude | Vs | of the output voltage vector Vs and the phase θv from the γ-axis are as follows if the values of the γ-axis voltage Vγ and the δ-axis voltage Vδ on the control axis (γ-δ axis) of the rotating coordinate system are obtained. It can obtain | require from Formula (1) and Formula (2).

The γ-axis voltage Vγ and the δ-axis voltage Vδ are based on the angular velocity command value ω * (= 2π × f *) and the phase current information flowing through the permanent magnet synchronous motor 4, for example, as disclosed in Japanese Patent No. 3860031. It can be calculated by the method.

Further, the modulation factor in this case is obtained from the following equation (3) based on the DC voltage Vdc detected by the DC voltage detection circuit 6.

Subsequently, the relationship between the output voltage vector Vs and the switching elements of the inverter main circuit 3 will be described.

FIG. 3 shows the output voltage vector Vs per calculation cycle calculated by the inverter control unit according to Embodiment 1 of the present invention, and the output per half carrier cycle of the control carrier 1 before correction by the output voltage vector correction unit 10. It is a figure which shows the relationship with the voltage vector Vsc. FIG. 4 is a diagram showing a correspondence relationship between the switching state of the switching element of the inverter main circuit and the phase current information reproduced from the DC current Idc with respect to the basic voltage vector. FIG. 5 is a timing chart of the PWM drive signal corresponding to the output voltage vector Vsc shown in FIG. FIG. 6 shows the relationship between the output voltage vector Vs per calculation cycle calculated by the inverter control unit according to Embodiment 1 of the present invention and the output voltage vectors Vsa and Vsb after correction by the output voltage vector correction unit 10. FIG.

FIG. 3 shows an output voltage vector Vs calculated for the control carrier 1. V0 to V7 shown in FIG. 3 are basic voltage vectors. In FIG. 4, each of the eight basic voltage vectors V0 to V7 corresponds to the ON or OFF state of each of the switching elements SW1 to SW6 of the inverter main circuit 3. It is attached.

As shown in FIG. 4, in the basic voltage vector V0, the switching elements SW1, SW2, and SW3 are OFF, and the switching elements SW4, SW5, and SW6 are ON. In the basic voltage vector V1, the switching elements SW2, SW3, SW4 are OFF, and the switching elements SW1, SW5, SW6 are ON. In the basic voltage vector V2, the switching elements SW3, SW4, SW5 are OFF, and the switching elements SW1, SW2, SW6 are ON. In the basic voltage vector V3, the switching elements SW1, SW3, SW5 are OFF, and the switching elements SW2, SW4, SW6 are ON. In the basic voltage vector V4, the switching elements SW1, SW5, SW6 are OFF, and the switching elements SW2, SW3, SW4 are ON. In the basic voltage vector V5, the switching elements SW1, SW2, and SW6 are OFF, and the switching elements SW3, SW4, and SW5 are ON. In the basic voltage vector V6, the switching elements SW2, SW4, SW6 are OFF, and the switching elements SW1, SW3, SW5 are ON. In the basic voltage vector V7, the switching elements SW4, SW5, SW6 are OFF, and the switching elements SW1, SW2, SW3 are ON.

FIG. 4 also shows phase current information flowing in the permanent magnet synchronous motor 4 reproduced from the direct current Idc when each of the switching elements SW1 to SW6 is in a non-zero voltage vector state of the basic voltage vectors V1 to V6. Are associated with the basic voltage vectors V1 to V6.

The basic voltage vector V1 corresponds to the phase current information “+ Iu”, the basic voltage vector V2 corresponds to the phase current information “−Iw”, and the basic voltage vector V3 corresponds to the phase current information “+ Iv”. The phase current information “−Iu” corresponds to the voltage vector V4, the phase current information “+ Iw” corresponds to the basic voltage vector V5, and the phase current information “−Iv” corresponds to the basic voltage vector V6. . The phase current information “+” indicates the direction of the phase current flowing from the inverter main circuit 3 toward the permanent magnet synchronous motor 4, and the phase current information “−” indicates the direction from the permanent magnet synchronous motor 4 to the inverter main circuit 3. The direction of the flowing phase current.

In FIG. 3, the magnitude of the output voltage vector Vs is indicated by the magnitude per calculation cycle Ts. In the first embodiment, since the control carrier period Tc1 is set to Tc1 = 2Ts / 3, the output voltage vector Vsc per half carrier period (Tc · 1/2) is 1 / of the magnitude of the output voltage vector Vs. 3 ti is the output time per half carrier period of the basic voltage vector V1 in the rotation direction out of V1 and V2 which are non-zero basic voltage vectors adjacent to the output voltage vector Vsc. The direction of rotation means backward with respect to the direction of rotation of the output voltage vector. tk is an output time per half carrier period of V2, which is a basic voltage vector ahead in the rotation direction. The rotation direction ahead means forward with respect to the rotation direction of the output voltage vector. TMIN is the minimum time required to detect the direct current supplied to the inverter main circuit 3. The minimum time TMIN is the response delay time of the drive circuits 3a to 3f and the switching elements SW1 to SW6, the ringing time generated in the DC current supplied to the inverter main circuit 3, the delay time of the DC current detection circuit 5, and AD It is set in consideration of the sample hold time of the converter 8 and a vertical short circuit prevention time described later.

Here, the angle from the basic voltage vector V1 that is the original in the rotation direction to the output voltage vector Vs among the basic voltage vectors V1 and V2 that are adjacent to the output voltage vector Vsc is non-illustrated. It is assumed that θx [°]. At this time, each of time ti and tk can be calculated | required by following formula (4) and Formula (5).

In FIG. 5, (a) shows the control carrier 1. (B) shows PWM drive signals UP to WN of the switching elements SW1 to SW6. (C) shows the direct current Idc. (D) shows a voltage vector state corresponding to the PWM drive signal. FIG. 5 shows a case where the PWM drive signal reflection interval starts from the falling edge of the carrier as in the AF interval of FIG.

Vsc shown in the control carrier 1 in FIG. 5A indicates an output voltage vector output in the half carrier cycle of the control carrier 1, and in FIG. 2 Vsc and one Vsc output in the rising half cycle of the control carrier 1 are shown.

In FIG. 5B, when the PWM drive signal is “H (ON)”, the corresponding switching element is turned ON, and when it is “L (OFF)”, the corresponding switching element is turned OFF. For example, when UP of the PWM drive signal is “H (ON)”, the corresponding switching element SW1 is turned ON, and when UP is “L (OFF)”, the switching element SW1 is turned OFF. In the first embodiment, the output ratio of the zero vectors V0 and V7 in the half carrier period is 1: 1, but this output ratio can be arbitrarily set.

Further, when the switching state of the PWM drive signal UP and the PWM drive signal UN is switched from “ON to OFF” or “OFF to ON”, it is necessary to provide a vertical short circuit prevention time for preventing the vertical short circuit of the switching element. However, it is omitted for simplification of explanation. The upper and lower short-circuit prevention time when the switching state of the PWM drive signal VP and the PWM drive signal VN is switched from “ON to OFF” or “OFF to ON” and the switching state of the PWM drive signal WP and the PWM drive signal WN are changed from “ON”. The same applies to the upper and lower short-circuit prevention time when switching from “OFF” or “OFF to ON”.

If the output voltage vector is obtained in this way, a PWM drive signal corresponding to the vector can be generated. However, as shown in FIG. 3, the time ti of the output voltage vector Vsc is equal to or greater than TMIN, but the time tk of the output voltage vector Vsc is less than TMIN, and the inverter control unit 7 uses the DC current Idc for two phases. Phase current information cannot be reproduced.

Therefore, as shown in FIG. 6, the output voltage vector correction unit 10 of the inverter control unit 7 according to the first embodiment corrects the output voltage vector Vs, and converts the output voltage vector Vs per calculation cycle Ts to a direct current. The output voltage vector Vsa in which the phase current information for two phases is reproduced from the Idc and the output voltage vector Vsb in which the combination of the output voltage vector Vsa becomes Vs is output. In this way, two sets of phase currents can be reproduced from the direct current during one calculation cycle, and the output voltage vector per calculation cycle can be kept the same.

Specifically, the output time per half carrier period of V1, which is the basic voltage vector in the rotation direction, among V1 and V2, which are adjacent to the output voltage vector Vsa and have a non-zero magnitude. Is tia, “tia = ti”, the output time per half carrier period of V2, which is the basic voltage vector ahead in the rotation direction, is tka, and “tka = TMIN”.

When “(tia + tka)> (Tc1 / 2)”, the longer output time of tia and tka is defined as “(Tc1 / 2) −TMIN”. Further, let tib be the remaining output section of the basic voltage vector in the rotation direction of the output voltage vector Vsb, that is, the output time per carrier cycle shown in FIG. The remaining output section of the basic voltage vector ahead of the rotation direction of the output voltage vector Vsb, that is, the output time per carrier period shown in FIG. The output voltage vector correction unit 10 of the inverter control unit 7 outputs the output time so that “(tib + tkb) = (Tc1 / 2) × Nc” when “(tib + tkb)> (Tc1 / 2) × Nc”. The shorter one of tib and tkb is brought closer to zero. Nc is the number of half carrier periods in the section in which the output voltage vector Vsb is output. In this case, Nc = 2.

If “(tib + tkb) = (Tc1 / 2) × Nc” is not satisfied even if the shorter output time is zero, the output voltage vector correction unit 10 of the inverter control unit 7 sets the longer output time to “(Tc1 / 2) × Nc ”. When the modulation factor is 1 or more, the output voltage vector Vsb is in such a state. In this case, the combined vector of the output voltage vector Vsa and the output voltage vector Vsb is completely different from the output voltage vector Vs. It does not match. However, such a state is a high rotation region where the PWM drive signal is saturated such that the modulation rate becomes 1 or more, and the output voltage vector per one calculation cycle before and after correction is held substantially the same. The

FIG. 7 is a first timing chart of the PWM drive signal corrected by the output voltage vector correction unit corresponding to the output voltage vectors Vsa and Vsb shown in FIG. FIG. 7 shows a case where the inverter control unit 7 outputs the output voltage vector Vsa in the first half carrier period of the PWM drive signal reflection interval and outputs the output voltage vector Vsb in the remaining PWM drive signal reflection interval. FIG. 7 shows a case where the PWM drive signal reflection section starts from the falling edge of the carrier as in FIG. The meanings of (a) to (d) shown in FIG. 7 are the same as (a) to (d) shown in FIG. Further, Trg1 and Trg2 in (c) shown in FIG. 7 represent detection timings for obtaining phase current information for two phases from the direct current Idc.

Here, in the first embodiment, the interval between the detection timing Trg1 and the detection timing Trg2 is a PWM drive signal having an intermediate ON width among a plurality of PWM drive signals for controlling the upper arm side switching element group, that is, FIG. 7 is set to the minimum time for obtaining phase current information for two phases before and after the timing when the PWM drive signal VP is switched from ON to OFF. This minimum time is the same length as the minimum time TMIN described above.

In this case, the inverter control unit 7 can obtain the phase current information for two phases based on the direct current Idc at the minimum time interval, so that the remaining one-phase phase current is also calculated based on the relationship of “Iu + Iv + Iw = 0”. There is an advantage that it can be accurately reproduced. However, the detection timing Trg1 is a timing near the end of the detected voltage vector state, and the detection timing Trg2 is a timing immediately after switching to the detected voltage vector state, so that the value of the detected phase current is actually Thus, the controllability of the permanent magnet synchronous motor 4 is deteriorated.

As a countermeasure, a carrier cycle Tc in which the state of the triangular wave carrier in the section in which the DC current Idc is detected for each calculation period, such as the control carrier 1 or the control carrier 3, is switched between the carrier rising section and the falling section is detected. By changing the relationship between the timing Trg1, the detection timing Trg2, and the voltage vector state, it is possible to mitigate the effect of deviating from the actual center value of the phase current. Although the control response is slightly sacrificed, the above effect can be further mitigated by taking a moving average of the reproduced phase current or the current value obtained by converting the phase current onto the control axis (γ-δ axis). .

FIG. 8 is a second timing chart of the PWM drive signal corrected by the output voltage vector correction unit corresponding to the output voltage vectors Vsa and Vsb shown in FIG. The difference between FIG. 7 and FIG. 8 is that in FIG. 7, the PWM drive signal reflection section starts from the falling edge of the carrier, whereas in FIG. 8, the PWM drive signal reflection section is the carrier like the FK section of FIG. It starts from the rise.

Here, the interval between the detection timing Trg1 and the detection timing Trg2 is a PWM drive signal having an intermediate ON width among a plurality of PWM drive signals for controlling the upper arm side switching element group, that is, the PWM drive signal in FIG. Before and after the timing when VP is switched from OFF to ON, the minimum time for obtaining phase current information for two phases is set. This minimum time is the same length as the minimum time TMIN described above.

As shown in FIG. 7, when the PWM drive signal reflection section starts from the falling edge of the carrier, the phase current (−Iw) corresponding to the basic voltage vector V2 is reproduced from the DC current Idc at the detection timing Trg1, and the DC current Idc is detected at the detection timing Trg2. Thus, the phase current (+ Iu) corresponding to the basic voltage vector V1 is reproduced.

On the other hand, when starting from the rising edge of the carrier as shown in FIG. 8, the phase current (+ Iu) corresponding to the basic voltage vector V1 is reproduced from the DC current Idc at the detection timing Trg1, and corresponding to the basic voltage vector V2 at the detection timing Trg2. The phase current (-Iw) is reproduced.

As described above, the inverter device 100 according to the first embodiment includes the inverter main circuit 3 that converts the DC power supplied from the DC bus into three-phase AC power using the plurality of switching elements SW1 to SW6, and the DC bus. A DC current detection circuit 5 that detects a flowing DC current, and an inverter control unit that outputs PWM drive signals UP to WN that control the plurality of switching elements SW1 to SW6 based on the DC current Idc detected by the DC current detection circuit 5 7. Then, the inverter control unit 7 sets “Tx <(Ts−Tc / Tc) to the control carrier cycle Tc of the PWM drive signals UP to WN, where Ts is the calculation cycle for calculating the PWM drive signals UP to WN and Tx is the calculation processing time. 2) ”is set, so that the PWM drive signal UP generated by the immediately preceding calculation process is used for the next calculation process even in applications where the calculation processing time Tx is ½ or more of the calculation cycle Ts. The inverter apparatus 100 can be obtained which can detect the direct current generated by .about.WN and has higher control responsiveness. Thereby, it is possible to follow load fluctuations during high-speed rotation, and it is possible to suppress the occurrence of step-out and overcurrent interruption.

Further, the inverter control unit 7 generates the PWM drive signals UP to WN based on the triangular wave carrier, and the state of the triangular wave carrier in the interval in which the DC current Idc is detected every calculation cycle Ts alternates between the carrier rising interval and the falling interval. By setting the control carrier cycle Tc so as to be switched, it is possible to suppress deterioration in controllability of the permanent magnet synchronous motor 4 that occurs when the phase current information reproduced from the DC current Idc deviates from the actual center value of the phase current. .

Further, the inverter control unit 7 corrects the output voltage vector in order to reproduce the phase current for two phases from the direct current Idc during one calculation cycle, corrects the output voltage vector, and calculates the output voltage vector before and after the correction. The output voltage vector correction unit 10 corrects the output voltage vectors to be the same. Thereby, the distortion of the phase current waveform due to the correction of the output voltage vector can be suppressed as much as possible, and the noise generated therewith can also be suppressed.

Further, when the modulation rate is 1 or more, the inverter control unit 7 outputs the output voltage vector Vsa in which the phase current information for two phases is reproduced from the DC current Idc and the remaining PWM other than the output voltage vector Vsa. Since the combined vector with the output voltage vector Vsb output in the drive signal reflecting section does not necessarily match the output voltage vector Vs per calculation cycle Ts, phase current information for two phases is always obtained from the DC current Idc. can get.

In addition, since the inverter device 100 can suppress switching loss by using wide band gap semiconductor elements such as SiC-MOSFETs for the switching elements SW1 to SW6 of the inverter main circuit 3, "Tx <(Ts-Tc / 2) "can be set with a high degree of freedom in setting the control carrier period Tc.

Although the SiC-MOSFET is used for the switching elements SW1 to SW6 of the inverter main circuit 3 according to the first embodiment and the parasitic diodes of the SiC-MOSFET are used for the diodes D1 to D6 which are freewheeling diodes, The elements SW1 to SW6 and the diodes D1 to D6 are not limited to these. Si-IGBT (Silicon-Insulated Gate Bipolar Transistor) used mainly in the inverter main circuit 3 for driving the compressor provided in the air conditioner may be used as the switching elements SW1 to SW6, or Si-FRD ( Silicon-Fast Recovery Diode) may be used as the diodes D1 to D6. In the first embodiment, generation of a PWM drive signal using a triangular wave carrier is described. However, the case where a similar PWM drive signal can be generated also in other carriers such as a sawtooth wave carrier is not limited to this. Needless to say.

Embodiment 2. FIG.
In the first embodiment, the example in which the control carrier period is a constant value has been described. In the second embodiment, an example in which the control carrier period is changed according to the modulation rate will be described. The hardware configuration of the inverter device 100 according to the second embodiment is the same as that of the inverter device 100 according to the first embodiment, and hereinafter, an example of calculation for changing the control carrier cycle in the inverter device 100 according to the second embodiment. explain.

In the inverter main circuit 3 for driving the compressor provided in the air conditioner, Si-IGBT is mainly used as the switching elements SW1 to SW6, and Si-FRD is mainly used as the reflux diode. In such an inverter main circuit 3, there is a point where the overall efficiency of the inverter main circuit 3 and the permanent magnet synchronous motor 4 is maximized at a control carrier frequency of around 5 kHz.

On the other hand, like the inverter device 100 according to the first embodiment, SiC-MOSFETs are used as the switching elements SW1 to SW6, and the switching elements SW1 to SW6 are the free-wheeling diodes D1, D2, D3, D4, D5, and D6. In the inverter main circuit 3 in which the parasitic diode of SW6 is used, the switching loss of the inverter main circuit 3 is reduced as compared with the case where Si-IGBT and Si-FRD are used. Therefore, the balance between the switching loss in the inverter main circuit 3 and the iron loss of the permanent magnet synchronous motor 4 changes, and the control carrier frequency at which the overall efficiency of the inverter main circuit 3 and the permanent magnet synchronous motor 4 is maximized is much higher than 6 kHz. Change to 18 kHz.

However, when the inverter control unit 7 performs control so as to obtain phase current information for two phases flowing in the permanent magnet synchronous motor 4 during one calculation cycle based on the DC current Idc, the output voltage as shown in FIG. It is necessary to change the vector. This means that the fluctuation of the output voltage supplied to the permanent magnet synchronous motor 4 becomes large. In this way, the fluctuation of the phase current flowing through the permanent magnet synchronous motor 4 becomes large. Therefore, especially when the modulation rate is low, the iron loss of the permanent magnet synchronous motor 4 is not improved even if the control carrier period is lowered, that is, the control carrier frequency is increased, and the modulation rate depends on the modulation rate as shown in FIG. As a result, the control carrier period at which the total efficiency is maximized changes.

The relationship between the overall efficiency and the control carrier cycle will be described with reference to FIG. FIG. 9 is a graph showing the relationship between the control carrier period and the overall efficiency at the modulation rates Vk1, Vk2, and Vk3 (Vk1 <Vk2 <Vk3). The horizontal axis of FIG. 9 represents the control carrier cycle Tc, and the vertical axis of FIG. 9 represents the overall efficiency of the inverter main circuit 3 and the permanent magnet synchronous motor 4 when the control carrier cycle Tc is changed.

FIG. 9 shows three modulation rates Vk1, Vk2, Vk3 and control carrier periods Tc1, Tc2, Tc3. The control carrier cycle that maximizes the total efficiency when the modulation factor Vk3 is the highest value is Tc3, and the control carrier cycle that maximizes the total efficiency when the modulation factor Vk1 is the lowest value is Tc1, The control carrier period at which the total efficiency is maximum when the modulation rate Vk2 is lower than the modulation rate Vk3 and higher than the modulation rate Vk1 is Tc2. That is, the three modulation factors Vk1, Vk2, and Vk3 shown in FIG. 9 have a relationship of Vk1 <Vk2 <Vk3, and the three control carrier periods Tc1, Tc2, and Tc3 have a relationship of Tc3 <Tc2 <Tc1.

FIG. 10 is a diagram illustrating a setting example of the control carrier period with respect to the modulation rate. The horizontal axis in FIG. 10 is the modulation factor Vk, and the vertical axis in FIG. 10 is the control carrier period Tc. The seven modulation factors Vk1, Vk1a, Vk2a, Vk2, Vk2b, Vk3a, and Vk3 shown on the horizontal axis of FIG. 10 have a relationship of Vk1 <Vk1a <Vk2a <Vk2 <Vk2b <Vk3a <Vk3. The three control carrier periods Tc1, Tc2, and Tc3 shown on the vertical axis in FIG. 10 have a relationship of Tc3 <Tc2 <Tc1.

The inverter control unit 7 of the inverter device 100 according to the second embodiment sets the control carrier cycle Tc1 when the modulation factor Vk is Vk1a or less, and sets the control carrier cycle Tc2 when the modulation factor Vk is Vk2a or more and Vk2b or less. When the modulation rate Vk is equal to or higher than Vk3a, the control carrier period Tc3 is set. When the modulation factor Vk exceeds Vk1a and less than Vk2a, the inverter control unit 7 holds the value of the immediately preceding control carrier cycle Tc. When the modulation rate Vk exceeds Vk2b and is less than Vk3a, the inverter control unit 7 holds the value of the immediately preceding control carrier cycle Tc.

Here, the inverter control unit 7 changes the control carrier cycle Tc while keeping the value of the calculation cycle Ts constant as shown in FIG. For example, when the control carrier cycle Tc is changed from Tc1 to Tc2 at the timing D in FIG. 2, the output of the section of Vsb0_2 is set by recalculating the output of the section of Vsb0_1. In this recalculation, Nc is changed from 2 to 3. By doing so, fluctuations in the phase current when switching the control carrier period Tc can be suppressed.

The inverter device 100 can be operated in a state close to the control carrier cycle Tc in which the total efficiency is maximized, that is, in a state close to the control carrier frequency, with the calculation cycle Ts fixed. However, it is assumed that the condition of “Tx <(Ts−Tc / 2)” is satisfied even when the control carrier period Tc is the highest value Tc1.

As described above, the inverter device 100 according to the second embodiment includes the inverter main circuit 3, the DC current detection circuit 5, and the inverter control unit 7. The inverter control unit 7 calculates the PWM drive signals UP to WN. In a state where Ts is a constant value, the carrier cycle Tc is switched according to the modulation rate. With this configuration, the inverter device 100 with high control responsiveness can be obtained, and the control carrier frequency Tc is close to the control carrier cycle Tc in which the overall efficiency of the inverter main circuit 3 and the permanent magnet synchronous motor 4 is maximized, that is, the control carrier frequency. The inverter device 100 can be operated in a close state.

In the second embodiment, the carrier period value is switched in three stages according to the value of the modulation factor Vk. However, the inverter control unit 7 according to the second embodiment uses the value of the modulation factor Vk as follows: It is good also as a structure which switches the value of a carrier period in two steps. For example, the inverter control unit 7 controls the control carrier cycle at only two locations of the control carrier 1 and the control carrier 3 where the state of the triangular wave carrier in the section in which the DC current Idc is detected for each computation cycle is switched between the carrier rising section and the falling section. Switch Tc.

Further, the inverter control unit 7 according to the second embodiment switches the control carrier cycle Tc according to the modulation rate Vk. However, the control carrier cycle Tc depends on other parameters that can obtain the same effect, for example, the frequency of the permanent magnet synchronous motor 4. May be switched. According to the present invention, in order to obtain an inverter device having a high overall efficiency of the inverter main circuit 3 and the permanent magnet synchronous motor 4 in a configuration using wide gap semiconductors such as SiC-MOSFETs for the switching elements SW1 to SW6. Even if the control carrier frequency is set in the range of 6 kHz to 18 kHz, it can be based on the PWM modulation generated by the calculation immediately before the detected current value, so that the control responsiveness is maintained. It can be realized as it is. *

Embodiment 3 FIG.
FIG. 11 is a configuration diagram of a compressor driving device and an air conditioner according to Embodiment 3 of the present invention. A compressor drive device 200 shown in FIG. 11 uses the inverter device 100 according to the first or second embodiment as a drive device of the compressor 20, and the air conditioner 300 shown in FIG. A machine drive device 200, a compressor 20 driven by the compressor drive device 200, a four-way valve 31, an outdoor heat exchanger 32-1, an indoor heat exchanger 32-2, and an expansion valve 33.

The compressor 20 includes a compression unit 21 that compresses the refrigerant, and a permanent magnet synchronous motor 4 that drives the compression unit 21. The compressor 20, the four-way valve 31, the outdoor heat exchanger 32-1, the indoor heat exchanger 32-2, and the expansion valve 33 are connected to each other by a refrigerant pipe 30 to constitute a refrigerant circuit that circulates the refrigerant. When the refrigerant evaporates or condenses, the air conditioner 300 performs the air conditioning operation while changing the pressure of the refrigerant passing through the pipe by utilizing heat absorption or heat dissipation with respect to the air to be heat exchanged. Wind generated by rotation of a blower fan (not shown) flows to the outdoor heat exchanger 32-1. As a result, the outdoor heat exchanger 32-1 performs heat exchange between the refrigerant and the air.

Similarly, wind generated by rotation of a blower fan (not shown) flows to the indoor heat exchanger 32-2. As a result, heat is exchanged between the refrigerant and the air in the indoor heat exchanger 32-2.

In the air conditioner 300 according to the third embodiment, since the inverter device 100 according to the first embodiment is used as the compressor driving device 200, the air conditioner 300 with high responsiveness is obtained and noise is generated. Can be suppressed.

The inverter device 100 according to the first embodiment and the second embodiment is not limited to the device for driving the compressor 20 of the air conditioner 300, and can be applied to any device using the permanent magnet synchronous motor 4. It is.

The configuration described in the above embodiment shows an example of the contents of the present invention, and can be combined with another known technique, and can be combined with other configurations without departing from the gist of the present invention. It is also possible to omit or change the part.

1 AC power supply, 2 converter circuit, 3 inverter main circuit, 3-1, 3-2, 3-3 connection point, 3a, 3b, 3c, 3d, 3e, 3f drive circuit, 4 permanent magnet synchronous motor, 4a stator 4b permanent magnet rotor, 5 DC current detection circuit, 5a shunt resistor, 5b amplifier, 6 DC voltage detection circuit, 7 inverter control unit, 8, 9 AD converter, 10 output voltage vector correction unit, 20 compressor, 21 Compressor, 30 refrigerant piping, 31 four-way valve, 32-1, outdoor heat exchanger, 32-2, indoor heat exchanger, 33 expansion valve, 41 U-phase winding, 42 V-phase winding, 43 W-phase winding, 100 Inverter device, 200 compressor drive device, 300 air conditioner.

Claims

An inverter main circuit for converting DC power supplied from the DC bus into three-phase AC power using a plurality of semiconductor switching elements;
A direct current detection circuit for detecting a direct current flowing in the direct current bus;
An inverter control unit that outputs a pulse width modulation drive signal for controlling the plurality of semiconductor switching elements based on the direct current detected by the direct current detection circuit;
The inverter control unit
When the calculation cycle for calculating the pulse width modulation drive signal is Ts, the calculation processing time of the pulse width modulation drive signal is Tx, and the control carrier cycle of the pulse width modulation drive signal is Tc, Tc is expressed as “Tx < A value satisfying (Ts−Tc / 2) ”is set.
The inverter control unit outputs the calculated pulse width modulation drive signal before the start timing of the next calculation process, and the pulse width modulation drive signal output before the start timing in the next calculation process The inverter device according to claim 1, wherein the phase current information for two phases is reproduced from the direct current generated by.
The inverter control unit generates the pulse width modulation drive signal based on a triangular wave carrier so that the state of the triangular wave carrier in the interval in which the DC current is detected is alternately switched between a rising interval and a falling interval for each calculation cycle. The inverter device according to claim 2, wherein the control carrier period is set to the inverter device.
The inverter control unit corrects the output voltage vector in order to reproduce the phase current for two phases from the direct current during one calculation cycle, and the output voltage vector per calculation cycle before and after the correction is the same. The inverter apparatus according to any one of claims 1 to 3, further comprising an output voltage vector correction unit configured to correct the output as described above.
5. The inverter device according to claim 1, wherein the inverter control unit switches the control carrier cycle according to a modulation rate in a state where the calculation cycle is set to a constant value. 6. .
6. The inverter device according to claim 1, wherein the semiconductor switching element is formed of a wide band gap semiconductor element.
The inverter device according to claim 6, wherein the control carrier frequency of the pulse width modulation drive signal is set in the range of 6 kHz to 18 kHz in the inverter control unit.
The inverter device according to any one of claims 1 to 7 is provided as a drive device for a compressor equipped with a permanent magnet motor driven by three-phase AC power output from the inverter main circuit. A compressor driving device characterized by the above.
An air conditioner comprising the compressor drive device according to claim 8 and circulating a refrigerant using the compressor drive device.