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WO2018055318A1 - A Power MOSFET with an Integrated Schottky Diode - Google Patents

A Power MOSFET with an Integrated Schottky Diode Download PDF

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Publication number
WO2018055318A1
WO2018055318A1 PCT/GB2016/052966 GB2016052966W WO2018055318A1 WO 2018055318 A1 WO2018055318 A1 WO 2018055318A1 GB 2016052966 W GB2016052966 W GB 2016052966W WO 2018055318 A1 WO2018055318 A1 WO 2018055318A1
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Prior art keywords
region
power semiconductor
semiconductor device
source
conductivity type
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PCT/GB2016/052966
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French (fr)
Inventor
Huaping JIANG
Maolong Ke
Ian DEVINY
Jin Wei
Original Assignee
Dynex Semiconductor Limited
Zhuzhou Crrc Times Electric Co. Ltd
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Application filed by Dynex Semiconductor Limited, Zhuzhou Crrc Times Electric Co. Ltd filed Critical Dynex Semiconductor Limited
Priority to PCT/GB2016/052966 priority Critical patent/WO2018055318A1/en
Priority to GB1905012.9A priority patent/GB2569497B/en
Publication of WO2018055318A1 publication Critical patent/WO2018055318A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H01L29/7806—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a Schottky barrier diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor

Definitions

  • the present invention relates to a power Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with an integrated Schottky diode, particularly but not exclusively, relates to a silicon carbide (SiC) based power MOSFET.
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • SiC silicon carbide
  • MOSFET power MOSFET
  • the first way of integration is the chip level integration, i.e., the active region of the power MOSFET (MOSBD) contains a plurality of MOS cells and a plurality of Schottky Barrier Diode (SBD) cells [2]-[4].
  • MOSBD power MOSFET
  • SBD Schottky Barrier Diode
  • the second way of integration is the cell level integration, i.e., MOS and SBD cells are merged to be a MOSBD cell.
  • MOS and SBD cells are merged to be a MOSBD cell.
  • the planar gate MOSBDs are difficult to save the active area due to the difficulty to share both the p-body/p-grid and the current conduction path [6]-[7].
  • the prior art [8]-[9] of the trench gate MOSBDs are not suitable for SiC-based devices because they are prone to high gate oxide electric field at the trench corner which results in the well-known problems in long-term oxide reliability [8]-[9].
  • the present invention aims to save active area (cell region area) of a power MOSFET with an integrated Schottky diode (MOSBD) and as a result, to reduce the device cost.
  • the invention saves 50% active areas compared to the conventional MOSFET-SBD pair by effectively sharing both the p-body/p-grid and the current conduction paths of MOS and SBD cells.
  • a power semiconductor device comprising:
  • drift region of the first conductivity type disposed on the drain region, the drift region having a lower doping concentration compared to the doping concentration of the drain region;
  • a source region of the first conductivity type disposed within the body region
  • a source ohmic contact being disposed on the source region
  • a trench gate region being in contact with the source region, the body region and the drift region, wherein the trench gate region is configured to form a channel in the body region between the source region and the drift region;
  • a Schottky contact formed on a surface of the power semiconductor device, the Schottky contact extending from an edge of the trench gate region.
  • the body region can be formed directly on the drift region or can be formed within a separate region (e.g. a JFET region) which is directly formed on the drift region.
  • the differences between the proposed device and the structure of Ref. [4] are: (a) the proposed device is cell level integration, i.e., every cell has a MOS cell and a SBD cell as, whereas the structure of Ref. [4] is chip level integration, i.e., plurality of MOS and SBD cells are independently placed on the same chip; (b) the invented device features a lateral channel at the bottom of the trench, whereas the structure of Ref.
  • [4] features a vertical channel at the sidewall of the trench; (c) the Schottky contact of the proposed device is at the top of the mesa, whereas that of the structure of Ref. [4] is at the bottom of the trench.
  • the trench gate region may be configured such that the channel region is formed in parallel to a lateral surface of the device. The current flows initially to a lateral direction through the channel and then after the channel the current bends towards a vertical direction to the drain.
  • the trench gate region may be configured such that the channel region is formed underneath the trench gate region.
  • the power semiconductor device may further comprise a junction field effect transistor (JFET) region formed on the drift region, the JFET region having the first conductivity type and having a higher doping concentration than the doping concentration of the drift region.
  • JFET region can be formed directly on the drift region and then the body region is formed within the JFET region. Alternatively, the JFET region may be formed adjacent to the body region. In such a case, the JFET region may be deeper than the body region or the JFET region may be shallower than the body region. It will be appreciated that the JFET region is not essential for the invention. The device can operate without the JFET region as well.
  • the JFET region may comprise a recessed portion in which the trench gate region is formed and a flat surface portion on which the Schottky contact is formed.
  • the flat surface portion can be termed as a mesa portion on which the Schottky contact is formed.
  • the Schottky contact may be disposed on the JFET region and wherein the Schottky contact extends from a top edge of the gate region.
  • the top edge is the edge of the gate region which is distant from the source region (or not immediately next to the source region).
  • the gate region may be formed on the body region and partially on the JFET region.
  • the doping concentration of the JFET region may be about 10 16 cm “3 to 10 17 cm “3 .
  • the source ohmic contact and the Schottky contact may be electrically connected together to form a common source.
  • the doping profile of the JFET region may be a uniform doping profile.
  • the JFET region may comprise a plurality of regions in which each region may comprise a uniform doping profile.
  • the doping profile of the JFET region may have a non-uniform doping profile.
  • the gate region may comprise a bottom edge distant from the source region, and the body region may be spaced from the bottom edge of the gate region. It would be appreciated that the body region may not be spaced (or offset) from the bottom edge of the gate region.
  • the source ohmic contact and Schottky contact may be discrete contacts. Both the source ohmic contact and Schottkey contact may be electrically connected together during operation.
  • the device may comprise a metal oxide semiconductor (MOS) transistor and a Schottky barrier diode (SBD).
  • MOS metal oxide semiconductor
  • SBD Schottky barrier diode
  • the MOS transistor and the SBD may be integrated within a same cell of the device.
  • the MOS transistor and the SBD may share a same current path.
  • the device may be a silicon based device.
  • the device may be a silicon carbide (SiC) based device.
  • the device may comprise a material comprising 4-step hexagonal silicon carbide (4H- SiC). It would be appreciated that other types of wide band gap material can be equally applicable, for example, the device can be made of 3-step cubic silicon carbide (3C-SiC), 6-step hexagonal silicon carbide (6H-SiC).
  • 4H- SiC 4-step hexagonal silicon carbide
  • the device can be made of 3-step cubic silicon carbide (3C-SiC), 6-step hexagonal silicon carbide (6H-SiC).
  • the depth of the trench gate region may be about 0.2 ⁇ to 3 ⁇ .
  • the device may be a vertical metal oxide semiconductor field effect transistor (MOSFET).
  • MOSFET vertical metal oxide semiconductor field effect transistor
  • a method of manufacturing a power semiconductor device comprising: forming a drain region of a first conductivity type;
  • drift region of the first conductivity type disposed on the drain region the drift region having a lower doping concentration compared to the doping concentration of the drain region
  • the Schottky contact extending from an edge of the trench gate region.
  • the method may further comprises, prior to forming the body region, forming a junction field effect transistor (JFET) region on the drift region, the JFET region having the first conductivity type and having a higher doping concentration than the doping concentration of the drift region.
  • JFET junction field effect transistor
  • the body region and the source region may be formed by an ion implantation technique followed by an activation annealing at 1600°C to 1750°C.
  • the source ohmic contact and the Schottky contact may be formed using a sputtering technique.
  • FIG 1 illustrates a power MOSFET with an integrated Schottky diode (MOSBD);
  • Figure 2 illustrates an alternative MOSBD;
  • Figure 3 illustrates an alternative MOSBD
  • Figure 4 illustrates a schematic cross section of an alternative power MOSFET with an integrated diode in which A-A' is a cut line for representing doping profile of the JFET region;
  • Figure 5 (a), 5 (b), 5 (c), 5 (d) illustrate doping profile of the JFET region of the device of Figure 4;
  • Figure 6 (a), 6 (b), 6 (c), 6 (d) illustrate doping profile of the JFET region of the device of Figure 4;
  • Figure 7 illustrates an electric field distribution at a Schottky interface
  • FIG. 8 illustrates the results of the reverse transfer capacitance
  • Figure 9 illustrates the manufacturing steps of the device of Figure 1.
  • FIG. 1 illustrates a schematic cross section of a vertical MOSFET with an integrated diode (MOSBD).
  • the MOSBD 600 includes an n+ type substrate or drain region 601.
  • the MOSBD also includes a lowly doped n- type drift region 605 on the drain region 601.
  • a p-type body region 615 is formed on the drift region 605.
  • a heavily doped n+ source region 620 is formed within the body region 615.
  • a source ohmic contact 630 is provied in direct contact with the source region.
  • the source ohmic contact 630 is also formed on a p+ region 645 which is formed within the body region 615.
  • the p+ region 645 and source region 620 are shorted using the source ohmic contact 630.
  • a junction field effect transistor (JFET) region 610 is formed on the drift region 605.
  • the JFET region 610 generally comprises a higher doping concentration than the drift region.
  • a trench gate region 625 is formed partially in the body region 615 and partially in the JFET region 610.
  • the trench gate region 625 includes a polysilicon gate surrounded by an oxide.
  • the gate region is generally made of a gate electrode which is generally doped with poly-silicon heavily doped by either Boron (p-type) or Phosphorous (n-type).
  • the trench gate region 625 is formed such that a planar channel region 640 is formed under the gate region 625.
  • the channel region 640 is formed underneath the gate region 625 instead of a side of the gate region (like in a traditional trench gate device).
  • the current flows laterally from the source region 620 to the JFET region 610 and then bends towards a vertical direction to the drain region 601.
  • the JFET region 610 includes a recessed portion in which the trench gate 625 is formed and a flat surface portion (or a mesa portion) on which a Schottky contact 635 is formed. With the presence of the Schottky contact 635, the SBD and MOS device share a same current conduction path, which helps to reduce device area.
  • the proposed structure includes a DMOS at the bottom of the trench region 625 (MOS cell comprising 615, 620, 625, 630, 640, 645) and a Schottky contact 635 at the top of the mesa region (SBD cell).
  • the Schottky contact 635 is electrically connected to the DMOS source contact 630.
  • the Schottky contact 635 and the grounded p-body 640 form a Junction Barrier Schottky Diode.
  • the MOS and SBD cells share both the p- body/p-grid and the current conduction path, which benefits the active area saving.
  • the trench gate region 625 vincludes a bottom edge 650 which is distal (not immediately adjacent) from the source region 620 and there is a lateral distance (or offset) from an edge of the body region 615 to the bottom edge 650 of the trench gate region 625.
  • the edge of the body region 615 may not have an offset with the bottom edge 650 of the trench gate region 625.
  • the trench gate region 625 may have a sloped side-wall.
  • Figure 2 is a schematic cross section of an alternative power MOSFET with an integrated diode. Many features of the device of Figure 2 are the same as the features of Figure 1 , except the JFET region 610 is deeper than the body region 615. In this arrangement, body region 615 is formed within the JFET region 610 instead of formed within drift region 605 (like in Figure 1).
  • Figure 3 is a schematic cross section of an alternative power MOSFET with an integrated diode. Many features of the device of Figure 8 are the same as the features of Figure 6, except the JFET region 610 is shallower than the body region 615.
  • Figure 4 illustrates a schematic cross section of an alternative power MOSFET with an integrated diode in which A-A' is a cut line for representing doping profile of the JFET region.
  • Figure 5 (a), 5(b), 5 (c), 5 (d) illustrate doping profile of the JFET region of the device of Figure 4.
  • Figure 5 (a) a uniform doping profile is shown from the top surface of the device to the surface of JFET region and drift region.
  • Figure 5 (b), (c), and (d) show examples of more complex JFET doping profiles which may be formed by epitaxy. These JFET regions contain more than one sub-regions. Each sub-region may be uniformly doped.
  • Figure 6 shows some variants with non-uniformly doped JFET regions which may be formed by ion implantation, or ion implantation combined with epitaxy.
  • the basic idea is to avoid a high electric field at the Schottky junction. It will be appreciated that these are just some examples as other doping profiles are also possible.
  • TCAD simulations using Synopsys/Sentaurus have been performed to demonstrate the performances of the proposed MOSBD.
  • An MOS-SBD pair i.e., a conventional MOSFET and a conventional SBD in a parallel configuration
  • the devices are generally 600 V class.
  • the doping concentration of the drift region of the proposed MOSBD, the conventional MOSFET and the conventional SBD is 7.5e15 cm "3 .
  • the channel mobility and the gate oxide thickness is set to be 20 cm 2 /V-s and 50 nm respectively for both the proposed MOSBD and the conventional MOSFET.
  • the active areas of the proposed MOSBD, the conventional MOSFET and the conventional SBD are set to be 1 cm 2 .
  • Figure 7 illustrates an electric field distribution at a Schottky interface. As shown in Fig. 7, the proposed MOSBD shows lower peak electric field at the Schottky interface, comparing to the conventional SBD.
  • Figure 8 illustrates the results of the reverse transfer capacitance. As can be seen, the reverse transfer capacitance of the proposed MOSBD is much lower than that of the conventional MOSFET ( Figure. 8), which is important to reduce the switching losses.
  • Figure 9 illustrates the manufacturing steps of the device of Figure 1 (reference numerals are used from Figure 1). The detailed processing steps of the proposed structure are described as follows:
  • the first conductivity type generally refers to n- type doping and the second conductivity type generally refers to p-type doping.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

We disclose herein a power semiconductor device comprising a drain region of a first conductivity type, a drift region of the first conductivity type disposed on the drain region, the drift region having a lower doping concentration compared to the doping concentration of the drain region; a body region of a second conductivity type, opposite to the first conductivity type, disposed over the drift region; a source region of the first conductivity type, disposed within the body region; a source ohmic contact being disposed on the source region; a trench gate region being in contact with the source region, the body region and the drift region, wherein the source and the body regions are disposed at the bottom of a trench in which a trench gate region is disposed and the trench gate region is configured to form a channel in the body region between the source region and the drift region; and a Schottky contact formed on a surface of the power semiconductor device, the Schottky contact extending from an edge of the trench gate region.

Description

A Power MOSFET with an Integrated Schottky Diode
FIELD OF THE INVENTION The present invention relates to a power Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with an integrated Schottky diode, particularly but not exclusively, relates to a silicon carbide (SiC) based power MOSFET.
BACKGROUND OF THE INVENTION
Generally, there are two ways to integrate a Schottky diode into a power MOSFET (MOSBD). This integration results in lower packaging and chip cost and better electrical performances owing to the elimination of the stray inductance of the bonding wires between the conventional MOSFET and its externally paralleled SBD [1].
The first way of integration is the chip level integration, i.e., the active region of the power MOSFET (MOSBD) contains a plurality of MOS cells and a plurality of Schottky Barrier Diode (SBD) cells [2]-[4]. This technique cannot save any active area, although it may provide the absence of stray inductance of the bonding wires between the conventional MOSFET and its externally paralleled SBD [5].
The second way of integration is the cell level integration, i.e., MOS and SBD cells are merged to be a MOSBD cell. However, the planar gate MOSBDs are difficult to save the active area due to the difficulty to share both the p-body/p-grid and the current conduction path [6]-[7]. Furthermore, the prior art [8]-[9] of the trench gate MOSBDs are not suitable for SiC-based devices because they are prone to high gate oxide electric field at the trench corner which results in the well-known problems in long-term oxide reliability [8]-[9]. SUMMARY
The present invention aims to save active area (cell region area) of a power MOSFET with an integrated Schottky diode (MOSBD) and as a result, to reduce the device cost. The invention saves 50% active areas compared to the conventional MOSFET-SBD pair by effectively sharing both the p-body/p-grid and the current conduction paths of MOS and SBD cells.
According to one aspect of the present invention, there is a power semiconductor device comprising:
a drain region of a first conductivity type;
a drift region of the first conductivity type disposed on the drain region, the drift region having a lower doping concentration compared to the doping concentration of the drain region;
a body region of a second conductivity type, opposite to the first conductivity type, disposed over the drift region;
a source region of the first conductivity type, disposed within the body region;
a source ohmic contact being disposed on the source region;
a trench gate region being in contact with the source region, the body region and the drift region, wherein the trench gate region is configured to form a channel in the body region between the source region and the drift region; and
a Schottky contact formed on a surface of the power semiconductor device, the Schottky contact extending from an edge of the trench gate region.
It would be appreciated that the body region can be formed directly on the drift region or can be formed within a separate region (e.g. a JFET region) which is directly formed on the drift region. The differences between the proposed device and the structure of Ref. [4] are: (a) the proposed device is cell level integration, i.e., every cell has a MOS cell and a SBD cell as, whereas the structure of Ref. [4] is chip level integration, i.e., plurality of MOS and SBD cells are independently placed on the same chip; (b) the invented device features a lateral channel at the bottom of the trench, whereas the structure of Ref. [4] features a vertical channel at the sidewall of the trench; (c) the Schottky contact of the proposed device is at the top of the mesa, whereas that of the structure of Ref. [4] is at the bottom of the trench. The trench gate region may be configured such that the channel region is formed in parallel to a lateral surface of the device. The current flows initially to a lateral direction through the channel and then after the channel the current bends towards a vertical direction to the drain. The trench gate region may be configured such that the channel region is formed underneath the trench gate region.
The power semiconductor device may further comprise a junction field effect transistor (JFET) region formed on the drift region, the JFET region having the first conductivity type and having a higher doping concentration than the doping concentration of the drift region. The JFET region can be formed directly on the drift region and then the body region is formed within the JFET region. Alternatively, the JFET region may be formed adjacent to the body region. In such a case, the JFET region may be deeper than the body region or the JFET region may be shallower than the body region. It will be appreciated that the JFET region is not essential for the invention. The device can operate without the JFET region as well.
The JFET region may comprise a recessed portion in which the trench gate region is formed and a flat surface portion on which the Schottky contact is formed. The flat surface portion can be termed as a mesa portion on which the Schottky contact is formed.
The Schottky contact may be disposed on the JFET region and wherein the Schottky contact extends from a top edge of the gate region. The top edge is the edge of the gate region which is distant from the source region (or not immediately next to the source region).
The gate region may be formed on the body region and partially on the JFET region.
The doping concentration of the JFET region may be about 1016 cm"3 to 1017 cm"3.
The source ohmic contact and the Schottky contact may be electrically connected together to form a common source.
The doping profile of the JFET region may be a uniform doping profile. The JFET region may comprise a plurality of regions in which each region may comprise a uniform doping profile.
The doping profile of the JFET region may have a non-uniform doping profile.
The gate region may comprise a bottom edge distant from the source region, and the body region may be spaced from the bottom edge of the gate region. It would be appreciated that the body region may not be spaced (or offset) from the bottom edge of the gate region.
The source ohmic contact and Schottky contact may be discrete contacts. Both the source ohmic contact and Schottkey contact may be electrically connected together during operation. The device may comprise a metal oxide semiconductor (MOS) transistor and a Schottky barrier diode (SBD).
The MOS transistor and the SBD may be integrated within a same cell of the device. The MOS transistor and the SBD may share a same current path. The device may be a silicon based device.
The device may be a silicon carbide (SiC) based device.
The device may comprise a material comprising 4-step hexagonal silicon carbide (4H- SiC). It would be appreciated that other types of wide band gap material can be equally applicable, for example, the device can be made of 3-step cubic silicon carbide (3C-SiC), 6-step hexagonal silicon carbide (6H-SiC).
The depth of the trench gate region may be about 0.2 μηι to 3 μηι.
The device may be a vertical metal oxide semiconductor field effect transistor (MOSFET).
According to a further aspect of the present invention, there is provided a method of manufacturing a power semiconductor device, the method comprising: forming a drain region of a first conductivity type;
forming a drift region of the first conductivity type disposed on the drain region, the drift region having a lower doping concentration compared to the doping concentration of the drain region;
forming a body region of a second conductivity type, opposite to the first conductivity type, on the drift region;
forming a source region of the first conductivity type within the body region;
forming a source ohmic contact on the source region;
forming a trench gate region in contact with the source region, the body region and the drift region, wherein the trench gate region forms a channel in the body region between the source region and the drift region; and
forming a Schottky contact on a surface of the power semiconductor device, the Schottky contact extending from an edge of the trench gate region.
The method may further comprises, prior to forming the body region, forming a junction field effect transistor (JFET) region on the drift region, the JFET region having the first conductivity type and having a higher doping concentration than the doping concentration of the drift region.
The body region and the source region may be formed by an ion implantation technique followed by an activation annealing at 1600°C to 1750°C. The source ohmic contact and the Schottky contact may be formed using a sputtering technique.
BRIEF DESCRIPTION OF THE PREFERRED EMBODIMENTS
Some preferred embodiments of the invention will now be described by way of example only and with reference to the accompanying drawings, in which:
Figure 1 illustrates a power MOSFET with an integrated Schottky diode (MOSBD); Figure 2 illustrates an alternative MOSBD;
Figure 3 illustrates an alternative MOSBD; Figure 4 illustrates a schematic cross section of an alternative power MOSFET with an integrated diode in which A-A' is a cut line for representing doping profile of the JFET region;
Figure 5 (a), 5 (b), 5 (c), 5 (d) illustrate doping profile of the JFET region of the device of Figure 4;
Figure 6 (a), 6 (b), 6 (c), 6 (d) illustrate doping profile of the JFET region of the device of Figure 4;
Figure 7 illustrates an electric field distribution at a Schottky interface;
Figure 8 illustrates the results of the reverse transfer capacitance; and
Figure 9 illustrates the manufacturing steps of the device of Figure 1.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Figure 1 illustrates a schematic cross section of a vertical MOSFET with an integrated diode (MOSBD). The MOSBD 600 includes an n+ type substrate or drain region 601. The MOSBD also includes a lowly doped n- type drift region 605 on the drain region 601. A p-type body region 615 is formed on the drift region 605. A heavily doped n+ source region 620 is formed within the body region 615. A source ohmic contact 630 is provied in direct contact with the source region. The source ohmic contact 630 is also formed on a p+ region 645 which is formed within the body region 615. The p+ region 645 and source region 620 are shorted using the source ohmic contact 630. The presence of the p+ region 645 shorted by the source ohmic contact 620 helps to reduce a body parasitic effect within the device. In Figure 1 , a junction field effect transistor (JFET) region 610 is formed on the drift region 605. The JFET region 610 generally comprises a higher doping concentration than the drift region. A trench gate region 625 is formed partially in the body region 615 and partially in the JFET region 610. The trench gate region 625 includes a polysilicon gate surrounded by an oxide. The gate region is generally made of a gate electrode which is generally doped with poly-silicon heavily doped by either Boron (p-type) or Phosphorous (n-type). The trench gate region 625 is formed such that a planar channel region 640 is formed under the gate region 625. In other words, the channel region 640 is formed underneath the gate region 625 instead of a side of the gate region (like in a traditional trench gate device). In such a configuration, the current flows laterally from the source region 620 to the JFET region 610 and then bends towards a vertical direction to the drain region 601.
In Figure 1 , the JFET region 610 includes a recessed portion in which the trench gate 625 is formed and a flat surface portion (or a mesa portion) on which a Schottky contact 635 is formed. With the presence of the Schottky contact 635, the SBD and MOS device share a same current conduction path, which helps to reduce device area.
The proposed structure includes a DMOS at the bottom of the trench region 625 (MOS cell comprising 615, 620, 625, 630, 640, 645) and a Schottky contact 635 at the top of the mesa region (SBD cell). The Schottky contact 635 is electrically connected to the DMOS source contact 630. The Schottky contact 635 and the grounded p-body 640 form a Junction Barrier Schottky Diode. The MOS and SBD cells share both the p- body/p-grid and the current conduction path, which benefits the active area saving.
In the example of Figure 1 , the trench gate region 625vincludes a bottom edge 650 which is distal (not immediately adjacent) from the source region 620 and there is a lateral distance (or offset) from an edge of the body region 615 to the bottom edge 650 of the trench gate region 625. In one example, the edge of the body region 615 may not have an offset with the bottom edge 650 of the trench gate region 625. In one embodiment, the trench gate region 625 may have a sloped side-wall.
Exemplary doping concentrations of the device of Figure 1 are set out below:
Figure imgf000008_0001
Figure 2 is a schematic cross section of an alternative power MOSFET with an integrated diode. Many features of the device of Figure 2 are the same as the features of Figure 1 , except the JFET region 610 is deeper than the body region 615. In this arrangement, body region 615 is formed within the JFET region 610 instead of formed within drift region 605 (like in Figure 1).
Figure 3 is a schematic cross section of an alternative power MOSFET with an integrated diode. Many features of the device of Figure 8 are the same as the features of Figure 6, except the JFET region 610 is shallower than the body region 615.
Figure 4 illustrates a schematic cross section of an alternative power MOSFET with an integrated diode in which A-A' is a cut line for representing doping profile of the JFET region. Figure 5 (a), 5(b), 5 (c), 5 (d) illustrate doping profile of the JFET region of the device of Figure 4. In Figure 5 (a), a uniform doping profile is shown from the top surface of the device to the surface of JFET region and drift region. Figure 5 (b), (c), and (d) show examples of more complex JFET doping profiles which may be formed by epitaxy. These JFET regions contain more than one sub-regions. Each sub-region may be uniformly doped.
Figure 6 shows some variants with non-uniformly doped JFET regions which may be formed by ion implantation, or ion implantation combined with epitaxy. The basic idea is to avoid a high electric field at the Schottky junction. It will be appreciated that these are just some examples as other doping profiles are also possible.
Simulation and Results: TCAD simulations using Synopsys/Sentaurus have been performed to demonstrate the performances of the proposed MOSBD. An MOS-SBD pair (i.e., a conventional MOSFET and a conventional SBD in a parallel configuration) is used for comparison with the proposed MOSBD. The devices are generally 600 V class. The doping concentration of the drift region of the proposed MOSBD, the conventional MOSFET and the conventional SBD is 7.5e15 cm"3. The channel mobility and the gate oxide thickness is set to be 20 cm2/V-s and 50 nm respectively for both the proposed MOSBD and the conventional MOSFET. The active areas of the proposed MOSBD, the conventional MOSFET and the conventional SBD are set to be 1 cm2.
Figure 7 illustrates an electric field distribution at a Schottky interface. As shown in Fig. 7, the proposed MOSBD shows lower peak electric field at the Schottky interface, comparing to the conventional SBD.
Figure 8 illustrates the results of the reverse transfer capacitance. As can be seen, the reverse transfer capacitance of the proposed MOSBD is much lower than that of the conventional MOSFET (Figure. 8), which is important to reduce the switching losses.
The performances of the proposed MOSBD and the conventional MOS-SBD pair are comparatively summarised in Table I. It is apparent that, the proposed MOSBD not only saves 50% of the active area but also shows 70% lower Crss (at VDs = 400 V) than that of the conventional MOSFET without sacrifice of other key performances (e.g., Ron, ¼ and Es). The 50% of active area saving is beneficial for the cost reduction and the 70% lower Crss is beneficial for the switching loss reduction.
Table I. Key performances.
Parameter Symbol Conv MOS-SBD paii MOSBD Unit
Total Active Area AA 2 1 cm2
Forward on-state resistance 3.02 2.96 111Ω
SBD voltage drop @300A Vt 1.19 1.19 V
Reverse transfer capacitance 177 54 PF
Peak Electric field at Schottky contact 1.17 1.14 MV/cm
Figure 9 illustrates the manufacturing steps of the device of Figure 1 (reference numerals are used from Figure 1). The detailed processing steps of the proposed structure are described as follows:
(a) Starting with n-type epitaxial layer on the Silicon-face of the 4° off-axis 4H-SiC substrate 601 ;
(b) Forming JFET region 610 by nitrogen ion implantation with depth from 0.8 μηι to 2 μηι and doping concentration of 1e16 cm"3 to 1 e17 cm"3
(c) Trench etching with depth from about 0.2 μηι to about 3 μηι;
(d) Forming p-body 615, n+ source 620 and p+ regions 630 by ion implantation followed by activation annealing at 1600-1750°C for 30 min; (e) Thermally growing of 50 nm gate oxide and polysilicon deposition as the gate electrode followed by patterning respectively, then thick oxide deposited as isolation dielectric layer to overall form the trench gate region 625;
(f) Ohmic contact metal deposition, patterning and annealing followed by Schottky contact metal deposition 635, patterning and annealing, thick aluminium layer is sputtered and patterned on the top side for electrical connection and wire bonding, finally, tri-metal-layer is sputtered on the bottom side for soldering.
It would generally be appreciated that the first conductivity type generally refers to n- type doping and the second conductivity type generally refers to p-type doping.
The skilled person will understand that in the preceding description and appended claims, positional terms such as 'above', 'below', 'front', 'back', 'vertical', 'underneath' etc. are made with reference to conceptual illustrations of a semiconductor device, such as those showing standard cross-sectional perspectives and those shown in the appended drawings. These terms are used for ease of reference but are not intended to be of limiting nature. These terms are therefore to be understood as referring to a semiconductor device when in an orientation as shown in the accompanying drawings. List of Documents Cited in the Background Section
[1] Hirao, Takashi, and Takayuki Hashimoto. "Low Reverse Recovery Charge 30 V Power MOSFET With Double Epi Structure for DC-DC Converters." IEEE Transactions on Electron Devices 63.3 (2016): 1 154-1160.
[2] Ono, Syotara, et al. "High density MOSBD (UMOS with built-in trench Schottky barrier diode) for synchronous buck converters." 2006 IEEE International Symposium on Power Semiconductor Devices and IC's. IEEE, 2006.
[3] Ryu, Sei-Hyung. "Silicon carbide MOSFETs with integrated antiparallel junction barrier Schottky free wheeling diodes and methods of fabricating the same." U.S. Patent No. 6,979,863. 27 Dec. 2005.
[4] Blanchard, Richard A., Fwu-luan Hshieh, and Koon Chong So. "Trench DMOS transistor with embedded trench schottky rectifier." U.S. Patent No. 6,621 , 107. 16 Sep. 2003. [5] Calafut, Dan. "Trench power MOSFET lowside switch with optimized integrated Schottky diode." Power Semiconductor Devices and ICs, 2004. Proceedings. ISPSD'04. The 16th International Symposium on. IEEE, 2004.
[6] Mondal, K., R. Natarajan, and T. P. Chow. "An integrated 500-V power DMOSFET/antiparallel rectifier device with improved diode reverse recovery characteristics." IEEE Electron Device Letters 23.9 (2002): 562-564.
[7] Huaping Jiang, Jin Wei, Xiaoping Dai, Maolong Ke, Changwei Zheng, and Ian Deviny, "Silicon Carbide Split-Gate MOSFET with Merged Schottky Barrier Diode and Reduced Switching Loss." Proceeding of ISPSD 2016.
[8] Chuang, Chiao-Shun Patrick, et al. "Forward-voltage-tunable schottky-integrated trench MOSFETs." 2014 IEEE 26th International Symposium on Power Semiconductor Devices & ICs (ISPSD). IEEE, 2014.
[9] Hirao, Takashi, et al. "Low reverse recovery charge 30-V power MOSFETs for DC- DC converters." 2013 25th International Symposium on Power Semiconductor Devices & ICs (ISPSD). IEEE, 2013.
Although the invention has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in the invention, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.

Claims

CLAIMS:
1. A power semiconductor device comprising:
a drain region of a first conductivity type;
a drift region of the first conductivity type disposed on the drain region, the drift region having a lower doping concentration compared to the doping concentration of the drain region;
a body region of a second conductivity type, opposite to the first conductivity type, disposed over the drift region;
a source region of the first conductivity type, disposed within the body region;
a source ohmic contact being disposed on the source region;
a trench gate region being in contact with the source region, the body region and the drift region, wherein the trench gate region is configured to form a channel in the body region between the source region and the drift region; and
a Schottky contact formed on a surface of the power semiconductor device, the Schottky contact extending from an edge of the trench gate region.
2. A power semiconductor device according to claim 1 , wherein the trench gate region is configured such that the channel region is formed in parallel to a lateral surface of the device.
3. A power semiconductor device according to claim 1 or 2, wherein the trench gate region is configured such that the channel is region is formed underneath the trench gate region.
4. A power semiconductor device according to any preceding claim, further comprising a junction field effect transistor (JFET) region formed on the drift region, the JFET region having the first conductivity type and having a higher doping concentration than the doping concentration of the drift region.
A power semiconductor device according to claim 4, wherein the JFET region comprises a recessed portion in which the trench gate region is formed and a flat surface portion on which the Schottky contact is formed.
A power semiconductor device according to claim 4 or 5, wherein the Schottky contact is disposed on the JFET region and wherein the Schottky contact extends from a top edge of the gate region.
A power semiconductor device according to any one of claims 4 to 6, wherein the gate region is formed on the body region and partially on the JFET region.
A power semiconductor device according to any one of claims 4 to 7, wherein the doping concentration of the JFET region is about 1016 cm"3 to 1017 cm"3.
A power semiconductor device according to any one of claims 4 to 8, wherein the doping profile of the JFET region is a uniform doping profile.
A power semiconductor device according to any one of claims 4 to 8, wherein the JFET region comprises a plurality of regions, wherein each region comprises a uniform doping profile.
A power semiconductor device according to any one of claims 4 to 8, wherein the doping profile of the JFET region is a non-uniform doping profile.
A power semiconductor device according to any preceding claim, wherein the gate region comprises a bottom edge distant from the source region, and wherein the body region is spaced from the bottom edge of the gate region.
A power semiconductor device according to any preceding claim, wherein the source ohmic contact and Schottky contact are discrete contacts.
14. A power semiconductor device according to any preceding claim, wherein the source ohmic contact and the Schottky contact are c electrically connected together to form a common source.
15. A power semiconductor device according to any preceding claim, wherein the device comprises a metal oxide semiconductor (MOS) transistor and a Schottky barrier diode (SBD).
16. A power semiconductor device according to claim 15, wherein the MOS transistor and the SBD are integrated within a same cell of the device.
17. A power semiconductor device according to claim 15 or 16, wherein the MOS transistor and the SBD share a same current path.
18. A power semiconductor device according to any preceding claim, wherein the device is a silicon based device.
19. A power semiconductor device according to any one of claims 1 to 17, wherein the device is a silicon carbide (SiC) based device.
20. A power semiconductor device according to claim 19, wherein the device comprises a material comprising 4-step hexagonal silicon carbide (4H-SiC).
21. A power semiconductor device according to any preceding claim, wherein the depth of the trench gate region is about 0.2 μηι to 3 μηι.
22. A power semiconductor device according to any preceding claim, wherein the device is a vertical metal oxide semiconductor field effect transistor (MOSFET).
23. A method of manufacturing a power semiconductor device, the method comprising:
forming a drain region of a first conductivity type; forming a drift region of the first conductivity type disposed on the drain region, the drift region having a lower doping concentration compared to the doping concentration of the drain region;
forming a body region of a second conductivity type, opposite to the first conductivity type, on the drift region;
forming a source region of the first conductivity type within the body region;
forming a source ohmic contact on the source region;
forming a trench gate region in contact with the source region, the body region and the drift region, wherein the trench gate region forms a channel in the body region between the source region and the drift region; and
forming a Schottky contact on a surface of the power semiconductor device, the Schottky contact extending from an edge of the trench gate region.
A method according to claim 23, further comprising, prior to forming the body region, forming a junction field effect transistor (JFET) region on the drift region, the JFET region having the first conductivity type and having a higher doping concentration than the doping concentration of the drift region.
A method according to claim 23 or 24, wherein the body region and the source region are formed by an ion implantation technique followed by an activation annealing at 1600°C to 1750°C.
A method according to claim 23 to 25, wherein the source ohmic contact and the Schottky contact are formed using a sputtering technique.
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CN117059672B (en) * 2023-10-11 2024-01-23 通威微电子有限公司 Semiconductor device integrated with SBD and manufacturing method thereof
CN117253923A (en) * 2023-11-20 2023-12-19 深圳平创半导体有限公司 Boss split gate silicon carbide MOSFET integrated with JBS and preparation process
CN118136672A (en) * 2024-04-30 2024-06-04 河北博威集成电路有限公司 Silicon carbide MOSFET device integrated with SBD and preparation method thereof
CN118693161A (en) * 2024-08-27 2024-09-24 西安龙飞电气技术有限公司 Multi-groove power device integrated with SiC diode

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