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WO2018040038A1 - 一种闪存介质的访问方法及控制器 - Google Patents

一种闪存介质的访问方法及控制器 Download PDF

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Publication number
WO2018040038A1
WO2018040038A1 PCT/CN2016/097718 CN2016097718W WO2018040038A1 WO 2018040038 A1 WO2018040038 A1 WO 2018040038A1 CN 2016097718 W CN2016097718 W CN 2016097718W WO 2018040038 A1 WO2018040038 A1 WO 2018040038A1
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WO
WIPO (PCT)
Prior art keywords
controller
queue
function
instruction
die
Prior art date
Application number
PCT/CN2016/097718
Other languages
English (en)
French (fr)
Inventor
李涛
周冠锋
李生
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN201680004002.5A priority Critical patent/CN108156823B/zh
Priority to EP16914604.0A priority patent/EP3495958B1/en
Priority to PCT/CN2016/097718 priority patent/WO2018040038A1/zh
Publication of WO2018040038A1 publication Critical patent/WO2018040038A1/zh
Priority to US16/289,139 priority patent/US10802960B2/en

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Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/0223User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023Free address space management
    • G06F12/0238Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0668Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671In-line storage system
    • G06F3/0673Single storage device
    • G06F3/0679Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/06Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0615Address space extension
    • G06F12/063Address space extension for I/O modules, e.g. memory mapped I/O
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
    • G06F13/1689Synchronisation and timing concerns
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
    • G06F13/1694Configuration of memory controller to different memory types
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0602Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604Improving or facilitating administration, e.g. storage management
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0628Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659Command handling arrangements, e.g. command buffers, queues, command scheduling
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/20Employing a main memory using a specific memory technology
    • G06F2212/202Non-volatile memory
    • G06F2212/2022Flash memory

Definitions

  • the present invention relates to the field of storage, and in particular, to a method and a controller for accessing a flash medium.
  • SSD Solid State Device
  • the main storage medium for SSDs is flash media, such as Nand Flash
  • Nand Flash is a device
  • one device can be composed of one or more chips, and one chip can be divided into multiple flash chips.
  • a flash chip can be divided into a number of blocks, and a block is divided into a plurality of pages.
  • the basic unit of data read and write operations of Nand Flash is page, and data erasure is performed in units of blocks.
  • Nand Flash produced by different Nand Flash manufacturers has different modes, speeds, commands and protocols. Even the different processes and batches of Nand Flash of the same manufacturer may have different modes, speeds, commands and protocols.
  • the Nand Flash controller uses firmware to control flash media and is not compatible with different types of flash media.
  • the operation method of the Nand Flash controller is: after receiving the operation instruction, the operation instruction is first divided into a plurality of basic instructions, and then the plurality of basic instructions are sequentially sent to the flash medium, and the Nand Flash controller waits for the flash medium. After executing a basic instruction, the next basic instruction is sent to the flash media. Due to the difference in execution time of different basic instructions, the controller will waste a lot of waiting time to wait for the current instruction to be executed by the flash medium before sending a new instruction, resulting in low efficiency of the operation instruction.
  • the present application discloses a method and a controller for accessing a flash memory medium, which can improve the execution efficiency of the operation instructions and are compatible with different types of storage media.
  • the first aspect of the present application provides a method for accessing a flash medium.
  • the storage medium may be a Nand Flash
  • the controller may be a Nand Flash controller.
  • the controller may be located in a personal computer, a server, a disk array, or a solid state drive.
  • the N function queues can be set in the internal memory of the controller, for example, in the internal register or cache of the controller, and the function queue is used to store the basic instructions.
  • the upper-layer device can be an SSD (Solid State Drives, SSD) controller.
  • the controller is coupled to at least one flash medium, and each of the at least one flash medium includes at least one Die.
  • the number of function queues in the controller is equal to the number of Dies connected to the controller, that is, the number of Dies is also N, and the N function queues and the N Dies are in a one-to-one mapping relationship, that is, a unique pair of Dies corresponding to one function queue.
  • the operation instruction indicates the logical operation issued by the SSD controller for Nand Flash, for example, a page reading operation or an erase block operation.
  • the operation instruction needs to be specifically executed by the Nand Flash controller, and the Nand Flash controller executes the SSD controller.
  • the micro-operation is the basic instruction.
  • the basic instruction can be directly executed by the controller.
  • the basic instructions are: block erase operation, write data operation, write wait operation, and status query operation. .
  • the controller selects a target function queue from the N function queues according to the predefined rules, wherein the selected target function queue satisfies the flash memory of the non-empty queue and the target function queue corresponding to the Die.
  • the condition that the medium is idle, the non-empty queue indicates that at least one basic instruction is stored in the function queue.
  • the method for detecting the state of the flash medium in which the controller is located may be: the controller sends a proprietary status detection instruction to the flash medium on which the Die is located, and the status detection instruction can preferentially be responded to by the flash medium, returning to Die in a very short time.
  • the controller can detect the state of the flash media in which the Die is located; it should be noted that when the flash media includes multiple Dies, when at least one of the plurality of Dies has the flash medium in the idle state, it indicates Corresponding flash media idle state.
  • the method for the controller to obtain the number of basic instructions in the function queue may be: the controller may maintain a record table, and the record table stores entries indicating the current number of basic instructions in each function queue of the N function queues. When a basic instruction of a queue header in a function queue enters a queue operation or a dequeue operation, the controller updates the record table to store the entry of the function queue. The controller takes a basic instruction from the target function queue.
  • the controller determines the Die associated with the target function queue according to the preset queue mapping information, and determines the flash media in which the associated Die is located according to the preset correspondence between the flash media and the Die, and the controller generates the rule according to the preset signal generation rule.
  • the timing signal corresponding to the basic instruction, the signal generation rule indicates the timing signal generation rule of the basic instruction, for example, the number of output clock cycles, the serial number of the output pin, the level state on the pin in each clock cycle, etc., control
  • the device sends timing signals to the flash media on which the associated Die is located.
  • the communication protocol between the controller and the flash media may follow a Toggle or ONFI (Open Nand Flash Interface) protocol.
  • the controller selects the target function queue according to the predefined rule, the flash memory medium in which the target function queue is a non-empty queue and the Die associated with the target function queue is in an idle state is satisfied, so that different Die parallel execution control can be implemented.
  • the basic instructions sent by the device improve the execution efficiency of the operation instructions.
  • the timing signal corresponding to the basic instruction is generated by a preset signal generation rule, so that the signal generation rules corresponding to different types of flash media can be configured to match the functions of different types of flash media, and the controller is improved to the flash memory.
  • the method further includes:
  • the controller receives an operation instruction, and the type of the operation instruction may be a read operation instruction or a write operation instruction, and the operation instruction carries an access address.
  • the operation instruction may be composed of different types of basic instructions by different combinations.
  • the controller may split the operation instruction into at least two basic instructions according to a preset splitting rule, and the splitting rule may be: according to a predefined operation instruction. Split the mapping relationship with the base directive.
  • the splitting rule may be: when the read operation command is a read page command, the read command may carry its own identifier, and the controller may obtain the associated 3 according to the correspondence between the identifier of the pre-stored operation command and the identifier of the basic instruction.
  • the identification of the basic command will split the read page command into three basic instructions: send read command, check status register and read data transfer, each base command carries its own identifier;
  • the dividing rule may be: when the write operation instruction is a write page command, the operation instruction may be split into three basic instructions according to the mapping relationship between the identifier of the pre-stored write page command and the identifier of the basic instruction: 1.
  • Check the status register, 3, transfer data, each base command can carry its own identity.
  • the splitting rules of the operation instructions in this embodiment are not limited to the above examples, and may be split according to any one of the existing methods as needed.
  • the controller is connected to at least one flash medium.
  • Each flash medium in the at least one flash medium includes at least one Die, and the number of Dies connected to the controller is equal to the number N of function queues, and each Die of the N Dies has a different address range. Since the N function queues and the N pairs are in a one-to-one mapping relationship, each function queue corresponds to an address range, and the controller determines the associated function queue from the N function queues according to the address range in which the access address carried in the operation instruction is located. . The controller puts the split at least two basic instructions into the associated function queue. It should be noted that when the controller puts the split base command into the function queue, the order of sending the basic commands may be in accordance with the first in first out rule.
  • the method of splitting the operation instructions of different manufacturers' flash media may be different.
  • the types and quantities of the basic instructions obtained by different manufacturers split operation instructions may be different, and the specific splitting rules may be different.
  • the invention is not limited.
  • the operation instruction is split into a plurality of basic instructions, and the split basic instructions are placed in the corresponding function queue according to the access address, so that the basic instructions corresponding to the different operation instructions are concurrently executed, and the Die of the flash medium is improved. Concurrency, reducing execution time.
  • the controller when the controller receives an operation instruction sent by the upper layer device, the controller may cache the received operation instruction in the command queue, and the command queue may be a first in first out queue, the command The queue acts as a buffer, and the controller takes an operation instruction from the command queue each time.
  • the command queue may be set in a memory inside the controller or a memory outside the controller, which is not limited in this embodiment.
  • different types of basic instructions are pre-allocated with different identifiers, and the identifier of the basic instruction is used to indicate the identity of the basic instruction, and after the controller splits the operation instruction, the controller may be pre-allocated to the basic instruction.
  • the identifier is added to the basic instruction.
  • the identifier of the basic instruction can be represented by a field specified in the basic instruction
  • the controller can read the specified field in the basic instruction to determine the identifier of the basic instruction, and the controller queries and The at least one pin level state information and output sequence information associated with the identification of the base instruction, the pin level status information indicating a level state on the designated pin within one clock cycle, the level state including a high level or a low level
  • the specified pin is a control pin for transmitting control signals, and does not include a data pin for transmitting data information and an address pin for transmitting address information, and different pin level status information is indicated on the designated pin. The level status is different.
  • the output sequence information indicates the output order of the pin level status information, and one pin level status information may be repeated, and the output order information may indicate a repetition condition by adding a field after the pin level status information.
  • the controller generates a timing signal according to at least one of the pin level state information and the output sequence information, and the controller sends the timing signal to the flash medium where the associated Die is located through the designated pin.
  • the generation rules of the timing signals are represented by a plurality of different types of pin level state information and output sequence information, and it is not necessary to store pin level state information corresponding to all clock cycles to avoid redundancy and reduce storage space. Occupied.
  • the signal timings of different types of flash media are different. If the controller is to be compatible with a certain type of flash media, the configuration device needs to configure the controller according to the characteristics of the signal timing of the flash media.
  • the configuration device may be a computer, a test platform or other device.
  • the configuration process may be: configuring the device to obtain a timing signal corresponding to the basic instruction, and obtaining a level state on a designated pin in each clock cycle, if two pin levels
  • the status information indicates that the level status of the specified pin is the same in one clock cycle, then the two pin level status information are of the same type, statistical timing.
  • the number of different types of pin level status information in the signal determines the output order of different types of pin level status information to generate output order information.
  • the signal generation rule may be pre-stored in a memory inside the controller,
  • the memory includes WCS (Writable Control Storage, WCS for short), a register or a cache.
  • the signal generation rules of the timing signals are represented by a plurality of different types of pin level state information and output sequence information, and it is not necessary to store pin level state information corresponding to all clock cycles to avoid redundancy and reduce storage space. Occupy.
  • the controller generates a timing signal corresponding to the basic instruction according to the preset signal generation rule, and sends the timing signal to the flash medium where the associated Die is located, where the controller acquires the identifier of the basic instruction, and controls
  • the controller queries the clock cycle quantity information and the level state information associated with the identifier of the basic instruction according to the preset signal generation rule; wherein the clock cycle number information indicates the number of clock cycles to be output, and the level state information indicates the clock to be output The level state of each clock cycle on the specified pin in the cycle; the controller generates a timing signal according to the number of clock cycles and the level state information; the controller sends a timing signal to the flash medium where the associated Die is located through the designated pin.
  • the controller can quickly query the level state on the designated pin in the current clock cycle by looking up the table, thereby avoiding complicated calculation process and reducing The delay of timing signal generation.
  • the configuration device needs to perform related configuration on the controller according to the characteristics of the timing signal of the flash medium, and the configuration method includes: configuring the device to set the identifier of the basic instruction, and configuring the device to The identification of the basic instruction is bound to the clock cycle quantity information and the level status information and stored in the signal generation rule.
  • the controller can quickly generate a timing signal according to the preset clock cycle quantity information and the level state information, and the level state information indicates the level state on the designated pin in each clock cycle, so that when the table is checked It can quickly query the level status and reduce the time to generate timing signals.
  • the controller determines that the function queue associated with the access address among the N function queues includes: the controller is connected to the at least one flash medium, and each of the at least one flash medium includes at least one Die, and the control The number of Dies connected is equal to the number of function queues.
  • the controller can pre-store the address range of each of the N Dies.
  • the controller can be in the memory. Obtaining an address range corresponding to each of the pre-stored Dies, the controller determines the target Die according to the address range of the access address carried in the operation instruction, and the target Die is one of N Dies, and the controller determines and matches according to the preset queue mapping information.
  • the function queue associated with the target Die includes: the controller is connected to the at least one flash medium, and each of the at least one flash medium includes at least one Die, and the control The number of Dies connected is equal to the number of function queues.
  • the controller can pre-store the address range of each of the N Dies.
  • the controller can be in the memory. Obtaining an address range corresponding to
  • the controller determines the target Die according to the address range in which the access address carried in the operation instruction is located, and then determines the function queue associated with the target Die according to the mapping relationship between the Die and the function queue, so that the basic instruction obtained after the operation instruction is split is accurate. Enter the specified function queue to improve the efficiency of the basic command enqueue.
  • the controller selects a target function queue according to a predefined rule from the N function queues each time: the N function queues are preset with different priorities, and the controller is configured from the N function queues.
  • the method for selecting the target function queue is as follows: the controller selects a non-empty and associated Die as the target function queue from the N function queues each time according to the priority descending order. Or the controller selects the target function queue from the N function queues by: the controller random mode selects a function queue that is not empty and the associated Die is idle state as the target function queue each time from the N function queues.
  • N function queues are preset with different queue IDs, queue IDs indicate the identity of the function queues, different function queues have different queue IDs, and the controllers are sorted from the N controllers according to the queue ID ascending order or the queue ID descending order.
  • a non-empty and associated Die is selected from the N function queues as an idle function function queue as a target function queue.
  • the operation instruction in each function queue can be sent to the flash medium for execution in parallel, thereby preventing the controller from continuously fetching instructions in a function queue, thereby reducing the controller. Waiting time, improve the concurrency of multiple Dies and the efficiency of basic instruction execution.
  • the second aspect of the present application provides a controller, including: a queue selection module, an instruction fetching module, a first determining module, a generating module, and a sending module.
  • the queue selection module is configured to select a target function queue from the N function queues, wherein the target function queue is a non-empty queue, the flash media in which the Die associated with the target function queue is located is in an idle state, and N is an integer greater than 1, N
  • Each function queue in the function queue is used to store the basic instruction obtained by splitting the operation instruction, and the non-empty queue indicates that at least one basic instruction is stored in the function queue; the instruction instruction module is configured to take out a basic instruction from the target function queue.
  • the first determining module is configured to determine, according to the preset queue mapping information, a Die associated with the target function queue; wherein the controller is connected to at least a flash medium, each of the at least one flash medium includes at least one Die, the number of Dies connected to the controller is equal to the number N of function queues, and the queue mapping information represents the N function queues and the N
  • the mapping module is configured to generate a timing signal corresponding to the basic instruction according to a preset signal generation rule, and the sending module is configured to send the timing signal to the flash medium in which the associated Die is located, Signal generation rules are used to represent the correspondence between the underlying instructions and the waveforms output on the specified pins.
  • the controller selects the target function queue according to the predefined rule
  • the flash memory medium in which the target function queue is the non-empty queue and the target function queue associated with the Die is in an idle state, so that different Die parallel execution control can be implemented.
  • the basic instruction sent by the device reduces the execution time of the operation instruction; at the same time, the timing signal corresponding to the basic instruction is generated by a preset signal generation rule, so that the signal generation rules corresponding to different types of flash media can be configured to achieve different matching.
  • the role of the type of flash media improves the controller's compatibility with flash media.
  • the generating module is specifically configured to acquire an identifier of the basic instruction, and query at least one pin level state information and output order information associated with the identifier of the basic instruction;
  • the pin level status information indicates a level state on a designated pin within one clock cycle, the level state includes a high level or a low level, and the output sequence information indicates the at least one pin level state information An output sequence; generating the timing signal according to the at least one pin level state information and the output sequence information; the transmitting module transmitting the timing signal to the flash medium in which the associated Die is located through the designated pin
  • the designated pin can be a control pin of the controller for transmitting control signals, and does not include a data pin for transmitting data and an address pin for transmitting address information.
  • the operation instruction is split into a plurality of basic instructions, and the split basic instruction is placed in the corresponding function queue according to the access address, so that the basic instructions corresponding to the different operation instructions are alternately executed, and the concurrent convergence of the flash medium is improved. Sex, reduce execution time.
  • the generating module is specifically configured to:
  • the generation rules of the timing signals are represented by a plurality of different types of pin level state information and output sequence information, and it is not necessary to store pin level state information corresponding to all clock cycles to avoid redundancy and reduce storage space. Occupied.
  • the controller further includes: a receiving module, a splitting module, a second determining module, and a storing instruction module.
  • the receiving module is configured to receive an operation instruction, where the operation instruction carries an access address
  • the splitting module is configured to split the operation instruction into at least two basic instructions
  • the second determining module is configured to determine, from the N function queues, a function queue associated with the access address
  • the store instruction module is configured to place the at least two base instructions into the associated function queue.
  • the operation instruction is split into a plurality of basic instructions, and the split basic instruction is placed in the corresponding function queue according to the access address, so that the basic instructions corresponding to the different operation instructions are alternately executed, and the concurrent convergence of the flash medium is improved. Sex, reduce execution time.
  • the second determining module is specifically configured to: obtain an address interval corresponding to each of the N Dies;
  • the controller determines the target Die according to the address range in which the access address carried in the operation instruction is located, and then determines the function queue associated with the target Die according to the mapping relationship between the Die and the function queue, so that the basic instruction obtained after the operation instruction is split is accurate. Enter the specified function queue to improve the efficiency of the basic command enqueue.
  • the selecting a queue module is used to:
  • a function queue that is not empty and the associated Die is an idle state is selected as the target function queue each time from the N function queues according to the queue ID ascending order or the queue ID descending order.
  • the target function queues selected in the two adjacent manners can be effectively prevented, and the controller continuously fetches instructions in a function queue, thereby reducing the waiting time of the controller and providing Die's concurrency improves the efficiency of basic instruction execution.
  • a third aspect of the present application provides a controller, including:
  • One or more processors, memories, bus systems, and one or more programs, the processors and memories are connected by a bus system;
  • One or more programs are stored in the memory, and the one or more programs include instructions that, when executed by the terminal, cause the controller to perform any one of the fifth possible implementations of the first aspect to the first aspect Said method.
  • a fourth aspect of the present application provides a computer readable storage medium storing one or more programs, the one or more programs including instructions that, when executed by a controller, cause the controller to perform the first aspect to the first aspect The method of any of the fifth possible embodiments.
  • FIG. 1 is a schematic flowchart of a method for accessing a flash memory according to an embodiment of the present invention
  • FIG. 2 is a schematic flowchart of still another method for accessing a flash media according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of a principle of splitting an operation instruction according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a principle of a timing signal generating method according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of another principle of generating a timing signal according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of a controller according to an embodiment of the present invention.
  • 6b is a schematic structural diagram of still another controller according to an embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of a system according to an embodiment of the present invention.
  • FIG. 8 is a schematic structural diagram of still another controller according to an embodiment of the present invention.
  • FIG. 1 is a schematic flowchart diagram of a method for a flash memory medium according to an embodiment of the present invention, where the method includes but is not limited to the following steps.
  • the controller selects a target function queue from the N function queues.
  • the N function queues may be pre-stored in the internal memory of the controller, for example, in a register or a cache of the controller memory, the controller is connected to at least one flash medium, and at least one flash medium includes at least one flash medium.
  • a Die the number of Dies connected to the controller is equal to the number of function queues N, and each of the N queues is uniquely associated with one Die, wherein a queue mapping indicating a one-to-one mapping relationship between N queues and N Dies can be pre-stored. information.
  • the controller may first select a non-empty function queue from the N queues, and then the controller acquires the Die associated with each function queue in the remaining function queue.
  • the controller selects a function queue from the function queue that satisfies the above two conditions according to the predefined rule as the current target function queue.
  • Each function queue in the N function queues may be a first in first out queue.
  • the controller is connected to 4 flash media, and each flash media includes 2 Dies.
  • the four flash media include 8 Dies.
  • the eight Dies are Die0, Die1, Die2, Die3, Die4, Die5, Die6 and Die7.
  • There are 8 function queues preset in the controller and the 8 function queues are function queue 0, function queue 1, function queue 2, function queue 3, function queue 4, function queue 5, function queue 6 and function queue 7.
  • 8 The function queue and the eight Dies are in a one-to-one mapping relationship, and each function queue corresponds to a unique one of the Dies.
  • Function queue 0 is associated with Die0
  • function queue 1 is associated with Die1
  • the process of selecting the target function queue by the controller may be: the controller selects the non-empty queue from the eight function queues, and assumes that the filtered non-empty queue is function queue 1, function queue 2, function queue 3, function queue 5, function Queue 6, the controller next obtains the state of the flash medium in which the Die associated with each of the above five queues is located, assuming that the state of the flash medium of Die1 is idle, the state of the flash medium where Die2 is idle, and the flash medium where Die3 is located. The status is busy, the state of the flash media where Die4 is busy is busy, and the state of the flash media where Die5 is located is busy.
  • the function queue finally filtered by the controller is function queue 1 and function queue 2, and the controller is from the above. In the two queues, one function queue is selected as the target function queue according to the predefined rules.
  • the controller may maintain a record table, where the storage location of the record table may be in an internal register or a cache of the controller, and the record table may be external to the controller and independent of the controller.
  • the record table includes a plurality of entries for recording the number of basic instructions currently stored in the function queue.
  • the controller updates the record table. The entry corresponding to the function queue. In this way, before selecting the target function queue, the controller can exclude the empty function queue according to the record table, and select a non-empty function queue as the target function queue.
  • the controller extracts a basic instruction from the target function queue.
  • the target queue may be a first in first out queue
  • the controller may take out a basic instruction from the head of the target function queue. After detecting the dequeuing operation of the basic instruction in the target function queue, the controller updates the entry of the target function queue in the record table, and decrements the value of the basic instruction in the target function queue stored in the entry.
  • the controller determines, according to the preset queue mapping information, the association with the target function queue. Die.
  • the controller generates a timing signal corresponding to the basic instruction according to the preset signal generation rule, and sends the timing signal to the flash medium where the associated Die is located.
  • the signal generation rule indicates a mapping relationship between the basic instruction and the timing signal generation rule
  • the timing signal generation rule indicates a rule of the waveform outputted on the designated pin of the controller
  • the controller generates and forms a rule according to the preset signal generation rule.
  • the timing signal corresponding to the instruction the controller determines the flash medium in which the associated Die is located according to the correspondence between the flash medium and the Die, and the controller sends a timing signal to the flash medium.
  • the flash medium is based on The level signal on the address pin acquires the location of the memory cell to be read, and the flash medium transmits the data in the memory cell to the Nand Flash controller through the data pin under the control of the level signal on the control pin; If the type of the basic instruction is a write operation, the flash medium acquires the position of the memory cell to be written according to the level state on the address pin, and the media control controls the data signal under the control of the level signal input on the control pin. The data to be written is written to the storage unit.
  • the controller is connected to a flash medium, and the flash medium includes three Dies, namely Die0, Die1 and Die2.
  • the flash medium includes three Dies, namely Die0, Die1 and Die2.
  • function queue 0 There are currently three basic instructions stored in function queue 0: basic instruction 00, basic instruction 01 and basic instruction 02.
  • the above three basic instructions are obtained by the controller splitting the received first operation instruction; the current function queue 1 is currently
  • the basic instruction 10 the basic instruction 11 and the basic instruction 12
  • the above three basic instructions are obtained by the controller splitting the received second operation instruction;
  • the function queue 2 currently stores three basics.
  • the instruction: the basic instruction 20, the basic instruction 21, and the basic instruction 22, and the above three basic instructions are obtained by the controller splitting the received third operation instruction.
  • the basic instruction 00 sends the basic instruction 00 to the associated Die0, where Die0 is busy; then, the controller selects the target function queue again, and the target function queue is full.
  • the flash memory medium in which the non-empty queue and the associated Die are located is in an idle state.
  • the function queues satisfying the condition are function queue 1 and function queue 2, and the controller selects any one of the two function queues as the target function queue.
  • the controller selects the basic instruction of the head of the queue from function queue 1 and sends it to the associated Die1.
  • the controller selects the target function queue again, because Die0 may have executed the basic instruction at this time.
  • the function queue that satisfies the condition at this time may be function queue 0 and function queue 2, and the controller randomly selects one of the above two queues as the target function queue, assuming function queue 2, the controller will function
  • the base instruction of the queue head of queue 2 is sent to the associated Die2. In this way, the controller can send the next instruction to another Die during the execution of a Die instruction, and does not need to wait until the instruction on one Die is executed before sending the next instruction, and multiple Dies can execute the instructions in parallel. Improve the efficiency of the execution of operational instructions.
  • the controller selects the target function queue according to the predefined rule to satisfy the non-empty queue and the associated flash memory is in an idle state. Since each function queue corresponds to a different Die, different Die parallel executions can be implemented.
  • the basic instructions sent by the controller improve the execution efficiency of the operation instructions.
  • the waveform of the timing signal corresponding to the basic instruction is generated by a preset signal generation rule, so that the signal generation rules corresponding to different types of flash media can be configured to match different types of flash media, and the controller is improved. Compatibility with flash media.
  • FIG. 2 is a schematic flowchart diagram of a method for a flash memory medium according to an embodiment of the present invention, where the method includes but is not limited to the following steps:
  • the configuration device pre-configures the controller to make the controller compatible with the connected flash media
  • the configuration device may be a computer, a test host, a workstation, or a server, and the configuration device may be configured according to the type of the storage medium.
  • the configuration file, the configuration device can burn the configuration file into the high speed memory through the programmer, and the high speed memory can be a readable memory in the flash chip.
  • the configuration device determines the number M of flash media that the controller needs to connect, each flash media in the M flash media includes at least one Die, and the configuration device determines that the number of Dies included in the M flash media is N, M and N are integers greater than zero, for example: M flash media can be the same type of flash media, and the same type indicates that the flash media have the same pin and timing signal format.
  • the configuration information required to configure the device includes but is not limited to:
  • the configuration device configures the number of function queues to be N according to the number of Dies included in the M flash media.
  • the device is configured to obtain a mapping relationship between the M flash media and the N Dies, and generate flash mapping information.
  • the configuration device configures a splitting rule for each operation instruction in all the operation instructions, and the split rule can be expressed as a correspondence between the identifier of the operation instruction and the identifier of the basic instruction, and the configuration device is pre-defined for each type of foundation.
  • the instruction assigns an identifier and assigns an identifier to each type of operational instruction;
  • the configuration signal generation rule includes: configuring a device, setting an identifier of the basic instruction, configuring the device to store the identifier of the basic instruction, the number of clock cycles, and the level state information as a signal generation rule; or configuring the identifier of the basic instruction, and setting the basic instruction
  • the signal is generated by binding the at least one pin level state information and the output sequence information to generate a signal generation rule.
  • the configuration device writes a configuration file including 1-5 configuration information into a memory, which may be a register or a cache internal to the controller, the memory may be independent of the controller, and the controller and the memory are located inside the storage device.
  • a memory which may be a register or a cache internal to the controller, the memory may be independent of the controller, and the controller and the memory are located inside the storage device.
  • the controller is connected to two flash media, each flash media includes 2 Dies, and the total number of Dies connected to the controller is 4.
  • the mapping relationship between the flash media and the Die configured by the device configuration is as follows:
  • the number of flash media connected by the controller the number of Dies included in the flash media, the mapping relationship between the flash media and the Die, and the mapping relationship between the function queue and the Die are not limited to this. , can be configured as needed.
  • the controller receives an operation instruction.
  • the operation instruction may be sent by an upper layer device, and the upper layer device may be an SSD controller, and the operation instruction carries an access address.
  • Both read and write operations are in page units. Read operations can randomly read pages at any position. Write operations can only be written in page order.
  • the controller splits the operation instruction into at least two basic instructions.
  • the controller may pre-store a mapping relationship between the identifier of the operation instruction and the identifier of the basic instruction, and after receiving an operation instruction, the controller may query multiple basic instructions associated with the identifier of the operation instruction according to the mapping relationship.
  • the corresponding corresponding identifiers are divided into a plurality of basic instructions, and the format of the basic instructions carrying the basic instructions may be a message, and the controller splits the operation instructions into a plurality of basic instructions, and adds the basic instructions to the basic instructions.
  • the identifier that is queried according to the mapping relationship.
  • the read operation instruction is a page read instruction
  • the controller splits the read page instruction into three basic instructions according to a preset mapping relationship.
  • the basic instruction 1 sending a read command
  • the basic instruction 2 checking Status register
  • base instruction 3 Transfer data.
  • the controller determines, from the N function queues, a function queue associated with the access address.
  • the N pairs of the controllers are respectively assigned an address interval. Since the N function queues and the N pairs are in a one-to-one mapping relationship, each function queue corresponds to an address interval, and the controller determines the operation instructions.
  • the access address is located in which of the N address ranges, whereby the controller can determine the function queue associated with the access address from the N function queues.
  • the address range of Die0 is [a, b], Die0 is associated with function queue 1; the address range of Die1 is [c, d], and Die1 is associated with function queue 1; the address range of Die2 is [e, f], and Die2 is associated.
  • the controller puts at least two basic instructions into an associated function queue.
  • At least two basic instructions after the controller splits the S203 may be sequentially placed in the queue end of the associated function queue according to the first in first out sequence.
  • the controller may maintain a record table in which the entry indicating the number of basic instructions currently stored in each function queue is stored, and the controller detects a function queue in the N function queues. When the number of base instructions in the update is updated, the controller updates the entry of the function queue in the record table.
  • the controller selects a non-empty function queue from the N function queues as the target function queue each time according to the priority descending order.
  • the N function queues are pre-configured with priority, and the controller selects a non-empty function queue from the N queues as the target function queue each time.
  • the controller selects a target function queue from N function queues according to a priority from high to low. Assume that the priority of function queue 0 is 4, the priority of function queue 1 is 2, the priority of function queue 2 is 1, the priority of function queue 3 is 3, and the pairs associated with 4 function queues are idle, according to The preset selection rule, the controller selects function queue 0 as the target function queue for the first time, selects function queue 3 as the target function queue for the second time, selects function queue 1 as the target function queue for the third time, and selects the function queue for the fourth time. 2 as the target function queue.
  • the method for the controller to select the target function queue is: the controller randomly selects one non-empty and associated Die from the N function queues each time to be in an idle state.
  • the function queue acts as the target function queue.
  • the method for the controller to select the target function queue is: the controller selects one of the N function queues each time according to the queue ID ascending order or the queue ID descending order.
  • a non-empty and associated Die is a function queue of the idle state as the target function queue.
  • the controller takes a basic instruction from the target function queue.
  • the controller fetches a basic instruction from the queue head of the target function queue, and the base instruction becomes a new queue header.
  • the number of basic instructions stored in the target function queue changes, and the controller updates the entries of the target function queue in the record table.
  • the controller determines, according to preset queue mapping information, a Die associated with the target function queue.
  • the controller acquires an identifier of the basic instruction.
  • the controller may obtain the identifier of the instruction in the specified field, and the different types of basic instructions correspond to different identifiers.
  • the controller queries, according to the preset signal generation rule, the clock cycle quantity information and the level state information associated with the identifier of the basic instruction.
  • the number of clock cycles indicates the number of clock cycles to be output, and the number of clock cycles corresponding to different types of basic instructions may be equal or unequal.
  • the level status information indicates the level state on the designated pin for each clock cycle to be output, and the number of level states is equal to the number of clock cycles to be output.
  • the controller generates a timing signal according to the clock cycle quantity information and the level state information.
  • the controller outputs a level state corresponding to the clock cycle on the designated pin according to the level state information until the level state is output on the designated pin in all clock cycles.
  • FIG. 4 is a waveform diagram of a timing signal corresponding to a basic instruction.
  • the clock cycle quantity information and level state information of the basic instruction are shown in Table 3.
  • C0-C15 represents a clock.
  • the serial number of the cycle, the timing signal of the basic instruction lasts for 16 clock cycles
  • I0-I15 represents the level state on the designated pin corresponding to each clock cycle.
  • the designated pins are: CE# pin, CLE pin, ALE Pin and WE# pins, the level state on each pin can be high or low, or it can be a rising or falling edge.
  • the pins of the flash media and their functions are as follows:
  • ALE Address Latch Enable
  • the number of clock cycles queried by the controller according to the basic instruction is 16.
  • the controller executes the basic instruction and needs to output 16 clock cycles C0-C15, the level status information is I0-I15, and the controller is in the output clock cycle C0.
  • the CE# pin When the level state of the specified pin indicated by I0 is queried, the CE# pin outputs a low level, the CLE pin outputs a low level, the ALE pin outputs a low level, and the WE# pin outputs a high level.
  • the DQ pin outputs a high level; when the controller outputs the clock cycle C1, the level state of the specified pin indicated by I1 is queried: the CE# pin outputs a low level, and the CLE pin outputs a high level.
  • the ALE pin outputs a low level and the WE# pin outputs a low level.
  • the controller outputs a timing signal on the designated pin as described above until the end of all clock cycles.
  • the controller queries the associated level state according to the serial number of the clock cycle, and outputs a corresponding high level or low level on the designated pin according to the level state.
  • the controller sends a timing signal to the flash medium where the associated Die is located through a designated pin.
  • the controller may query the flash media in which the associated Die is located according to the pre-stored flash mapping information, and the controller sends the timing signal to the flash medium through the designated pin.
  • the controller generates a timing signal corresponding to the basic instruction according to the preset signal generation rule, and sends the timing signal to the flash medium where the associated Die is located.
  • the controller includes: obtaining, by the controller, an identifier of the basic instruction; the controller queries at least one of the pin level status information and the output sequence information associated with the identifier of the basic instruction; wherein the pin level status information indicates a designated pin within one clock cycle The upper level state, the output sequence information indicates an arrangement order of at least one pin level state information; the controller generates a timing signal according to at least one of the pin level state information and the output order information; the controller is associated with the specified pin
  • the flash media on which Die is located sends timing signals.
  • the pin level status information indicates a level status of an output on a designated pin within one clock cycle
  • the output sequence information indicates an arrangement order of at least one type of pin level status information
  • the controller queries the pin level status information associated with the basic instruction as I0-I7, a total of 8 pin level status information, and obtains I0-I7 according to the queried output order information.
  • the order is I0, I1, I2, I3, I4, I3, I4, I3, I4, I3, I4, I3, I4, I5, I6, I7, where I3, I4 are repeated 4 times after I2, and the controller is in the output clock cycle.
  • the level state on the specified pin indicated by I0 is: CE# pin output low level, CLE pin output low level, ALE pin output low level, WE# pin output high power
  • the DQ pin outputs a high level, and the output method of the subsequent timing signals will not be described again.
  • the pin level state information for multiple repetitions can be represented by the output order, and it is not necessary to store multiple sets of the same pin level state information, thereby reducing information redundancy and saving storage space.
  • the controller when the target function queue is selected, the controller satisfies the target function queue as a non-empty queue and the flash medium in which the target function queue is associated is in an idle state, so that different Die parallel execution controllers can be implemented.
  • the instruction reduces the execution time of the operation instruction; at the same time, the timing signal corresponding to the basic instruction is generated by a preset signal generation rule, so that the signal generation rules corresponding to different types of flash media can be configured to match different types of flash media.
  • the role of the controller to improve the compatibility of flash media.
  • FIG. 6a is a schematic structural diagram of a controller according to an embodiment of the present invention.
  • the controller 6 may include a queue selection module 601, an instruction fetching module 602, a first determining module 603, a generating module 604, and a sending module. 605, wherein the detailed description of each module is as follows.
  • the queue selection module 601 is configured to select a target function queue from the N function queues, wherein the target function queue is a non-empty queue, and the flash medium in which the Die associated with the target function queue is located is in an idle state, N Is an integer greater than 1.
  • the fetch module 602 is configured to fetch a basic instruction from the target function queue.
  • a first determining module 603 configured to determine a Die associated with the target function queue according to preset queue mapping information, where the controller is connected to at least one flash medium, and each flash media in the at least one flash medium includes At least one Die, the number of Dies connected to the controller is equal to N, and the queue mapping information represents a mapping relationship between the N function queues and N Dies.
  • a generating module 604 configured to generate a timing signal corresponding to the basic instruction according to a preset signal generation rule
  • the sending module 605 is configured to send the timing signal to a flash medium in which the associated Die is located.
  • the controller when the target function queue is selected, the controller satisfies the target function queue as a non-empty queue and the flash medium in which the target function queue is associated is in an idle state, so that different Die parallel execution controllers can be implemented.
  • the instruction reduces the execution time of the operation instruction; at the same time, the timing signal corresponding to the basic instruction is generated by a preset signal generation rule, so that the signal generation rules corresponding to different types of flash media can be configured to match different types of flash media.
  • the role of the controller to improve the compatibility of flash media.
  • each module may also correspond to the corresponding description of the method embodiment shown in FIG. 1 .
  • FIG. 6b is a schematic structural diagram of still another controller according to an embodiment of the present invention.
  • the controller includes a queuing module 601, an instruction fetching module 602, a first determining module 603, a generating module 604, and a sending module. 605.
  • the receiving module 606, the splitting module 607, the second determining module 608, and the storing instruction module 609 are further included. The detailed description of each unit is as follows.
  • the receiving module 606 is configured to receive an operation instruction, where the operation instruction carries an access address.
  • the splitting module 607 is configured to split the operation instruction into at least two basic instructions.
  • a second determining module 608 configured to determine, from the N function queues, the access address The function queue.
  • the storage instruction module 609 is configured to put the at least two basic instructions into the associated function queue.
  • the generating module 605 is specifically configured to:
  • pin level status information indicates a level status on a designated pin within one clock cycle
  • output sequence Information indicating an output order of the at least one pin level state information
  • the timing signal is generated based on the at least one pin level state information and the output sequence information.
  • the generating module 605 is specifically configured to:
  • clock cycle quantity information indicates the number of clock cycles to be output
  • level state information indicates that The level state of each clock cycle on the specified pin in the output clock cycle
  • the timing signal is generated based on the clock cycle number information and the level state information.
  • the second determining module 608 is specifically configured to:
  • the queue selection module 601 is specifically configured to:
  • a non-empty function queue is selected from the N function queues as the target function queue each time according to the queue ID ascending order or the queue ID descending order.
  • each unit may also correspond to the corresponding description of the method embodiment shown in FIG. 2 .
  • the controller 6 can be implemented by an application-specific integrated circuit (English: Application-Specific Integrated Circuit, ASIC) or a programmable logic device (English: Programmable Logic Device, abbreviated as PLD).
  • the PLD may be a Complex Programmable Logic Device (CPLD), an FPGA, a Generic Array Logic (GAL), or any combination thereof.
  • the controller 6 is used to implement the access method of the flash medium shown in FIG. 1.
  • the controller 6 and its respective modules may also be software modules, such as software modules implementing the Nand Flash controller.
  • the controller when the target function queue is selected according to the predefined rule, the controller satisfies the target function queue as a non-empty queue and the flash medium in which the target function queue is associated is in an idle state, so that different Die parallel executions can be implemented.
  • the basic instruction sent by the controller reduces the execution time of the operation instruction; at the same time, the timing signal corresponding to the basic instruction is generated by a preset signal generation rule, so that the signal generation rule corresponding to different types of flash media can be configured to achieve matching.
  • the role of different types of flash media improves the controller's compatibility with flash media.
  • the system includes a configuration device 8 and a storage device 7, the storage device 7 including a controller 700 and k flash media 701-70k, k being an integer greater than zero, each of the k flash media including at least one Die.
  • the configuration device 8 is configured to configure queue mapping information and signal generation rules, and send queue mapping information and signal generation rules to the controller 700, wherein the configuration information may be stored in a register set of the controller 700 or In the cache.
  • the controller 700 is configured to select a target function queue from the N function queues at a time; wherein the target function queue is a non-empty queue and the flash media in which the Die corresponding to the target function queue is located is in an idle state, and N is an integer greater than one;
  • the controller 700 extracts a basic instruction from the target function queue; the controller 700 maps information according to preset queues.
  • the controller 700 Determining a pair associated with the target function queue, the queue mapping information indicating that the N function queues are in a one-to-one mapping relationship with the N Dies; and the controller 700 generates a rule according to a preset signal generation rule and the basis a timing signal corresponding to the instruction, and transmitting the timing signal to a flash medium in which the associated Die is located; the flash medium in which the associated Die is located is a flash medium in a k flash medium; the flash memory in which the associated Die is located The medium is configured to receive the timing signal and perform a corresponding operation.
  • the controller when the target function queue is selected, the controller satisfies the target function queue as a non-empty queue and the flash medium in which the target function queue is associated is in an idle state, so that different Die parallel execution controllers can be implemented.
  • the instruction reduces the execution time of the operation instruction; at the same time, the timing signal corresponding to the basic instruction is generated by a preset signal generation rule, so that the signal generation rules corresponding to different types of flash media can be configured to match different types of flash media.
  • the role of the controller to improve the compatibility of flash media.
  • FIG. 8 is a schematic structural diagram of a controller according to an embodiment of the present invention.
  • the controller 800 includes a processor 801, a memory 802, and a communication interface 803.
  • the communication interface 803 is configured to be connected to at least one flash medium, each flash medium includes at least one Die; when the number of the flash media exceeds one, the controller 800 can connect to the plurality of flash media in parallel by using the communication interface 803;
  • the communication interface can be an ONFI or a toggle interface.
  • two flash media are connected by controller 800: flash media 804 and 805.
  • the number of flash media to which the controller 800 is connected and the number of Dies included in the flash media are not limited thereto.
  • the number of processors 801 in controller 800 can be one or more.
  • the processor 801, the memory 802, and the communication interface 803 may be connected by a bus system or other manner, and the processor 801, the memory 802, and the communication interface 803 may be connected by wire, or may be wirelessly transmitted. Other means to achieve communication. Controller 800 can be used to perform the method illustrated in FIG. For the meanings and examples of the terms involved in this embodiment, reference may be made to the corresponding embodiment of FIG. 1 , and details are not described herein again.
  • the program code is stored in the memory 802.
  • the processor 801 is configured to call program code stored in the memory 802 for performing the following operations:
  • Target function queue is a non-empty queue, and the flash medium in which the Die associated with the target function queue is located is in an idle state, and N is an integer greater than 1;
  • Determining a Die associated with the target function queue according to preset queue mapping information wherein the controller is connected to at least one flash medium, each of the at least one flash medium includes at least one Die, the controller The number of connected Dies is equal to N, and the queue mapping information represents a mapping relationship between the N function queues and N Dies;
  • the timing signal is sent to a flash media in which the associated Die is located.
  • the executing, by the processor 801, the timing signal corresponding to the basic instruction according to the preset signal generation rule includes:
  • pin level status information indicates a level status on a designated pin within one clock cycle
  • output sequence Information indicating an output order of the at least one pin level state information
  • the timing signal is generated based on the at least one pin level state information and the output sequence information.
  • the executing, by the processor 801, the timing signal corresponding to the basic instruction according to the preset signal generation rule includes:
  • clock cycle quantity information indicates the number of clock cycles to be output
  • level state information indicates that The level state of each clock cycle on the specified pin in the output clock cycle
  • the timing signal is generated based on the clock cycle number information and the level state information.
  • processor 701 is further configured to execute;
  • the at least two base instructions are placed in the associated function queue.
  • the determining, by the processor 701, the function queue that is associated with the access address in the N function queues includes:
  • the processor 701 performs the step of selecting a target function queue according to a predefined rule from the N function queues each time:
  • a non-empty function queue is selected from the N function queues as the target function queue each time according to the queue ID ascending order or the queue ID descending order.
  • the controller satisfies the non-empty queue and the flash media in which the Die associated with the target queue is in an idle state when the target function queue is selected, and can implement different Die parallel execution controllers.
  • Basic instructions to improve the efficiency of the execution of operating instructions.
  • the waveform of the timing signal corresponding to the basic instruction is generated by a preset signal generation rule, so that the signal generation rules corresponding to different types of flash media can be configured to match different types of flash media, and the controller is improved. Compatibility with flash media.
  • a person skilled in the art can understand that all or part of the process of implementing the above embodiment method can be completed by a computer program to instruct related hardware, and the program can be stored in a computer readable storage medium. When executed, the flow of an embodiment of the methods as described above may be included.
  • the foregoing storage medium includes: ROM, RAM, disk, or optical disk, etc., which can store various generations of programs. The medium of the code.

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Abstract

本申请公开了一种闪存介质的访问方法,包括:控制器从N个功能队列中按照预定义规则选择一个目标功能队列;其中,目标功能队列为非空队列,且与目标功能队列关联的Die所在的闪存介质为空闲状态,N为大于1的整数;从目标功能队列中取出一个基础指令;根据预设的队列映射信息确定与目标功能队列关联的Die;其中,控制器连接至少一个闪存介质,至少一个闪存介质包括N个Die,队列映射信息表示N个功能队列与N个Die呈一一映射关系;根据预设的信号生成规则生成与基础指令对应的时序信号,以及向关联的Die所在的闪存介质发送时序信号。采用本发明,能提高闪存介质指令执行的效率以及控制器对不同闪存介质的兼容性。

Description

一种闪存介质的访问方法及控制器 技术领域
本发明涉及存储领域,尤其涉及一种闪存介质的访问方法及控制器。
背景技术
固态硬盘(Solid State Device,SSD)因其具有存取速度快和抗震性能好等优点,使其应用越来越广泛。固态硬盘的主要存储介质为闪存介质,例如Nand Flash,一个Nand Flash为一个设备(device),一个设备可以由1个或多个晶片(Die)构成,一个晶片可以分成多个闪存片(Plane),一个闪存片可以分成若干个块(Block),一个块又被分成很多个页(Page)。Nand Flash的数据读写操作的基本单位为页,以块为单位进行数据擦除。
不同的Nand Flash厂家生产的Nand Flash拥有不同的模式、速度、命令和协议,甚至相同的生产厂家的不同工艺和批次的Nand Flash对应的模式、速度、命令和协议也可能不相同,现有的Nand Flash控制器采用固件的形式来控制闪存介质,无法兼容不同类型的闪存介质。同时,Nand Flash控制器的操作方法是:在接收到操作指令后,先将操作指令拆分为多个基础指令,再将多个基础指令依次发送给闪存介质,Nand Flash控制器在等待闪存介质执行完一个基础指令后,再将下一个基础指令发送给闪存介质。由于不同的基础指令执行时间的差异,控制器将会浪费很多的等待时间去等待当前指令被闪存介质执行完之后再发送新的指令,造成操作指令执行效率低。
发明内容
本申请公开了一种闪存介质的访问方法及控制器,能够提高操作指令的执行效率和兼容不同类型的存储介质。
本申请第一方面提供了一种闪存介质的访问方法,存储介质可以为Nand Flash,控制器可以为Nand Flash控制器,控制器可位于个人计算机、服务器、磁盘阵列或固态硬盘中。N个功能队列可以设置于控制器内部的存储器中,例如:控制器内部的寄存器或缓存中,功能队列用于存放基础指令。基础指令由 控制器的上层设备发出的操作指令拆分而成,上层设备可以为SSD(Solid State Drives,固态硬盘,简称SSD)控制器。控制器连接有至少一个闪存介质,至少一个闪存介质中每个闪存介质包括至少一个Die。控制器中功能队列的数量等于控制器连接的的Die的数量,即Die的数量也为N个,N个功能队列和N个Die呈一一映射关系,即一个功能队列唯一对应的一个Die。操作指令表示SSD控制器发出的针对Nand Flash的逻辑操作,例如:读页操作或擦除块操作等,操作指令需要由Nand Flash控制器具体来执行,Nand Flash控制器在执行SSD控制器发出的操作指令时需要执行的一组微操作,该微操作即为基础指令,基础指令可由控制器可直接执行例如:基础指令为:块擦除操作、写数据操作、写等待操作和状态查询操作等。
下面对控制器的工作原理进行说明:控制器从N个功能队列中根据预定义规则选择一个目标功能队列,其中,选择的目标功能队列满足非空队列和目标功能队列对应的Die所在的闪存介质为空闲状态的条件,非空队列表示功能队列中至少存放一个基础指令。控制器检测Die所在的闪存介质的状态的方法可以是:控制器向Die所在的闪存介质发送专有的状态检测指令,状态检测指令能优先被闪存介质响应,在极短的时间内返回Die的状态,由此控制器可检测Die所在的闪存介质的状态;需要说明的是,在闪存介质包括多个Die的情况下,多个Die中至少有1个Die所在的闪存介质为空闲状态时表明对应的闪存介质空闲状态。其中,控制器获取功能队列中的基础指令的数量的方法可以是:控制器可以维护一个记录表,记录表中存放表示N个功能队列中每个功能队列中当前的基础指令数量的表项,当某个功能队列中队列头的基础指令发生入队操作或出队操作时,控制器更新记录表中存储该功能队列的表项。控制器从目标功能队列中取出一个基础指令。控制器根据预设的队列映射信息确定与目标功能队列关联的Die,同时根据预设的闪存介质与Die的对应关系,确定关联的Die所在的闪存介质,控制器根据预设的信号生成规则生成与基础指令对应的时序信号,信号生成规则表示基础指令的时序信号生成规则,例如:输出的时钟周期数量、输出的引脚的序号、每个时钟周期内引脚上的电平状态等,控制器向关联的Die所在的闪存介质发送时序信号。其中,控制器与闪存介质之间的通信协议可遵循Toggle(切换)或ONFI(Open Nand Flash Interface,开放Nand闪存接口)协议。
上述实施例,控制器在根据预定义规则选择目标功能队列时,满足目标功能队列为非空队列且目标功能队列关联的Die所在的闪存介质为空闲状态,这样能实现不同的Die并行的执行控制器发送的基础指令,提高操作指令的执行效率。同时,基础指令对应的时序信号由预设的信号生成规则生成,这样可以通过配置与不同类型的闪存介质对应的信号生成规则,以达到匹配不同类型的闪存介质的作用,提高了控制器对闪存介质的兼容性。
在一种可能的实施方式中,所述方法还包括:
控制器接收操作指令,操作指令的类型可以是读操作指令或写操作指令,操作指令携带访问地址。操作指令可以由不同类型的基础指令通过不同的组合方式构成,控制器可以根据预设的拆分规则将操作指令拆分为至少两个基础指令,拆分规则可以为:根据预先定义的操作指令与基础指令的映射关系进行拆分。例如拆分规则可以是:当读操作指令为读页命令时,读命令中可携带自身的标识,控制器可根据预存的操作命令的标识与基础指令的标识的对应关系,得到关联的3个基础命令的标识,根据3个基础命令的标识将将读页命令拆分为三个基础指令:发送读命令、检查状态寄存器和读数据传输,每个基础命令中携带自身的标识;又例如拆分规则可以是:写操作指令为写页命令时,根据预存的写页命令的标识与基础指令的标识的映射关系可以将操作指令拆分成3个基础指令:1、擦除块,2、检查状态寄存器,3、传输数据,每个基础指令可携带自身的标识。本实施例中操作指令的拆分规则并不限于上述举例,可以根据需要采用现有的任意一种方法进行拆分。控制器连接有至少一个闪存介质,至少一个闪存介质中每个闪存介质包括至少一个Die,控制器连接的Die的数量等于功能队列的数量N,N个Die中每个Die具有不同的地址区间,由于N个功能队列和N个Die是一一映射关系,每个功能队列对应一个地址区间,控制器根据操作指令中携带的访问地址所在的地址区间来从N个功能队列中确定关联的功能队列。控制器将拆分后的至少两个基础指令放入关联的功能队列。需要说明的是,控制器将拆分后的基础指令放入功能队列时,发送基础指令的顺序可按照先进先出的规则。
值得说明的是,不同厂商的闪存介质对操作指令拆分的方法可不相同,例如对于同一操作指令,不同厂商拆分操作指令得到的基础指令的类型和数量可以各不相同,具体的拆分规则本发明不作限制。
上述实施例,将操作指令拆分为多个基础指令,将拆分后的基础指令根据访问地址放入对应的功能队列,以便不同操作指令对应的基础指令并发的被执行,提高闪存介质的Die的并发性,减少执行时间。
在本发明的一种可能的实施方式中,控制器接收到上层设备发送的一个操作指令时,控制器可将接收到的操作指令缓存在命令队列中,命令队列可以为先进先出队列,命令队列起到缓冲作用,控制器每次从命令队列中取出一个操作指令。其中,命令队列可以设置在控制器内部的存储器或控制器外部的存储器,本实施例不作限制。
在一种可能的实施方式中,不同类型的基础指令预先分配有不同的标识,基础指令的标识用于表示基础指令的身份,控制器对操作指令进行拆分后,可以根据预先分配给基础指令的标识,将标识增加到基础指令中,例如:基础指令的标识可以用基础指令中指定的字段来表示,控制器可以读取基础指令中指定字段来确定该基础指令的标识,控制器查询与基础指令的标识关联的至少一种引脚电平状态信息和输出顺序信息,引脚电平状态信息表示一个时钟周期内指定引脚上的电平状态,电平状态包括高电平或低电平;指定引脚为传输控制信号的控制引脚,不包括用于传输数据信息的数据引脚和用于传输地址信息的地址引脚,不同的引脚电平状态信息表示的指定引脚上的电平状态不同。输出顺序信息表示引脚电平状态信息的输出顺序,一种引脚电平状态信息可以重复出现,输出顺序信息可通过在引脚电平状态信息后面添加字段来表示重复条件。控制器根据至少一种引脚电平状态信息和输出顺序信息生成时序信号,控制器通过指定引脚向关联的Die所在的闪存介质发送时序信号。
上述实施例,通过多个不同种类的引脚电平状态信息和输出顺序信息来表示时序信号的生成规则,不需要存储所有时钟周期对应的引脚电平状态信息避免冗余,减少存储空间的占用。
在一种可能的实施方式中,不同类型的闪存介质的信号时序不相同,如果要控制器兼容某种类型的闪存介质,配置设备需要根据闪存介质的信号时序的特点对控制器进行相关的配置,配置设备可以是计算机、测试平台或其他设备,配置过程可以是:配置设备获取基础指令对应的时序信号,获取每个时钟周期内指定引脚上的电平状态,如果两个引脚电平状态信息表示的一个时钟周期内指定引脚上电平状态相同,则两个引脚电平状态信息为相同的类型,统计时序 信号中不同类型的引脚电平状态信息的数量,确定不同类型的引脚电平状态信息的输出顺序,生成输出顺序信息。设置基础指令的标识,将基础指令的标识与划分的至少一种引脚电平状态信息和输出顺序信息进行绑定后生成信号生成规则,信号生成规则可预先存储在控制器内部的存储器中,例如:存储器包括WCS(Writable Control Storage,可写控制存储器,简称WCS)、寄存器或缓存。
上述实施例,通过多个不同种类的引脚电平状态信息和输出顺序信息来表示时序信号的信号生成规则,不需要存储所有时钟周期对应的引脚电平状态信息避免冗余,减少存储空间的占用。
在一种可能的实施方式中,控制器根据预设的信号生成规则生成与基础指令对应的时序信号,以及向关联的Die所在的闪存介质发送时序信号包括:控制器获取基础指令的标识,控制器根据预设的信号生成规则查询与基础指令的标识关联的时钟周期数量信息和电平状态信息;其中,时钟周期数量信息表示待输出的时钟周期的数量,电平状态信息表示待输出的时钟周期中每个时钟周期在指定引脚上的电平状态;控制器根据时钟周期数量信息和电平状态信息生成时序信号;控制器通过指定引脚向关联的Die所在的闪存介质发送时序信号。
上述实施例,由于每个时钟周期都预先对应有电平状态信息,控制器能快捷的通过查表的方式查询到当前时钟周期内指定引脚上的电平状态,避免复杂的计算过程,减少时序信号生成的时延。
在一种可能的实施方式中,控制器接收操作指令之前,配置设备需要根据闪存介质的时序信号的特点对控制器进行相关的配置,配置方法包括:配置设备设置基础指令的标识,配置设备将基础指令的标识与时钟周期数量信息和电平状态信息进行绑定后存储至信号生成规则中。
上述实施例,控制器能根据预先设置的时钟周期数量信息和电平状态信息快速的生成时序信号,电平状态信息表示每个时钟周期内指定引脚上的电平状态,这样在查表时能快速的查询电平状态,减少生成时序信号的时间。
在一种可能的实施方式中,控制器确定N个功能队列中与访问地址关联的功能队列包括:控制器连接有至少一个闪存介质,至少一个闪存介质中每个闪存介质包括至少一个Die,控制器连接的Die的数量等于功能队列的数量,控制器可预先存储有N个Die中每个Die的地址区间,控制器可以在存储器中 获取预存的N个Die各自对应的地址区间,控制器根据操作指令中携带的访问地址所在地址区间确定目标Die,目标Die为N个Die中的一个,控制器根据预设的队列映射信息确定与所述目标Die关联的功能队列。
上述实施例,控制器根据操作指令中携带的访问地址所在的地址区间确定目标Die,再根据Die与功能队列的映射关系确定目标Die关联的功能队列,便于操作指令拆分后得到的基础指令准确的进入指定的功能队列,提高基础指令入队的效率。
在一种可能的实施方式中,控制器每次从N个功能队列中根据预定义规则选择出一个目标功能队列包括:N个功能队列预先设置有不同的优先级,控制器从N个功能队列中选择目标功能队列的方法为:控制器根据优先级降序的方式每次从N个功能队列中选择一个非空且关联的Die为空闲状态的功能队列作为目标功能队列。或者控制器从N个功能队列中选择目标功能队列的方法为:控制器随机方式每次从N个功能队列中选择一个非空且关联的Die为空闲状态的功能队列作为目标功能队列。或者N个功能队列预先设置有不同的队列ID,队列ID表示功能队列的身份,不同的功能队列具有不同的队列ID,控制器从N个控制器根据队列ID升序或队列ID降序的方式每次从N个功能队列中选择一个非空的且关联的Die为空闲状态功能队列作为目标功能队列。
上述实施例,通过上述的目标功能队列的选择方法,能并行地将各个功能队列中的操作指令发送给闪存介质去执行,避免控制器持续在一个功能队列中取指令,从而能减少控制器的等待时间,提高多个Die的并发性和基础指令执行的效率。
本申请第二方面提供了一种控制器,包括:选队列模块、取指令模块、第一确定模块、生成模块和发送模块。
选队列模块用于从N个功能队列中选择一个目标功能队列;其中,目标功能队列为非空队列、目标功能队列关联的Die所在的闪存介质为空闲状态,N为大于1的整数,N个功能队列中每个功能队列用来存放操作指令拆分得到的基础指令,非空队列表示功能队列中至少存放1个基础指令;取指令模块用于从所述目标功能队列中取出一个基础指令。第一确定模块用于根据预设的队列映射信息确定与所述目标功能队列关联的Die;其中,所述控制器连接至少 一个闪存介质,所述至少一个闪存介质中每个闪存介质包括至少一个Die,控制器连接的Die的数量等于功能队列的数量N,所述队列映射信息表示所述N个功能队列与所述N个Die呈一一映射关系;生成模块用于根据预设的信号生成规则生成与所述基础指令对应的时序信号,发送模块用于向所述关联的Die所在的闪存介质发送所述时序信号,信号生成规则用于表示基础指令与指定引脚上输出的波形的对应关系。
上述实施例,控制器在根据预定义规则选择目标功能队列时,满足目标功能队列为非空队列和目标功能队列关联的Die所在的闪存介质为空闲状态,这样能实现不同的Die并行的执行控制器发送的基础指令,减少操作指令的执行时间;同时,基础指令对应的时序信号由预设的信号生成规则生成,这样可以通过配置与不同类型的闪存介质对应的信号生成规则,以达到匹配不同类型的闪存介质的作用,提高了控制器对闪存介质的兼容性。
在一种可能的实施方式中,所述生成模块具体用于获取所述基础指令的标识;查询与所述基础指令的标识关联的至少一种引脚电平状态信息和输出顺序信息;其中,引脚电平状态信息表示一个时钟周期内指定引脚上的电平状态,电平状态包括高电平或低电平,所述输出顺序信息表示所述至少一种引脚电平状态信息的输出顺序;根据所述至少一种引脚电平状态信息和所述输出顺序信息生成所述时序信号;发送模块通过所述指定引脚向所述关联的Die所在的闪存介质发送所述时序信号,指定引脚可以是控制器的用于传输控制信号的控制引脚,不包括用于传输数据的数据引脚和用于传输地址信息的地址引脚。
上述实施例,将操作指令拆分为多个基础指令,将拆分后的基础指令根据访问地址放入对应的功能队列,以便不同操作指令对应的基础指令交替执行,提高闪存介质的Die的并发性,减少执行时间。
在一种可能的实施方式中,所述生成模块具体用于:
获取所述基础指令的标识;不同类型的基础指令具有不同的标识,该标识可以携带在基础指令中的指定字段中;根据预设的信号生成规则查询与所述基础指令的标识关联的时钟周期数量信息和电平状态信息;其中,所述时钟周期数量信息表示待输出的时钟周期的数量,电平状态信息表示待输出的时钟周期中每个时钟周期在指定引脚上的电平状态;根据所述时钟周期数量信息和所述电平状态信息生成所述时序信号;发送模块通过所述指定引脚向所述关联的 Die所在的闪存介质发送所述时序信号。
上述实施例,通过多个不同种类的引脚电平状态信息和输出顺序信息来表示时序信号的生成规则,不需要存储所有时钟周期对应的引脚电平状态信息避免冗余,减少存储空间的占用。
在一种可能的实施方式中,控制器还包括:接收模块、拆分模块、第二确定模块和存指令模块。
接收模块用于接收操作指令,所述操作指令携带访问地址;
拆分模块用于将所述操作指令拆分为至少两个基础指令;
第二确定模块用于从所述N个功能队列中确定与所述访问地址关联的功能队列;
存指令模块用于将所述至少两个基础指令放入所述关联的功能队列。
上述实施例,将操作指令拆分为多个基础指令,将拆分后的基础指令根据访问地址放入对应的功能队列,以便不同操作指令对应的基础指令交替执行,提高闪存介质的Die的并发性,减少执行时间。
在一种可能的实施方式中,所述第二确定模块具体用于:获取所述N个Die各自对应的地址区间;
根据所述访问地址所在的地址区间确定目标Die,以及根据所述队列映射信息确定与所述目标Die关联的功能队列,目标Die为N个Die中的一个。
上述实施例,控制器根据操作指令中携带的访问地址所在的地址区间确定目标Die,再根据Die与功能队列的映射关系确定目标Die关联的功能队列,便于操作指令拆分后得到的基础指令准确的进入指定的功能队列,提高基础指令入队的效率。
结合第二方面至第二方面的第四种可能的实施方式中的任意一种,在第五种可能的实现方式中,所述选队列模块用于:
根据优先级降序的方式每次从所述N个功能队列中选择一个非空且关联的Die为空闲状态的功能队列作为所述目标功能队列;或
随机方式每次从所述N个功能队列中选择一个非空且关联的Die为空闲状态的功能队列作为所述目标功能队列;或
根据队列ID升序或队列ID降序的方式每次从所述N个功能队列中选择一个非空且关联的Die为空闲状态的功能队列作为所述目标功能队列。
上述实施例,通过上述的目标功能队列的选择方法,能有效的避免相邻两次选择的目标功能队列相同造成控制器持续在一个功能队列中取指令,从而能减少控制器的等待时间,提供Die的并发性,提高基础指令执行的效率。
本申请第三方面提供了一种控制器,其特征在于,包括:
一个或多个处理器、存储器、总线系统以及一个或多个程序,处理器、存储器通过总线系统相连;
其中一个或多个程序被存储在存储器中,一个或多个程序包括指令,指令当被终端执行时使控制器执行如第一方面至第一方面的第五种可能的实施方式中任意一项所述的方法。
本申请第四方面提供了一种存储一个或多个程序的计算机可读存储介质,一个或多个程序包括指令,指令当控制器执行时使所述控制器执行如第一方面至第一方面的第五种可能的实施方式中任意一项所述的方法。
附图说明
为了更清楚地说明本发明实施例中的技术方案,下面将对实施例中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1是本发明实施例提供的一种闪存介质的访问方法的流程示意图;
图2是本发明实施例提供的又一种闪存介质的访问方法的流程示意图;
图3是本发明实施例提供的操作指令的拆分方法的原理示意图;
图4是本发明实施例提供的时序信号生成方法的原理示意图;
图5是本发明实施例提供的又一种时序信号生成方法的原理示意图;
图6a是本发明实施例提供的一种控制器的结构示意图;
图6b是本发明实施例提供的又一种控制器的结构示意图;
图7是本发明实施例提供的一种系统的结构示意图;
图8是本发明实施例提供的又一种控制器的结构示意图。
具体实施方式
需要说明的是,在本发明实施例中使用的术语是出于描述特定实施例的目的,而非旨在限制本发明。在本发明实施例和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式,除非上下文清楚地表示其他含义。还应当理解,本文中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能组合。另外,本发明的说明书和权利要求书及上述附图中的术语“第一”、“第二”、“第三”和“第四”等是用于区别不同对象,而不是用于描述特定顺序。此外,术语“包括”和“具有”以及它们任何变形,意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元,而是可选地还包括没有列出的步骤或单元,或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。
请参见图1,图1是本发明实施例提供的一种闪存介质的方法方法的流程示意图,该方法包括但不限于如下步骤。
S101、控制器从N个功能队列中选择一个目标功能队列。
具体的,N个功能队列可预先存放在控制器的内部的存储器中,例如:控制器内存的寄存器或缓存中,控制器连接有至少一个闪存介质,至少一个闪存介质中每个闪存介质包括至少一个Die,控制器连接的Die的数量等于功能队列的数量N个,N个队列中每个队列唯一关联一个Die,其中可以预先存储表示N个队列和N个Die的一一映射关系的队列映射信息。在一种可能的实施方式中,控制器在选择目标功能队列时,可以首先从N个队列中筛选出非空功能队列,接下来控制器获取剩下的功能队列中每个功能队列关联的Die所在的闪存介质的状态,移除Die所在的闪存介质的状态为忙碌状态的功能队列,即最后剩下的功能队列满足两个条件:非空队列以及关联的Die所在的闪存介质的状态为空闲状态,控制器从满足上述两个条件的功能队列中根据预定义规则选取一个功能队列作为当前的目标功能队列。其中,N个功能队列中每个功能队列可以为先进先出队列。
举例说明,控制器连接有4个闪存介质,每个闪存介质包括2个Die,则 4个闪存介质包括8个Die。8个Die分别为Die0、Die1、Die2、Die3、Die4、Die5、Die6和Die7。控制器中预先设置有8个功能队列,8个功能队列分别为功能队列0、功能队列1、功能队列2、功能队列3、功能队列4、功能队列5、功能队列6和功能队列7。8个功能队列和8个Die呈一一映射关系,每个功能队列对应唯一的1个Die。功能队列0关联Die0、功能队列1关联Die1、…、功能队列7关联Die7。控制器选取目标功能队列的过程可以是:控制器从8个功能队列中筛选出非空队列,假设筛选出的非空队列为功能队列1、功能队列2、功能队列3、功能队列5、功能队列6,控制器接下来获取上述5个队列各自关联的Die所在的闪存介质的状态,假设Die1的闪存介质的状态为空闲状态、Die2所在的闪存介质的状态为空闲状态,Die3所在的闪存介质的状态为忙碌状态、Die4所在的闪存介质的状态为忙碌状态、Die5所在的闪存介质的状态为忙碌状态,则控制器最后筛选出的功能队列为功能队列1和功能队列2,控制器从上述两个队列中根据预定义规则选取1个功能队列作为目标功能队列。
在本发明的一种可能的实现方式中,控制器可维护一个记录表,记录表的存储位置可以是控制器的内部的寄存器或缓存中,记录表可以位于控制器的外部且独立与控制器的存储器中,控制器和存储器位于存储设备的内部。记录表包括多个用于记录功能队列当前存放的基础指令的数量的表项,当某个功能队列中基础指令的数量发生更新(例如:出队操作或入队操作),控制器更新记录表中该功能队列对应的表项。这样控制器在选择目标功能队列之前,可根据记录表排除空的功能队列,选择一个非空的功能队列作为目标功能队列。
S102、所述控制器从所述目标功能队列中取出一个基础指令。
具体的,目标队列可以为先进先出队列,控制器可从目标功能队列的队首取出一个基础指令。控制器检测到目标功能队列中的基础指令发生出队操作后,更新记录表中目标功能队列的表项,将表项存储的表示目标功能队列中基础指令的数值减1。
S103、控制器根据预设的队列映射信息确定与所述目标功能队列关联的 Die。
S104、控制器根据预设的信号生成规则生成与基础指令对应的时序信号,以及向关联的Die所在的闪存介质发送时序信号。
具体的,信号生成规则表示基础指令与时序信号生成规则之间的映射关系,时序信号生成规则表示控制器的指定引脚上输出的波形的规则,控制器根据预设的信号生成规则生成与基础指令对应的时序信号,控制器根据闪存介质与Die之间的对应关系,确定关联的的Die所在的闪存介质,控制器向闪存介质发送时序信号,如果基础指令的类型为读操作,闪存介质根据地址引脚上的电平信号获取待读取的存储单元的位置,闪存介质在控制引脚上的电平信号的控制下,将存储单元中的数据通过数据引脚发送给Nand Flash控制器;如果基础指令的类型为写操作,闪存介质根据地址引脚上的电平状态获取待写入的存储单元的位置,介质控制在控制引脚上输入的电平信号的控制下,将数据引脚上待写入的数据写入到该存储单元中。
下面就一个具体的实施例对存储介质的方法进行说明:控制器连接有一个闪存介质,该闪存介质包括三个Die,分别为Die0、Die1和Die2。控制器内部设置有两个功能队列,分别为功能队列0、功能队列1和功能队列2,功能队列0与Die0映射,功能队列1与Die1映射,功能队列2与Die2映射。
功能队列0中当前存放有3个基础指令:基础指令00、基础指令01和基础指令02,上述3个基础指令由控制器对接收到的第一操作指令拆分得到的;功能队列1中当前存放有3个基础指令:基础指令10、基础指令11和基础指令12,上述3个基础指令由控制器对接收到的第二操作指令拆分得到的;功能队列2中当前存放有3个基础指令:基础指令20、基础指令21和基础指令22,上述3个基础指令由控制器对接收到的第三操作指令拆分得到的。控制器首次发送基础指令时,所有的Die所在的闪存介质都为空闲状态,控制器选取任意1个功能队列作为目标功能队列,假设首先选取功能队列0为目标功能队列,从功能队列0中取出基础指令00,将基础指令00发送给关联的Die0,此处Die0为忙碌状态;然后,控制器再次选取目标功能队列,目标功能队列满 足非空队列和关联的Die所在的闪存介质为空闲状态,此时满足条件的功能队列为功能队列1和功能队列2,控制器从上述两个功能队列中选取任意1个作为目标功能队列,假设选取功能队列1作为目标功能队列,控制器从功能队列1中选取队首的基础指令发送给关联的Die1;接下来,控制器再次选取目标功能队列,由于Die0可能此时已经执行完基础指令00,处于空闲状态,那么此时满足条件的功能队列可能为功能队列0和功能队列2,控制器从上述两个队列中任意选取一个作为目标功能队列,假设为功能队列2,控制器将功能队列2中队首的基础指令发送给关联的Die2。这样控制器在一个Die执行指令的过程中可以将下一条指令发送给另一个Die,不需要等到一个Die上的指令执行完毕后再发送下一个指令,多个Die之间可以并行的执行指令,提高操作指令的执行效率。
上述实施例,控制器在根据预定义规则选择目标功能队列满足非空队列且关联的Die所在的闪存介质为空闲状态,由于每个功能队列对应不同的Die,这样能实现不同的Die并行的执行控制器发送的基础指令,提高操作指令的执行效率。同时,基础指令对应的时序信号的波形由预设的信号生成规则生成,这样可以通过配置与不同类型的闪存介质对应的信号生成规则,以达到匹配不同类型的闪存介质的作用,提高了控制器对闪存介质的兼容性。
请参见图2,图2是本发明实施例提供的一种闪存介质的方法方法的流程示意图,该方法包括但不限于如下步骤:
S201、配置设备进行预先配置。
具体的,配置设备预先为控制器进行相关的配置,使控制器兼容连接的闪存介质,其中配置设备可以是计算机、测试主机、工作站或服务器等,配置设备根据存储介质的类型完成配置后可生成配置文件,配置设备可以通过烧录器将配置文件烧录到高速存储器中,高速存储器可以是闪存芯片中的可读存储器。配置设备确定控制器需要连接的闪存介质的数量M,M个闪存介质中每个闪存介质包括至少一个Die,配置设备确定M个闪存介质包括的Die的数量为N, M和N为大于0的整数,例如:M个闪存介质可以为相同类型的闪存介质,相同类型表示闪存介质具有相同的引脚和时序信号格式。配置设备需要预先配置的信息包括但不限于:
1、配置设备根据M个闪存介质包括的Die的数量N配置功能队列的数量为N;
2、配置设备获取M个闪存介质与N个Die的映射关系,生成闪存映射信息;
3、配置设备配置N个功能队列和N个Die的一一映射关系,生成队列映射信息;
4、配置设备为所有的操作指令中每个操作指令配置拆分规则,拆分规则可以表示为操作指令的标识和基础指令的标识之间的对应关系,配置设备为预先为每种类型的基础指令分配一个标识,且为每种类型的操作指令分配一个标识;
5、配置设备配置每种类型的基础指令对应的时序信号的信号生成规则。其中,配置信号生成规则包括:配置设备,设置基础指令的标识配置设备将基础指令的标识与时钟周期数量信息和电平状态信息存储为信号生成规则;或配置设置基础指令的标识,将基础指令的标识与划分的至少一种引脚电平状态信息和输出顺序信息进行绑定后生成信号生成规则。
配置设备将包括1-5配置信息的配置文件写入到存储器中,存储器可以为控制器内部的寄存器或缓存,存储器可以独立于控制器,控制器和存储器位于存储设备的内部。
举例说明:控制器连接有2个闪存介质,每个闪存介质包括2个Die,控制器连接的Die的总数量为4,配置设备配置的闪存介质与Die的映射关系如下:
Figure PCTCN2016097718-appb-000001
表1
配置设备根据Die的数量配置功能队列的数量为4,外部设备配置的队列映射信息如表2所示:
功能队列0 Die0
功能队列1 Die1
功能队列2 Die2
功能队列3 Die3
表2
需要说明的是,上述举例仅为示例性的说明,控制器连接的闪存介质的数量、闪存介质包括的Die的数量、闪存介质与Die的映射关系以及功能队列与Die的映射关系并不限于此,可以根据需要进行配置。
S202、控制器接收操作指令。
具体的,操作指令可以由上层设备发出,上层设备可以是SSD控制器,操作指令携带访问地址。读操作和写操作均以页为单位,读操作可以随机读取任意位置的页,写操作只能按照页顺序写入。
S203、控制器将操作指令拆分为至少两个基础指令。
具体的,控制器可预先存储的操作指令的标识与基础指令的标识之间的映射关系,控制器在接收到一个操作指令后,可以根据映射关系查询与操作指令的标识关联的多个基础指令各自对应的标识,将接收到的操作指令拆分为多个基础指令,基础指令中携带基础指令的格式可以为消息,控制器将操作指令拆分为多个基础指令,且在基础指令中增加根据映射关系查询到的标识。
例如,参见图3,读操作指令为读页指令,控制器根据预设的映射关系将读页指令拆分为3个基础指令,基础指令1:发送读命令、基础指令2:检查 状态寄存器、基础指令3:传输数据。
S204、控制器从N个功能队列中确定与访问地址关联的功能队列。
具体的,控制器连接的N个Die分别分配有一个地址区间,由于N个功能队列和N个Die为一一映射关系,因此每个功能队列对应一个地址区间,控制器确定操作指令中携带的访问地址位于N个地址区间中的哪个地址区间,由此控制器可以从N个功能队列中确定与访问地址关联的功能队列。
举例说明,Die0的地址区间为[a,b],Die0关联功能队列1;Die1的地址区间为[c,d],Die1关联功能队列1;Die2的地址区间为[e,f],Die2关联功能队列2;Die3的地址区间为[g,h],Die3关联功能队列3。假设操作指令中携带的访问地址位于地址区间[a,b],则控制器确定关联的功能队列为功能队列0。
S205、控制器将至少两个基础指令放入关联的功能队列。
具体的,控制器将S203拆分后的至少两个基础指令可以根据先进先出的顺序依次放入关联的功能队列的队列尾。
在一种可能的实施方式中,控制器可维护一个记录表,记录表中存储表示各个功能队列中当前存放的基础指令的数量的表项,控制器检测到N个功能队列中某个功能队列中的基础指令的数量发生更新时,控制器在记录表中更新该功能队列的表项。
S206、控制器根据优先级降序的方式每次从N个功能队列中选择一个非空的功能队列作为目标功能队列。
具体的,N个功能队列预先配置有优先级,控制器每次从N个队列中选择一个非空的功能队列作为目标功能队列。
举例说明:控制器根据优先级从高到低的顺序从N个功能队列中选择目标功能队列。假设功能队列0的优先级为4,功能队列1的优先级为2,功能队列2的优先级为1,功能队列3的优先级为3,4个功能队列关联的Die均为空闲状态,根据预设的选择规则,控制器第1次选择功能队列0作为目标功能队列,第2次选择功能队列3作为目标功能队列,第3次选择功能队列1作为目标功能队列,第4次选择功能队列2作为目标功能队列。
可选的,在本发明的一种可能的实施方式中,控制器选择目标功能队列的方法为:控制器随机方式每次从N个功能队列中选择一个非空且关联的Die为空闲状态的功能队列作为所述目标功能队列。
可选的,在本发明的一种可能的实施方式中,控制器选择目标功能队列的方法为:控制器根据队列ID升序或队列ID降序的方式每次从所述N个功能队列中选择一个非空且关联的Die为空闲状态的功能队列作为所述目标功能队列。
S207、控制器从目标功能队列中取出一个基础指令。
具体的,控制器从目标功能队列的队列头取出一个基础指令,该基础指令后面基础指令成为新的队列头。目标功能队列中存放的基础指令的数量发生变动,控制器更新记录表中该目标功能队列的表项。
S208、控制器根据预设的队列映射信息确定与目标功能队列关联的Die。
S209、控制器获取基础指令的标识。
具体的,根据S203中添加的基础指令的标识,控制器可以在指定字段中获取指令的标识,不同类型的基础指令对应不同的标识。
S210、控制器根据预设的信号生成规则查询与基础指令的标识关联的时钟周期数量信息和电平状态信息。
具体的,时钟周期数量信息表示待输出的时钟周期的数量,不同类型的基础指令对应的时钟周期的数量可以相等,也可以不相等。电平状态信息表示每个待输出的时钟周期内指定引脚上的电平状态,电平状态的数量与待输出的时钟周期的数量相等。
S211、控制器根据时钟周期数量信息和电平状态信息生成时序信号。
具体的,每到来一个时钟周期时,控制器根据电平状态信息在指定引脚上输出与该时钟周期对应的电平状态,直到在所有的时钟周期内在指定引脚上输出电平状态。
举例说明,参见图4,图4为某个基础指令对应的时序信号的波形图,该基础指令的时钟周期数量信息和电平状态信息如表3所示,C0-C15表示时钟 周期的序号,该基础指令的时序信号持续16个时钟周期,I0-I15表示每个时钟周期对应的指定引脚上的电平状态,指定引脚为:CE#引脚、CLE引脚、ALE引脚和WE#引脚,每个引脚上的电平状态可以为高电平或低电平,也可以为上升沿或下降沿。在一种可能的实施方式中,闪存介质的引脚及其功能如下:
1.CLK:时钟引脚,用于输出时钟周期;
2.CLE(Command Latch Enable,命令锁存使能),在输入命令之前,要先在模式寄存器中,设置CLE使能;
3.ALE(Address Latch Enable,地址锁存使能),在输入地址之前,要先在模式寄存器中,设置ALE使能;
4.CE#(Chip Enable,芯片使能),在操作Nand Flash之前,要先选中此芯片,才能操作;
5.RE#(Read Enable,读使能),在读取数据之前,要先使CE#有效;
6.WE#(Write Enable,写使能),在写取数据之前,要先使WE#有效;
7.WP#(Write Protect,写保护);
8.R/B#(Ready/Busy Output,就绪/忙),主要用于在发送完编程/擦除命令后,检测这些操作是否完成,忙,表示编程/擦除操作仍在进行中,就绪表示操作完成;
9.Vcc(Power,电源);
10.Vss(Ground,接地);
11.NC(Non-Connection,未连接)。
图4中,控制器根据基础指令查询到的时钟周期数量信息为16,控制器执行基础指令需要输出16个时钟周期C0-C15,电平状态信息为I0-I15,控制器在输出时钟周期C0时,查询到I0表示的指定引脚上的电平状态为:CE#引脚输出低电平,CLE引脚输出低电平,ALE引脚输出低电平,WE#引脚输出高电平,DQ引脚输出高电平;控制器在输出时钟周期C1时,查询到I1表示的指定引脚上的电平状态为:CE#引脚输出低电平,CLE引脚输出高电平, ALE引脚输出低电平,WE#引脚输出低电平。控制器根据上述方式在指定引脚上输出时序信号,直到全部的时钟周期结束。
时钟周期 电平状态
C0 I0
C1 I1
C2 I2
C3 I3
C4 I4
C5 I5
C6 I6
C7 I7
C8 I8
C9 I9
C10 I10
C11 I11
C12 I12
C13 I13
C14 I14
C15 I15
表3
控制器在每到来一个时钟周期时,根据时钟周期的序号查询关联的电平状态,根据电平状态在指定引脚上输出对应的高电平或低电平。
S212、控制器通过指定引脚向关联的Die所在的闪存介质发送时序信号。
具体的,控制器可以根据预先存储的闪存映射信息查询关联的Die所在的闪存介质,控制器通过指定引脚向闪存介质发送时序信号。
在本发明的一种可能的实施方式中,控制器根据预设的信号生成规则生成与基础指令对应的时序信号,以及向关联的Die所在的闪存介质发送时序信号 包括:控制器获取基础指令的标识;控制器查询与基础指令的标识关联的至少一种引脚电平状态信息和输出顺序信息;其中,引脚电平状态信息表示一个时钟周期内指定引脚上的电平状态,输出顺序信息表示至少一个引脚电平状态信息的排列顺序;控制器根据至少一种引脚电平状态信息和输出顺序信息生成时序信号;控制器通过指定引脚向关联的Die所在的闪存介质发送时序信号。
具体的,引脚电平状态信息表示一个时钟周期内指定引脚上输出的电平状态,输出顺序信息表示至少一种引脚电平状态信息的排列顺序。
举例说明,参见图5所示,控制器查询到基础指令关联的引脚电平状态信息为I0-I7,共8个引脚电平状态信息,根据查询到的输出顺序信息得到I0-I7的排列顺序为I0、I1、I2、I3、I4、I3、I4、I3、I4、I3、I4、、I5、I6、I7,其中,I3、I4在I2后重复4次,控制器在输出时钟周期C0时,查询到I0表示的指定引脚上的电平状态为:CE#引脚输出低电平,CLE引脚输出低电平,ALE引脚输出低电平,WE#引脚输出高电平,DQ引脚输出高电平,后续时序信号的输出方法不再赘述。在本实施例中,对于多次重复的引脚电平状态信息可通过输出顺序来表示,不需要存储多组相同的引脚电平状态信息,减少信息的冗余,节省存储空间。
上述实施例,控制器在选择目标功能队列时,满足目标功能队列为非空队列且目标功能队列关联的Die所在的闪存介质为空闲状态,这样能实现不同的Die并行的执行控制器发送的基础指令,减少操作指令的执行时间;同时,基础指令对应的时序信号由预设的信号生成规则生成,这样可以通过配置与不同类型的闪存介质对应的信号生成规则,以达到匹配不同类型的闪存介质的作用,提高了控制器对闪存介质的兼容性。
上述详细阐述了本发明实施例的方法,为了便于更好地实施本发明实施例的上述方案,相应地,下面提供了本发明实施例的装置。
请参见图6a,图6a是本发明实施例提供的一种控制器的结构示意图,该控制器6可以包括选队列模块601、取指令模块602、第一确定模块603、生成模块604和发送模块605,其中,各个模块的详细描述如下。
选队列模块601,用于从N个功能队列中选择一个目标功能队列;其中,所述目标功能队列为非空队列,且与所述目标功能队列关联的Die所在的闪存介质为空闲状态,N为大于1的整数。
取指令模块602,用于从所述目标功能队列中取出一个基础指令。
第一确定模块603,用于根据预设的队列映射信息确定与所述目标功能队列关联的Die;其中,所述控制器连接至少一个闪存介质,所述至少一个闪存介质中每个闪存介质包括至少一个Die,所述控制器连接的Die的数量等于N,所述队列映射信息表示所述N个功能队列与N个Die之间的映射关系。
生成模块604,用于根据预设的信号生成规则生成与所述基础指令对应的时序信号;
发送模块605,用于向所述关联的Die所在的闪存介质发送所述时序信号。
上述实施例,控制器在选择目标功能队列时,满足目标功能队列为非空队列且目标功能队列关联的Die所在的闪存介质为空闲状态,这样能实现不同的Die并行的执行控制器发送的基础指令,减少操作指令的执行时间;同时,基础指令对应的时序信号由预设的信号生成规则生成,这样可以通过配置与不同类型的闪存介质对应的信号生成规则,以达到匹配不同类型的闪存介质的作用,提高了控制器对闪存介质的兼容性。
需要说明的是,在本发明实施例中,各个模块的具体实现还可以对应参照图1所示的方法实施例的相应描述。
请参见图6b,图6b是本发明实施例提供的又一种控制器的结构示意图,该控制器除包括选队列模块601、取指令模块602、第一确定模块603、生成模块604和发送模块605,还可以包括接收模块606、拆分模块607、第二确定模块608和存指令模块609,其中,各个单元的详细描述如下。
接收模块606,用于接收操作指令;其中,所述操作指令携带访问地址。
拆分模块607,用于将所述操作指令拆分为至少两个基础指令。
第二确定模块608,用于从所述N个功能队列中确定与所述访问地址关联 的功能队列。
存指令模块609,用于将所述至少两个基础指令放入所述关联的功能队列。
可选的,生成模块605具体用于:
获取所述基础指令的标识;
查询与所述基础指令的标识关联的至少一种引脚电平状态信息和输出顺序信息;其中,引脚电平状态信息表示一个时钟周期内指定引脚上的电平状态,所述输出顺序信息表示所述至少一种引脚电平状态信息的输出顺序;
根据所述至少一种引脚电平状态信息和所述输出顺序信息生成所述时序信号。
可选的,生成模块605具体用于:
获取所述基础指令的标识;
根据预设的信号生成规则查询与所述基础指令的标识关联的时钟周期数量信息和电平状态信息;其中,所述时钟周期数量信息表示待输出的时钟周期的数量,电平状态信息表示待输出的时钟周期中每个时钟周期在指定引脚上的电平状态;
根据所述时钟周期数量信息和所述电平状态信息生成所述时序信号。
可选的,第二确定模块608具体用于:
根据所述访问地址所在的地址区间确定目标Die,以及根据所述队列映射信息确定与所述目标Die关联的功能队列,所述目标Die为所述控制连接的N个Die中的1个,所述N个Die中每个Die对应一个地址区间。
可选的,选队列模块601具体用于:
根据优先级降序的方式每次从所述N个功能队列中选择一个非空的功能队列作为所述目标功能队列;或
随机方式每次从所述N个功能队列中选择一个非空的功能队列作为所述目标功能队列;或
根据队列ID升序或队列ID降序的方式每次从所述N个功能队列中选择一个非空的功能队列作为所述目标功能队列。
需要说明的是,在本发明实施例中,各个单元的具体实现还可以对应参照图2所示的方法实施例的相应描述。
其中,控制器6可以通过专用集成电路(英文:Application-Specific Integrated Circuit,缩写:ASIC)实现,或可编程逻辑器件(英文:Programmable Logic Device,缩写:PLD)实现。上述PLD可以是复杂可编程逻辑器件(英文:Complex Programmable Logic Device,缩写:CPLD),FPGA,通用阵列逻辑(英文:Generic Array Logic,缩写:GAL)或其任意组合。该控制器6用于实现图1所示的闪存介质的访问方法。通过软件实现图1所示的闪存介质的访问方法时,控制器6及其各个模块也可以为软件模块,例如实现Nand Flash控制器的软件模块。
上述实施例,控制器在根据预定义规则选择目标功能队列时,满足目标功能队列为非空队列且目标功能队列关联的Die所在的闪存介质为空闲状态且,这样能实现不同的Die并行的执行控制器发送的基础指令,减少操作指令的执行时间;同时,基础指令对应的时序信号由预设的信号生成规则生成,这样可以通过配置与不同类型的闪存介质对应的信号生成规则,以达到匹配不同类型的闪存介质的作用,提高了控制器对闪存介质的兼容性。
上述详细阐述了本发明实施例的方法和装置,为了便于更好地实施本发明实施例的上述方案,相应地,下面提供了本发明实施例的系统。
该系统包括配置设备8和存储设备7,存储设备7包括控制器700和k个闪存介质701~70k,k为大于0的整数,k个闪存介质中每个闪存介质包括至少一个Die。
在上述的系统中,配置设备8用于配置队列映射信息和信号生成规则,以及将队列映射信息和信号生成规则发送给控制器700,其中,上述配置信息可以存储在控制器700的寄存器组或缓存中。控制器700用于每次从N个功能队列中选择一个目标功能队列;其中,目标功能队列为非空队列且目标功能队列对应的Die所在的闪存介质为空闲状态,N为大于1的整数;控制器700从所述目标功能队列中取出一个基础指令;控制器700根据预设的队列映射信息 确定与所述目标功能队列关联的Die,所述队列映射信息表示所述N个功能队列与所述N个Die呈一一映射关系;控制器700根据预设的信号生成规则生成与所述基础指令对应的时序信号,以及向所述关联的Die所在的闪存介质发送所述时序信号;所述关联的Die所在的闪存介质为k闪存介质中的一个闪存介质;所述关联的Die所在的闪存介质用于接收所述时序信号,执行相应的操作。
上述实施例,控制器在选择目标功能队列时,满足目标功能队列为非空队列且目标功能队列关联的Die所在的闪存介质为空闲状态,这样能实现不同的Die并行的执行控制器发送的基础指令,减少操作指令的执行时间;同时,基础指令对应的时序信号由预设的信号生成规则生成,这样可以通过配置与不同类型的闪存介质对应的信号生成规则,以达到匹配不同类型的闪存介质的作用,提高了控制器对闪存介质的兼容性。
参见图8,为本发明实施例提供的一种控制器的结构示意图,在本发明实施例中,控制器800包括处理器801、存储器802和通信接口803。通信接口803用于与至少一个闪存介质连接,每个闪存介质包括至少一个Die;当闪存介质的数量超过1个时,控制器800可利用通信接口803以并联方式与多个闪存介质进行连接;其中,通信接口可以是ONFI或toggle接口。例如:图8中以控制器800连接两个闪存介质:闪存介质804和805,具体实施例控制器800连接的闪存介质的数量以及闪存介质包括的Die的数量并不限于此。控制器800中的处理器801的数量可以是一个或多个。本发明的一些实施例中,处理器801、存储器802和通信接口803可通过总线系统或其他方式连接,处理器801、存储器802和通信接口803之间可通过有线方式连接,也可以通过无线传输等其他手段实现通信。控制器800可以用于执行图1所示的方法。关于本实施例涉及的术语的含义以及举例,可以参考图1对应的实施例,此处不再赘述。
其中,存储器802中存储程序代码。处理器801用于调用存储器802中存储的程序代码,用于执行以下操作:
从N个功能队列中选择一个目标功能队列;其中,所述目标功能队列为非空队列,且与所述目标功能队列关联的Die所在的闪存介质为空闲状态,N为大于1的整数;
从所述目标功能队列中取出一个基础指令;
根据预设的队列映射信息确定与所述目标功能队列关联的Die;其中,所述控制器连接至少一个闪存介质,所述至少一个闪存介质中每个闪存介质包括至少一个Die,所述控制器连接的Die的数量等于N,所述队列映射信息表示所述N个功能队列与N个Die之间的映射关系;
根据预设的信号生成规则生成与所述基础指令对应的时序信号;
向所述关联的Die所在的闪存介质发送所述时序信号。
可选的,处理器801执行所述根据预设的信号生成规则生成与所述基础指令对应的时序信号包括:
获取所述基础指令的标识;
查询与所述基础指令的标识关联的至少一种引脚电平状态信息和输出顺序信息;其中,引脚电平状态信息表示一个时钟周期内指定引脚上的电平状态,所述输出顺序信息表示所述至少一种引脚电平状态信息的输出顺序;
根据所述至少一种引脚电平状态信息和所述输出顺序信息生成所述时序信号。
可选的,处理器801执行所述根据预设的信号生成规则生成与所述基础指令对应的时序信号包括:
获取所述基础指令的标识;
根据预设的信号生成规则查询与所述基础指令的标识关联的时钟周期数量信息和电平状态信息;其中,所述时钟周期数量信息表示待输出的时钟周期的数量,电平状态信息表示待输出的时钟周期中每个时钟周期在指定引脚上的电平状态;
根据所述时钟周期数量信息和所述电平状态信息生成所述时序信号。
可选的,处理器701还用于执行;
接收操作指令;其中,所述操作指令携带访问地址;
将所述操作指令拆分为至少两个基础指令;
从所述N个功能队列中确定与所述访问地址关联的功能队列;
将所述至少两个基础指令放入所述关联的功能队列。
可选的,处理器701执行所述确定所述N个功能队列中与所述访问地址关联的功能队列包括:
根据所述访问地址所在的地址区间确定目标Die,以及根据所述队列映射信息确定与所述目标Die关联的功能队列,所述目标die为所述控制连接的N个Die中的一个,所述N个Die中每个Die对应一个地址区间。
可选的,处理器701执行所述每次从N个功能队列中按照预定义规则选择一个目标功能队列包括:
根据优先级降序的方式每次从所述N个功能队列中选择一个非空的功能队列作为所述目标功能队列;或
随机方式每次从所述N个功能队列中选择一个非空的功能队列作为所述目标功能队列;或
根据队列ID升序或队列ID降序的方式每次从所述N个功能队列中选择一个非空的功能队列作为所述目标功能队列。
综上所述,通过实施本发明实施例,控制器在选择目标功能队列时满足非空队列和目标队列关联的Die所在的闪存介质为空闲状态,能实现不同的Die并行的执行控制器发送的基础指令,提高操作指令的执行效率。同时,基础指令对应的时序信号的波形由预设的信号生成规则生成,这样可以通过配置与不同类型的闪存介质对应的信号生成规则,以达到匹配不同类型的闪存介质的作用,提高了控制器对闪存介质的兼容性。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程,是可以通过计算机程序来指令相关的硬件来完成,所述的程序可存储于计算机可读取存储介质中,该程序在执行时,可包括如上述各方法的实施例的流程。而前述的存储介质包括:ROM、RAM、磁碟或者光盘等各种可以存储程序代 码的介质。
以上实施例仅揭露了本发明中较佳实施例,不能以此来限定本发明之权利范围,本领域普通技术人员可以理解实现上述实施例的全部或部分流程,并依本发明权利要求所作的等同变化,仍属于发明所涵盖的范围。

Claims (13)

  1. 一种闪存介质的访问方法,其特征在于,包括:
    控制器从N个功能队列中选择一个目标功能队列;其中,所述目标功能队列为非空队列,且与所述目标功能队列关联的Die所在的闪存介质为空闲状态,N为大于1的整数;
    所述控制器从所述目标功能队列中取出一个基础指令;
    所述控制器根据预设的队列映射信息确定与所述目标功能队列关联的Die;其中,所述控制器连接至少一个闪存介质,所述至少一个闪存介质中每个闪存介质包括至少一个Die,所述控制器连接的Die的数量等于N,所述队列映射信息表示所述N个功能队列与N个Die之间的映射关系;
    所述控制器根据预设的信号生成规则生成与所述基础指令对应的时序信号;
    所述控制器向所述关联的Die所在的闪存介质发送所述时序信号。
  2. 如权利要求1所述的方法,其特征在于,所述控制器根据预设的信号生成规则生成与所述基础指令对应的时序信号包括:
    所述控制器获取所述基础指令的标识;
    所述控制器查询与所述基础指令的标识关联的至少一种引脚电平状态信息和输出顺序信息;其中,引脚电平状态信息表示一个时钟周期内指定引脚上的电平状态,所述输出顺序信息表示所述至少一种引脚电平状态信息的输出顺序,所述指定引脚为所述控制器上的控制引脚;
    所述控制器根据所述至少一种引脚电平状态信息和所述输出顺序信息生成所述时序信号。
  3. 如权利要求1所述的方法,其特征在于,所述控制器根据预设的信号生成规则生成与所述基础指令对应的时序信号包括:
    所述控制器获取所述基础指令的标识;
    所述控制器根据预设的信号生成规则查询与所述基础指令的标识关联的时钟周期数量信息和电平状态信息;其中,所述时钟周期数量信息表示待输出 的时钟周期的数量,电平状态信息表示待输出的时钟周期中每个时钟周期在指定引脚上的电平状态;
    所述控制器根据所述时钟周期数量信息和所述电平状态信息生成所述时序信号。
  4. 如权利要求1-3任意一项所述的方法,其特征在于,还包括;
    所述控制器接收SSD固态硬盘控制器发送的操作指令;其中,所述操作指令携带访问地址;
    所述控制器将所述操作指令拆分为至少两个基础指令;
    所述控制器从所述N个功能队列中确定与所述访问地址关联的功能队列;
    所述控制器将所述至少两个基础指令放入所述关联的功能队列。
  5. 如权利要求4所述的方法,其特征在于,所述控制器确定所述N个功能队列中与所述访问地址关联的功能队列包括:
    根据所述访问地址所在的地址区间确定目标Die;其中,所述N个Die中每个Die对应一个地址区间;
    根据所述队列映射信息确定与所述目标Die关联的功能队列,其中,所述目标Die为所述控制器连接的N个Die中的一个。
  6. 如权利要求1-5任意一项所述的方法,其特征在于,所述控制器从N个功能队列中选择一个目标功能队列包括:
    所述控制器根据优先级降序的方式每次从所述N个功能队列中选择一个非空的功能队列作为所述目标功能队列;或
    所述控制器随机方式每次从所述N个功能队列中选择一个非空的功能队列作为所述目标功能队列;或
    所述控制器根据队列ID升序或队列ID降序的方式每次从所述N个功能队列中选择一个非空的功能队列作为所述目标功能队列。
  7. 一种控制器,其特征在于,包括:
    选队列模块,用于从N个功能队列中选择一个目标功能队列;其中,所述目标功能队列为非空队列,且与所述目标功能队列关联的Die所在的闪存介 质为空闲状态,N为大于1的整数;
    取指令模块,用于从所述目标功能队列中取出一个基础指令;
    第一确定模块,用于根据预设的队列映射信息确定与所述目标功能队列关联的Die;其中,所述控制器连接至少一个闪存介质,所述至少一个闪存介质包括N个Die,所述队列映射信息表示所述N个功能队列与所述N个Die之间的映射关系;
    生成模块,用于根据预设的信号生成规则生成与所述基础指令对应的时序信号;
    发送模块,用于向所述关联的Die所在的闪存介质发送所述时序信号。
  8. 如权利要求7所述的控制器,其特征在于,所述生成模块具体用于:
    获取所述基础指令的标识;
    查询与所述基础指令的标识关联的至少一种引脚电平状态信息和输出顺序信息;其中,引脚电平状态信息表示一个时钟周期内指定引脚上的电平状态,所述输出顺序信息表示所述至少一种引脚电平状态信息的输出顺序,所述指定引脚为所述控制器上的控制引脚;
    根据所述至少一种引脚电平状态信息和所述输出顺序信息生成所述时序信号。
  9. 如权利要求7所述的控制器,其特征在于,所述生成模块具体用于:
    获取所述基础指令的标识;
    根据预设的信号生成规则查询与所述基础指令的标识关联的时钟周期数量信息和电平状态信息;其中,所述时钟周期数量信息表示待输出的时钟周期的数量,电平状态信息表示待输出的时钟周期中每个时钟周期在指定引脚上的电平状态;
    根据所述时钟周期数量信息和所述电平状态信息生成所述时序信号。
  10. 如权利要求7-9任意一项所述的控制器,其特征在于,所述的控制器还包括:
    接收模块,用于接收操作指令;其中,所述操作指令携带访问地址;
    拆分模块,用于将所述操作指令拆分为至少两个基础指令;
    第二确定模块,用于从所述N个功能队列中确定与所述访问地址关联的功能队列;
    存指令模块,用于将所述至少两个基础指令放入所述关联的功能队列。
  11. 如权利要求10所述的控制器,其特征在于,所述第二确定模块具体用于:
    根据所述访问地址所在的地址区间确定目标Die,以及根据所述队列映射信息确定与所述目标Die关联的功能队列;其中,所述目标Die为所述控制器连接的N个Die中的一个,所述N个Die中每个Die对应一个地址区间。
  12. 如权利要求7-11任意一项所述的控制器,其特征在于,所述选队列模块用于:
    根据优先级降序的方式从所述N个功能队列中选择一个非空的功能队列作为所述目标功能队列;或
    随机方式从所述N个功能队列中选择一个非空的功能队列作为所述目标功能队列;或
    根据队列ID升序或队列ID降序的方式从所述N个功能队列中选择一个非空的功能队列作为所述目标功能队列。
  13. 一种控制器,其特征在于,包括:
    一个或多个处理器、存储器、总线系统以及一个或多个程序,处理器、存储器通过总线系统相连;
    其中一个或多个程序被存储在存储器中,一个或多个程序包括指令,指令当被终端执行时使控制器执行如权利要求1至6任意一项所述的方法。
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Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109445698B (zh) * 2018-10-22 2022-04-05 深圳市硅格半导体有限公司 查询多片flash状态的方法、装置及计算机可读存储介质
CN109683823B (zh) * 2018-12-20 2022-02-11 湖南国科微电子股份有限公司 一种管理存储器多并发请求的方法及装置
CN109857342B (zh) 2019-01-16 2021-07-13 盛科网络(苏州)有限公司 一种数据读写方法及装置、交换芯片及存储介质
CN112395237B (zh) * 2019-08-19 2023-08-08 广州汽车集团股份有限公司 一种至少两个控制器之间通信的方法及其系统
WO2022104611A1 (zh) * 2020-11-18 2022-05-27 京东方科技集团股份有限公司 数据分发系统及数据分发方法
CN112817542A (zh) * 2021-02-24 2021-05-18 成都佰维存储科技有限公司 Nand指令调度方法、装置、可读存储介质及电子设备
US11915780B2 (en) * 2021-08-27 2024-02-27 Pixart Imaging Inc. Device ID setting method and electronic device applying the device ID setting method
CN116244225A (zh) * 2021-12-08 2023-06-09 华为技术有限公司 存储介质、存储元件、存储介质配置方法及数据传输方法
CN114579499B (zh) * 2022-01-20 2023-10-24 飞腾信息技术有限公司 处理器通信接口的控制方法、装置、设备及存储介质
CN115145487A (zh) * 2022-07-01 2022-10-04 英韧科技(上海)有限公司 用于存储器设备的指令传输方法、存储系统
CN116661684B (zh) * 2023-05-10 2024-02-23 珠海妙存科技有限公司 一种闪存数据的读取方法、系统、设备及介质
CN117668318B (zh) * 2023-12-29 2024-07-02 深圳市安信达存储技术有限公司 基于芯片闪存晶圆的叠加电路检索方法及装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101082891A (zh) * 2007-05-10 2007-12-05 忆正存储技术(深圳)有限公司 并行闪存控制器
CN101498994A (zh) * 2009-02-16 2009-08-05 华中科技大学 一种固态硬盘控制器
CN102236625A (zh) * 2010-04-20 2011-11-09 上海华虹集成电路有限责任公司 一种可同时进行读写操作的多通道NANDflash控制器
CN102567257A (zh) * 2011-12-26 2012-07-11 华中科技大学 一种控制多通道固态盘数据读写的方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1553327A (zh) * 2003-05-30 2004-12-08 上海华园微电子技术有限公司 测试eeprom的电路及其测试方法
US8533562B2 (en) * 2007-09-12 2013-09-10 Sandisk Technologies Inc. Data protection after possible write abort or erase abort
TWI428918B (zh) * 2009-09-29 2014-03-01 Silicon Motion Inc 記憶裝置以及記憶裝置之資料存取方法
US20130019053A1 (en) * 2011-07-14 2013-01-17 Vinay Ashok Somanache Flash controller hardware architecture for flash devices
CN104407997B (zh) * 2014-12-18 2017-09-19 中国人民解放军国防科学技术大学 带有指令动态调度功能的与非型闪存单通道同步控制器

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101082891A (zh) * 2007-05-10 2007-12-05 忆正存储技术(深圳)有限公司 并行闪存控制器
CN101498994A (zh) * 2009-02-16 2009-08-05 华中科技大学 一种固态硬盘控制器
CN102236625A (zh) * 2010-04-20 2011-11-09 上海华虹集成电路有限责任公司 一种可同时进行读写操作的多通道NANDflash控制器
CN102567257A (zh) * 2011-12-26 2012-07-11 华中科技大学 一种控制多通道固态盘数据读写的方法

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