WO2017220133A1

WO2017220133A1 - Snubber circuit operable with a power converter

Info

Publication number: WO2017220133A1
Application number: PCT/EP2016/064327
Authority: WO
Inventors: Magnus Karlsson; Mikael Appelberg; Jonas Malmberg; Fredrik Wahledow
Original assignee: Telefonaktiebolaget Lm Ericsson (Publ)
Priority date: 2016-06-21
Filing date: 2016-06-21
Publication date: 2017-12-28

Abstract

A snubber circuit operable with a power converter. The power converter includes a controller configured to provide a control signal to control a conductivity of a power switch of the power converter. In an embodiment, the snubber circuit includes a snubber capacitor coupled to the power switch and an active snubber switch coupled to the snubber capacitor. The snubber circuit is configured to receive an offset control signal from the controller to offset a timing of a conductivity of the active snubber switch with respect to the power switch.

Description

SNUBBER CIRCUIT OPERABLE WITH A POWER CONVERTER

TECHNICAL FIELD

The present invention is directed, in general, to the field of power electronics and, more specifically, to a snubber circuit operable with a power converter.

BACKGROUND

A switched-mode power converter is a type of power converter having a diverse range of applications by virtue of its small size, weight and high efficiency. For example, switched-mode power converters are widely used in personal computers and portable electronic devices such as cellphones. A switching device (e.g. , a metal-oxide semiconductor field-effect transistor ("MOSFET")) of a power train of the switched- mode power converter is controlled to convert an input voltage to a desired output voltage. A frequency (also referred to as a "switching frequency") and duty cycle of the switching device is adjusted using a feedback signal to convert the input voltage to the desired output voltage.

Passive snubber circuits are widely used to dampen voltage and current ringing induced by switching of the switching devices in the switched-mode power converters. A problem with conventional snubber circuits is a high power dissipation associated with the resistive circuit elements employed to facilitate attenuation of the ringing. A further problem is inherent delays in diodes that are employed in the design of the passive snubber circuits. Such delays can leave residual voltage spikes that can unnecessarily stress components in the power converter.

It is highly desirable, therefore, to develop a snubber circuit to attenuate the voltage and current ringing associated with the switching devices in switch-mode power converters that reduce the power dissipation and unnecessary delays. A snubber circuit that addresses the aforementioned limitations may enhance a power conversion efficiency of the switch-mode power converters. SUMMARY

These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by advantageous embodiments of the present invention for a snubber circuit operable with a power converter. The power converter includes a controller configured to provide a control signal to control a conductivity of a power switch of the power converter. In an embodiment, the snubber circuit includes a snubber capacitor coupled to the power switch and an active snubber switch coupled to the snubber capacitor. The snubber circuit is configured to receive an offset control signal from the controller to offset a timing of a conductivity of the active snubber switch with respect to the power switch.

The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter, which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIGURES 1 and 2 illustrate schematic diagrams of embodiments of power converters;

FIGURES 3 to 6 illustrate schematic diagrams of embodiments of a snubber circuit;

FIGURES 7 and 8 illustrate timing diagrams demonstrating an operation of a power converter; and

FIGURE 9 illustrates a flow diagram of an embodiment of a method of operating a power converter. Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated, and may not be redescribed in the interest of brevity after the first instance. The FIGURES are drawn to illustrate the relevant aspects of exemplary embodiments.

DETAILED DESCRIPTION

The making and using of the present exemplary embodiments are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the systems, subsystems, and modules associated with a snubber circuit operable with a power converter.

A system will be described herein with respect to exemplary embodiments in a specific context, namely, a snubber circuit operable with a power converter. While the principles will be described in the environment of a switched-mode power converter, any environment such as a motor controller or power amplifier that may benefit from such a system and method that enables these functionalities is well within the broad scope of the present disclosure.

Referring initially to FIGURE 1 , illustrated is a schematic diagram of an embodiment of a power converter 100. The power converter 100 receives an input current In, and converts a direct current ("dc") input voltage V_in (from an input power source) to a desired dc output voltage I_out . The output voltage I_out is applied across a load (designated "LD") connected in parallel with an output capacitor C_out. An output current I_out is split between the output capacitor C_out (receiving a capacitor current Ic) and the load LD (receiving a load current II). The power converter 100 includes an inductor L, the output capacitor C_out and first and second power switches Ql , Q2. The power converter 100 also includes a controller 1 10 (including a processor ("PR") 120 and memory ("M") 130) that controls the first and second power switches Ql , Q2 to regulate the output voltage I_out of the power converter 100.

The controller 110 applies the control signals Csl , Cs2 at an appropriate frequency (e.g. , 300 kilohertz ("kHz")) to control terminals of the first and second power switches (also referred to as "switching devices") Ql , Q2, respectively. The controller 110 regulates the output voltage I_out by adjusting the duty cycles D, 1 -D of the control signals Csl, Cs2 for the first and second power switches Ql, Q2, respectively, as a function of the output current I_out and/or the output voltage I_out .

The processor 120 may be embodied as any type of processor and associated circuitry configured to perform one or more of the functions described herein. For example, the processor 120 may be embodied as or otherwise include a single or multi- core processor, an application specific integrated circuit, a collection of logic devices, or other circuits. The memory 130 may be embodied as read-only memory devices and/or random access memory devices. For example, the memory 130 may be embodied as or otherwise include dynamic random access memory devices ("DRAM"), synchronous dynamic random access memory devices ("SDRAM"), double-data rate dynamic random access memory devices ("DDR SDRAM"), and/or other volatile or non-volatile memory devices. The memory 130 may have stored therein programs including a plurality of instructions or computer program code for execution by the processor 120 to control particular functions of the power converter 100 as discussed in more detail below.

A circuit node "a" illustrated in FIGURE 1 is alternately coupled to ground when the second power switch Q2 is forward biased or otherwise enabled to conduct, or to the input voltage V_in when the first power switch Ql is turned on during a switching operation of the power converter 100. Due to circuit parasitic elements such as inherent capacitances of the first and second power switches Ql, Q2 and due to an inductance of the inductor L, an undesired ringing voltage is produced at the circuit node "a" by the switching operation. The circuit node "a" is a location for coupling to a snubber circuit as set forth herein. In accordance therewith, the controller 130 also produces an offset control signal Cos that is employed to control a conductivity of an active snubber switch in the snubber circuit.

As introduced herein, a snubber circuit with an active switch is employed to more efficiently attenuate voltage and/or current ringing in switched-mode power converters. The snubber circuit itself also consumes less power than a conventional passive snubber. In a switched-mode power converter (particularly a digitally controlled power converter), timing of transient events in transformers and power switches is well defined and well known to a controller therein. Known timing of power switches enables the use of digitally controlled snubber circuits. This enables control signals for snubber circuit start times and end times to be tuned with the respect to the transient switching event initiated by the controller.

Turning now to FIGURE 2, illustrated is a schematic diagram of another embodiment of a power converter 200. A power train 240 of the power converter 200 receives an input current I_in and an input voltage V_in and includes first and second high- side power switches Ql , Q2, and first and second low-side power switches Q3, Q4 arranged in a full bridge configuration and including parasitic capacitances (illustrated with dotted lines as parallel capacitances). The first high-side power switch Ql is coupled in series at a first circuit node Va with the first low-side power switch Q3. The second high-side power switch Q2 is coupled in series at a second circuit node Vb with the second low-side power switch Q4. The first and second circuit nodes Va, Vb are coupled to opposite ends of a primary winding of a transformer TR. A secondary winding of the transformer TR is coupled to a synchronous rectifier formed by a third low-side power switch Q5 (including a parasitic capacitance, not shown) coupled to a fourth low-side power switch Q6 (including a parasitic capacitance, not shown). A center tap of the secondary winding of the transformer TR is coupled to an output filter including output inductor L and output capacitor C_out that filters an output voltage I_out provided to a load (designated "LD"). An output current I_out is split between the output capacitor C_out (receiving a capacitor current Ic) and the load LD (receiving a load current II).

The first and second high-side power switches Ql , Q2, and the first and second low-side power switches Q3, Q4 are controlled to provide a high frequency ac voltage to the primary winding of the transformer TR. The high frequency ac voltage is impressed across to the secondary winding of the transformer TR and the third and fourth low-side power switches Q5, Q6 are controlled to provide a rectified dc voltage. The rectified dc voltage is then filtered by the output filter, which provides the output voltage I_out to the load LD. While the power switches are illustrated as MOSFETs, it should be understood that any semiconductor switch technology can be used as the application dictates. Also, while the power train includes a full bridge configuration and synchronous rectifier, other topologies and rectification techniques may be employed to advantage. A controller 210 including a processor ("PR") 220 and memory ("M") 230 receives the output current I_out and/or the output voltage I_out and generates control signals Csl , Cs2, Cs3, Cs4 for the first and second high-side power switches Ql, Q2, and first and second low- side power switches Q3, Q4 to regulate the output voltage I_out (an output characteristic of the power converter 200). The controller 210 also generates control signals Cs5, Cs6 for the synchronous rectifier formed by the third and fourth low-side power switches Q5, Q6. A description of analogous controller 110 is described above with respect to FIGURE 1. The circuit nodes "a" are candidate locations for applying a snubber circuit as set forth herein. In accordance therewith, the controller 210 also produces an offset control signal Cos that is employed to control a conductivity of an active switch in the snubber circuit.

Turning now to FIGURE 3, illustrated is a schematic diagram of an embodiment of a snubber circuit 300. The snubber circuit 300 is active in response to an offset control signal Cos produced by a controller. The snubber circuit 300 is formed with a first active snubber switch QS1 (e.g. , a P-channel metal-oxide semiconductor ("PMOS") switch), a resistor-capacitor timing network 310, a snubber capacitor C4, and a second active snubber switch QS2 (e.g. , an N-channel metal oxide semiconductor ("NMOS") switch). The resistor-capacitor timing network 310 includes a voltage divider formed with resistors R3, R4, and a capacitor C3. A drain terminal of the first active snubber switch QS1 is coupled to a circuit node "a" (see, e.g. , FIGURE 2), and a source terminal of the first active snubber switch QS 1 is coupled to the snubber capacitor C4. Accordingly, switched terminals of the first active snubber switch QS 1 are coupled between the circuit node "a" and the snubber capacitor C4 to form a series circuit arrangement therebetween.

In operation, the first active snubber switch QS 1 is enabled to conduct when a control terminal (the gate) is pulled negative with respect to its source terminal, which source terminal is also functional as the cathode of its body diode. When a power switch (such as the third low- side power switch Q5 of FIGURE 2) coupled to the circuit node "a" is disabled to conduct, a voltage spike (voltage ringing) is generally produced at the drain terminal of the power switch before the voltage of the drain terminal settles to an open-circuit positive voltage level. The snubber capacitor C4 typically retains a charge to produce a voltage thereacross roughly equal to this open-circuit positive voltage level. By causing the first active snubber switch QS 1 to conduct when the power switch is disabled to conduct, the voltage spike at the drain of the power switch is substantially clamped to the voltage of the snubber capacitor C4.

The second active snubber switch QS2 receives the offset control signal Cos and provides a control signal, via the resistor-capacitor timing network 310, to control a conductivity of the first active snubber switch QS 1. A positive voltage level of the offset control signal Cos enables the second active snubber switch QS2 to conduct, which clamps the voltage at the left side of the resistor R3 to ground potential. The voltage divider applies a net negative voltage to the gate of the first active snubber switch QS 1 relative to the source thereof. The capacitor C3 retards changing the voltage of the gate of the first active snubber switch QS 1. Thus, the resistor-capacitor timing network 310 formed with resistors R3, R4 and a capacitor C3 can provide a delay for the control signal from the second active snubber switch QS2 to the first active snubber switch QS 1.

When the second active snubber switch QS2 is disabled to conduct by the offset control signal Cos (e.g., when the voltage of the offset control signal Cos returns to zero), the voltage produced across the terminals of the snubber capacitor C4 is not discharged. The result is the voltage at the circuit node "a" is clamped by the offset control signal Cos to the voltage of the snubber capacitor C4, and unnecessary power loss in discharging the snubber capacitor C4 by a resistor is avoided. Timing of the offset control signal Cos is selected in view of practical delays in implementing the snubber circuit 300. Thus, the snubber circuit 300 can efficiently attenuate the voltage and current ringing associated with the power switch.

Turning now to FIGURE 4, illustrated is a schematic diagram of an embodiment of a snubber circuit 400. The snubber circuit 400 is active in response to an offset control signal Cos produced by a controller. The snubber circuit 400 is formed with an active snubber switch QS 1 (e.g. , a P-channel metal-oxide semiconductor ("PMOS") switch), a driver 410, an amplitude shifting network 420, and a snubber capacitor C5. The amplitude shifting network 420 includes a capacitor C6 and a diode D5. As illustrated in FIGURE 4, control of the active snubber switch QS 1 is different, as the second active snubber switch QS2 of FIGURE 3 is replaced with the driver 410 that can enable timing control of the active snubber switch QS 1. The amplitude shifting network 420 transitions the offset control signal Cos (via the driver 410) to be negative to control the active snubber switch QS 1. Otherwise, the snubber circuit 400 operates analogously to the snubber circuit 300 of FIGURE 3 to efficiently attenuate the voltage and current ringing associated with a power switch (such as the third low-side power switch Q5 of FIGURE 2).

Turning now to FIGURE 5, illustrated is a schematic diagram of an embodiment of a snubber circuit 500. The snubber circuit 500 is active in response to an offset control signal Cos produced by a controller. The snubber circuit 500 is formed with an active snubber switch QS 1 (e.g. , a P-channel metal-oxide semiconductor ("PMOS") switch), a driver 510, and a snubber capacitor C7. The driver 510 is coupled to positive and negative bias supplies vdd, -vss. As illustrated in FIGURE 5, control of the active snubber switch QS 1 is different, as the second active snubber switch QS2 of FIGURE 3 is replaced with the driver 510 that can enable timing control of the active snubber switch QS1. Additionally, the amplitude shifting network 420 of FIGURE 4 is now replaced by the positive and negative bias supplies vdd, -vss. Otherwise, the snubber circuit 500 operates analogously to the snubber circuit 300 of FIGURE 3 to efficiently attenuate the voltage and current ringing associated with a power switch (such as the third low-side power switch Q5 of FIGURE 2).

Turning now to FIGURE 6, illustrated is a schematic diagram of an embodiment of a snubber circuit 600. The snubber circuit 600 is active in response to an offset control signal Cos produced by a controller. The snubber circuit 600 is formed with an active snubber switch QS 1 (e.g. , a P-channel metal-oxide semiconductor ("PMOS") switch), a driver 610, and a snubber capacitor C8. The driver 610 is coupled to positive and negative bias supplies vdd, -vss. In the illustrated embodiment, the orientation of the active snubber switch QS 1 and the snubber capacitor C8 is reversed. Analogous to FIGURE 5, control of the active snubber switch QS 1 is different, as the second active snubber switch QS2 of FIGURE 3 is replaced with the driver 610 that can enable timing control of the active snubber switch QS 1. Additionally, the amplitude shifting network 420 of FIGURE 4 is now replaced by the positive and negative bias supplies vdd, -vss. Otherwise, the snubber circuit 600 operates analogously to the snubber circuit 300 of

FIGURE 3 to efficiently attenuate the voltage and current ringing associated with a power switch (such as the third low-side power switch Q5 of FIGURE 2). Turning now to FIGURE 7, illustrated is a timing diagram demonstrating an operation of a power converter. A control signal Csn represents a control signal to a power switch Qn (e.g. , the control signal Cs5 to the third low-side power switch Q5 of FIGURE 2) for a duty cycle D with a start time ts and an end time te. An offset control signal Cos represents a control signal to a snubber circuit (e.g. , the offset control signal Cos to the snubber circuit 300 of FIGURE 3) with a start time t_start and an end time t_stop. As illustrated, a start time t_start of the offset control signal Cos is delayed by a time tl with respect to a start time ts of the control signal Csn for the power switch Qn. An end time t_stop of the offset control signal Cos is delayed by a time t2 with respect to an end time te of the control signal Csn for the power switch Qn. An active snubber switch (e.g. , the first active snubber circuit QS 1 of the snubber circuit 300 of FIGURE 3) is enabled to conduct when the offset control signal Cos is low, and disabled to conduct when the offset control signal Cos is high. The active snubber switch is enabled to conduct by the offset control signal Cos when an amplitude of a voltage 710 of a circuit node coupled to the power switch Qn (e.g. , the circuit node "a" coupled to the third low-side power switch Q5 of FIGURE 2) attains a preset voltage level 720.

Turning now to FIGURE 8, illustrated is a timing diagram demonstrating an operation of a power converter. A control signal Csn represents a control signal to a power switch Qn (e.g. , the control signal Cs5 to the third low-side power switch Q5 of FIGURE 2) for a duty cycle D with a start time ts and an end time te. An offset control signal Cos represents a control signal to a snubber circuit (e.g. , the offset control signal Cos to the snubber circuit 300 of FIGURE 3) with a start time t_start and an end time t_stop. As illustrated, a start time t_start of the offset control signal Cos is delayed by a time tl with respect to a start time ts of the control signal Csn for the power switch Qn. An end time t_stop of the offset control signal Cos is delayed by a time t2 with respect to an end time te of the control signal Csn for the power switch Qn. An active snubber switch (e.g. , the first active snubber circuit QS 1 of the snubber circuit 300 of FIGURE 3) is enabled to conduct when the offset control signal Cos is high, and disabled to conduct when the offset control signal Cos is low. The active snubber switch is enabled to conduct by the offset control signal Cos when an amplitude of a voltage 810 of a circuit node coupled to the power switch Qn (e.g. , the circuit node "a" coupled to the third low-side power switch Q5 of FIGURE 2) attains a preset voltage level 820. Hence, a voltage ringing at a circuit node associated with a power switch of a power converter can be dampened without introducing unnecessary energy loss. When the voltage ringing is sufficiently dampened, the snubber circuit can be disabled at the end time t_stop relative to the end time te of the control signal Csn for the power switch Qn. This allows a damping of the voltage ringing to be obtained without the snubber circuit consuming excess power as the snubber circuit is only active when necessary to attenuate the ringing.

Turning now to FIGURE 9, illustrated is a flow diagram of an embodiment of a method of operating a power converter. With continuing reference to the preceding FIGURES, the power converter includes a snubber circuit 300 and a controller 210 coupled to a power switch such as the third low-side power switch Q5. The method begins at a start step or module 910. At a step or module 920, the method includes providing control signals Cs5 to control a conductivity of the third low-side power switch Q5. At a step or module 930, the method includes providing an offset control signal Cos to the snubber circuit 300. The method may also include delaying the offset control signal Cos at a step or module 940.

At a step or module 950, the method includes providing the offset control signal Cos to an active snubber switch QS 1 to offset a timing of a conductivity of the active snubber switch QS1 with respect to the third low-side power switch Q5. The active snubber switch QS 1 may be enabled to conduct by the offset control signal Cos when an amplitude of a voltage 710 of a circuit node "a" coupled to the third low-side power switch Q5 attains a preset voltage level 720. A start time t_start of the offset control signal Cos may be delayed by a time tl with respect to a start time ts of the control signal Cs5 for the third low-side power switch Q5. An end time t_stop of the offset control signal Cos may be delayed by a time t2 with respect to an end time te of the control signal Cs5 for the third low-side power switch Q5.

The method also includes attenuating a voltage ringing associated with the third low-side power switch Q5 at a step or module 960. In particular, the voltage ringing is clamped to a voltage across a snubber capacitor in series with the active snubber switch QS1 coupled to a circuit node "a" coupled to the third low-side power switch Q5. The method concludes at a step or module 970. Thus, the present disclosure introduces a power converter (200) including a power train (240) including a power switch (Q5) and a controller (210) configured to provide a control signal (Cs5) to control a conductivity of the power switch (Q5). A snubber circuit (300) includes a snubber capacitor (C4) coupled to the power switch (Q5) and an active snubber switch (QSl) coupled to the snubber capacitor (C4). The snubber circuit is configured to receive an offset control signal (Cos) from the controller (210) to offset a timing of a conductivity of the active snubber switch (QSl) with respect to the power switch (Q5). A start time (t_start) of the offset control signal (Cos) is delayed by a time (tl) with respect to a start time (ts) of the control signal (Cs5) for the power switch (Q5). An end time (t_stop) of the offset control signal (Cos) is delayed by a time (t2) with respect to an end time (te) of the control signal (Cs5) for the power switch (Q5). The active snubber switch (QSl) may be disabled to conduct when the offset control signal (Cos) is low. The active snubber switch (QSl) may be enabled to conduct by the offset control signal (Cos) when an amplitude of a voltage (710) of a node (a) coupled to the power switch (Q5) attains a preset voltage level (720).

The snubber circuit (300) may include another active snubber switch (QS2) configured to provide the offset control signal (Cos) to the active snubber switch (QSl). The snubber circuit (300) may also include a resistor-capacitor timing network (310) configured to delay the offset control signal (Cos) to the active snubber switch (QSl). The active snubber switch (QSl) may receive the offset control signal (Cos) via a driver (410) coupled to the controller (210). The active snubber switch (QSl) may receive the offset control signal (Cos) via a driver (410) and an amplitude shifting network (420) coupled to the controller (210). The amplitude shifting network (420) may include a capacitor (C6) coupled to an output of the driver (410) and a diode (D5) coupled between the capacitor (C6) and the active snubber switch (QSl).

The foregoing description of embodiments of the present proposed solution has been presented for the purpose of illustration and description. It is not intended to be exhaustive or to limit the proposed solution to the present form disclosed. Alternations, modifications and variations can be made without departing from the spirit and scope of the present proposed solution.

As described above, the exemplary embodiment provides both a method and corresponding apparatus consisting of various modules providing functionality for performing the steps of the method. The modules may be implemented as hardware (embodied in one or more chips including an integrated circuit such as an application specific integrated circuit), or may be implemented as software or firmware for execution by a processor. In particular, in the case of firmware or software, the exemplary embodiment can be provided as a computer program product including a computer readable storage medium embodying computer program code (i.e., software or firmware) thereon for execution by the computer processor. The computer readable storage medium may be non-transitory (e.g., magnetic disks; optical disks; read only memory; flash memory devices; phase-change memory) or transitory (e.g., electrical, optical, acoustical or other forms of propagated signals-such as carrier waves, infrared signals, digital signals, etc.). The coupling of a processor and other components is typically through one or more busses or bridges (also termed bus controllers). The storage device and signals carrying digital traffic respectively represent one or more non-transitory or transitory computer readable storage medium. Thus, the storage device of a given electronic device typically stores code and/or data for execution on the set of one or more processors of that electronic device such as a controller.

Although the embodiments and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope thereof as defined by the appended claims. For example, many of the features and functions discussed above can be implemented in software, hardware, or firmware, or a combination thereof. Also, many of the features, functions, and steps of operating the same may be reordered, omitted, added, etc. , and still fall within the broad scope of the various embodiments.

Moreover, the scope of the various embodiments is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized as well.

Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Claims

IN THE CLAIMS:

1. A snubber circuit (300) operable with a power converter (200) having a controller (210) configured to provide a control signal (Cs5) to control a conductivity of a power switch (Q5) of said power converter (200), comprising:

a snubber capacitor (C4) coupled to said power switch (Q5); and

an active snubber switch (QS1) coupled to said snubber capacitor (C4), said snubber circuit (300) configured to receive an offset control signal (Cos) from said controller (210) to offset a timing of a conductivity of said active snubber switch (QS1) with respect to said power switch (Q5).

2. The snubber circuit (300) as recited in Claim 1 wherein a start time (t_start) of said offset control signal (Cos) is delayed by a time (tl) with respect to a start time (ts) of said control signal (Cs5) for said power switch (Q5).

3. The snubber circuit (300) as recited in Claim 1 wherein an end time (t_stop) of said offset control signal (Cos) is delayed by a time (t2) with respect to an end time (te) of said control signal (Cs5) for said power switch (Q5).

4. The snubber circuit (300) as recited in Claim 1 wherein said active snubber switch (QS1) is disabled to conduct when said offset control signal (Cos) is low.

5. The snubber circuit (300) as recited in Claim 1 wherein said active snubber switch (QS1) is enabled to conduct by said offset control signal (Cos) when an amplitude of a voltage (710) of a node (a) coupled to said power switch (Q5) attains a preset voltage level (720).

6. The snubber circuit (300) as recited in Claim 1 further comprising another active snubber switch (QS2) configured to provide said offset control signal (Cos) to said active snubber switch (QS1).

7. The snubber circuit (300) as recited in Claim 1 further comprising a resistor-capacitor timing network (310) configured to delay said offset control signal (Cos) to said active snubber switch (QS1).

8. The snubber circuit (300, 400) as recited in Claim 1 wherein said active snubber switch (QS1) is configured to receive said offset control signal (Cos) via a driver (410) coupled to said controller (210).

9. The snubber circuit (300, 400) as recited in Claim 1 wherein said active snubber switch (QSl) is configured to receive said offset control signal (Cos) via a driver (410) and an amplitude shifting network (420) coupled to said controller (210).

10. The snubber circuit (300, 400) as recited in Claim 9 wherein said amplitude shifting network (420) comprises a capacitor (C6) coupled to an output of said driver (410) and a diode (D5) coupled between said capacitor (C6) and said active snubber switch (QSl).

11. A power converter (200), comprising:

a power train (240) including a power switch (Q5);

a controller (210) configured to provide a control signal (Cs5) to control a conductivity of said power switch (Q5); and

a snubber circuit (300), including:

a snubber capacitor (C4) coupled to said power switch (Q5), and an active snubber switch (QSl) coupled to said snubber capacitor (C4), said snubber circuit (300) configured to receive an offset control signal (Cos) from said controller (210) to offset a timing of a conductivity of said active snubber switch (QSl) with respect to said power switch (Q5).

12. The power converter (200) as recited in Claim 11 wherein a start time (t_start) of said offset control signal (Cos) is delayed by a time (tl) with respect to a start time (ts) of said control signal (Cs5) for said power switch (Q5).

13. The power converter (200) as recited in Claim 11 wherein an end time (t_stop) of said offset control signal (Cos) is delayed by a time (t2) with respect to an end time (te) of said control signal (Cs5) for said power switch (Q5).

14. The power converter (200) as recited in Claim 11 wherein said active snubber switch (QSl) is disabled to conduct when said offset control signal (Cos) is low.

15. The power converter (200) as recited in Claim 11 wherein said active snubber switch (QSl) is enabled to conduct by said offset control signal (Cos) when an amplitude of a voltage (710) of a node (a) coupled to said power switch (Q5) attains a preset voltage level (720).

16. The power converter (200) as recited in Claim 11 wherein said snubber circuit (300) further comprises another active snubber switch (QS2) configured to provide said offset control signal (Cos) to said active snubber switch (QSl).

17. The power converter (200) as recited in Claim ! 1 wherein said snubber circuit (300) f urther comprises a resistor-capacitor timing network (310) configured to delay said offset control signal (Cos) to said active snubber .switch (QS 1 ).

18. The power converter (200) as recited in Claim ! i wherein said active snubber switch (QS I ) is configured to receive said offset control signal (Cos) via a dri ver (410) coupled to said controller (210).

19. The power converter (200) as recited in Claim 1 1 wherein said active snubber switch (QS I ) is configured to receive said offset control signal (Cos) via a driver (410) and an amplitude shifting network (420) coupled to said controller (210).

20. The power converter (200) as recited in Claim 19 wherein said amplitude shifting network (420) comprises a capacitor (C6) coupled to an output of said driver (410) and a diode (D5) coupled between said capacitor (C6) and said active snubber switch (QS I ).

2_* I , A method of operating a power converter (200) including a power train (240) having a power switch (Q5);

providi ng (920) a control signal (Cs5) to control a conductivity of said power switch (Q5); and

providing (930) an offset control signal (Cs5) to a snubber circuit (300) including a snubber capacitor (C4) coupled to said power switch (Q5);

providing (950) said offset control signal (Cs5) to an active snubber switch (QS 1 ) coupled to said snubber capacitor (C4) to offset a titning of a conductivity of said active snubber switch (QS I ) with respect to said power switch (Q5); and

attenuate (960) a voltage ringing with a snubber capacitor (C4) associated with said power switch (Q5).

22. The method as recited in Claim 2 i wherein a start time (t_start) of said offset control signal (Cos) is delayed by a time (t ! ) with respect to a start time (ts) of a control signal (Cs5) for said power switch (Q5).

23. The method as recited in Claim 21 wherein an end time (t_stop) of said offset control signal (Cos) is delayed by a time (t2) with respect to an end time (te) of said control signal (Cs5) for said power switch (Q5).

24. The method as recited in Claim 21 wherein said active snubber switch. (QS I ) is disabled to conduct when said offset control signal (Cos) is low.

25. The method as recited in Claim 21 wherein said active snubber switch (QSl) is enabled to conduct by said offset control signal (Cos) when an amplitude of a voltage (710) of a node (a) coupled to said power switch (Q5) attains a preset voltage level (720).

26. The method as recited in Claim 21 wherein said snubber circuit (300) further comprises another active snubber switch (QS2) configured to provide said offset control signal (Cos) to said active snubber switch (QSl).

27. The method as recited in Claim 21 further comprising delaying (940) said offset control signal (Cos) with a resistor-capacitor timing network (310) of said snubber circuit (300).

28. The method as recited in Claim 21 wherein said active snubber switch (QSl) is configured to receive said offset control signal (Cos) via a driver (410) coupled to said controller (210).

29. The method as recited in Claim 21 wherein said active snubber switch (QSl) is configured to receive said offset control signal (Cos) via a driver (410) and an amplitude shifting network (420) coupled to said controller (210).

30. The method as recited in Claim 29 wherein said amplitude shifting network (420) comprises a capacitor (C6) coupled to an output of said driver (410) and a diode (D5) coupled between said capacitor (C6) and said active snubber switch (QSl).