WO2017107285A1 - 用于窄边框液晶显示面板的goa电路 - Google Patents
用于窄边框液晶显示面板的goa电路 Download PDFInfo
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- WO2017107285A1 WO2017107285A1 PCT/CN2016/072426 CN2016072426W WO2017107285A1 WO 2017107285 A1 WO2017107285 A1 WO 2017107285A1 CN 2016072426 W CN2016072426 W CN 2016072426W WO 2017107285 A1 WO2017107285 A1 WO 2017107285A1
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- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 44
- 239000010409 thin film Substances 0.000 claims abstract description 188
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- 230000000750 progressive effect Effects 0.000 claims abstract description 17
- 230000002146 bilateral effect Effects 0.000 claims description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 239000004065 semiconductor Substances 0.000 claims description 13
- 229920005591 polysilicon Polymers 0.000 claims description 12
- 230000000630 rising effect Effects 0.000 claims description 12
- 230000000087 stabilizing effect Effects 0.000 claims description 8
- 238000012546 transfer Methods 0.000 claims description 8
- 238000012423 maintenance Methods 0.000 claims description 5
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- 230000008569 process Effects 0.000 description 8
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- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
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- 230000000694 effects Effects 0.000 description 1
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- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
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- G—PHYSICS
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
- G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
- G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
Definitions
- the present invention relates to the field of display technologies, and in particular, to a GOA circuit for a narrow bezel liquid crystal display panel.
- LCD Liquid crystal display
- PDAs personal digital assistants
- digital cameras computer screens or laptop screens, etc.
- GOA technology (Gate Driver on Array) is an array substrate row driving technology.
- the original array process of the liquid crystal display panel is used to fabricate a horizontal scanning line driving circuit on a substrate around the display area, so that it can replace the external integrated circuit board ( (Integrated Circuit, IC) to complete the horizontal scanning line drive.
- IC integrated circuit board
- GOA technology can reduce the bonding process of external ICs, have the opportunity to increase productivity and reduce product cost, and can make LCD panels more suitable for making narrow borders or no borders. Display product.
- LTPS-TFT liquid crystal displays have attracted more and more attention.
- LTPS-TFT liquid crystal displays have high resolution, fast response, high brightness and high opening. Rate and other advantages. Since the low-temperature polysilicon has an order of arrangement of amorphous silicon (a-Si), the low-temperature polysilicon semiconductor itself has an ultra-high electron mobility, which is 100 times higher than that of the amorphous silicon semiconductor, and the gate driver can be fabricated by using GOA technology. On the thin film transistor array substrate, the goal of system integration, space saving and cost of driving the IC are achieved.
- a-Si amorphous silicon
- a common GOA circuit includes: a cascaded multi-level GOA unit, each stage GOA unit includes: a control input unit 100, a voltage stabilization unit 200, a control output unit 300, and a pull-down maintenance unit. 400, the pull-down unit 500, and the second node control unit 600, let n be a positive integer, in addition to the first-level GOA unit, in the n-th GOA unit:
- the control input unit 100 includes a first thin film transistor T1, a gate of the first thin film transistor T1 is electrically connected to the control clock signal XCK, and a source is electrically connected to the upper n-1th stage GOA unit.
- the output terminal G(n-1), the drain is electrically connected to the third node K(n);
- the voltage stabilizing unit 200 includes a second thin film transistor T2.
- the gate of the second thin film transistor T2 is electrically connected to a constant voltage high potential VGH, and the source is electrically connected to the third node K(n). Sexually connected to the first node Q(n);
- the control output unit 300 includes a third thin film transistor T3.
- the gate of the third thin film transistor T3 is electrically connected to the first node Q(n), and the source is electrically connected to the output clock signal CK.
- the pull-down maintaining unit 400 includes: a fifth thin film transistor T5, a gate of the fifth thin film transistor T5 is electrically connected to the second node P(n), and a source is electrically connected to the output terminal G(n), and the drain
- the second terminal C2 is electrically connected to the second node P(n), and the other end is electrically connected to the constant voltage low potential VGL;
- the pull-down unit 500 includes a sixth thin film transistor T6.
- the gate of the sixth thin film transistor T6 is electrically connected to the output clock signal CK, and the source is electrically connected to the third node K(n).
- the gate of the seventh thin film transistor T7 is electrically connected to the second node P(n), and the drain is electrically connected to the constant voltage low potential VGL;
- the second node control unit 600 includes: a fourth thin film transistor T4, the gate of the fourth thin film transistor T4 is electrically connected to the third node K(n), and the source is electrically connected to the control clock signal XCK. Electrode is electrically connected to the second node P(n); and an eighth thin film transistor T8. The gate of the eighth thin film transistor T8 is electrically connected to the control clock signal XCK, and the source is electrically connected to the constant voltage high potential VGH. The drain is electrically connected to the second node P(n).
- FIG. 2 is a schematic diagram showing the architecture of a GOA circuit for bilaterally driving progressive scanning.
- a GOA circuit is disposed on each of the left and right sides of the display panel.
- Each GOA circuit includes a first stage to a final stage GOA unit, and GOA circuits on both sides. The timings are the same, and the GOA circuits of each side of each side are connected to the first clock signal CK(1) and the second clock signal CK(2), respectively, as the control clock signal XCK and the output clock signal CK, and the GOA circuits on each side are respectively.
- the scanning is performed line by line in the order of pixel arrangement, and the GOA units of the same level on both sides act together on the driving of the pixels in the same row. Referring to FIG.
- FIG. 4 is a schematic diagram showing the architecture of a GOA circuit for bilaterally driving interlaced scanning.
- a GOA circuit is disposed on each of the left and right sides of the display panel.
- the GOA circuit on one side includes only odd-numbered GOA units, and the GOA circuit on the other side includes only even-numbered GOAs. unit.
- the timings of the GOA circuits on both sides are different, and the GOA circuits of one of the stages access the first clock signal CK(1) and the third clock signal CK(3), respectively, as the control clock signal XCK and the output clock signal CK, for the odd-line pixels.
- the leakage of the first node Q(n) causes the GOA circuit to fail, and after the output of the output terminal G(n) is completed, there is a dead zone where the control clock signal XCK and the output clock signal CK are simultaneously low, which also leads to the GOA circuit. Unstable, severely may cause the GOA circuit to fail. Therefore, the existing GOA circuit shown in FIG. 1 cannot work stably under the bilateral drive interlaced scanning architecture and needs to be improved.
- the first node leaks, ensuring stable operation of the circuit and greatly improving the reliability of the GOA circuit.
- the present invention provides a GOA circuit for a narrow bezel liquid crystal display panel, comprising: a cascaded multi-level GOA unit, each stage GOA unit comprising: a control input unit, a voltage stabilizing unit, and a control output. a unit, a pull-down maintaining unit, a pull-down unit, a second node control unit, and a first node leakage protection unit;
- n be a positive integer, in the nth level GOA unit:
- the control input unit includes: a first thin film transistor, a gate of the first thin film transistor is electrically connected to the level transfer signal, a source is electrically connected to the first constant piezoelectric position, and a drain is electrically connected to the third node ;
- the voltage stabilizing unit includes: a second thin film transistor, a gate of the second thin film transistor is electrically connected to the first constant piezoelectric position, a source is electrically connected to the third node, and a drain is electrically connected to the first node ;
- the control output unit includes: a third thin film transistor, a gate of the third thin film transistor is electrically connected to the first node, a source is electrically connected to the output clock signal, and a drain is electrically connected to the output end; a capacitor, one end of the first capacitor is electrically connected to the first node, and the other end is electrically connected to the output end;
- the pull-down maintaining unit includes: a fifth thin film transistor, a gate of the fifth thin film transistor is electrically connected to the second node, a source is electrically connected to the output end, and a drain is electrically connected to the second constant piezoelectric level; And a second capacitor, one end of the second capacitor is electrically connected to the second node, and the other end is electrically connected to the second constant piezoelectric position;
- the pull-down unit includes: a sixth thin film transistor, a gate of the sixth thin film transistor is electrically connected to the fourth node, a source is electrically connected to the third node, and a drain is electrically connected to the source of the seventh thin film transistor And a seventh thin film transistor, the gate of the seventh thin film transistor is electrically connected to the second node, and the drain is electrically connected to the second constant voltage;
- the second node control unit includes: a fourth thin film transistor, a gate of the fourth thin film transistor is electrically connected to the third node, a source is electrically connected to the control clock signal, and a drain is electrically connected to the second node And an eighth thin film transistor, the gate of the eighth thin film transistor is electrically connected to the control clock signal, the source is electrically connected to the first constant piezoelectric position, and the drain is electrically connected to the second node;
- the first node leakage protection unit includes: a ninth thin film transistor, the gate and the source of the ninth thin film transistor are electrically connected to the output clock signal, the drain is electrically connected to the fourth node; and the tenth thin film transistor The gate of the tenth thin film transistor is electrically connected to the level transfer signal, the source is electrically connected to the fourth node, the drain is electrically connected to the second constant voltage; and the third capacitor is the third capacitor. One end is electrically connected to the fourth node, and the drain is electrically connected to the second constant voltage bit.
- each of the thin film transistors is an N-type low temperature polysilicon semiconductor thin film transistor, wherein the first constant piezoelectric potential is a constant voltage high potential, and the second constant piezoelectric potential is a constant voltage low potential.
- each of the thin film transistors is a P-type low temperature polysilicon semiconductor thin film transistor, wherein the first constant piezoelectric potential is a constant voltage low potential, and the second constant piezoelectric potential is a constant voltage high potential.
- the GOA circuit for the narrow-border liquid crystal display panel can be applied to a display panel of a bilaterally driven progressive scan architecture.
- a GOA circuit is disposed on each of the left and right sides of the display panel, and the GOA circuits on each side include the first stage to the last one.
- Level GOA unit; each stage of the GOA unit is connected to two clock signals: a first clock signal and a second clock signal, the first clock signal and the second clock signal are opposite in phase.
- the first clock signal and the second clock signal are respectively rotated as an output clock signal and a control clock signal.
- the pass signal of the nth stage GOA unit is an output signal of the n-1th stage GOA unit of the previous stage, except for the first stage GOA unit;
- the level-transmitted signal of the first-stage GOA unit is the circuit start signal.
- the GOA circuit for a narrow-border liquid crystal display panel can also be applied to a display panel of a bilaterally driven interlaced scanning architecture.
- a GOA circuit is respectively disposed on the left and right sides of the display panel, and the GOA circuit on one side includes only odd-numbered GOA units, and the other side The GOA circuit only includes even-numbered GOA units;
- Each of the GOA units of one GOA circuit is connected to two clock signals: a first clock signal and a third clock signal;
- the GOA units of each level of the GOA circuit are connected to the other two clock signals, the second clock signal and the fourth clock signal.
- the pulse periods of the first, second, third, and fourth clock signals are the same, and the falling edge of the first clock signal is generated simultaneously with the rising edge of the second clock signal, the second A falling edge of the strip clock signal is generated simultaneously with a rising edge of the third clock signal, and a falling edge of the third clock signal is simultaneously generated with a rising edge of the fourth clock signal, the fourth clock The falling edge of the signal is generated simultaneously with the rising edge of the first clock signal.
- the first clock signal and the third clock signal are respectively taken as an output clock signal and a control clock signal; in each level of the GOA unit of the GOA circuit, the The two clock signals and the fourth clock signal are respectively rotated as an output clock signal and a control clock signal.
- the level-transmitting signal of the n-th stage GOA unit is an output signal of the upper two-stage n-2th GOA unit, except for the first-stage and second-stage GOA units;
- the level signals of the first and second stage GOA units are circuit start signals.
- the invention also provides a GOA circuit for a narrow bezel liquid crystal display panel, comprising: a cascaded multi-level GOA unit, each stage GOA unit comprises: a control input unit, a voltage stabilization unit, a control output unit, and a pull-down maintenance unit a pull-down unit, a second node control unit, and a first node leakage protection unit;
- n be a positive integer, in the nth level GOA unit:
- the control input unit includes: a first thin film transistor, a gate of the first thin film transistor is electrically connected to the level transfer signal, a source is electrically connected to the first constant piezoelectric position, and a drain is electrically connected to the third node ;
- the voltage stabilizing unit includes: a second thin film transistor, a gate of the second thin film transistor is electrically connected to the first constant piezoelectric position, a source is electrically connected to the third node, and a drain is electrically connected to the first node ;
- the control output unit includes: a third thin film transistor, a gate of the third thin film transistor is electrically connected to the first node, a source is electrically connected to the output clock signal, and a drain is electrically connected to the output end; a capacitor, one end of the first capacitor is electrically connected to the first node, and the other end is electrically connected to the output end;
- the pull-down maintaining unit includes: a fifth thin film transistor, a gate of the fifth thin film transistor is electrically connected to the second node, a source is electrically connected to the output end, and a drain is electrically connected to the second constant piezoelectric level; And a second capacitor, one end of the second capacitor is electrically connected to the second node, and the other end is electrically connected to the second constant piezoelectric position;
- the pull-down unit includes: a sixth thin film transistor, and a gate of the sixth thin film transistor Connected to the fourth node, the source is electrically connected to the third node, the drain is electrically connected to the source of the seventh thin film transistor, and the seventh thin film transistor is electrically connected to the gate of the seventh thin film transistor a second node, the drain is electrically connected to the second constant piezoelectric position;
- the second node control unit includes: a fourth thin film transistor, a gate of the fourth thin film transistor is electrically connected to the third node, a source is electrically connected to the control clock signal, and a drain is electrically connected to the second node And an eighth thin film transistor, the gate of the eighth thin film transistor is electrically connected to the control clock signal, the source is electrically connected to the first constant piezoelectric position, and the drain is electrically connected to the second node;
- the first node leakage protection unit includes: a ninth thin film transistor, the gate and the source of the ninth thin film transistor are electrically connected to the output clock signal, the drain is electrically connected to the fourth node; and the tenth thin film transistor The gate of the tenth thin film transistor is electrically connected to the level transfer signal, the source is electrically connected to the fourth node, the drain is electrically connected to the second constant voltage; and the third capacitor is the third capacitor. One end is electrically connected to the fourth node, and the drain is electrically connected to the second constant piezoelectric level;
- the display panel is applied to the bilateral driving progressive scanning architecture, and a GOA circuit is respectively disposed on the left and right sides of the display panel, and the GOA circuit on each side includes the first to the last stage GOA units; each level of the GOA unit
- Each of the two clock signals is connected: a first clock signal and a second clock signal, and the first clock signal and the second clock signal have opposite phases;
- the first clock signal and the second clock signal are respectively taken as an output clock signal and a control clock signal;
- the level-transmitted signal of the n-th stage GOA unit is an output signal of the upper-stage n-1th-level GOA unit;
- the level-transmitted signal of the first-stage GOA unit is the circuit start signal.
- the invention provides a GOA circuit for a narrow-framed liquid crystal display panel, and a first node leakage protection unit composed of a ninth thin film transistor, a tenth thin film transistor and a third capacitor is added, wherein The gate and the source of the ninth thin film transistor are electrically connected to the output clock signal to form a diode structure, and the third capacitor and the fourth node are charged to a high potential during the output period, and the tenth thin film transistor is fourth during the signal level transmission.
- the node performs zeroing processing to ensure normal charging of the first node.
- the GOA circuit is applicable to both the bilateral driving progressive scanning architecture and the bilateral driving interlaced scanning architecture, and can prevent the first when applied to the bilateral driving interlaced scanning architecture. Node leakage, to ensure stable operation of the circuit, greatly improve the reliability of the GOA circuit, and only set two clock signals on each side, which is conducive to the design of the narrow bezel display panel.
- 1 is a circuit diagram of a conventional GOA circuit
- FIG. 2 is a schematic structural diagram of a GOA circuit of a conventional bilateral drive progressive scan
- FIG. 3 is a timing diagram of the GOA circuit shown in FIG. 1 applied to the architecture shown in FIG. 2;
- FIG. 4 is a schematic structural diagram of a conventional bilaterally driven interlaced GOA circuit
- FIG. 5 is a timing diagram of the GOA circuit shown in FIG. 1 applied to the architecture shown in FIG. 4;
- FIG. 6 is a circuit diagram of a first embodiment of a GOA circuit for a narrow bezel liquid crystal display panel of the present invention.
- FIG. 7 is a circuit diagram of a second embodiment of a GOA circuit for a narrow bezel liquid crystal display panel of the present invention.
- FIG. 8 is a circuit diagram of a third embodiment of a GOA circuit for a narrow bezel liquid crystal display panel of the present invention.
- FIG. 9 is a circuit diagram of a fourth embodiment of a GOA circuit for a narrow bezel liquid crystal display panel of the present invention.
- FIG. 10 is a circuit diagram of a first stage GOA unit in the first and third embodiments of the GOA circuit for a narrow bezel liquid crystal display panel of the present invention
- FIG. 11 is a circuit diagram of a first stage GOA unit in the second and fourth embodiments of the GOA circuit for a narrow bezel liquid crystal display panel of the present invention
- FIG. 12 is a circuit diagram of a second stage GOA unit in a third embodiment of a GOA circuit for a narrow bezel liquid crystal display panel of the present invention.
- FIG. 13 is a circuit diagram of a second stage GOA unit in a fourth embodiment of a GOA circuit for a narrow bezel liquid crystal display panel of the present invention.
- FIG. 14 is a timing diagram of a first embodiment of a GOA circuit for a narrow bezel liquid crystal display panel applied to the bilaterally driven progressive scan architecture of FIG. 2;
- FIG. 15 is a timing diagram of a third embodiment of a GOA circuit for a narrow bezel liquid crystal display panel applied to the bilaterally driven interlaced scanning architecture of FIG.
- the present invention provides a GOA circuit for a narrow bezel liquid crystal display panel, comprising: a cascaded multi-level GOA unit, each level of the GOA unit
- the control input unit 100, the voltage stabilization unit 200, the control output unit 300, the pull-down maintenance unit 400, the pull-down unit 500, the second node control unit 600, and the first node leakage protection unit 700 are included.
- n be a positive integer, in the nth level GOA unit:
- the control input unit 100 includes: a first thin film transistor T1, a gate of the first thin film transistor T1 is electrically connected to a level transmission signal, a source is electrically connected to the first constant piezoelectric position, and a drain is electrically connected to the drain Third node K(n);
- the voltage stabilizing unit 200 includes: a second thin film transistor T2, the gate of the second thin film transistor T2 is electrically connected to the first constant piezoelectric position, and the source is electrically connected to the third node K(n), and the drain Electrically connected to the first node Q(n);
- the control output unit 300 includes a third thin film transistor T3.
- the gate of the third thin film transistor T3 is electrically connected to the first node Q(n), and the source is electrically connected to the output clock signal CK.
- the pull-down maintaining unit 400 includes: a fifth thin film transistor T5, a gate of the fifth thin film transistor T5 is electrically connected to the second node P(n), and a source is electrically connected to the output terminal G(n), and the drain
- the second capacitor C2 is electrically connected to the second node P(n), and the other end is electrically connected to the second constant voltage;
- the pull-down unit 500 includes a sixth thin film transistor T6.
- the gate of the sixth thin film transistor T6 is electrically connected to the fourth node H(n), and the source is electrically connected to the third node K(n).
- a gate electrically connected to the source of the seventh thin film transistor T7;
- a seventh thin film transistor T7 the gate of the seventh thin film transistor T7 is electrically connected to the second node P(n), and the drain is electrically connected to the first Two constant piezoelectric position;
- the second node control unit 600 includes:
- a fourth thin film transistor T4 the gate of the fourth thin film transistor T4 is electrically connected to the third node K(n), the source is electrically connected to the control clock signal XCK, and the drain is electrically connected to the second node P (
- an eighth thin film transistor T8 the gate of the eighth thin film transistor T8 is electrically connected to the control clock signal XCK, the source is electrically connected to the first constant piezoelectric position, and the drain is electrically connected to the second node P(n);
- the first node leakage protection unit 700 includes: a ninth thin film transistor T9, the gate and the source of the ninth thin film transistor T9 are electrically connected to the output clock signal CK, and the drain is electrically connected to the fourth node H.
- a ninth thin film transistor T9 the gate and the source of the ninth thin film transistor T9 are electrically connected to the output clock signal CK, and the drain is electrically connected to the fourth node H.
- a tenth thin film transistor T10 the gate of the tenth thin film transistor T10 is electrically connected to the level transfer signal, the source is electrically connected to the fourth node H(n), and the drain is electrically connected to the second a constant voltage; and a third capacitor C3, one end of the third capacitor C3 is electrically connected to the first
- the four nodes H(n) are electrically connected to the second constant piezoelectric potential.
- each of the thin film transistors is an N-type low temperature polysilicon semiconductor thin film transistor;
- the first constant piezoelectric position is Constant voltage high potential VGH, the second constant piezoelectric position is constant voltage low potential VGL;
- the level pass signal of the nth stage GOA unit is the output signal G of the upper n-1th stage GOA unit (n-1), in particular, as shown in FIG. 10, the level-transmitted signal of the first-stage GOA unit is the circuit start signal STV.
- each of the thin film transistors is a P-type low temperature polysilicon semiconductor thin film transistor;
- the first constant piezoelectric position is a constant voltage low The potential VGL,
- the second constant piezoelectric potential is a constant voltage high potential VGH;
- the pass signal of the nth stage GOA unit is the output signal G of the upper n-1th GOA unit except the first stage GOA unit (n- 1)
- the level-transmitted signal of the first-stage GOA unit is the circuit start signal STV.
- the first and second embodiments are applicable to a display panel applied to a bilaterally driven progressive scan architecture as shown in FIG. 2, that is, a GOA circuit is disposed on each of the left and right sides of the display panel, and the GOA circuits on each side include the first Level 1 to final stage GOA unit; each side of the GOA unit is connected to two clock signals: a first clock signal CK (1) and a second clock signal CK (2), the first clock The phase of the signal CK(1) and the second clock signal CK(2) are opposite.
- the first clock signal CK(1) and the second clock signal CK(2) are alternately used as the output clock signal CK and the control clock signal XCK, respectively.
- each of the thin film transistors is an N-type low temperature polysilicon semiconductor thin film transistor;
- the first constant piezoelectric potential is a constant voltage The potential VGH
- the second constant piezoelectric position is a constant voltage low potential VGL;
- the level signal of the nth stage GOA unit is the output signal of the upper two stage n-2th GOA unit G(n-2), in particular, as shown in FIGS. 10 and 12, the level-transmitting signals of the first-stage and second-stage GOA units are circuit start signals STV.
- each of the thin film transistors is a P-type low temperature polysilicon semiconductor thin film transistor;
- the first constant piezoelectric position is a constant voltage low The potential VGL,
- the second constant piezoelectric potential is a constant voltage high potential VGH;
- the level pass signal of the nth stage GOA unit is the output signal of the upper two level n-2th GOA unit G(n-2), in particular, as shown in FIGS. 11 and 13, the level-transmitting signals of the first-stage and second-stage GOA units are circuit start signals STV.
- the third and fourth embodiments are applicable to the display panel of the bilaterally driven interlaced scanning architecture as shown in FIG. 4, that is, a GOA circuit is disposed on each of the left and right sides of the display panel, and the GOA circuit is disposed on one side.
- the path includes only odd-numbered GOA units for scanning odd-line pixels, and the other side of the GOA circuit includes only even-numbered GOA units for scanning even-line pixels.
- Each of the GOA units of the GOA circuit is connected to two clock signals: a first clock signal CK(1) and a third clock signal CK(3); and the GOA units of the other GOA circuit are connected to each other.
- Two clock signals a second clock signal CK(2) and a fourth clock signal CK(4).
- first, second, third, and fourth clock signals CK(1), CK(2), CK(3), and CK(4) have the same pulse period, and the first clock A falling edge of the signal CK(1) is generated simultaneously with a rising edge of the second clock signal CK(2), and a falling edge of the second clock signal CK(2) is opposite to the third clock signal CK ( The rising edge of 3) is simultaneously generated, and the falling edge of the third clock signal CK(3) is simultaneously generated with the rising edge of the fourth clock signal CK(4), and the fourth clock signal CK(4) The falling edge of ) is generated simultaneously with the rising edge of the first clock signal CK(1).
- the first clock signal CK(1) and the third clock signal CK(3) are respectively taken as the output clock signal CK and the control clock signal XCK; on the other side of the GOA circuit
- the second clock signal CK(2) and the fourth clock signal CK(4) are respectively taken as the output clock signal CK and the control clock signal XCK.
- the control clock signal XCK and the output signal G(n-1) of the n-1th stage GOA unit provide a high potential
- the first thin film transistor T1 and the eighth thin film transistor T8 are turned on
- the second thin film transistor T2 is subjected to a constant voltage high potential.
- the control of VGH is always on, the third node K(n), the first node Q(n) and the second node P(n) are charged to a high potential;
- the tenth thin film transistor T10 is turned on, and the fourth node H(n) is pulled down to At a low potential, the sixth thin film transistor T6 controlled by the fourth node H(n) is turned off.
- the control clock signal XCK and the output signal G(n-1) of the n-1th stage GOA unit are both turned to a low potential, and at the same time, the output clock signal CK provides a high potential, first, eighth, and tenth.
- the thin film transistors T1, T8, and T10 are turned off, the first node Q(n) is kept at a high potential by the storage of the first capacitor C1, and the third thin film transistor T3 is turned on, and the high potential of the output clock signal CK is used as the nth-level GOA unit.
- the output signal G(n) is output, and the first node Q(n) is raised to a higher potential; the fourth thin film transistor T4 is turned on, and the second node P(n) is pulled low to the low potential control clock signal XCK. Potential, turn off the fifth and seventh thin film transistors T5, T7 to ensure G(n) normal output; the ninth thin film transistor T9 is controlled by the high potential output clock signal CK, and the fourth node H(n) is charged to a high potential;
- control clock signal XCK is again supplied with a high potential
- the eighth thin film transistor T8 is turned on, the second node P(n) is charged to a high potential, the fifth thin film transistor T5 is turned on, and the output signal G(n) is pulled down to a low potential;
- the thin film transistor T7 is turned on, and the fourth node H(n) is at the third capacitor C3.
- the memory remains high and the sixth thin film transistor is turned on, pulling the third node K(n) and the first node Q(n) low and stabilizing at a low potential.
- the waveforms of the respective nodes are stable, and are suitable for the display panel of the bilaterally driven progressive scan architecture.
- the second embodiment shown in FIG. 7 is similar to the specific working process of the first embodiment, and only needs to change the potential of each signal and node, and details are not described herein again.
- the control clock signal XCK and the output signal G(n-2) of the n-2th stage GOA unit provide a high potential
- the first thin film transistor T1 and the eighth thin film transistor T8 are turned on
- the second thin film transistor T2 is subjected to a constant voltage high potential.
- the control of VGH is always on, the third node K(n), the first node Q(n) and the second node P(n) are charged to a high potential;
- the tenth thin film transistor T10 is turned on, and the fourth node H(n) is pulled down to At a low potential, the sixth thin film transistor T6 controlled by the fourth node H(n) is turned off.
- the control clock signal XCK and the output signal G(n-2) of the n-2th GOA unit are all outputted to a low potential, and the first node Q(n) remains high under the storage of the first capacitor C1.
- the potential, the first, tenth, and eighth thin film transistors T1, T10, and T8 are turned off, the fourth thin film transistor T4 controlled by the third node K(n) is turned on, and the second node P(n) is controlled by the low potential clock.
- the signal XCK is pulled low to a low potential
- the potential of the second node P(n) is pulled low
- the fifth and seventh thin film transistors T5, T7 are turned off
- the fourth node H(n) remains low under the storage of the third capacitor C3.
- the potential, the sixth thin film transistor T6 controlled by the fourth node H(n) is still turned off, blocking the leakage path of the first node Q(n), and performing leakage protection on the first node Q(n).
- the output clock signal CK provides a high potential
- the first, eighth and tenth thin film transistors T1, T8, T10 are still turned off, and the first node Q(n) remains high under the storage of the first capacitor C1
- the three thin film transistor T3 is turned on, and the high potential of the output clock signal CK is output as the output signal G(n) of the nth stage GOA unit, and the first node Q(n) is raised to a higher potential
- the fourth thin film transistor T4 is still Open, the second node P(n) is still low, turning off the fifth and seventh thin film transistors to ensure G(n) normal output
- the ninth thin film transistor T9 is controlled by the high potential output clock signal CK, fourth Node H(n) is charged to a high potential;
- the control clock signal XCK is again supplied with a high potential, the eighth thin film transistor T8 is turned on, the second node P(n) is charged to a high potential, the fifth thin film transistor T5 is turned on, and the output signal G(n) is pulled down to a low potential;
- the thin film transistor T7 is turned on, the fourth node H(n) is kept at a high potential by the storage of the third capacitor C3, and the sixth thin film transistor is turned on to pull the third node K(n) and the first node Q(n) low. Stable at low potential.
- the first node Q(n) has leakage protection during the period of maintaining a high potential, and is suitable for a display panel of a bilaterally driven progressive scan architecture.
- the fourth embodiment shown in FIG. 9 is similar to the specific working process of the third embodiment described above, and only needs to change the potential of each signal and node, and details are not described herein again.
- the GOA circuit for a narrow-border liquid crystal display panel of the present invention adds a first node leakage protection unit composed of a ninth thin film transistor, a tenth thin film transistor, and a third capacitor, wherein the ninth thin film transistor
- the gate and the source are electrically connected to the output clock signal to form a diode structure, and the third capacitor and the fourth node are charged to a high potential during the output period, and the tenth thin film transistor clears the fourth node during the signal level transmission.
- the GOA circuit is applicable to both the bilateral driving progressive scanning architecture and the bilateral driving interlaced scanning architecture, and can prevent the first node from leaking when applied to the bilateral driving interlaced scanning architecture, ensuring The circuit works stably, greatly improving the reliability of the GOA circuit, and only two clock signals are provided on each side, which is beneficial to the design of the narrow bezel display panel.
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Abstract
一种用于窄边框液晶显示面板的GOA电路,增设了由第九薄膜晶体管(T9)、第十薄膜晶体管(T10)、及第三电容(C3)构成的第一节点漏电防护单元(700);第九薄膜晶体管(T9)栅极与源极均与输出时钟信号(CK)电性连接,形成二极管结构,在输出期间将第三电容(C3)及第四节点(H(n))充电至高电位,第十薄膜晶体管(T10)在信号级传期间对第四节点(H(n))进行清零处理,保证第一节点(Q(n))的正常充电;该GOA电路既适用于双边驱动逐行扫描架构,又适用于双边驱动隔行扫描架构,在应用于双边驱动隔行扫描架构时,能够防止第一节点漏电,保证电路稳定工作,大幅提高GOA电路的可靠性,且每一边均只设置两条时钟信号,有利于窄边框显示面板的设计。
Description
本发明涉及显示技术领域,尤其涉及一种用于窄边框液晶显示面板的GOA电路。
液晶显示器(Liquid Crystal Display,LCD)具有机身薄、省电、无辐射等众多优点,得到了广泛的应用。如:液晶电视、移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等,在平板显示领域中占主导地位。
GOA技术(Gate Driver on Array)即阵列基板行驱动技术,是运用液晶显示面板的原有阵列制程将水平扫描线的驱动电路制作在显示区周围的基板上,使之能替代外接集成电路板((Integrated Circuit,IC)来完成水平扫描线的驱动。GOA技术能减少外接IC的焊接(bonding)工序,有机会提升产能并降低产品成本,而且可以使液晶显示面板更适合制作窄边框或无边框的显示产品。
随着低温多晶硅(Low Temperature Poly-silicon,LTPS)半导体薄膜晶体管的发展,LTPS-TFT液晶显示器也越来越受关注,LTPS-TFT液晶显示器具有高分辨率、反应速度快、高亮度、高开口率等优点。由于低温多晶硅较非晶硅(a-Si)的排列有次序,低温多晶硅半导体本身具有超高的电子迁移率,比非晶硅半导体相对高100倍以上,可以采用GOA技术将栅极驱动器制作在薄膜晶体管阵列基板上,达到系统整合的目标、节省空间及驱动IC的成本。
请参阅图1,现有的一种常见的GOA电路包括:级联的多级GOA单元,每一级GOA单元均包括:控制输入单元100、稳压单元200、控制输出单元300、下拉维持单元400、下拉单元500、及第二节点控制单元600,设n为正整数,除第一级GOA单元外,在第n级GOA单元中:
所述控制输入单元100包括:第一薄膜晶体管T1,所述第一薄膜晶体管T1的栅极电性连接于控制时钟信号XCK,源极电性连接于上一级第n-1级GOA单元的输出端G(n-1),漏极电性连接于第三节点K(n);
所述稳压单元200包括:第二薄膜晶体管T2,所述第二薄膜晶体管T2的栅极电性连接恒压高电位VGH,源极电性连接于第三节点K(n),漏极电
性连接于第一节点Q(n);
所述控制输出单元300包括:第三薄膜晶体管T3,所述第三薄膜晶体管T3的栅极电性连接于第一节点Q(n),源极电性连接于输出时钟信号CK,漏极电性连接于输出端G(n);以及第一电容C1,所述第一电容C1的一端电性连接于第一节点Q(n),另一端电性连接于输出端G(n);
所述下拉维持单元400包括:第五薄膜晶体管T5,所述第五薄膜晶体管T5的栅极电性连接于第二节点P(n),源极电性连接于输出端G(n),漏极电性连接于恒压低电位VGL;以及第二电容C2,所述第二电容C2的一端电性连接于第二节点P(n),另一端电性连接于恒压低电位VGL;
所述下拉单元500包括:第六薄膜晶体管T6,所述第六薄膜晶体管T6的栅极电性连接于输出时钟信号CK,源极电性连接于第三节点K(n),漏极电性连接于第七薄膜晶体管T7的源极;以及第七薄膜晶体管T7,所述第七薄膜晶体管T7的栅极电性连接于第二节点P(n),漏极电性连接于恒压低电位VGL;
所述第二节点控制单元600包括:第四薄膜晶体管T4,所述第四薄膜晶体管T4的栅极电性连接于第三节点K(n),源极电性连接于控制时钟信号XCK,漏极电性连接于第二节点P(n);以及第八薄膜晶体管T8,所述第八薄膜晶体管T8的栅极电性连接于控制时钟信号XCK,源极电性连接于恒压高电位VGH,漏极电性连接于第二节点P(n)。
图2所示为双边驱动逐行扫描的GOA电路的架构示意图,在显示面板左、右两边分别设置一GOA电路,每一GOA电路均包括第一级至最后一级GOA单元,两边的GOA电路的时序相同,每一边的各级GOA电路均接入第一时钟信号CK(1)和第二时钟信号CK(2)分别轮流作为控制时钟信号XCK和输出时钟信号CK,每一边的GOA电路均按照像素排列顺序逐行扫描,两边同级的GOA单元共同作用于同一行像素的驱动。请参阅图3,图1所示的GOA电路进行双边驱动逐行扫描时,各级GOA单元内的第一节点Q(n)、第二节点P(n)、输出端G(n)的波形都是稳定的,因此图1所示的GOA电路能够在双边驱动逐行扫描架构下稳定工作。
图4所示为双边驱动隔行扫描的GOA电路的架构示意图,在显示面板左、右两边分别设置一GOA电路,一边的GOA电路仅包括奇数级GOA单元,另一边的GOA电路仅包括偶数级GOA单元。两边GOA电路的时序不同,其中一边的各级GOA电路接入第一时钟信号CK(1)和第三时钟信号CK(3)分别轮流作为控制时钟信号XCK和输出时钟信号CK,对奇数行像素进行逐行扫描;另一边的各级GOA电路接入第二时钟信号CK(2)和第
三时钟信号CK(4)分别轮流作为控制时钟信号XCK和输出时钟信号CK,对偶数行像素进行逐行扫描。请参阅图5,图1所示的GOA电路进行双边驱动隔行扫描时,电路中存在很多不稳定的因素,这是因为每一边的两条时钟信号不连续,而该现有的GOA电路中也没有设置任何对第一节点Q(n)进行漏电防护的设计。第一节点Q(n)出现漏电会造成GOA电路失效的问题,且在输出端G(n)输出完成后存在控制时钟信号XCK与输出时钟信号CK同时为低电位的盲区,也会导致GOA电路不稳定,严重时可能造成GOA电路失效。因此,图1所示的现有的GOA电路在双边驱动隔行扫描架构下不能稳定工作,需进行改进。
发明内容
本发明的目的在于提供一种用于窄边框液晶显示面板的GOA电路,既适用于双边驱动逐行扫描架构,又适用于双边驱动隔行扫描架构,在应用于双边驱动隔行扫描架构时,能够防止第一节点漏电,保证电路稳定工作,大幅提高GOA电路的可靠性。
为实现上述目的,本发明提供了一种用于窄边框液晶显示面板的GOA电路,包括:级联的多级GOA单元,每一级GOA单元均包括:控制输入单元、稳压单元、控制输出单元、下拉维持单元、下拉单元、第二节点控制单元、及第一节点漏电防护单元;
设n为正整数,在第n级GOA单元中:
所述控制输入单元包括:第一薄膜晶体管,所述第一薄膜晶体管的栅极电性连接于级传信号,源极电性连接于第一恒压电位,漏极电性连接于第三节点;
所述稳压单元包括:第二薄膜晶体管,所述第二薄膜晶体管的栅极电性连接于第一恒压电位,源极电性连接于第三节点,漏极电性连接于第一节点;
所述控制输出单元包括:第三薄膜晶体管,所述第三薄膜晶体管的栅极电性连接于第一节点,源极电性连接于输出时钟信号,漏极电性连接于输出端;以及第一电容,所述第一电容的一端电性连接于第一节点,另一端电性连接于输出端;
所述下拉维持单元包括:第五薄膜晶体管,所述第五薄膜晶体管的栅极电性连接于第二节点,源极电性连接于输出端,漏极电性连接于第二恒压电位;以及第二电容,所述第二电容的一端电性连接于第二节点,另一端电性连接于第二恒压电位;
所述下拉单元包括:第六薄膜晶体管,所述第六薄膜晶体管的栅极电性连接于第四节点,源极电性连接于第三节点,漏极电性连接于第七薄膜晶体管的源极;以及第七薄膜晶体管,所述第七薄膜晶体管的栅极电性连接于第二节点,漏极电性连接于第二恒压电位;
所述第二节点控制单元包括:第四薄膜晶体管,所述第四薄膜晶体管的栅极电性连接于第三节点,源极电性连接于控制时钟信号,漏极电性连接于第二节点;以及第八薄膜晶体管,所述第八薄膜晶体管的栅极电性连接于控制时钟信号,源极电性连接于第一恒压电位,漏极电性连接于第二节点;
所述第一节点漏电防护单元包括:第九薄膜晶体管,所述第九薄膜晶体管的栅极与源极均电性连接于输出时钟信号,漏极电性连接于第四节点;第十薄膜晶体管,所述第十薄膜晶体管的栅极电性连接于级传信号,源极电性连接于第四节点,漏极电性连接于第二恒压电位;以及第三电容,所述第三电容的一端电性连接于第四节点,漏极电性连接于第二恒压电位。
可选的,各个薄膜晶体管均为N型低温多晶硅半导体薄膜晶体管,所述第一恒压电位为恒压高电位,第二恒压电位为恒压低电位。
可选的,各个薄膜晶体管均为P型低温多晶硅半导体薄膜晶体管,所述第一恒压电位为恒压低电位,第二恒压电位为恒压高电位。
所述用于窄边框液晶显示面板的GOA电路可应用于双边驱动逐行扫描架构的显示面板,显示面板左、右两边分别设置一GOA电路,每一边的GOA电路均包括第一级至最后一级GOA单元;每一边的各级GOA单元均接入两条时钟信号:第一条时钟信号和第二条时钟信号,所述第一条时钟信号和第二条时钟信号的相位相反。
在各级GOA单元中,所述第一条时钟信号和第二条时钟信号分别轮流作为输出时钟信号和控制时钟信号。
除第一级GOA单元外,第n级GOA单元的级传信号为上一级第n-1级GOA单元的输出信号;
第一级GOA单元的级传信号为电路起始信号。
所述用于窄边框液晶显示面板的GOA电路还可应用于双边驱动隔行扫描架构的显示面板,显示面板左、右两边分别设置一GOA电路,一边的GOA电路仅包括奇数级GOA单元,另一边的GOA电路仅包括偶数级GOA单元;
其中一边GOA电路的各级GOA单元均接入两条时钟信号:第一条时钟信号和第三条时钟信号;
另一边GOA电路的各级GOA单元均接入另两条时钟信号,第二条时钟信号和第四条时钟信号。
所述第一、第二、第三、及第四条时钟信号的脉冲周期相同,所述第一条时钟信号的下降沿与所述第二条时钟信号的上升沿同时产生,所述第二条时钟信号的下降沿与所述第三条时钟信号的上升沿同时产生,所述第三条时钟信号的下降沿与所述第四条时钟信号的上升沿同时产生,所述第四条时钟信号的下降沿与所述第一条时钟信号的上升沿同时产生。
在一边GOA电路的各级GOA单元中,所述第一条时钟信号和第三条时钟信号分别轮流作为输出时钟信号和控制时钟信号;在另一边GOA电路的各级GOA单元中,所述第二条时钟信号和第四条时钟信号分别轮流作为输出时钟信号和控制时钟信号。
除第一级和第二级GOA单元外,第n级GOA单元的级传信号为上两级第n-2级GOA单元的输出信号;
第一级和第二级GOA单元的级传信号均为电路起始信号。
本发明还提供一种用于窄边框液晶显示面板的GOA电路,包括:级联的多级GOA单元,每一级GOA单元均包括:控制输入单元、稳压单元、控制输出单元、下拉维持单元、下拉单元、第二节点控制单元、及第一节点漏电防护单元;
设n为正整数,在第n级GOA单元中:
所述控制输入单元包括:第一薄膜晶体管,所述第一薄膜晶体管的栅极电性连接于级传信号,源极电性连接于第一恒压电位,漏极电性连接于第三节点;
所述稳压单元包括:第二薄膜晶体管,所述第二薄膜晶体管的栅极电性连接于第一恒压电位,源极电性连接于第三节点,漏极电性连接于第一节点;
所述控制输出单元包括:第三薄膜晶体管,所述第三薄膜晶体管的栅极电性连接于第一节点,源极电性连接于输出时钟信号,漏极电性连接于输出端;以及第一电容,所述第一电容的一端电性连接于第一节点,另一端电性连接于输出端;
所述下拉维持单元包括:第五薄膜晶体管,所述第五薄膜晶体管的栅极电性连接于第二节点,源极电性连接于输出端,漏极电性连接于第二恒压电位;以及第二电容,所述第二电容的一端电性连接于第二节点,另一端电性连接于第二恒压电位;
所述下拉单元包括:第六薄膜晶体管,所述第六薄膜晶体管的栅极电
性连接于第四节点,源极电性连接于第三节点,漏极电性连接于第七薄膜晶体管的源极;以及第七薄膜晶体管,所述第七薄膜晶体管的栅极电性连接于第二节点,漏极电性连接于第二恒压电位;
所述第二节点控制单元包括:第四薄膜晶体管,所述第四薄膜晶体管的栅极电性连接于第三节点,源极电性连接于控制时钟信号,漏极电性连接于第二节点;以及第八薄膜晶体管,所述第八薄膜晶体管的栅极电性连接于控制时钟信号,源极电性连接于第一恒压电位,漏极电性连接于第二节点;
所述第一节点漏电防护单元包括:第九薄膜晶体管,所述第九薄膜晶体管的栅极与源极均电性连接于输出时钟信号,漏极电性连接于第四节点;第十薄膜晶体管,所述第十薄膜晶体管的栅极电性连接于级传信号,源极电性连接于第四节点,漏极电性连接于第二恒压电位;以及第三电容,所述第三电容的一端电性连接于第四节点,漏极电性连接于第二恒压电位;
其中,应用于双边驱动逐行扫描架构的显示面板,显示面板左、右两边分别设置一GOA电路,每一边的GOA电路均包括第一级至最后一级GOA单元;每一边的各级GOA单元均接入两条时钟信号:第一条时钟信号和第二条时钟信号,所述第一条时钟信号和第二条时钟信号的相位相反;
其中,在各级GOA单元中,所述第一条时钟信号和第二条时钟信号分别轮流作为输出时钟信号和控制时钟信号;
其中,除第一级GOA单元外,第n级GOA单元的级传信号为上一级第n-1级GOA单元的输出信号;
第一级GOA单元的级传信号为电路起始信号。
本发明的有益效果:本发明提供的一种用于窄边框液晶显示面板的GOA电路,增设了由第九薄膜晶体管、第十薄膜晶体管、及第三电容构成的第一节点漏电防护单元,其中第九薄膜晶体管的栅极与源极均与输出时钟信号电性连接,形成二极管结构,在输出期间将第三电容及第四节点充电至高电位,第十薄膜晶体管在信号级传期间对第四节点进行清零处理,保证第一节点的正常充电,该GOA电路既适用于双边驱动逐行扫描架构,又适用于双边驱动隔行扫描架构,在应用于双边驱动隔行扫描架构时,能够防止第一节点漏电,保证电路稳定工作,大幅提高GOA电路的可靠性,且每一边均只设置两条时钟信号,有利于窄边框显示面板的设计。
为了能更进一步了解本发明的特征以及技术内容,请参阅以下有关本
发明的详细说明与附图,然而附图仅提供参考与说明用,并非用来对本发明加以限制。
附图中,
图1为现有的一种常见的GOA电路的电路示意图;
图2为现有的双边驱动逐行扫描的GOA电路的架构示意图;
图3为图1所示GOA电路应用于图2所示架构时的时序图;
图4为现有的双边驱动隔行扫描的GOA电路的架构示意图;
图5为图1所示GOA电路应用于图4所示架构时的时序图;
图6为本发明的用于窄边框液晶显示面板的GOA电路的第一实施例的电路图;
图7为本发明的用于窄边框液晶显示面板的GOA电路的第二实施例的电路图;
图8为本发明的用于窄边框液晶显示面板的GOA电路的第三实施例的电路图;
图9为本发明的用于窄边框液晶显示面板的GOA电路的第四实施例的电路图;
图10为本发明的用于窄边框液晶显示面板的GOA电路的第一和第三实施例中第一级GOA单元的电路图;
图11为本发明的用于窄边框液晶显示面板的GOA电路的第二和第四实施例中第一级GOA单元的电路图;
图12为本发明的用于窄边框液晶显示面板的GOA电路的第三实施例中第二级GOA单元的电路图;
图13为本发明的用于窄边框液晶显示面板的GOA电路的第四实施例中第二级GOA单元的电路图;
图14为本发明的用于窄边框液晶显示面板的GOA电路的第一实施例应用于图2所示双边驱动逐行扫描架构的时序图;
图15为本发明的用于窄边框液晶显示面板的GOA电路的第三实施例应用于图4所示双边驱动隔行扫描架构的时序图。
为更进一步阐述本发明所采取的技术手段及其效果,以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图6、图7、图8、或图9,本发明提供一种用于窄边框液晶显示面板的GOA电路,包括:级联的多级GOA单元,每一级GOA单元均
包括:控制输入单元100、稳压单元200、控制输出单元300、下拉维持单元400、下拉单元500、第二节点控制单元600、及第一节点漏电防护单元700。
设n为正整数,在第n级GOA单元中:
所述控制输入单元100包括:第一薄膜晶体管T1,所述第一薄膜晶体管T1的栅极电性连接于级传信号,源极电性连接于第一恒压电位,漏极电性连接于第三节点K(n);
所述稳压单元200包括:第二薄膜晶体管T2,所述第二薄膜晶体管T2的栅极电性连接于第一恒压电位,源极电性连接于第三节点K(n),漏极电性连接于第一节点Q(n);
所述控制输出单元300包括:第三薄膜晶体管T3,所述第三薄膜晶体管T3的栅极电性连接于第一节点Q(n),源极电性连接于输出时钟信号CK,漏极电性连接于输出端G(n);以及第一电容C1,所述第一电容C1的一端电性连接于第一节点Q(n),另一端电性连接于输出端G(n);
所述下拉维持单元400包括:第五薄膜晶体管T5,所述第五薄膜晶体管T5的栅极电性连接于第二节点P(n),源极电性连接于输出端G(n),漏极电性连接于第二恒压电位;以及第二电容C2,所述第二电容C2的一端电性连接于第二节点P(n),另一端电性连接于第二恒压电位;
所述下拉单元500包括:第六薄膜晶体管T6,所述第六薄膜晶体管T6的栅极电性连接于第四节点H(n),源极电性连接于第三节点K(n),漏极电性连接于第七薄膜晶体管T7的源极;以及第七薄膜晶体管T7,所述第七薄膜晶体管T7的栅极电性连接于第二节点P(n),漏极电性连接于第二恒压电位;
所述第二节点控制单元600包括:
第四薄膜晶体管T4,所述第四薄膜晶体管T4的栅极电性连接于第三节点K(n),源极电性连接于控制时钟信号XCK,漏极电性连接于第二节点P(n);以及第八薄膜晶体管T8,所述第八薄膜晶体管T8的栅极电性连接于控制时钟信号XCK,源极电性连接于第一恒压电位,漏极电性连接于第二节点P(n);
所述第一节点漏电防护单元700包括:第九薄膜晶体管T9,所述第九薄膜晶体管T9的栅极与源极均电性连接于输出时钟信号CK,漏极电性连接于第四节点H(n);第十薄膜晶体管T10,所述第十薄膜晶体管T10的栅极电性连接于级传信号,源极电性连接于第四节点H(n),漏极电性连接于第二恒压电位;以及第三电容C3,所述第三电容C3的一端电性连接于第
四节点H(n),漏极电性连接于第二恒压电位。
具体地,在图6所示的本发明的用于窄边框液晶显示面板的GOA电路的第一实施例中,各个薄膜晶体管均为N型低温多晶硅半导体薄膜晶体管;所述第一恒压电位为恒压高电位VGH,第二恒压电位为恒压低电位VGL;除第一级GOA单元外,第n级GOA单元的级传信号为上一级第n-1级GOA单元的输出信号G(n-1),特别地,如图10所示,第一级GOA单元的级传信号为电路起始信号STV。
在图7所示的本发明的用于窄边框液晶显示面板的GOA电路的第二实施例中,各个薄膜晶体管均为P型低温多晶硅半导体薄膜晶体管;所述第一恒压电位为恒压低电位VGL,第二恒压电位为恒压高电位VGH;除第一级GOA单元外,第n级GOA单元的级传信号为上一级第n-1级GOA单元的输出信号G(n-1),特别地,如图11所示,第一级GOA单元的级传信号为电路起始信号STV。
所述第一与第二实施例适用于如图2所示的应用于双边驱动逐行扫描架构的显示面板,即显示面板左、右两边分别设置一GOA电路,每一边的GOA电路均包括第一级至最后一级GOA单元;每一边的各级GOA单元均接入两条时钟信号:第一条时钟信号CK(1)和第二条时钟信号CK(2),所述第一条时钟信号CK(1)和第二条时钟信号CK(2)的相位相反。在各级GOA单元中,所述第一条时钟信号CK(1)和第二条时钟信号CK(2)分别轮流作为输出时钟信号CK和控制时钟信号XCK。
在图8所示的本发明的用于窄边框液晶显示面板的GOA电路的第三实施例中,各个薄膜晶体管均为N型低温多晶硅半导体薄膜晶体管;所述第一恒压电位为恒压高电位VGH,第二恒压电位为恒压低电位VGL;除第一级和第二级GOA单元外,第n级GOA单元的级传信号为上两级第n-2级GOA单元的输出信号G(n-2),特别地,如图10、图12所示,第一级和第二级GOA单元的级传信号均为电路起始信号STV。
在图9所示的本发明的用于窄边框液晶显示面板的GOA电路的第四实施例中,各个薄膜晶体管均为P型低温多晶硅半导体薄膜晶体管;所述第一恒压电位为恒压低电位VGL,第二恒压电位为恒压高电位VGH;除第一级和第二级GOA单元外,第n级GOA单元的级传信号为上两级第n-2级GOA单元的输出信号G(n-2),特别地,如图11、图13所示,第一级和第二级GOA单元的级传信号均为电路起始信号STV。
所述第三与第四实施例适用于如图4所示的双边驱动隔行扫描架构的显示面板,即显示面板左、右两边分别设置一GOA电路,一边的GOA电
路仅包括奇数级GOA单元,用于对奇数行像素进行扫描,另一边的GOA电路仅包括偶数级GOA单元,用于对偶数行像素进行扫描。其中一边GOA电路的各级GOA单元均接入两条时钟信号:第一条时钟信号CK(1)和第三条时钟信号CK(3);另一边GOA电路的各级GOA单元均接入另两条时钟信号:第二条时钟信号CK(2)和第四条时钟信号CK(4)。进一步的,所述第一、第二、第三、及第四条时钟信号CK(1)、CK(2)、CK(3)、CK(4)的脉冲周期相同,所述第一条时钟信号CK(1)的下降沿与所述第二条时钟信号CK(2)的上升沿同时产生,所述第二条时钟信号CK(2)的下降沿与所述第三条时钟信号CK(3)的上升沿同时产生,所述第三条时钟信号CK(3)的下降沿与所述第四条时钟信号CK(4)的上升沿同时产生,所述第四条时钟信号CK(4)的下降沿与所述第一条时钟信号CK(1)的上升沿同时产生。在一边GOA电路的各级GOA单元中,所述第一条时钟信号CK(1)和第三条时钟信号CK(3)分别轮流作为输出时钟信号CK和控制时钟信号XCK;在另一边GOA电路的各级GOA单元中,所述第二条时钟信号CK(2)和第四条时钟信号CK(4)分别轮流作为输出时钟信号CK和控制时钟信号XCK。
请同时参阅图6与图14,并结合图2,本发明的用于窄边框液晶显示面板的GOA电路的第一实施例的具体工作过程为:
首先,控制时钟信号XCK及第n-1级GOA单元的输出信号G(n-1)提供高电位,第一薄膜晶体管T1和第八薄膜晶体管T8打开,第二薄膜晶体管T2受恒压高电位VGH的控制始终打开,第三节点K(n)、第一节点Q(n)和第二节点P(n)充电至高电位;第十薄膜晶体管T10打开,拉低第四节点H(n)至低电位,关闭受第四节点H(n)控制的第六薄膜晶体管T6。
紧接着,控制时钟信号XCK及第n-1级GOA单元的输出信号G(n-1)均转变为低电位,于此同时,输出时钟信号CK提供高电位,第一、第八和第十薄膜晶体管T1、T8、T10关闭,第一节点Q(n)在第一电容C1的存储作用下保持高电位,第三薄膜晶体管T3打开,将输出时钟信号CK的高电位作为第n级GOA单元的输出信号G(n)输出,并将第一节点Q(n)抬升至更高电位;第四薄膜晶体管T4打开,第二节点P(n)被低电位的控制时钟信号XCK拉低至低电位,关闭第五和第七薄膜晶体管T5、T7,保证G(n)正常输出;第九薄膜晶体管T9受高电位的输出时钟信号CK的控制打开,第四节点H(n)充电至高电位;
随后,控制时钟信号XCK再次提供高电位,第八薄膜晶体管T8打开,第二节点P(n)被充电至高电位,第五薄膜晶体管T5打开,下拉输出信号G(n)至低电位;第七薄膜晶体管T7打开,第四节点H(n)在第三电容C3的
存储作用下保持高电位,第六薄膜晶体管打开,将第三节点K(n)和第一节点Q(n)拉低并稳定在低电位。
可见,该第一实施例在工作过程中,各个节点的波形都是稳定的,适用于双边驱动逐行扫描架构的显示面板。
图7所示的第二实施例与上述第一实施例的具体工作过程类似,仅需要将各信号、节点的电位高低进行调换即可,此处不再赘述。
请同时参阅图8与图15,并结合图4,本发明的用于窄边框液晶显示面板的GOA电路的第三实施例的具体工作过程为:
首先,控制时钟信号XCK及第n-2级GOA单元的输出信号G(n-2)提供高电位,第一薄膜晶体管T1和第八薄膜晶体管T8打开,第二薄膜晶体管T2受恒压高电位VGH的控制始终打开,第三节点K(n)、第一节点Q(n)和第二节点P(n)充电至高电位;第十薄膜晶体管T10打开,拉低第四节点H(n)至低电位,关闭受第四节点H(n)控制的第六薄膜晶体管T6。
紧接着,控制时钟信号XCK与第n-2级GOA单元的输出信号G(n-2)输出完毕均转变为低电位,第一节点Q(n)在第一电容C1的存储作用下保持高电位,第一、第十、和第八薄膜晶体管T1、T10、T8关闭,受第三节点K(n)控制的第四薄膜晶体管T4打开,第二节点P(n)被低电位的控制时钟信号XCK拉低至低电位,拉低第二节点P(n)的电位,关闭第五和第七薄膜晶体管T5、T7,第四节点H(n)在第三电容C3的存储作用下保持低电位,受第四节点H(n)控制的第六薄膜晶体管T6仍关闭,阻断了第一节点Q(n)的漏电路径,对第一节点Q(n)进行漏电防护。
随后,输出时钟信号CK提供高电位,第一、第八和第十薄膜晶体管T1、T8、T10仍关闭,第一节点Q(n)在第一电容C1的存储作用下仍保持高电位,第三薄膜晶体管T3打开,将输出时钟信号CK的高电位作为第n级GOA单元的输出信号G(n)输出,并将第一节点Q(n)抬升至更高电位;第四薄膜晶体管T4仍打开,第二节点P(n)仍为低电位,关闭第五和第七薄膜晶体管,保证G(n)正常输出;第九薄膜晶体管T9受高电位的输出时钟信号CK的控制打开,第四节点H(n)充电至高电位;
然后,控制时钟信号XCK再次提供高电位,第八薄膜晶体管T8打开,第二节点P(n)被充电至高电位,第五薄膜晶体管T5打开,下拉输出信号G(n)至低电位;第七薄膜晶体管T7打开,第四节点H(n)在第三电容C3的存储作用下保持高电位,第六薄膜晶体管打开,将第三节点K(n)和第一节点Q(n)拉低并稳定在低电位。
可见,该第三实施例在工作过程中,各个节点的波形都是稳定的,在
第一节点Q(n)维持高电位的期间有漏电防护,适用于双边驱动逐行扫描架构的显示面板。
图9所示的第四实施例与上述第三实施例的具体工作过程类似,仅需要将各信号、节点的电位高低进行调换即可,此处不再赘述。
综上所述,本发明的用于窄边框液晶显示面板的GOA电路,增设了由第九薄膜晶体管、第十薄膜晶体管、及第三电容构成的第一节点漏电防护单元,其中第九薄膜晶体管的栅极与源极均与输出时钟信号电性连接,形成二极管结构,在输出期间将第三电容及第四节点充电至高电位,第十薄膜晶体管在信号级传期间对第四节点进行清零处理,保证第一节点的正常充电,该GOA电路既适用于双边驱动逐行扫描架构,又适用于双边驱动隔行扫描架构,在应用于双边驱动隔行扫描架构时,能够防止第一节点漏电,保证电路稳定工作,大幅提高GOA电路的可靠性,且每一边均只设置两条时钟信号,有利于窄边框显示面板的设计。
以上所述,对于本领域的普通技术人员来说,可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形,而所有这些改变和变形都应属于本发明权利要求的保护范围。
Claims (13)
- 一种用于窄边框液晶显示面板的GOA电路,包括:级联的多级GOA单元,每一级GOA单元均包括:控制输入单元、稳压单元、控制输出单元、下拉维持单元、下拉单元、第二节点控制单元、及第一节点漏电防护单元;设n为正整数,在第n级GOA单元中:所述控制输入单元包括:第一薄膜晶体管,所述第一薄膜晶体管的栅极电性连接于级传信号,源极电性连接于第一恒压电位,漏极电性连接于第三节点;所述稳压单元包括:第二薄膜晶体管,所述第二薄膜晶体管的栅极电性连接于第一恒压电位,源极电性连接于第三节点,漏极电性连接于第一节点;所述控制输出单元包括:第三薄膜晶体管,所述第三薄膜晶体管的栅极电性连接于第一节点,源极电性连接于输出时钟信号,漏极电性连接于输出端;以及第一电容,所述第一电容的一端电性连接于第一节点,另一端电性连接于输出端;所述下拉维持单元包括:第五薄膜晶体管,所述第五薄膜晶体管的栅极电性连接于第二节点,源极电性连接于输出端,漏极电性连接于第二恒压电位;以及第二电容,所述第二电容的一端电性连接于第二节点,另一端电性连接于第二恒压电位;所述下拉单元包括:第六薄膜晶体管,所述第六薄膜晶体管的栅极电性连接于第四节点,源极电性连接于第三节点,漏极电性连接于第七薄膜晶体管的源极;以及第七薄膜晶体管,所述第七薄膜晶体管的栅极电性连接于第二节点,漏极电性连接于第二恒压电位;所述第二节点控制单元包括:第四薄膜晶体管,所述第四薄膜晶体管的栅极电性连接于第三节点,源极电性连接于控制时钟信号,漏极电性连接于第二节点;以及第八薄膜晶体管,所述第八薄膜晶体管的栅极电性连接于控制时钟信号,源极电性连接于第一恒压电位,漏极电性连接于第二节点;所述第一节点漏电防护单元包括:第九薄膜晶体管,所述第九薄膜晶体管的栅极与源极均电性连接于输出时钟信号,漏极电性连接于第四节点;第十薄膜晶体管,所述第十薄膜晶体管的栅极电性连接于级传信号,源极电性连接于第四节点,漏极电性连接于第二恒压电位;以及第三电容,所 述第三电容的一端电性连接于第四节点,漏极电性连接于第二恒压电位。
- 如权利要求1所述的用于窄边框液晶显示面板的GOA电路,其中,各个薄膜晶体管均为N型低温多晶硅半导体薄膜晶体管,所述第一恒压电位为恒压高电位,第二恒压电位为恒压低电位。
- 如权利要求1所述的用于窄边框液晶显示面板的GOA电路,其中,各个薄膜晶体管均为P型低温多晶硅半导体薄膜晶体管,所述第一恒压电位为恒压低电位,第二恒压电位为恒压高电位。
- 如权利要求1所述的用于窄边框液晶显示面板的GOA电路,其中,应用于双边驱动逐行扫描架构的显示面板,显示面板左、右两边分别设置一GOA电路,每一边的GOA电路均包括第一级至最后一级GOA单元;每一边的各级GOA单元均接入两条时钟信号:第一条时钟信号和第二条时钟信号,所述第一条时钟信号和第二条时钟信号的相位相反。
- 如权利要求4所述的用于窄边框液晶显示面板的GOA电路,其中,在各级GOA单元中,所述第一条时钟信号和第二条时钟信号分别轮流作为输出时钟信号和控制时钟信号。
- 如权利要求4所述的用于窄边框液晶显示面板的GOA电路,其中,除第一级GOA单元外,第n级GOA单元的级传信号为上一级第n-1级GOA单元的输出信号;第一级GOA单元的级传信号为电路起始信号。
- 如权利要求1所述的用于窄边框液晶显示面板的GOA电路,其中,应用于双边驱动隔行扫描架构的显示面板,显示面板左、右两边分别设置一GOA电路,一边的GOA电路仅包括奇数级GOA单元,另一边的GOA电路仅包括偶数级GOA单元;其中一边GOA电路的各级GOA单元均接入两条时钟信号:第一条时钟信号和第三条时钟信号;另一边GOA电路的各级GOA单元均接入另两条时钟信号:第二条时钟信号和第四条时钟信号。
- 如权利要求7所述的用于窄边框液晶显示面板的GOA电路,其中,所述第一、第二、第三、及第四条时钟信号的脉冲周期相同,所述第一条时钟信号的下降沿与所述第二条时钟信号的上升沿同时产生,所述第二条时钟信号的下降沿与所述第三条时钟信号的上升沿同时产生,所述第三条时钟信号的下降沿与所述第四条时钟信号的上升沿同时产生,所述第四条时钟信号的下降沿与所述第一条时钟信号的上升沿同时产生。
- 如权利要求7所述的用于窄边框液晶显示面板的GOA电路,其中,在一边GOA电路的各级GOA单元中,所述第一条时钟信号和第三条时钟 信号分别轮流作为输出时钟信号和控制时钟信号;在另一边GOA电路的各级GOA单元中,所述第二条时钟信号和第四条时钟信号分别轮流作为输出时钟信号和控制时钟信号。
- 如权利要求7所述的用于窄边框液晶显示面板的GOA电路,其中,除第一级和第二级GOA单元外,第n级GOA单元的级传信号为上两级第n-2级GOA单元的输出信号;第一级和第二级GOA单元的级传信号均为电路起始信号。
- 一种用于窄边框液晶显示面板的GOA电路,包括:级联的多级GOA单元,每一级GOA单元均包括:控制输入单元、稳压单元、控制输出单元、下拉维持单元、下拉单元、第二节点控制单元、及第一节点漏电防护单元;设n为正整数,在第n级GOA单元中:所述控制输入单元包括:第一薄膜晶体管,所述第一薄膜晶体管的栅极电性连接于级传信号,源极电性连接于第一恒压电位,漏极电性连接于第三节点;所述稳压单元包括:第二薄膜晶体管,所述第二薄膜晶体管的栅极电性连接于第一恒压电位,源极电性连接于第三节点,漏极电性连接于第一节点;所述控制输出单元包括:第三薄膜晶体管,所述第三薄膜晶体管的栅极电性连接于第一节点,源极电性连接于输出时钟信号,漏极电性连接于输出端;以及第一电容,所述第一电容的一端电性连接于第一节点,另一端电性连接于输出端;所述下拉维持单元包括:第五薄膜晶体管,所述第五薄膜晶体管的栅极电性连接于第二节点,源极电性连接于输出端,漏极电性连接于第二恒压电位;以及第二电容,所述第二电容的一端电性连接于第二节点,另一端电性连接于第二恒压电位;所述下拉单元包括:第六薄膜晶体管,所述第六薄膜晶体管的栅极电性连接于第四节点,源极电性连接于第三节点,漏极电性连接于第七薄膜晶体管的源极;以及第七薄膜晶体管,所述第七薄膜晶体管的栅极电性连接于第二节点,漏极电性连接于第二恒压电位;所述第二节点控制单元包括:第四薄膜晶体管,所述第四薄膜晶体管的栅极电性连接于第三节点,源极电性连接于控制时钟信号,漏极电性连接于第二节点;以及第八薄膜晶体管,所述第八薄膜晶体管的栅极电性连接于控制时钟信号,源极电性连接于第一恒压电位,漏极电性连接于第二 节点;所述第一节点漏电防护单元包括:第九薄膜晶体管,所述第九薄膜晶体管的栅极与源极均电性连接于输出时钟信号,漏极电性连接于第四节点;第十薄膜晶体管,所述第十薄膜晶体管的栅极电性连接于级传信号,源极电性连接于第四节点,漏极电性连接于第二恒压电位;以及第三电容,所述第三电容的一端电性连接于第四节点,漏极电性连接于第二恒压电位;其中,应用于双边驱动逐行扫描架构的显示面板,显示面板左、右两边分别设置一GOA电路,每一边的GOA电路均包括第一级至最后一级GOA单元;每一边的各级GOA单元均接入两条时钟信号:第一条时钟信号和第二条时钟信号,所述第一条时钟信号和第二条时钟信号的相位相反;其中,在各级GOA单元中,所述第一条时钟信号和第二条时钟信号分别轮流作为输出时钟信号和控制时钟信号;其中,除第一级GOA单元外,第n级GOA单元的级传信号为上一级第n-1级GOA单元的输出信号;第一级GOA单元的级传信号为电路起始信号。
- 如权利要求11所述的用于窄边框液晶显示面板的GOA电路,其中,各个薄膜晶体管均为N型低温多晶硅半导体薄膜晶体管,所述第一恒压电位为恒压高电位,第二恒压电位为恒压低电位。
- 如权利要求11所述的用于窄边框液晶显示面板的GOA电路,其中,各个薄膜晶体管均为P型低温多晶硅半导体薄膜晶体管,所述第一恒压电位为恒压低电位,第二恒压电位为恒压高电位。
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