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WO2017156705A1 - Affine prediction for video coding - Google Patents

Affine prediction for video coding Download PDF

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Publication number
WO2017156705A1
WO2017156705A1 PCT/CN2016/076360 CN2016076360W WO2017156705A1 WO 2017156705 A1 WO2017156705 A1 WO 2017156705A1 CN 2016076360 W CN2016076360 W CN 2016076360W WO 2017156705 A1 WO2017156705 A1 WO 2017156705A1
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WIPO (PCT)
Prior art keywords
block
affine
mvs
neighboring
amvr
Prior art date
Application number
PCT/CN2016/076360
Other languages
French (fr)
Inventor
Tzu-Der Chuang
Ching-Yeh Chen
Han HUANG
Xiaozhong Xu
Shan Liu
Original Assignee
Mediatek Inc.
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Filing date
Publication date
Application filed by Mediatek Inc. filed Critical Mediatek Inc.
Priority to PCT/CN2016/076360 priority Critical patent/WO2017156705A1/en
Priority to EP17765801.0A priority patent/EP3414900A4/en
Priority to CN202110949285.3A priority patent/CN113612994B/en
Priority to CN201780017425.5A priority patent/CN108781284B/en
Priority to PCT/CN2017/076420 priority patent/WO2017157259A1/en
Priority to RU2018134794A priority patent/RU2696551C1/en
Priority to US16/083,662 priority patent/US10638152B2/en
Priority to SG11201806865YA priority patent/SG11201806865YA/en
Priority to TW106108289A priority patent/TWI617185B/en
Publication of WO2017156705A1 publication Critical patent/WO2017156705A1/en
Priority to US16/827,881 priority patent/US11375226B2/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
    • H04N19/503—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving temporal prediction
    • H04N19/51—Motion estimation or motion compensation
    • H04N19/513—Processing of motion vectors
    • H04N19/517—Processing of motion vectors by encoding
    • H04N19/52—Processing of motion vectors by encoding by predictive encoding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
    • H04N19/503—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving temporal prediction
    • H04N19/51—Motion estimation or motion compensation
    • H04N19/537—Motion estimation other than block-based

Definitions

  • the invention relates generally to video processing.
  • the present invention relates to methods for affine prediction in video coding and its extensions, 3D video coding, scalable video coding, screen content coding et al.
  • Acronym CE Core Experiments
  • CTB Long coding unit
  • HEVC High Efficiency Video Coding
  • IntraBC Intra picture Block Copy
  • the affine model can be shown in Fig .
  • the transformed block is a rectangular block.
  • the motion vector field of each point in this moving block can be described by the following equation.
  • (v0x, v0y) is the control point motion vector on top left corner
  • (v1x, v1y) is another control point motion vector on above right corner of the block.
  • an affine_flag is signalled to indicate whether the affine inter mode is applied or not. If the current CU is in affine inter mode, a candidate MVP pair list is built using the neighbour valid reconstructed blocks. As shown in Fig , the v0 is selected from the motion vectors of the block A0, A1 or A2, and the v1 is selected from the motion vectors of the block B0 and B1. The index of candidate MVP pair is signalled in the bit stream. The MV difference (MVD) of the two control points are coded in the bitstream.
  • MVD MV difference
  • an affine merge mode is also proposed. If current is a merge PU, the neighboring five blocks (C0, B0, B1, C1, and A0 blocks in Fig.2) are checked whether one of them is affine inter mode or affine merge mode. If yes, an affine_flag is signaled to indicate whether the current PU is affine mode.
  • the current PU When the current PU is applied in affine merge mode, it gets the first block coded with affine mode from the valid neighbour reconstructed blocks. The selection order for the candidate block is from left, above, above right, left bottom to above left (C0 ⁇ B0 ⁇ B1 ⁇ C1 ⁇ A0) as shown in Fig 2.
  • the affine parameter of the first affine coded block is used to derive the v0 and v1 for the current PU.
  • the decoded MVs of each PU are downsampled with a 16:1 ratio and stored in the temporal MV buffer for the MVP derivation for the following frames.
  • the top-left 4x4 MV is stored in the temporal MV buffer and the stored MV represents the MV of the whole 16x16 block.
  • Fig.1 is a diagram illustrating four parameter affine motion model.
  • Fig.2 is a diagram illustrating MVP derivation for affine inter mode.
  • Fig.3 is a diagram illustrating example of required MVs of the neighboring blocks in affine parameter derivation.
  • Fig.4 is a diagram illustrating the concept of storing two rows and two columns. DETAILED DESCRIPTION OF THE INVENTION
  • the neighboring block is affine coded block (includes affine inter mode block and affine merge mode block)
  • the MV of bottom-left NxN block is also used.
  • the block B and block E are the affine coded blocks.
  • the MVs of VB0, VB1 (and sometimes VB2 if a third control point is needed), VE0, and VE1 (and sometimes VE2 if a third control point is needed) are required.
  • MVs of the neighboring 4x4 block row and 4x4 block column of the current CU/CTU and the MVs of current CTU are stored.
  • Other MVs are downsampled stored in temporal MV buffer for the following frames or discarded. It requires additional MV buffers to stores the MVs of neighboring blocks for affine parameter derivation.
  • M M MV rows and K MV columns.
  • Fig.4(a) to derive the affine parameters of block B, E, and A, the VB0’and VB1’ are used instead of VB0 and VB1.
  • the VE0’, VE1’and VE2’ are used instead of VE0, VE1 and VE2.
  • the VA0’and are used instead of VA0 and VA2.
  • the VB1’and VB2’ are used instead of VB0 ,VB1 and VB2.
  • the VE0’, VE1’ and VE2’ are used instead of VE0, VE1 and VE2.
  • the VA0’ and VA2’ are used instead of VA0 and VA2.
  • other positions in the two row blocks and two column blocks can be used for affine parameter derivation. Without loss of generality, only the method in Fig.2(a) is described in the following.
  • the derived 3 control points affine MVP from block B can be modified as follow:
  • VB0’, VB1’, and VB2 can be replaced by the corresponding MVs of any other selected reference/neighboring PU
  • (posCurPU_X, posCurPU_Y) are the pixel position of the top-left sample of the current PU relative to the top-left sample of the picture
  • (posRefPU_X, posRefPU_Y) are the pixel position of the top-left sample of the reference/neighboring PU relative to the top-left sample of the picture
  • (posB0’_X, posB0’_Y) are the pixel position of the top-left sample of the B0 block relative to the top- left sample of the picture.
  • the derived MVs are (v0x, v0y) plus the position dependent offset MV.
  • the horizontal direction offset MV is ((v1x– v0x)*N/w, (v1y– v0y)*N/w) and the vertical direction offset MV is (–(v1y– v0y)*N/w, (v1x– v0x)*N/w).
  • the top-left, top-right, and the bottom-left MVs are v0, v1, and v2, the MVs of each pixel can be as follow.
  • the horizontal direction offset MV is ((v1x– v0x)*N/w, (v1y– v0y)*N/w) and the vertical direction offset MV is ((v2x– v0x)*N/h, (v2y– v0y)*N/h).
  • the derived MV is (vx, vy) in (6).
  • w and h are the width and height of the affine code block.
  • the denominator can be decreased by N.
  • the equation (2) can be rewritten as follow.
  • the horizontal and vertical direction offset MVs for an MxM block.
  • M can be equal to 8.
  • the ((v1x– v0x)*N/w, (v1y– v0y)*N/w) and ((v2x– v0x)*N/h, (v2y– v0y)*N/h) are stored.
  • the affine parameter of the affine merge candidate can be also derived.
  • the top-left MV of the neighboring block can be also stored with the offset MVs.
  • the offset MV can be multiplied by a scale number.
  • the scale number can be predefined or set equal to CTU size.
  • CTU size For example, the ((v1x– v0x)*S/w, (v1y– v0y)*S/w) and ((v2x– v0x)*S/h, (v2y– v0y)*S/h) are stored.
  • the S can be equal to CTU_size or CTU_size/4.
  • the adaptive MV resolution was proposed to reduce the MVD overhead.
  • An AMVR_flag is signaled for a CU or a PU. If the AMVR_flag is true, the MVD is in integer pixel resolution. For affine merge mode, the derived motion vectors for all control points can be in fractional resolution. No AMVR_flag will be signaled.
  • M is the number of control points for the affine AMVP coded PU
  • the number M can be 0, 1, 2, 3, 4.
  • affine prediction it is proposed to combine the affine prediction with AMVR. If a PU or a CU is coded in affine AMVP mode and the AMVR_flag is true, all the MVDs of control points are in integer pixel resolution. All the MVPs of the control points (if associated with a MVD) can be also rounded to integer pixel resolution. For those control points without an associated MVD (infer the MVD to be zero, a predicted or derived MV is used directly), the predicted or derived MV can still be in fractional pixel resolution.
  • the MVD can be signaled before the AMVR_flag.
  • AMVR_flag For affine AMVP mode, if there is at least one non-zero MVD for the control point(s), then the resolution of the decoded MV(s) should be determined by using the AMVR_flag. If the MVDs for all the control points are zero, the MVP of all control points can remain in fractional pixel resolution. In this case, the AMVR_flag is not necessary to be signaled.
  • the affine inter mode is restricted to uni-prediction. For example, if affine_flag is true, the interDir can be only 0 or 1 (L0 uni-prediction or L1 uni-prediction). However, in the case of AMVR_flag is true, the MVD overhead is relatively small. So it is proposed to allow the bi-prediction for affine inter mode when AMVR_flag is true.
  • an embodiment of the present invention can be a circuit integrated into a video compression chip or program codes integrated into video compression software to perform the processing described herein.
  • An embodiment of the present invention may also be program codes to be executed on a Digital Signal Processor (DSP) to perform the processing described herein.
  • DSP Digital Signal Processor
  • the invention may also involve a number of functions to be performed by a computer processor, a digital signal processor, a microprocessor, or field programmable gate array (FPGA).
  • processors can be configured to perform particular tasks according to the invention, by executing machine-readable software code or firmware code that defines the particular methods embodied by the invention.
  • the software code or firmware codes may be developed in different programming languages and different format or style.
  • the software code may also be compiled for different target platform.
  • different code formats, styles and languages of software codes and other means of configuring code to perform the tasks in accordance with the invention will not depart from the spirit and scope of the invention.

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Abstract

Methods for affine prediction are proposed. First, methods of affine MVP derivation are proposed. Second, methods of adaptive resolution and affine prediction are proposed.

Description

TITLE AFFINE PREDICTION FOR VIDEO CODING BACKGROUND OF THE INVENTION Field of the Invention
[0001] The invention relates generally to video processing. In particular, the present invention relates to methods for affine prediction in video coding and its extensions, 3D video coding, scalable video coding, screen content coding et al. Acronym CE: Core Experiments
CU: Coding Unit
CTB (LCU): Coded tree block (largest coding unit)
HEVC: High Efficiency Video Coding
IntraBC: Intra picture Block Copy
MC: Motion Compensation
MV: Motion Vector
PU: Prediction Unit
RExt: HEVC Range Extensions
WPP: wavefront parallel process Description of the Related Art [0002] In ITU-T13-SG16-C-1016 [1], a four parameter affine prediction which includes the affine merge mode and affine inter mode is proposed. When an affine motion block is moving, the motion vector field of the block can be described by two control point motion vectors or four parameters as the following,
Figure imgf000004_0001
[0003] The affine model can be shown in Fig . The transformed block is a rectangular block. The motion vector field of each point in this moving block can be described by the following equation.
Figure imgf000004_0002
Where (v0x, v0y) is the control point motion vector on top left corner, and (v1x, v1y) is another control point motion vector on above right corner of the block.
[0004] In ITU-T13-SG16-C-1016, for a inter mode coded CU, when the CU size is equal to or larger than 16x16, an affine_flag is signalled to indicate whether the affine inter mode is applied or not. If the current CU is in affine inter mode, a candidate MVP pair list is built using the neighbour valid reconstructed blocks. As shown in Fig , the v0 is selected from the motion vectors of the block A0, A1 or A2, and the v1 is selected from the motion vectors of the block B0 and B1. The index of candidate MVP pair is signalled in the bit stream. The MV difference (MVD) of the two control points are coded in the bitstream.
[0005] In ITU-T13-SG16-C-1016, an affine merge mode is also proposed. If current is a merge PU, the neighboring five blocks (C0, B0, B1, C1, and A0 blocks in Fig.2) are checked whether one of them is affine inter mode or affine merge mode. If yes, an affine_flag is signaled to indicate whether the current PU is affine mode. When the current PU is applied in affine merge mode, it gets the first block coded with affine mode from the valid neighbour reconstructed blocks. The selection order for the candidate block is from left, above, above right, left bottom to above left (C0^B0^B1^C1^A0) as shown in Fig 2. The affine parameter of the first affine coded block is used to derive the v0 and v1 for the current PU.
[0006] In HEVC, the decoded MVs of each PU are downsampled with a 16:1 ratio and stored in the temporal MV buffer for the MVP derivation for the following frames. For a 16x16 block, only the top-left 4x4 MV is stored in the temporal MV buffer and the stored MV represents the MV of the whole 16x16 block.
BRIEF SUMMARY OF THE INVENTION
[0007] Methods of using affine prediction for video coding are proposed. First, methods of affine MVP derivation are proposed. Second, methods of adaptive resolution and affine prediction are proposed.
[0008] Other aspects and features of the invention will become apparent to those with ordinary skill in the art upon review of the following descriptions of specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS
[0009] The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
[0010] Fig.1 is a diagram illustrating four parameter affine motion model.
[0011] Fig.2 is a diagram illustrating MVP derivation for affine inter mode.
[0012] Fig.3 is a diagram illustrating example of required MVs of the neighboring blocks in affine parameter derivation.
[0013] Fig.4 is a diagram illustrating the concept of storing two rows and two columns. DETAILED DESCRIPTION OF THE INVENTION
[0014] The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. [0015] In ITU-T13-SG16-C-1016 [1], the affine MVP are derived for affine inter mode and affine merge mode. In [1], for affine merge mode, if the neighboring block is affine coded block (includes affine inter mode block and affine merge mode block), the MV of top-left NxN ( the smallest block size to store an MV, N=4 in one embodiment) block of the neighboring block and the MV of the top-right NxN block of the neighboring block are used to derive the affine parameter (or the MVs of the control points) of the affine merge candidate. When a third control point is used, the MV of bottom-left NxN block is also used. For example, as shown in Fig. 3, the block B and block E are the affine coded blocks. To derive the affine parameter of block B and block E, the MVs of VB0, VB1 (and sometimes VB2 if a third control point is needed), VE0, and VE1 (and sometimes VE2 if a third control point is needed) are required. However, in HEVC, only MV of the neighboring 4x4 block row and 4x4 block column of the current CU/CTU and the MVs of current CTU are stored. Other MVs are downsampled stored in temporal MV buffer for the following frames or discarded. It requires additional MV buffers to stores the MVs of neighboring blocks for affine parameter derivation.
[0016] Here we propose several methods to reduce the buffer requirements.
[0017] In one embodiment, use the downsampled MV in temporal MV buffer. If the MVs are not in the neighboring NxN block row or NxN block column of the current CU/CTU or in the current CTU, use the MVs stored in the temporal MV buffer instead of the real MVs. Here NxN represents the smallest block size to store an MV. In one embodiment, N=4.
[0018] In another embodiment, store M MV rows and K MV columns. Instead of storing all MVs in the current frames, it is proposed to store the MVs of M neighboring row blocks and the MVs of K neighboring column blocks. Here M and K are integer numbers, M>=2 and K>=2. Each block refers to the smallest NxN block that can store an MV (N=4 in one embodiment). In one example, M=K=2, N=4 is shown in Fig.4. In Fig.4(a), to derive the affine parameters of block B, E, and A, the VB0’and VB1’ are used instead of VB0 and VB1. The VE0’, VE1’and VE2’ are used instead of VE0, VE1 and VE2. The VA0’and are used instead of VA0 and VA2. In Fig.4(b), to derive the affine parameters of block B, E, and A, the
Figure imgf000007_0001
VB1’and VB2’ are used instead of VB0 ,VB1 and VB2. The VE0’, VE1’ and VE2’ are used instead of VE0, VE1 and VE2. The VA0’ and VA2’ are used instead of VA0 and VA2.In general, other positions in the two row blocks and two column blocks can be used for affine parameter derivation. Without loss of generality, only the method in Fig.2(a) is described in the following. [0019] The derived 3 control points affine MVP from block B can be modified as follow:
Figure imgf000007_0002
[0020] where VB0’, VB1’, and VB2 can be replaced by the corresponding MVs of any other selected reference/neighboring PU, (posCurPU_X, posCurPU_Y) are the pixel position of the top-left sample of the current PU relative to the top-left sample of the picture, (posRefPU_X, posRefPU_Y) are the pixel position of the top-left sample of the reference/neighboring PU relative to the top-left sample of the picture, (posB0’_X, posB0’_Y) are the pixel position of the top-left sample of the B0 block relative to the top- left sample of the picture.
Figure imgf000007_0003
[0021] The derived 2 control points affine MVP from block B can be modified as follow:
Figure imgf000008_0002
_ _ _ _
[0022] In still another embodiment, considering the line buffer of storing the MVs from top CTUs is much larger than the column buffer of storing the MVs from left CTU, there is no need to constrain the value of M (M can be set to CTU_width/N).
[0023] In still another embodiment, store the affine parameter for every MxM block. In equation (2), the MVs of top-left and top-right NxN blocks are used to derive the MVs of all NxN sub-blocks (the smallest unit to store an MV, N=4 in one embodiment) in the CU/PU. The derived MVs are (v0x, v0y) plus the position dependent offset MV. From the equation (2), if it derived an MV for an NxN sub-block, the horizontal direction offset MV is ((v1x– v0x)*N/w, (v1y– v0y)*N/w) and the vertical direction offset MV is (–(v1y– v0y)*N/w, (v1x– v0x)*N/w). For a 6-parameter affine model, if the top-left, top-right, and the bottom-left MVs are v0, v1, and v2, the MVs of each pixel can be as follow.
Figure imgf000008_0001
From the equation (6), if it derived an MV for an NxN sub-block at position (x, y) (relative to the top-left corner), the horizontal direction offset MV is ((v1x– v0x)*N/w, (v1y– v0y)*N/w) and the vertical direction offset MV is ((v2x– v0x)*N/h, (v2y– v0y)*N/h). The derived MV is (vx, vy) in (6). In (2) and (6), w and h are the width and height of the affine code block.
If the MV of the control points is the MV of the center pixel of an NxN block, in equation (2) to (6), the denominator can be decreased by N. For example, the equation (2) can be rewritten as follow.
Figure imgf000009_0001
Here, it is proposed to store the horizontal and vertical direction offset MVs for an MxM block. For example, if the smallest affine inter mode or affine merge mode block size is 8x8, then M can be equal to 8. For each 8x8 block, the ((v1x– v0x)*N/w, (v1y– v0y)*N/w) and ((v2x– v0x)*N/h, (v2y– v0y)*N/h) are stored. Based on the direction MVs and the neighboring NxN sub-block MV, the v0, v1, and v2 of the neighboring block can be derived (N=4 in one embodiment). The affine parameter of the affine merge candidate can be also derived. The top-left MV of the neighboring block can be also stored with the offset MVs.
In order to preserve the precision, the offset MV can be multiplied by a scale number. The scale number can be predefined or set equal to CTU size. For example, the ((v1x– v0x)*S/w, (v1y– v0y)*S/w) and ((v2x– v0x)*S/h, (v2y– v0y)*S/h) are stored. The S can be equal to CTU_size or CTU_size/4.
[0024] In still another embodiment, the adaptive MV resolution (AMVR) was proposed to reduce the MVD overhead. An AMVR_flag is signaled for a CU or a PU. If the AMVR_flag is true, the MVD is in integer pixel resolution. For affine merge mode, the derived motion vectors for all control points can be in fractional resolution. No AMVR_flag will be signaled.
[0025] Assume M is the number of control points for the affine AMVP coded PU, M (M>=N) is the number of signaled MVDs in this PU. Here the number M can be 0, 1, 2, 3, 4.
[0026] In still another embodiment, it is proposed to combine the affine prediction with AMVR. If a PU or a CU is coded in affine AMVP mode and the AMVR_flag is true, all the MVDs of control points are in integer pixel resolution. All the MVPs of the control points (if associated with a MVD) can be also rounded to integer pixel resolution. For those control points without an associated MVD (infer the MVD to be zero, a predicted or derived MV is used directly), the predicted or derived MV can still be in fractional pixel resolution.
[0027] In still another embodiment, the MVD can be signaled before the AMVR_flag. For affine AMVP mode, if there is at least one non-zero MVD for the control point(s), then the resolution of the decoded MV(s) should be determined by using the AMVR_flag. If the MVDs for all the control points are zero, the MVP of all control points can remain in fractional pixel resolution. In this case, the AMVR_flag is not necessary to be signaled.
[0028] In still another embodiment, in order to reduce the MVD overhead, it was proposed that the affine inter mode is restricted to uni-prediction. For example, if affine_flag is true, the interDir can be only 0 or 1 (L0 uni-prediction or L1 uni-prediction). However, in the case of AMVR_flag is true, the MVD overhead is relatively small. So it is proposed to allow the bi-prediction for affine inter mode when AMVR_flag is true.
[0029] In still another embodiment, in the CU syntax structure where interDir and affine_flag are signaled prior to the AMVR_flag (and the MVDs of each PU for the CU), when interDir is equal to 2 (bi-direction) and affine_flag is true, the AMVR_flag can then be inferred to be true and not necessary to be signaled.
[0030] The proposed methods described above can be used in a video encoder as well as in a video decoder. Embodiments of the proposed method according to the present invention as described above may be implemented in various hardware, software codes, or a combination of both. For example, an embodiment of the present invention can be a circuit integrated into a video compression chip or program codes integrated into video compression software to perform the processing described herein. An embodiment of the present invention may also be program codes to be executed on a Digital Signal Processor (DSP) to perform the processing described herein. The invention may also involve a number of functions to be performed by a computer processor, a digital signal processor, a microprocessor, or field programmable gate array (FPGA). These processors can be configured to perform particular tasks according to the invention, by executing machine-readable software code or firmware code that defines the particular methods embodied by the invention. The software code or firmware codes may be developed in different programming languages and different format or style. The software code may also be compiled for different target platform. However, different code formats, styles and languages of software codes and other means of configuring code to perform the tasks in accordance with the invention will not depart from the spirit and scope of the invention.
[0031] The invention may be embodied in other specific forms without departing from its spirit or essential characteristics. The described examples are to be considered in all respects only as illustrative and not restrictive. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Claims

What is claimed is 1. Methods of affine MVP derivation, including: 1) Use the down sampled MV in temporal MV buffer. 2) Store M MV rows and K MV columns. 3) Store the affine parameter for every MxM block.
2. The method as claimed in claim 1, if the MVs are not in the neighboring NxN block row or NxN block column of the current CU/CTU or in the current CTU, use the MVs stored in the temporal MV buffer instead of the real MVs. Here NxN represents the smallest block size to store an MV.
3. The method as claimed in claim 2, N=4.
4. The method as claimed in claim 1, instead of storing all MVs in the current frames, it is proposed to store the MVs of M neighboring row blocks and the MVs of K neighboring column blocks.
5. The method as claimed in claim 4, M and K are integer numbers, M>=2 and K>=2.
6. The method as claimed in claim 4, each block refers to the smallest NxN block that can store an MV (N=4).
7. The method as claimed in claim 4, M=K=2, N=4 is shown in Fig.2.
8. The method as claimed in claim 4, as shown in Fig.4(a), to derive the affine parameters of block B, E, and A, the VB0’and VB1’ are used instead of VB0 and VB1. The VE0’, VE1’and VE2’ are used instead of VE0, VE1 and VE2. The VA0’and VA2’ are used instead of VA0 and VA2.
9. The method as claimed in claim 4, a shown in Fig.4(b), to derive the affine parameters of block B, E, and A, the VB0’ , VB1’ and VB2’ are used instead of VB0 ,VB1 and VB2. The VE0’, VE1’and VE2’ are used instead of VE0, VE1 and VE2. The VA0’and VA2’ are used instead of VA0 and VA2.
10. The method as claimed in claim 4, in general, other positions in the two row blocks and two column blocks can be used for affine parameter derivation.
11. The method as claimed in claim 8, the derived 3 control points affine MVP from block B can be modified as follow:
12. The method as claimed in claim 11, VB0’, VB1’, and VB2 can be replaced by the corresponding MVs of any other selected reference/neighboring PU, (posCurPU_X, posCurPU_Y) are the pixel position of the top-left sample of the current PU relative to the top-left sample of the picture, (posRefPU_X, posRefPU_Y) are the pixel position of the top-left sample of the reference/neighboring PU relative to the top-left sample of the picture, (posB0’_X, posB0’_Y) are the pixel position of the top-left sample of the B0 block relative to the top-left sample of the picture.
13. The method as claimed in claim 8, the derived 2 control points affine MVP from block B can be modified as follow: + (VB1’_y– VB0’_y ) * (posCurPU_X– posB0’_X) / RefPU_width V1_x = VB0’_x + (VB1’_x– VB0’_x) * PU_width / RefPU_width V1_y = VB0’_y + (VB1’_y– VB0’_y) * PU_width / RefPU_width
14. The method as claimed in claim 4, there is no need to constrain the value of M (M can be set to CTU_width/N).
15. The method as claimed in claim 1, store the horizontal and vertical direction offset MVs for an MxM block.
16. The method as claimed in claim 15, if the smallest affine inter mode or affine merge mode block size is 8x8, then M can be equal to 8.
17. The method as claimed in claim 15 and claim 16, for each 8x8 block, the ((v1x– v0x)*N/w, (v1y– v0y)*N/w) and ((v2x– v0x)*N/h, (v2y– v0y)*N/h) are stored.
18. The method as claimed in claim 1, 16 and 17, based on the direction MVs and the neighboring NxN sub-block MV, the v0, v1, and v2 of the neighboring block can be derived.
19. The method as claimed in claim 1, 16~18, N=4.
20. The method as claimed in claim 16~18, the affine parameter of the affine merge candidate can be also derived. The top-left MV of the neighboring block can be also stored with the offset MVs.
21. The method as claimed in claim 15, the offset MV can be multiplied by a scale number.
22. The method as claimed in claim 21, the scale number can be predefined or set equal to CTU size. For example, the ((v1x– v0x)*S/w, (v1y– v0y)*S/w) and ((v2x– v0x)*S/h, (v2y– v0y)*S/h) are stored. The S can be equal to CTU_size or CTU_size/4.
23. The method as claimed in claim 1, it is proposed to combine the affine prediction with AMVR.
24. The method as claimed in claim 23, if a PU or a CU is coded in affine AMVP mode and the AMVR_flag is true, all the MVDs of control points are in integer pixel resolution. All the MVPs of the control points (if associated with a MVD) can be also rounded to integer pixel resolution. For those control points without an associated MVD (infer the MVD to be zero, a predicted or derived MV is used directly), the predicted or derived MV can still be in fractional pixel resolution.
25. The method as claimed in claim 23, the MVD can be signaled before the AMVR_flag. For affine AMVP mode, if there is at least one non-zero MVD for the control point(s), then the resolution of the decoded MV(s) should be determined by using the AMVR_flag. If the MVDs for all the control points are zero, the MVP of all control points can remain in fractional pixel resolution. In this case, the AMVR_flag is not necessary to be signaled.
26. The method as claimed in claim 23, it’s proposed to allow the bi- prediction for affine inter mode when AMVR_flag is true but disable bi-prediction for affine when AMVR_FLAG is false.
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