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WO2016127357A1 - 一种基于fpga的时间数字变换器 - Google Patents

一种基于fpga的时间数字变换器 Download PDF

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Publication number
WO2016127357A1
WO2016127357A1 PCT/CN2015/072862 CN2015072862W WO2016127357A1 WO 2016127357 A1 WO2016127357 A1 WO 2016127357A1 CN 2015072862 W CN2015072862 W CN 2015072862W WO 2016127357 A1 WO2016127357 A1 WO 2016127357A1
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delay
signal
code
fpga
tap
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PCT/CN2015/072862
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English (en)
French (fr)
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王永纲
刘冲
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中国科学技术大学
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Priority to PCT/CN2015/072862 priority Critical patent/WO2016127357A1/zh
Publication of WO2016127357A1 publication Critical patent/WO2016127357A1/zh

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    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means

Definitions

  • the invention belongs to the field of digital measurement of time quantity, and in particular relates to a time-based digital converter based on FPGA.
  • Time measurement refers to measuring the moment when an event occurs, or measuring the time interval between two events.
  • Time measurement technology has important applications in many fields, such as high-energy physics experiment research, nuclear medicine imaging, military and civilian radar, and laser ranging, which require high-precision time measurement technology.
  • Time-Digital-Convertor (TDC: Time-Digital-Convertor) is a functional device that converts the amount of time into a digital quantity to realize the recording of an event occurrence time.
  • TDC Time-Digital-Convertor
  • the occurrence time of two events can generally be measured by two TDCs respectively, and the difference between the two occurrence moments is the time interval of the two events.
  • the implementation carrier of the TDC can be divided into an ASIC (Application Specific Integrated Circuit) dedicated chip and an FPGA (Field Programmable Gate Array) programmable device.
  • ASIC Application Specific Integrated Circuit
  • FPGA Field Programmable Gate Array
  • the amount of logic resources that a single-chip FPGA can provide is getting larger and larger, and the flexibility of its programmable configuration is getting stronger and stronger.
  • FPGA has become a platform for digital system integration design. On this platform, if some physical quantity measurement, such as the measurement of time quantity, can be realized at the same time, it is undoubtedly important for the FPGA-based user-specific data acquisition and processing system.
  • FPGA-based TDC design technology has been greatly developed.
  • One of the most important ways is to use the carry chain in the basic logic resources of the FPGA to form a multi-tap TAD (Tapped Delay Line) to realize the time. Interpolation of quantities to improve the measurement accuracy of TDC.
  • TDL-based TDC based on FPGA There are many possible implementations of TDL-based TDC based on FPGA. Different methods can achieve different TDC measurement accuracy and measurement dead time. The amount of FPGA logic resources occupied by single-channel TDC is also different. A small measurement dead time can increase the measurement throughput of the TDC. A small amount of logic resources can save FPGA resources for other parts of the data acquisition and processing system designed by the user, or can implement a multi-channel TDC system on a single FPGA. However, the current TDC implementation solution can not get good indicators in terms of improving measurement accuracy, reducing measurement dead time and reducing resource consumption.
  • TDL Tapped Delay Line
  • the simplest implementation of the digital measurement of the event occurrence time can be implemented with a high speed clock counter.
  • the state of the current counter is recorded, which is the time measurement of the event occurrence time.
  • the TDC accuracy of this method is the period of the counter clock signal.
  • a very high clock frequency must be used.
  • the highest clock frequency based on FPGA is about 710MHz, that is, the highest measurement accuracy is about 1.408ns.
  • a common method based on FPGA technology is to try to construct a delay chain composed of multiple delay units. The total delay time of the delay chain is greater than the period of one system clock, and the state of each delay unit is derived from the tap.
  • the measured signal is fed into the delay chain for transmission, and the state of the clock counter and the state of the delay chain are simultaneously recorded at the arrival time of each system clock.
  • the former is the coarse time mark of the signal to be measured
  • the latter is the fine time mark of the signal to be measured. Combining the two is the accurate measurement result of the measured signal.
  • the measurement accuracy of the TDC is mainly determined by the size and accuracy of the delay cells in the delay chain.
  • most of the delay chains are constructed by using the carry chain in the FPGA arithmetic logic operation resource, and the length of each delay unit is the transmission delay amount corresponding to the carry chain.
  • Triggers that use the same resource unit as the carry chain can derive the state of each tap of the delay amount for the encoded output of the delay state of the subsequent circuit.
  • two TDC channels can be used to record the occurrence time of two events, and the difference between them is the time interval.
  • the delay width of each delay unit has non-uniformity, and each measurement node has a measurement error.
  • Differential nonlinearity and integral nonlinearity can be used to represent the above non-uniformity and measurement error, respectively.
  • the differential nonlinearity can be defined as the difference between the delay width of the actual delay unit and the ideal delay width, and is generally expressed in units of the ideal delay width (1 LSB).
  • the integral nonlinearity can be defined as the sum of the differential nonlinearities of all delay elements from the first delay unit to the measurement node at which it is located. It represents the error between the reading value of the measuring node and the ideal measured value, and is generally ideal.
  • the delay width (LSB) is expressed in units.
  • the integral nonlinearity is the measurement error of each measurement node. Therefore, in order to remove the need for the unit-by-unit correction circuit, it is necessary to improve the integral nonlinearity as much as possible.
  • the invention aims to effectively improve the measurement accuracy of the TDC while reducing its measurement dead time and reducing the amount of FPGA logic resources occupied by a single TDC channel.
  • the present invention provides an FPGA-based time-to-digital converter including a coarse clock counter, a pulse signal generator, a signal delay chain, a flip-flop array, a connection network, a signal change edge finding and encoding circuit, and time.
  • the coarse clock counter is driven by a system clock signal for generating a coarse time stamp of the signal under test
  • the pulse signal generator is configured to generate a pulse with a varying edge and feed it under the trigger of the signal under test Transmitting into the signal delay chain
  • the signal delay chain is used for delay transmission of the signal under test, consisting of multiple delay units, and having a tap behind each delay unit, in front of the first delay unit And having a tap
  • the flip-flop array is configured to latch each tap state of the signal delay chain, and pass the latched tap state to the connected network according to the natural ordering of the tap
  • the connection network is used for The received tap state is transformed according to a preset connection relationship, and then transmitted to the signal change edge to find And an encoding circuit
  • the signal change edge finding and encoding circuit is configured to find a changed edge of the latched pulse transmitted in the signal delay chain, and generate a binary code representing the fine time stamp according to the position of the changed edge
  • the timestamp output circuit is configured to convert the
  • the transforming, by the connection network, the received tap state according to a preset connection relationship comprises: reordering each tap of the signal delay chain to determine a trigger
  • the array is coupled to the signal change edge to find a connection relationship with the encoding circuit.
  • the reordering comprises swapping the taps of the 0-width delay unit and the tap positions of the next delay unit.
  • the reordering may be performed multiple times, measuring the delay width of each delay unit after one adjustment sequence, determining whether the number of delay units of 0 width exceeds a threshold, and if so, weighing again Sort until the number of 0 width delay units does not exceed the threshold.
  • the measuring the delay width of each delay unit is to measure the delay width of each delay unit by a code density method.
  • the connecting network performs the transformation of the received tap state according to a preset connection relationship, including: extracting each tap of the signal delay chain, and determining a trigger for the trigger
  • the array is coupled to the signal change edge to find a connection relationship with the encoding circuit.
  • the rule of decimation is to minimize the integral nonlinearity of the time-interpolation measurements made based on the signal delay chain.
  • the tap S 1 , 1 ⁇ l ⁇ n which satisfies the following formula, is extracted:
  • the delay widths of the original delay units are B 1 , B 2 , B 3 , ..., B n , n is the number of delay units
  • the extracted taps are denoted as T 1 , T 2 , T 3 , ..., T R , the above formula for each given i, will calculate a minimum l, the minimum l value corresponding to the tap S l is the extracted T i .
  • the signal change along the seek and encode circuit generates a thermometer code indicating a change edge position based on a tap state received from the connection network, A "one-hot" code for indicating a change edge position is generated based on the thermometer code, and the "one-hot” code is converted into a binary code indicating a time stamp.
  • the width of the window is m
  • m is a natural number and 2 ⁇ m ⁇ 2 N
  • a "one-hot" code corresponding to the thermometer code is obtained by sequentially arranging the true values corresponding to the window values.
  • a truth table for conversion between all possible window values and corresponding true values is stored in the basic logical unit LUT in the FPGA.
  • the signal change edge search and encoding circuit when used to find the falling edge of the thermometer code, in the truth table, only the last bit is 0, and the remaining bits are 1 window.
  • the true value corresponding to the value is 1, and the true value corresponding to the remaining window values is 0; or, the true value of the window value corresponding to the last bit is 0, and the remaining bits are all 1, the true value corresponding to the remaining window values Both are 1.
  • the change edge seek and encode circuit performs a logical OR operation of 2 N-1 "one-hot” code words for a "one-hot” code represented by "1" To obtain the encoding of each bit of the binary code; for the "one-hot” code represented by "0”, obtain the binary code by calculating the logical AND of the 2 N-1 "one-hot” codewords. The code for each bit.
  • the change along the seek and encode circuit utilizes a pipeline structure in combination with the LUT of the FPGA to implement the logical OR operation or logical AND operation, each stage of the pipeline being one or several parallel A logical OR operation or a logical AND operation that relies on the LUT.
  • the present invention also provides an FPGA-based code-to-binary code conversion method
  • the thermometer code has 2 N bits
  • the binary code has N bits
  • N is a natural number
  • the method includes: passing one by one The bit moving window divides the thermometer code to obtain 2 N window values, the window has a bit width of m, m is a natural number and 2 ⁇ m ⁇ 2 N , and sequentially arranges the window values corresponding to The true value yields a "one-hot" code corresponding to the thermometer code; the "one-hot” code is converted to a binary code.
  • a truth table for conversion between all possible window values and corresponding true values is stored in the basic logical unit LUT in the FPGA.
  • the signal change edge search circuit when the signal change edge search circuit is used to find the rising edge of the thermometer code, in the truth table, only the window value corresponding to the first bit is 0 and the remaining bits are 1.
  • the true value is 1, and the true value corresponding to the remaining window values is 0; or, the true value of the window value corresponding to the first bit is 0, and the remaining bits are all 1, and the true values corresponding to the remaining window values are all 1;
  • the signal change edge search circuit is used to find the falling edge of the thermometer code, in the truth table, only the last bit is 0, and the remaining window values corresponding to 1 have a true value of 1,
  • the true values corresponding to the remaining window values are all 0; or, the true value of the window value corresponding to only the last bit is 0 and the remaining bits are 1 is 0, and the true values corresponding to the remaining window values are all 1.
  • the "one-hot" code to binary code conversion process in, “one-hot” with respect to the code "1" is represented by 2 N-1 th calculated “one-hot "Logical OR operation of the codeword to obtain the encoding of each bit of the binary code; for the "one-hot” code represented by "0", by calculating the logic of 2 N-1 "one-hot” codewords
  • the AND operation is used to obtain the encoding of each bit of the binary code.
  • the logical OR operation or logical AND operation is implemented using a LUT of an FPGA using a pipeline structure combination, and each stage of the pipeline is one or several parallel logics implemented by the LUT. Or "operation" or logical "and” operation.
  • the invention also provides an FPGA-based thermometer code to binary code encoding and converting device, the thermometer code has 2 N bits, the binary code has N bits, N is a natural number, and the code conversion device includes a signal change edge search a circuit and a "one-hot" code to a binary code conversion circuit, wherein the signal change along the seek circuit divides the thermometer code by a bit-by-bit moving window to obtain 2 N window values, the bit width of the window m, m is a natural number and 2 ⁇ m ⁇ 2 N , and a "one-hot" code corresponding to the thermometer code is obtained by sequentially arranging the true values corresponding to the window values; the "one-hot” A code to binary code conversion circuit is used to convert the "one-hot” code into a binary code.
  • the conversion truth table between all possible window values and the corresponding truth values is stored in the LUT of the FPGA logic resource.
  • the signal change edge search circuit when the signal change edge search circuit is used to find the rising edge of the thermometer code, in the truth table, only the window value corresponding to the first bit is 0 and the remaining bits are 1.
  • the true value is 1, and the true value corresponding to the remaining window values is 0; or, the true value of the window value corresponding to the first bit is 0, and the remaining bits are all 1, and the true values corresponding to the remaining window values are all 1;
  • the signal change edge search circuit is used to find the falling edge of the thermometer code, in the truth table, only the last bit is 0, and the remaining window values corresponding to 1 have a true value of 1,
  • the true values corresponding to the remaining window values are all 0; or, the true value of the window value corresponding to only the last bit is 0 and the remaining bits are 1 is 0, and the true values corresponding to the remaining window values are all 1.
  • the "one-hot" code to binary code conversion circuit calculates 2 N-1 "one-hot” code words for a "one-hot” code represented by "1" Logical OR operation to obtain the encoding of each bit of the binary code; for the "one-hot” code represented by "0", by computing the logical AND of the 2 N-1 "one-hot” codewords To get the encoding of each bit of the binary code.
  • the logical OR operation or logical AND operation is implemented using a LUT of an FPGA using a pipeline structure combination, and each stage of the pipeline is one or several parallel logics implemented by the LUT. Or "operation" or logical "and” operation.
  • the TDC of the invention can reasonably balance the performance indexes of measurement accuracy, measurement dead time and resource occupancy, thereby realizing a high-performance TDC measurement system, and has important application value in the related field of time measurement.
  • FIG. 1 is a schematic view showing the structure of a TDC of the present invention
  • FIG. 2 is a block diagram showing the overall composition of a TDC system according to an embodiment of the present invention.
  • FIG. 3a is a diagram showing a delay unit width distribution measured by a code density method in a natural arrangement order of delay chain taps according to an embodiment of the present invention
  • Figure 3b is a differential nonlinear diagram calculated from the delay cell width of Figure 3a;
  • Figure 3c is an integral nonlinearity diagram calculated from the delay cell width of Figure 3a;
  • FIG. 4 is a diagram showing a delay unit width distribution measured by a code density method after a delay chain tap state reordering according to an embodiment of the present invention
  • 5a is a differential nonlinear diagram obtained by using a code density method after extracting a delay chain tap state according to an embodiment of the present invention
  • FIG. 5b is an integral nonlinear diagram obtained by using a code density method after the delay chain tap state extraction according to an embodiment of the present invention
  • 6a is a measurement histogram of a 3.3 ns time interval measured by a dual TDC channel in a case where the delay chain tap state is originally natural connection output according to an embodiment of the present invention
  • FIG. 6b is a measurement histogram of a 3.3 ns time interval measured by a dual TDC channel in a case where a delay chain tap state is outputted by the transform connection relationship of the present invention
  • FIG. 7 is a schematic structural diagram of a basic lookup table of a Kintex-7 FPGA according to an embodiment of the present disclosure
  • FIG. 8 is a schematic diagram of a principle for finding a signal change edge using a sliding window structure according to an embodiment of the present invention.
  • FIG. 9 is a schematic diagram of a 128-bit logical OR operation structure using a pipeline structure according to an embodiment of the present invention.
  • FIG. 10 is a diagram showing a standard error relationship between the total number of tap extractions and the 3.3 ns time interval of the dual TDC channel measurement according to the embodiment of the present invention.
  • FIG. 1 is a schematic structural diagram of an FPGA-based time-to-digital converter provided by the present invention. As shown in FIG. 1, it includes a coarse clock counter, a pulse signal generator, a signal delay chain, a flip-flop array, a connection network, a signal change edge finding and encoding circuit, and a time stamp output circuit.
  • the coarse clock counter is driven by the system clock signal and is used to generate a coarse timestamp of the signal under test.
  • the pulse signal generator is externally triggered for generating a pulse with a varying edge triggered by the signal under test and feeding it into the signal delay chain for transmission.
  • the change edge can be selected as a rising edge or a falling edge.
  • the signal delay chain is used for delay transmission of the signal under test, which is composed of a plurality of delay units, and has a tap at the front end of each delay unit, so the signal delay chain is a multi-tap signal delay chain.
  • the flip-flop array is configured to latch the tap states of the signal delay chain under the control of the system clock, and pass the latched tap states to the connected network in a natural order.
  • connection network configured to convert the received tap state according to a preset connection relationship, and then transmit the signal to the signal change edge search and encoding circuit
  • the signal change edge seek and encode circuit is operative to find a changed edge of the latched pulse transmitted in the signal delay chain and to generate a binary code representing the fine time stamp based on the position of the changed edge.
  • the tap state of the signal delay chain is a thermometer code indicating the position of the change edge
  • the signal change edge search and encode circuit generates a "one-hot" code for indicating the position of the change edge according to the thermometer code, and then the one-one The hot" code is transformed into a binary code representing a timestamp, which is a fine timestamp.
  • thermometer code appears to consist of several consecutive “1”s (a mercury column imaginable as a thermometer) and a few remaining “0”s, or vice versa.
  • the "one-hot” code refers to an encoding in which one bit and the other bits are the same, for example, ...00001000..., or ...111110111....
  • the former may also be referred to as a "one-hot” code represented by "1”
  • the latter may also be referred to as a "one-hot” code represented by "0".
  • the default connection relationship of the connection network is to transfer the tap state of the flip-flop array latch to the signal change edge seek and encode circuit in the original natural order.
  • the FPGA-based time-to-digital converter can measure the distribution result of the delay width of each delay unit by using the code density method.
  • the taps of the signal delay chain are respectively reordered (tap realignment). And/or tap decimation, determining a connection relationship between the tap state latched by the flip-flop array and the signal edge search and encoding circuit.
  • the connection network converts the tap state outputted by the trigger array to the signal change edge finding and encoding circuit according to the connection relationship.
  • One way of reordering is to swap the taps of the 0-width delay unit with the tap positions of the next unit.
  • the sorting process may be repeated multiple times, that is, measuring the delay width of each delay unit after one adjustment sequence, determining whether there is still a delay unit of 0 width, or Whether the number of delay units of 0 width does not exceed a threshold, and if so, the order is adjusted again until the number of 0 width delay units satisfies the condition.
  • the delay amount of each delay unit can be measured by a code density method.
  • the tapping of the tap of the delay unit is to reduce the non-uniformity (i.e., differential nonlinearity) of the delay width of each delay unit and the measurement error (i.e., integral nonlinearity) of each tap node.
  • the "tap decimation" in the present invention means that the taps (output taps) of the respective delay units are selected such that the delay units are divided into the sequentially arranged delay unit groups in accordance with the selected taps.
  • the extraction and the reordering may be applied separately or in combination, but it is more preferable to perform extraction after reordering.
  • the signal change received along the seek and encode circuit is the tap state of the reordered and/or decimate delay cell group.
  • "Picking" can minimize the measurement error (ie, integral nonlinearity) of the time-interpolation measurement based on the delay chain while improving the consistency between the delay widths between the delay cell groups (ie, differential nonlinearity).
  • the present invention can obtain higher measurement accuracy without using the unit-by-unit correction circuit.
  • the "decimation" process essentially combines several consecutive delay units to form a tap close to the width of the ideal delay unit.
  • One rule of extraction is to minimize the integral nonlinearity measured at each tap node. For a signal delay chain of a given number of delay units, although the total number of taps to be extracted is generally smaller than the original total number of taps, it is also allowed to occur if the total number of taps to be extracted is greater than or equal to the original number of taps.
  • the unit between the extracted taps can be regarded as a recombination of the original continuous delay units, and thus can be referred to as a delay unit group. Since the total number of taps after decimation can be equal to, less than, or greater than the original number of taps, the number of consecutive delay units in the delay unit group can be 1, or can be greater than 1, or 0. When the number of consecutive delay cells is 0, it is equivalent to performing more than one decimation on the same tap to generate a virtual delay cell group having a delay width of zero.
  • one of the extraction rules is to minimize the error (ie, integral nonlinearity) at each measurement point, regardless of whether the tap has been previously drawn.
  • the error ie, integral nonlinearity
  • a tap is repeatedly extracted, a delay unit of 0 width is inevitably generated, and the result is still the need for minimum integral nonlinearity.
  • the delay chain based on the internal carry chain of the FPGA generally has very poor differential Nonlinearity and integral nonlinearity, the readout of the new delay chain state formed by the decimation unit group after decimation will greatly improve the nonlinearity (integral nonlinearity and/or differential nonlinearity) of the final time measurement.
  • each delay unit B 1 , B 2 , B 3 , ..., B n , where n is the number of delay units, and the output taps at the front end of each delay unit are respectively denoted as S 1 , S 2 , S 3 , ... , S n , the taps of the extracted delay unit group are denoted as T 1 , T 2 , T 3 , ..., T R .
  • T i of the extracted delay unit group 1 ⁇ i ⁇ R
  • connection network in Figure 1 represents an implementation of the reordering and extraction process described above.
  • the connection network also exists in the existing FPGA implementation of the TDC structure, except that the sequential connection relationship (ie, the above default connection relationship) is used there.
  • the invention undergoes reordering and decimation of the delay unit, and utilizes the reconfigurable feature of the FPGA, and the connection relationship of the connected network can be changed accordingly.
  • the variation along the seek and encode circuit of the present invention preferably converts the thermometer code to a "one-hot” code using a sliding window method.
  • the process of obtaining the "one-hot” code corresponding to the thermometer code is actually the process of finding the edge of the signal.
  • the sliding window method of the present invention first divides the thermometer code into 2 N window values by a bit-by-bit moving window, the window has a bit width of m, m is a natural number, and 2 ⁇ m ⁇ 2 N , and a "one-hot" code corresponding to the thermometer code is obtained by sequentially arranging the true values corresponding to the window values.
  • the change edge search and encode circuit obtains a binary code for each bit of a "one-hot” code represented by "1” by calculating a logical OR operation of 2 N-1 "one-hot” code words. Encoding; for a "one-hot” code represented by "0”, the encoding of each bit of the binary code is obtained by computing a logical AND operation of 2 N-1 "one-hot” code words.
  • the logical OR operation of the FPGA can be implemented by using a pipeline structure in combination with a LUT of the FPGA. Each stage of the pipeline is one or several parallel logical ORs implemented by the LUT. Operation or logical AND operation.
  • the time stamp output circuit is configured to convert the binary code outputted from the search and encoding circuit and the count signal output from the coarse clock counter according to the signal change into the arrival time of the measured signal.
  • FIG. 2 is a block diagram showing the overall composition of a TDC system according to an embodiment of the present invention. It consists of a pulse signal generator, a TDL (Tapped Delay Line) consisting of a carry chain, a flip-flop array, a signal change edge seek and encode circuit, and a coarse counter and time stamp output circuit driven by the system clock.
  • the FPGA chip used in this embodiment is a Kintex-7 xc7k325t-2ffg900.
  • the system clock frequency of the FPGA is 710 MHz and the period is 1.408 ns.
  • the total delay time of the TDL consisting of the carry chain is greater than the period of one system clock, and the total number of taps is less than 200.
  • the entire TDL can be completely realized by using logic resources in one clock domain. This avoids the large delay unit appearing at the boundary of the two clock domains due to the TDL cross-clock domain.
  • the output signal of the pulse generator is triggered to change from high level to low level.
  • the signal is transmitted along the TDL, and the flip-flop array latches the state of the TDL on the rising edge of the next system clock. This state will be sent to the signal edge change seek and encode circuit.
  • the result of the encoding is the position of the signal change along the TDL, which is the fine time stamp.
  • the output of the coarse counter is the coarse timestamp of the signal under test.
  • the combination of the fine time stamp and the coarse time stamp is the time stamp of the post-measurement measurement, which is output by the time stamp output circuit.
  • the delay amounts of the delay units in the TDL are generally unequal, plus the clock signal network of the control flip-flop array, Skew exists at the clock control end of each flip-flop (ie, the clock path length of the clock network is not changed, etc.)
  • the timing of the tap state of the latch is not strict at the same time, which causes the delay width (delay time) of each delay unit to be represented to be unequal, and even some units have an effective delay width of zero.
  • the delay width of each delay unit can be obtained by measurement.
  • the code density method is a method commonly used to measure the delay amount of each delay unit. It generates an externally generated square wave signal that is not related to the system clock as an external trigger signal. Each rising edge of the signal triggers the pulse generator. A falling edge of the signal is generated (note that in this embodiment, after a fixed time due to the falling edge, the output of the pulse generator is restored to a high level), a time stamp measurement record is taken. Since the external trigger signal is not correlated with the system clock signal, the arrival time of the external trigger signal should be evenly distributed within one cycle of the system clock. Therefore, the position of the falling edge of the TDL state latched by the flip-flop array should be equally distributed in one cycle. Conversely, the number of cases (measured times) occurring at the falling edge of each delay unit should be proportional to the delay unit width, and accordingly, the delay amount width of each delay unit can be measured.
  • FIG. 3a is a diagram showing the width distribution of the delay unit measured by the code density method according to the original natural sequence of the delay chain (ie, the connection order of the delay chains) according to the embodiment of the present invention, wherein the horizontal axis is the tap number and the vertical axis is the delay width. .
  • a 0-width delay unit is disadvantageous for obtaining a high time-interpolation resolution because it superimposes its own delay amount on other delay units, causing a large amount of delay in a part of the unit, and the number of effective delay units is reduced, and the time-interpolation is resolved. The rate is reduced.
  • a zero-width delay unit produces "bubbling" in the status sequence thermometer code.
  • the ideal state sequence should be ...11110000..., but due to the existence of a zero-width delay unit, there may be a sequence of states of ...11010000..., where the first 0 is "bubble", this has The "bubbling" status code will make the search for the falling edge difficult to achieve, and it is not accurate.
  • the present invention proposes to reorder the taps of the delay unit before sending the sequence of the tapped tap states into the signal change edge search and encoding circuit, which is equivalent to The tap state of the delay unit is reordered to minimize the number of delay cells of zero width.
  • the tap position of the 0-width unit and the tap position of the next unit are interchanged, and the delay unit width distribution map is again measured by the code density method after the order is adjusted ( Similar to Fig. 3a), if there is a delay unit of 0 width, it is adjusted again according to the above rules, measured again, and adjusted again until a delay unit with little or no 0 width appears. At this point, the reordering is completed, and then the tap state of the flip-flop array latch is sent to the next signal change edge seek and encode circuit in the new order.
  • FIG. 4 is a diagram showing the width distribution of the delay unit measured after reordering according to the above method in the embodiment of the present invention, and it can be seen that all the widths are not zero.
  • Figure 3a is a differential nonlinearity diagram calculated from the delay width of Figure 3a
  • Figure 3c is an integral nonlinearity diagram calculated from the delay width of Figure 3a.
  • the abscissa of Figures 3b and 3c is the number of taps of the delay chain, and the unit of the ordinate is the ideal delay cell width (an LSB: Least Significant Bit).
  • the nonlinearity error of the delay unit of this embodiment is shown to be very large from Figs. 3b and 3c.
  • the present invention eliminates the aforementioned non-linear errors by "decimating" techniques, thereby eliminating the need for a unit-by-unit correction circuit.
  • each delay unit can be calculated according to the clock cycle.
  • the delay length, the clock period of this embodiment is 1.408 ns, and the ideal delay unit length (one LSB) is 17.6 ns. Since the four delay units and pulse generators starting in Figure 3a are in the same logic unit (SLICE) of the FPGA, there are some exceptions to the delay width variation. In this embodiment, they are directly ignored, and the fifth delay unit is labeled as the first. B 1 .
  • the next step is the extraction process of 80 taps, which is calculated by a MATLAB program on the PC based on the following extraction formula.
  • each delay unit is denoted as B 1 , B 2 , . . . , B n
  • the output taps of the respective delay units are labeled as S 1 , S 2 , . . . , S n
  • Start setting B 0 0, T i is extracted as S l , l satisfies the following conditions:
  • a minimum l is calculated, and the tap S 1 corresponding to the smallest l value is the extracted T i .
  • Figures 5a and 5b are differential nonlinear and integral nonlinearities measured by the code density method for the extracted delay chain. It can be seen that the nonlinear errors exhibited by Figures 5a and 5b are much improved compared to Figures 3b and 3c.
  • extraction and reordering delay unit by using the characteristics of reconfigurable FPGA, the connection relationship of the network connection can be changed accordingly, that is, the directly connected network is connected to the tap S l T i.
  • This change can be achieved by automatically changing the Include file in the FPGA synthesis tool software using the MATLAB program, without the need for manual wiring.
  • the falling edge marks the transmission of the signal under test on the TDL, and the latched status code on the TDL has the form of ...11110000...
  • the codewords are respectively sent to the signal change edge search and encoding circuit, which finds the position of the falling edge and generates a "one-hot" of the falling edge position of the mark.
  • the code is then encoded by the "one-hot" code into a binary code output. This process is essentially equivalent to the basic problem of transcoding from thermometer code to binary code.
  • the FPGA logic resources used in the signal change edge search and encode circuits are the basic lookup tables in the smallest logical resource unit within the FPGA chip.
  • the basic structure of the basic lookup table resources in the two mainstream FPGAs (Xilinx and Altera) is not completely the same.
  • the main difference is that the input maximum bit width and the number of output signals of the basic lookup table are different, for example, Kintex- used in this embodiment.
  • the basic lookup table structure of 7FPGA is shown in Figure 7. It has 6 inputs and 2 outputs.
  • the lookup table can be used as a 6-input lookup table (6-LUT) or as a 5-input lookup table (5-LUT), where I5 is assigned a value of 1.
  • Lookup tables for FPGAs from other series or other companies are similar.
  • This embodiment uses the lookup table of Figure 7 as two 5-LUTs, one for the seek circuit of the falling edge and the other for the time being.
  • the search principle of the change edge is shown in Fig. 8.
  • the sliding window structure is used to find in parallel whether there are interesting edges in the window.
  • Each sliding window has a width of 5, which is the input bit width of the basic lookup table. If the input of the last window is less than 5 digits, it is filled with "1". If a change edge of interest is found in a window, the output of the window is 1, otherwise 0.
  • D i represents the "one-hot" code of the falling edge, and i is 0 or a positive integer.
  • Table 1 is a truth table for a basic lookup table for change edge search with "bubble" error correction capability according to an embodiment of the present invention, where D i is only 1 in the case of 11110, and all other cases are 0.
  • the above truth table is arranged such that the change edge seek has a certain "bubble" fault tolerance capability, for example, if a codeword of ...1111010000... appears, the last one will be ignored. This means that by looking up the table's truth table assignment, the change edge looks for "bubbling" error correction.
  • the maximum error correction is that there are three consecutive "bubbling”. This is sufficient for status code words that are reordered by TDL state, because in our practice, no two "bubbling" conditions have occurred.
  • the "one-hot" code of this embodiment there is only one 1, and the rest are all 0, wherein the position of 1 indicates the position of the change edge (of course, there may be only one 0, and the rest are 1, wherein the position of 0 is The position of the change edge).
  • the "one-hot" code is converted into an 8-bit binary code (A 7 , A 6 , A 5 , A 4 , A 3 , A 2 , A 1 , A 0 ).
  • the idea of the coding algorithm used is that which codewords in the "one-hot" code are 1 causes one of the binary codes to be one.
  • Table 2 of the present embodiment provides a "one-hot" encoding operation algorithm code to the embodiment described binary code table of the present invention.
  • the 128-bit position can be simply represented as x1xxxxxx, where x takes values of 0 and 1, respectively.
  • the circuit principle of the above coding algorithm is shown in FIG. 9.
  • the basic lookup table is still used here, but it is used here as a 6-LUT.
  • the coding OR operation of this embodiment is implemented using a three-stage pipeline structure.
  • the first stage consists of 22 6-LUTs, which can receive 132 inputs.
  • the second stage has 4 6-LUTs.
  • the third stage has only one 6-LUT.
  • Each stage uses a D flip-flop array to buffer data.
  • the truth table for all 6-LUTs is an OR operation.
  • the last output A i represents a bit in the binary code.
  • For the 8-bit binary code of the falling edge of this embodiment a total of 8 sets of the above-mentioned pipeline operation circuits are required, and they are operated in parallel, and the pipeline structure enables the speed of the coding operation to reach the system clock frequency.
  • the present invention is a TDC design method that minimizes nonlinear errors. Minimizing nonlinear errors inevitably leads to an increase in measurement accuracy.
  • the TDC of the two channels is realized by using the delay chain as shown in FIG. 3a, without using the unit-by-unit correction method, nor using the present invention. Reorder and extract, measuring a fixed time interval. The measured histogram is shown in Figure 6a.
  • Figure 10 shows the standard error of a fixed time interval measured by the TDC in this embodiment as a function of the total number of decimations.
  • the horizontal axis is the total number of taps extracted, and the vertical axis is the standard for the 3.3 ns time interval of the two-channel TDC measurement. error.

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Abstract

一种基于FPGA芯片的TDC，其包括一个脉冲信号发生器、多抽头的信号延迟链、触发器阵列、连接网络、信号变化沿寻找和编码电路、时间戳输出电路。脉冲信号发生器在被测信号的触发下产生一个下降沿并馈入到信号延迟链。触发器阵列在系统时钟的控制下对延迟链各抽头状态进行锁存，并传递给连接网络。连接网络根据事先测量到的延迟链各延迟单元延迟宽度的分布对锁存后的各抽头进行重排序和抽取，将抽头的状态传递给信号变化沿寻找和编码电路。能够最大限度地消除延迟链上的0延迟单元和非线性误差的影响，减少抽头状态温度计码中的"冒泡"现象。

Description

一种基于FPGA的时间数字变换器 技术领域
本发明属于时间量的数字化测量领域，具体涉及一种基于FPGA的时间数字变换器。
背景技术
时间测量是指测量一个事件发生的时刻，或者是测量两个事件之间的时间间隔。时间测量技术在许多领域都具有重要应用，例如高能物理实验研究、核医学成像、军事和民用雷达，以及激光测距等领域都需要高精度的时间测量技术。时间数字变换器(TDC：Time-Digital-Convertor)就是一种将时间量转化为数字量以实现一个事件发生时刻的记录的功能器件。对于两个事件之间的时间间隔的测量，一般可以由两个TDC分别测量两个事件的发生时刻，两个发生时刻的差值就是该两个事件的时间间隔。目前，TDC的实现载体可分为基于ASIC(Application Specific Integrated Circuit)专用芯片和基于FPGA(Field Programmable Gate Array)可编程器件两种。随着FPGA技术的不断发展，单片FPGA能够提供的逻辑资源量越来越大，其可编程配置的灵活性也越来越强，FPGA已经成为数字系统集成设计的平台。在此平台上，如果能够同时实现一些物理量的测量，例如时间量的测量，无疑对基于FPGA的用户特制的数据获取和处理系统有重要意义。近年来，基于FPGA的TDC设计技术有很大发展，其中最重要的一种途径是利用FPGA基本逻辑资源中的进位链构成多抽头的信号传输延迟链(TDL：Tapped Delay Line)，从而实现时间量的内插来提高TDC的测量精度。
基于FPGA的TDL型TDC有多种可能的具体实现方案，不同方案能够实现的TDC测量精度和测量死时间不同，单通道TDC所占用的FPGA逻辑资源量也不同。小的测量死时间可以提高TDC的测量吞吐量，少的逻辑资源占用量可以节省FPGA资源用于用户设计的数据获取和处理系统的其他部分，或者可以实现单片FPGA上的多通道TDC系统。 然而，当前的TDC实现方案不能在提高测量精度、降低测量死时间和减少资源占用量这三个方面均得到好的指标。
为便于理解，先对利用FPGA芯片的进位链逻辑资源构成多抽头传输延迟链(TDL：Tapped Delay Line)实现时间内插，从而提高TDC测量精度的原理进行简单介绍。
事件发生时刻的数字化测量的最简单实现方法可以是用一个高速时钟计数器来实现。在被测信号到来时，记录下当时的计数器的状态，该状态就是事件发生时刻的时间测量值。该方法的TDC精度就是计数器时钟信号的周期。为了获得高测量精度，必须使用非常高的时钟频率。目前基于FPGA的最高时钟频率大约为710MHz，即最高测量精度约为1.408ns。为了提高TDC的测量精度，目前基于FPGA技术的一种常用方法是设法构造出一条由多个延迟单元联成的延迟链。该延迟链的总延迟时间要大于一个系统时钟的周期，每个延迟单元的状态由抽头引出。将被测信号馈入该延迟链中传输，在每个系统时钟的到来时刻同时记录下时钟计数器的状态和延迟链的状态。前者是被测信号的粗时间标记，后者是被测信号的细时间标记，将两者结合就是被测信号的精确测量结果。使用这种时间内插技术，TDC的测量精度主要取决于延迟链中延迟单元的大小和精度。目前，大多是利用FPGA算术逻辑运算资源中的进位链来构成延迟链，每一个延迟单元的长度就是对应进位链的传输延迟量。使用和进位链处于同一资源单位中的触发器可以把延迟量各抽头的状态引出，以用于后续电路对延迟量状态的编码输出。对于要求测量两个事件的时间间隔的情况，可以采用两个TDC通道，分别记录两个事件的发生时刻，二者之间的差值就是时间间隔。
各延迟单元的延迟宽度具有非均匀性，且各测量节点存在测量误差。可以用微分非线性和积分非线性来分别表示上述非均匀性和测量误差。微分非线性可以定义为实际延迟单元的延迟宽度与理想延迟宽度的差，一般用理想延迟宽度(1个LSB)为单位表示。积分非线性可以定义为从第一个延迟单元到所在测量节点的所有延迟单元的微分非线性的和。它表示所在测量节点的读数值与理想测量值之间的误差，一般也用理想 延迟宽度(LSB)为单位表示。在TDC测量中，如果不借用逐单元校正的话，积分非线性就是各测量节点的测量误差，因此要去除逐单元校正电路的需要，必须要尽量改善积分非线性。
发明内容
本发明旨在有效地提高TDC的测量精度的同时，减小其测量死时间和降低单个TDC通道所要占用的FPGA逻辑资源量。
为解决上述技术问题，本发明提出一种基于FPGA的时间数字变换器，包括粗时钟计数器、脉冲信号发生器、信号延迟链、触发器阵列、连接网络、信号变化沿寻找和编码电路，以及时间戳输出电路，其中，粗时钟计数器由系统时钟信号驱动，用于产生被测信号的粗时间戳；所述脉冲信号发生器用于是在被测信号的触发下产生一个具有变化沿的脉冲并馈入到所述信号延迟链中进行传输；所述信号延迟链用于对被测信号进行延时传输，由多个延迟单元组成，且在每个延迟单元的后方具有抽头，第一个延迟单元前方也具有抽头；所述触发器阵列用于对信号延迟链的各抽头状态进行锁存，并将锁存的抽头状态按照所述抽头的自然排序传递给所述连接网络；所述连接网络用于将接收到的抽头状态按照预先设定的连接关系进行变换，再传递给所述信号变化沿寻找和编码电路；所述信号变化沿寻找和编码电路用于寻找被锁存的在所述信号延迟链中传输的脉冲的变化沿，并根据所述变化沿的位置生成表示细时间戳的二进制码；所述时间戳输出电路用于根据信号变化沿寻找和编码电路输出的二进制码细时间戳和粗时钟计数器输出的粗时间戳一起换算成被测信号的到来时间戳并将其输出。
根据本发明的具体实施方式，所述连接网络将接收到的抽头状态按照预先设定的连接关系进行的变换包括：将所述信号延迟链的各抽头进行重排序，确定一种将所述触发器阵列连接到所述信号变化沿寻找和编码电路的连接关系。
根据本发明的具体实施方式，所述重排序包括：将0宽度延迟单元的抽头和下一个延迟单元的抽头位置互换。
根据本发明的具体实施方式，所述重排序可重复多次进行，在一次调整顺序之后测量各延迟单元的延迟宽度，判断0宽度的延迟单元个数是否超过一个阈值，如果是，则再次重排序，直到0宽度延迟单元的个数不超过所述阈值。
根据本发明的具体实施方式，所述测量各延迟单元的延迟宽度是采用码密度法测量各延迟单元的延迟宽度。
根据本发明的具体实施方式，所述连接网络将接收到的抽头状态按照预先设定的连接关系进行的变换包括：对所述信号延迟链的各抽头进行抽取，确定一种将所述触发器阵列连接到所述信号变化沿寻找和编码电路的连接关系。
根据本发明的具体实施方式，所述抽取的规则是：使基于所述信号延迟链所作的时间内插测量的积分非线性最小。
根据本发明的具体实施方式，所述抽取为：先设定信号延迟链中被抽取后的总抽头数为R，然后根据系统时钟周期Tclock计算出抽取后形成的延迟单元组的理想延迟长度w：w＝Tclock/R Tclock，并根据该理想延迟长度w完成抽取。
根据本发明的具体实施方式，抽取的是满足下述公式的抽头Sl，1≤l≤n：
Figure PCTCN2015072862-appb-000001
其中，设原始的各延迟单元的延迟宽度为B1、B2、B3、…、Bn，n为延迟单元的个数，原始的各个延迟单元的输出抽头分别记为S1、S2、S3、…、Sn，上式中用到的B0是为了是上式成立而添加的一个虚拟延迟量，B0＝0，抽取后的抽头记为T1、T2、T3、…、TR，上式对每一个给定的i，都会计算得到一个最小的l，该最小的l值对应的抽头Sl就是抽取后的Ti。
根据本发明的具体实施方式，所述信号变化沿寻找和编码电路根据从所述连接网络接收的抽头状态生成一个表示变化沿位置的温度计码， 根据该温度计码生成用于表示变化沿位置的“one-hot”码，再将该“one-hot”码变换为表示时间戳的二进制码。
根据本发明的具体实施方式，所述信号变化沿寻找和编码电路通过一个逐位移动的窗口将所述温度计码切分得到2N个窗口值，n＝2N，n为延迟单元的个数，所述窗口的位宽为m，m为自然数且2≤m≤2N，并通过依序排列所述窗口值所对应的真值得到与所述温度计码对应的“one-hot”码。
根据本发明的具体实施方式，所有可能的窗口值与对应的真值之间转换的真值表存储在FPGA中的基本逻辑单元LUT中。
根据本发明的具体实施方式，当所述信号变化沿寻找和编码电路用于寻找温度计码的下降沿时，在所述真值表中，只有最后一位是0、其余位均为1的窗口值对应的真值为1，其余窗口值对应的真值均为0；或者，只有最后一位是0、其余位均为1的窗口值对应的真值为0，其余窗口值对应的真值均为1。
根据本发明的具体实施方式，所述变化沿寻找和编码电路对于用“1”表示的“one-hot”码，通过计算2N-1个“one-hot”码字的逻辑“或”运算来得到二进制码的每一位的编码；对于用“0”表示的“one-hot”码，通过计算2N-1个“one-hot”码字的逻辑“与”运算来得到二进制码的每一位的编码。
根据本发明的具体实施方式，所述变化沿寻找和编码电路利用流水线结构组合使用FPGA的LUT实现所述逻辑“或”运算或者逻辑“与”运算，流水线的每一级是一个或若干个并行的依靠LUT而实现的逻辑“或”运算或逻辑“与”运算。
此外，本发明还提出一种基于FPGA的温度计码到二进制码的编码转换方法，所述温度计码具有2N位，所述二进制码具有N位，N为自然数，所述方法包括：通过一个逐位移动的窗口将所述温度计码切分得到2N个窗口值，所述窗口的位宽为m，m为自然数且2≤m≤2N，并通过依序排列所述窗口值所对应的真值得到与所述温度计码对应的“one-hot”码；将所述“one-hot”码转换为二进制码。
根据本发明的具体实施方式，所有可能的窗口值与对应的真值之间转换的真值表存储在FPGA中的基本逻辑单元LUT中。
根据本发明的具体实施方式，当所述信号变化沿寻找电路用于寻找温度计码的上升沿时，在所述真值表中，只有第一位是0、其余位均为1的窗口值对应的真值为1，其余窗口值对应的真值均为0；或者，只有第一位是0、其余位均为1的窗口值对应的真值为0，其余窗口值对应的真值均为1；当所述信号变化沿寻找电路用于寻找温度计码的下降沿时，在所述真值表中，只有最后一位是0、其余位均为1的窗口值对应的真值为1，其余窗口值对应的真值均为0；或者，只有最后一位是0、其余位均为1的窗口值对应的真值为0，其余窗口值对应的真值均为1。
根据本发明的具体实施方式，在所述“one-hot”码到二进制码的转换过程中，对于用“1”表示的“one-hot”码，通过计算2N-1个“one-hot”码字的逻辑“或”运算来得到二进制码的每一位的编码；对于用“0”表示的“one-hot”码，通过计算2N-1个“one-hot”码字的逻辑“与”运算来得到二进制码的每一位的编码。
根据本发明的具体实施方式，利用流水线结构组合使用FPGA的LUT实现所述逻辑“或”运算或者逻辑“与”运算，流水线的每一级是一个或若干个并行的依靠LUT而实现的逻辑“或”运算或逻辑“与”运算。
本发明还提出一种基于FPGA的温度计码到二进制码的编码转换装置，所述温度计码具有2N位，所述二进制码具有N位，N为自然数，所述编码转换装置包括信号变化沿寻找电路和“one-hot”码到二进制码转换电路，其中，所述信号变化沿寻找电路通过一个逐位移动的窗口将所述温度计码切分得到2N个窗口值，所述窗口的位宽为m，m为自然数且2≤m≤2N，并通过依序排列所述窗口值所对应的真值得到与所述温度计码对应的“one-hot”码；所述“one-hot”码到二进制码转换电路用于将所述“one-hot”码转换为二进制码。
根据本发明的具体实施方式，所有可能的窗口值与对应的真值之间的转换真值表存储在在FPGA逻辑资源的LUT中。
根据本发明的具体实施方式，当所述信号变化沿寻找电路用于寻找温度计码的上升沿时，在所述真值表中，只有第一位是0、其余位均为1的窗口值对应的真值为1，其余窗口值对应的真值均为0；或者，只有第一位是0、其余位均为1的窗口值对应的真值为0，其余窗口值对应的真值均为1；当所述信号变化沿寻找电路用于寻找温度计码的下降沿时，在所述真值表中，只有最后一位是0、其余位均为1的窗口值对应的真值为1，其余窗口值对应的真值均为0；或者，只有最后一位是0、其余位均为1的窗口值对应的真值为0，其余窗口值对应的真值均为1。
根据本发明的具体实施方式，所述“one-hot”码到二进制码转换电路对于用“1”表示的“one-hot”码，通过计算2N-1个“one-hot”码字的逻辑“或”运算来得到二进制码的每一位的编码；对于用“0”表示的“one-hot”码，通过计算2N-1个“one-hot”码字的逻辑“与”运算来得到二进制码的每一位的编码。
根据本发明的具体实施方式，利用流水线结构组合使用FPGA的LUT实现所述逻辑“或”运算或者逻辑“与”运算，流水线的每一级是一个或若干个并行的依靠LUT而实现的逻辑“或”运算或逻辑“与”运算。
本发明的TDC能够使测量精度、测量死时间和资源占用量这三个方面的性能指标达到合理平衡，从而能够实现高性能的TDC测量系统，在时间测量的相关领域有重要应用价值。
附图说明
图1是本发明的TDC结构示意图；
图2为本发明的一个实施例提供的TDC系统总体组成框图；
图3a为本发明所述实施例提供的延迟链抽头自然排列顺序下使用码密度法所测量得到的延迟单元宽度分布图；
图3b为根据图3a的延迟单元宽度计算得到的微分非线性图；
图3c为根据图3a的延迟单元宽度计算得到的积分非线性图；
图4为本发明所述实施例提供的延迟链抽头状态重排序后使用码密度法所测量得到的延迟单元宽度分布图；
图5a为本发明实施例提供的延迟链抽头状态抽取后使用码密度法测量得到的微分非线性图；
图5b为本发明实施例提供的延迟链抽头状态抽取后的使用码密度法测量得到的积分非线性图；
图6a为本发明实施例提供的延迟链抽头状态原自然连接输出情况下，双TDC通道测量3.3ns时间间隔的测量直方图；
图6b为本发明实施例提供的延迟链抽头状态经过本发明变换连接关系后输出的情况下，双TDC通道测量3.3ns时间间隔的测量直方图；
图7为本发明所述实施例提供的Kintex-7FPGA基本查找表结构示意图；
图8为本发明所述实施例提供的使用滑动窗结构寻找信号变化沿原理示意图；
图9为本发明所述实施例提供的使用流水线结构实现128位逻辑“或”运算结构示意图；
图10为本发明所述实施例抽头抽取总数与双TDC通道测量3.3ns时间间隔的标准误差关系图。
具体实施方式
图1是本发明提供的基于FPGA的时间数字变换器的结构示意图。如图1所示，其包括粗时钟计数器、脉冲信号发生器、信号延迟链、触发器阵列、连接网络、信号变化沿寻找和编码电路以及时间戳输出电路。
粗时钟计数器由系统时钟信号驱动，并用于产生被测信号的粗时间戳。
脉冲信号发生器是外触发的，其用于是在被测信号的触发下产生一个具有变化沿的脉冲并馈入到信号延迟链中进行传输。所述变化沿可选为上升沿或者下降沿。
信号延迟链用于对被测信号进行延时传输，其由多个延迟单元组成，且在每个延迟单元的前端具有抽头，因此信号延迟链是多抽头的信号延迟链。
触发器阵列用于在系统时钟的控制下，对信号延迟链的各抽头状态进行锁存，并将该锁存的抽头状态按照自然排序传递给所述连接网络。
连接网络，用于将接收到的锁存的抽头状态按照预先设定的连接关系进行变换，再传递给所述信号变化沿寻找和编码电路；
信号变化沿寻找和编码电路用于寻找被锁存的在信号延迟链中传输的脉冲的变化沿，并根据所述变化沿的位置生成表示细时间戳的二进制码。通常，信号延迟链的抽头状态是一个表示变化沿位置的温度计码，信号变化沿寻找和编码电路根据该温度计码生成用于表示变化沿位置的“one-hot”码，再将该“one-hot”码变换为表示时间戳的二进制码，该时间戳是一个细时间戳。
温度计码表现为连续若干个“1”(可想象为温度计的水银柱)和剩余若干个“0”组成，或者相反。“one-hot”码则是指除了其中的一个位、其他的位均相同的编码，例如…00001000…，或者…111110111…。前者也可称为由“1”表示的“one-hot”码，后者也可称为由“0”表示的“one-hot”码。
根据本发明，所述连接网络的缺省连接关系是将触发器阵列锁存的抽头状态按照原始的自然排序传送给所述信号变化沿寻找和编码电路。在缺省连接情况下，所述基于FPGA的时间数字变换器可以使用码密度法测量得到各延迟单元延迟宽度的分布结果，在此基础上，对信号延迟链各抽头分别经过重排序(tap realignment)和/或抽取(tap decimation)，确定一种将触发器阵列锁存的抽头状态连接到所述信号变化沿寻找和编码电路之间的连接关系。所述连接网络根据该连接关系，将触发器阵列输出的抽头状态变换后输送给所述信号变化沿寻找和编码电路。
一种重排序的方式是：将0宽度延迟单元的抽头和下一个单元的抽头位置互换。该排序过程可以重复多次进行，即：在一次调整顺序之后测量各延迟单元的延迟宽度，判断是否还存在0宽度的延迟单元，或者 0宽度的延迟单元个数是否不超过一个阈值，如果是，则再次调整顺序，直到0宽度延迟单元的个数满足条件为止。其中，可通过码密度法测量各延迟单元的延迟量。
对延迟单元的抽头(tap)进行抽取(decimate)是为了减小各延迟单元的延迟宽度的非均匀性(即微分非线性)和各抽头节点的测量误差(即积分非线性)。本发明中的所述的“抽取(tap decimation)”是指对各延迟单元的抽头(输出抽头)进行选取，以使得根据所选取的抽头将各延迟单元划分成按顺序排列的延迟单元组。所述抽取和所述重排序可以单独应用，也可以结合使用，但更优选为在重排序后进行抽取。
所述信号变化沿寻找和编码电路接收的是重排序和/或抽取后的延迟单元组的抽头状态。“抽取”能使得基于该延迟链所作的时间内插测量的测量误差(即积分非线性)最小，同时改善延迟单元组之间延迟宽度之间的一致性(即微分非线性)。由此，本发明可以在不借助逐单元校正电路的情况下，获得较高的测量精度。
所述“抽取”的过程本质上是将几个连续的延迟单元连接起来尽量形成一个接近理想延迟单元宽度的抽头，抽取的一种规则是使在每一抽头节点测量的积分非线性最小。对于给定延迟单元的个数的信号延迟链，虽然要抽取的抽头总数一般都会小于原始的抽头总数，但也允许出现要抽取的抽头总数大于或等于原始抽头数的情况。
抽取后的各个抽头之间的单元可以看作是原始连续的延迟单元的重新组合，因此可称为延迟单元组。由于抽取后的抽头总数可以等于、小于或大于原始抽头数，因此延迟单元组内连续的延迟单元的个数可以是1，也可以大于1，或者是0。当连续的延迟单元的个数为0时，相当于对于同一抽头进行了多于1次的抽取而产生了一个延迟宽度为0的虚拟延迟单元组。
如前所述，抽取规则之一是使得在各个测量点的误差(即积分非线性)最小，而不管该抽头是否已被前面抽过。当一个抽头被重复抽取时，必然会产生0宽度的延迟单元，这样的结果仍然是积分非线性最小的需要。由于基于FPGA内部进位链构成的延迟链一般都具有非常差的微分 非线性和积分非线性，对抽取后形成的由延迟单元组构成的新延迟链状态的读出，都会使得最终的时间测量的非线性(积分非线性和/或微分非线性)大为改善。
抽取的一种具体实施方式是，先设定信号延迟链中被抽取后的总抽头数为R，然后根据系统时钟周期Tclock计算出抽取后形成的延迟单元组的理想延迟长度w：w＝Tclock/R，并根据该理想延迟长度w完成抽取。
设各延迟单元的延迟宽度为B1、B2、B3、…、Bn，n为延迟单元的个数，各个延迟单元前端的输出抽头分别记为S1、S2、S3、…、Sn，抽取后的延迟单元组的抽头记为T1、T2、T3、…、TR。对于抽取后的延迟单元组的抽头Ti，1≤i≤R，则其抽取的是满足下述公式最小l值对应的的抽头Sl，1≤l≤n：
Figure PCTCN2015072862-appb-000002
其中，B0是为了使上式成立而添加的一个虚拟延迟量，B0＝0。
在图1中的连接网络来代表上述重排序和抽取过程的实现形式。其实，该连接网络在现有的FPGA实现的TDC结构中也存在，只不过那里使用的是按顺序的连接关系(即上述缺省连接关系)。本发明经过了延迟单元的重排序和抽取，利用的是FPGA的可重配置特点，将连接网络的连接关系做相应改变即可。
为避免“冒泡”现象的干扰，本发明的变化沿寻找和编码电路优选为采用滑动窗法将温度计码转换为“one-hot”码。获得与温度计码对应的“one-hot”码的过程其实就是寻找信号变化沿的过程。在此，我们设信号延迟链的抽头数为n＝2N，则温度计码具有2N位，所转换得到的二进制码为N位，N为自然数。
具体来说，本发明的滑动窗法首先通过一个逐位移动的窗口将所述温度计码切分得到2N个窗口值，所述窗口的位宽为m，m为自然数且 2≤m≤2N，并通过依序排列所述窗口值所对应的真值得到与所述温度计码对应的“one-hot”码。
此外，为了消除“冒泡”的影响，在此规定，当所述变化沿寻找和编码电路用于寻找温度计码的下降沿时，只有最后一位是0、其余位均为1的窗口值对应的真值为1，其余窗口值对应的真值均为0(对于由“1”表示的“one-hot”码)；或者，只有最后一位是0、其余位均为1的窗口值对应的真值为0，其余窗口值对应的真值均为1(对于由“0”表示的“one-hot”码)。所有可能的窗口值与对应的真值之间的转换真值表存储在FPGA逻辑资源的LUT中。
所述变化沿寻找和编码电路对于用“1”表示的“one-hot”码，通过计算2N-1个“one-hot”码字的逻辑“或”运算来得到二进制码的每一位的编码；对于用“0”表示的“one-hot”码，通过计算2N-1个“one-hot”码字的逻辑“与”运算来得到二进制码的每一位的编码。通过FPGA实现时，可利用流水线结构组合使用FPGA的LUT实现所述逻辑“或”运算或者逻辑“与”运算，流水线的每一级是一个或若干个并行的依靠LUT而实现的逻辑“或”运算或逻辑“与”运算。
时间戳输出电路用于根据信号变化沿寻找和编码电路输出的二进制码和粗时钟计数器输出的计数信号一起换算成被测信号的到来时间。
下面通过对本发明的一个实施例的技术方案的描述来使本发明的特点和有益效果更加清楚、完整。应当了解，在此所描述的实施例仅仅是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
图2是本发明的一个实施例提供的TDC系统总体组成框图。它包括一个脉冲信号发生器、一条由进位链构成的TDL(Tapped Delay Line)、一个触发器阵列、一个信号变化沿寻找和编码电路以及一个由系统时钟驱动的粗计数器和时间戳输出电路。本实施例所使用的FPGA芯片是Kintex-7 xc7k325t-2ffg900。
在本实施例中，FPGA的系统时钟频率为710MHz，周期为1.408ns。由进位链构成的TDL的总延迟时间长度要大于一个系统时钟的周期，其总抽头数小于200个，整个TDL可以完整地在利用一个时钟域内的逻辑资源来实现。这样做可以避免由于TDL跨时钟域，在两个时钟域的边界处出现较大的延迟单元。每次被测信号到来，都会触发脉冲发生器的输出信号由高电平变化到低电平，该信号沿着TDL传输，触发器阵列在下一个系统时钟的上升沿锁存TDL的状态。该状态将送给信号沿变化寻找和编码电路。编码的结果就是信号变化沿在TDL中的位置，也就是细时间戳。所述粗计数器的输出是被测信号的粗时间戳。将细时间戳和粗时间戳的组合就是测后测量的时间标记，由时间戳输出电路输出。
由于TDL中各延迟单元的延迟量一般是不相等的，再加上控制触发器阵列的时钟信号网络在各个触发器的时钟控制端存在Skew(即由于时钟网络传输路径长度不等等原因造成触发器锁存的抽头状态的时刻不严格同时)，会造成所表现的各个延迟单元的延迟宽度(延迟时间)不等，甚至有些单元的有效延迟宽度为0。可以通过测量得到各延迟单元的延迟宽度。
码密度法是一种常用于测量各延迟单元延迟量大小的方法，它是在外部产生一个和系统时钟不相关的方波信号作为外触发信号，该信号的每个上升沿都会触发脉冲发生器产生一个信号下降沿(注意，在该实施例中，下降沿产生的固定时间后，脉冲发生器的输出会恢复为高电平)，进行一次时间标记测量记录。由于外触发信号和系统时钟信号不相关，外触发信号的到来时刻应该均匀地分布在系统时钟的一个周期内。因而触发器阵列锁存下来的TDL状态，其下降沿的位置应该等概率地分布在一个周期内。反过来说，发生在每个延迟单元的下降沿的事例数(测得次数)应该和延其迟单元宽度成正比，据此，就可以测得各个延迟单元的延迟量宽度。
图3a是本发明所述实施例按照延迟链的原始自然顺序(即延迟链的连接顺序)，利用码密度法测量得到的延迟单元宽度分布图，其横轴是抽头序号，纵轴是延迟宽度。
从图3a中可看出，有相当一大部分的延迟单元的有效延迟宽度为0，即这些单元从来不能独立地看到信号的变化沿。0宽度的延迟单元对获得高的时间内插分辨率不利，因为它将自己的延迟量叠加到了其它延迟单元上，造成部分单元延迟量较大，而且有效延迟单元个数减少，时间内插分辨率降低。另一方面，零宽度的延迟单元会在状态序列温度计码中产生“冒泡”。以下降沿为例，理想的状态序列应该为…11110000…，但由于零宽度的延迟单元存在，有可能会出现…11010000…的状态序列，其中第一个0就是“冒泡”，这种具有“冒泡”的状态码会造成下降沿的寻找难以实现，找到了也不准确。为了挽回这一部分造成的损失和降低变化沿寻找电路的设计难度，本发明提出在将锁存的抽头状态序列送入信号变化沿寻找和编码电路之前，将延迟单元的抽头重排序，相当于将延迟单元的抽头状态进行重排序以最大限度地减少0宽度的延迟单元数。
该实施例中，根据码密度法测到的各单元延迟量分布图，将0宽度单元的抽头和下一个单元的抽头位置互换，调整顺序后再次用码密度法测量延迟单元宽度分布图(类似于图3a)，如还有0宽度的延迟单元存在，就再次按上述规则调整，再次测量，再次调整，直到几乎没有或完全没有0宽度的延迟单元出现为止。至此，重排序完成，然后将触发器阵列锁存的抽头状态按照新的顺序送给接下来的信号变化沿寻找和编码电路。
图4是本发明实施例按上述方法重排序后测量得到的延迟单元宽度分布图，可见所有的宽度都不为0。
从图3a中还可看出，除了前四个延迟单元似乎看起来是例外，其他各延迟单元的延迟宽度的差别很大。图3b是根据图3a的延迟宽度计算的微分非线性图，图3c是根据图3a的延迟宽度计算的积分非线性图。图3b和图3c的横坐标是延迟链的抽头数，纵坐标的单位是理想的延迟单元宽度(一个LSB：Least Significant Bit))。从图3b和图3c显示了该实施例的延迟单元的非线性误差非常大。现有技术中，对于如此大的非线性误差必须要求对测量结果进行逐单元校正，一般的基于信号延迟链 的TDC结构中，都要有在线的逐单元校正电路，利用已经测量到的积分非线性来标定每一次的测量结果。但是，如前所述，本发明通过“抽取”技术来消除上述非线性误差，从而不需要逐单元校正电路。
在该实施例中，在抽取时，需要先设定好该TDL中需要进行抽取过程的抽头总数R，本实施例设定为R＝80，然后根据时钟周期可以计算出每一个延迟单元理想的延迟长度，本实施例的时钟周期为1.408ns，理想的延迟单元长度(一个LSB)为17.6ns。由于图3a中开始的四个延迟单元和脉冲发生器处于FPGA同一个逻辑单元(SLICE)中，其延迟宽度变化有些例外，本实施例中直接忽略它们，将第五个延迟单元标定为第一个B1。接下来就是80个抽头的抽取过程，该过程由PC机上的一个MATLAB程序根据下述抽取公式来计算实现。参见图2，各延迟单元的延迟宽度记为B1、B2、…、Bn，各个延迟单元的输出抽头分别标记为S1、S2、...、Sn，抽取后的抽头标记为T1、T2、...、TR，在本实施例中R＝80。开始设定为B0＝0，Ti抽取为Sl，l满足以下条件：
通过
Figure PCTCN2015072862-appb-000003
计算得到一个最小的l，该最小的l值对应的抽头Sl就是抽取后的Ti。
上式表示的抽取过程是使得积分非线性的误差最小化。
图5a和图5b是抽取后的延迟链用码密度法测量到的微分非线性图和积分非线性图。可见，和图3b和图3c相比，图5a和图5b表现的非线性误差改善很多。
本发明中对延迟单元的重排序和抽取，利用的是FPGA的可重配置特点，将连接网络的连接关系做相应改变即可，即该连接网络直接将抽头Sl连接到Ti。这一改变可以利用MATLAB程序自动更改FPGA综合工具软件中的Include文件来实现，不需要手工布线的参与。
在该实施例中，由于被测信号触发一个脉冲发生器的下降沿，该下降沿标志着被测信号在TDL上的传输，TDL上被锁存的状态码具有…11110000…的形式，现在这样的码字分别送给信号变化沿寻找和编码电路，由其找出下降沿的位置，并生成一个标志下降沿位置的“one-hot” 码，然后再由“one-hot”码编码为二进制码输出。这个过程实质上等同为由温度计码到二进制码的转换编码的基本问题。
信号变化沿寻找和编码电路所使用的FPGA逻辑资源都是FPGA芯片内最小逻辑资源单位中的基本查找表。目前两大主流FPGA(Xilinx和Altera)内的基本查找表资源的具体结构形式不完全相同，主要区别在基本查找表的输入最大位宽和输出信号数不同，例如本实施例所使用的Kintex-7FPGA的基本查找表结构如图7所示。它有6个输入端，2个输出端。该查找表可以被用作一个6输入查找表(6-LUT)，也可以被用作2个5输入查找表(5-LUT)，此时I5要被赋值为1。其它系列或其它公司的FPGA的查找表和此类似。本实施例将图7的查找表用作2个5-LUT，其中一个用于下降沿的寻找电路，另一个暂且不用。变化沿的寻找原理如图8所示。利用滑动窗结构并行寻找窗内是否有感兴趣的变化沿，每个滑动窗的宽度为5，它是基本查找表的输入位宽。最后一个窗的输入若不足5位，则用“1”补齐。如果一个窗内发现到了感兴趣的变化沿，该窗的输出为1，否则为0。这样所有窗的输出就将经过重排序了的TDL状态码变换为“one-hot”码。图8中用Di表示下降沿的“one-hot”码，i为0或正整数。
表1.变化沿寻找电路的真值表
Figure PCTCN2015072862-appb-000004
表1为本发明实施例提供的具有“冒泡”纠错能力的用于变化沿寻找的基本查找表的真值表，其中Di只有在11110情况下才为1，其它情况均为0。
上述真值表的安排，使得变化沿寻找具有一定的“冒泡”容错能力，例如如果出现…1111010000…的码字，则最后一个1将被忽略。这就是说通过查找表的真值表赋值，变化沿寻找具有“冒泡”纠错能力。对于本实施例，最大能够纠错的情况是出现连续3个“冒泡”。这对于经过TDL状态重排序的状态码字已是足够了，因为在我们实践中，没有发现有连续两个“冒泡”情况的发生。
在本实施例的“one-hot”码中只有一个1，其余都为0，其中1的位置标明变化沿的位置(当然，也可以是只有一个0，其余都为1，其中0的位置就是变化沿的位置)。本实施例要把该“one-hot”码转化为8位的二进制码(A7，A6，A5，A4，A3，A2，A1，A0)。所采用编码算法的思路是在“one-hot”码中哪些码字为1会造成二进制码中的某一个码字为1。
以A6的编码算法为例，表2为本发明实施例提供的“one-hot”码到二进制码的编码运算算法说明表。
表2.使编码输出A6＝1的所有Di情况
A7 A6 A5 A4 A3 A2 A1 A0 Di
0 1 0 0 0 0 0 0 D64
0 1 0 0 0 0 0 0 D65
… … … … … … … … …
0 1 1 1 1 1 1 1 D127
1 1 0 0 0 0 0 0 D128+64
1 1 0 0 0 0 0 0 D128+65
… … … … … … … … …
1 1 1 1 1 1 1 1 D128+127
表2列出了能够是A6＝1的所有Di，共有128个Di等于1的时候会使A6＝1。因此A6的编码算法应该就是该128位的逻辑“或”。该128位的位置可以简单地表示为x1xxxxxx，其中x分别取值为0和1。同样， 二进制码中的其他所有位都是对应128位Di的逻辑“或”，这些128位的位置有同样的表达式，例如使A3＝1的所有位在xxxx1xxx位置上。
上述编码算法的实现电路原理如图9所示。这里仍然使用基本查找表，不过这里把它用作6-LUT。利用三级流水线结构实现本实施例的编码“或”运算。其中第一级由22个6-LUT组成，共可接收132个输入，第二级有4个6-LUT，第三级只有一个6-LUT，每级之间用D触发器阵列缓冲数据。所有6-LUT的真值表都是“或”运算。最后输出的Ai表示二进制码中的一位。对于本实施例下降沿的8位二进制码，共需要上述流水线运算电路8套，它们并行运算，流水线结构使得编码运算的速度可以达到系统时钟频率。
本发明是面向非线性误差最小化的TDC设计方法。非线性误差最小化必然带来测量精度的提高。为了表明本发明带来的测量精度的提高，在所述实施例中，用如图3a所示的延迟链，实现了两个通道的TDC，不使用逐单元校正方法，也不采用本发明的重排序和抽取，测量一个固定的时间间隔。所测量得到的直方图如图6a。同样，我们用本发明的面向非线性误差最小化的重排序和抽取方法，实现两通道的TDC，测量同样的时间间隔，得到的直方图如图6b。将图5a和图5b相比较，可见直方图的形状改变了，测量的标准误差也由30.9ps改善为12.7ps。由此可证明，本发明可以在不需要逐单元校正硬件或软件的情况下，获得高的测量分辨率。
值得注意的是，对于一个给定的延迟链，存在一个最佳的抽取总抽头数。图10给出了本实施例所实现TDC测量一个固定时间间隔的标准误差随着总抽取数变化关系，其中横轴是抽取的总抽头数，纵轴是双通道TDC测量3.3ns时间间隔的标准误差。
以上所述的具体实施例，对本发明的目的、技术方案和有益效果进行了进一步详细说明，应理解的是，以上所述仅为本发明的具体实施例而已，并不用于限制本发明，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

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  1. 一种基于FPGA的时间数字变换器，包括粗时钟计数器、脉冲信号发生器、信号延迟链、触发器阵列、连接网络、信号变化沿寻找和编码电路，以及时间戳输出电路，其中
    所述粗时钟计数器由系统时钟信号驱动，用于产生被测信号的粗时间戳；
    所述脉冲信号发生器用于是在被测信号的触发下产生一个具有变化沿的脉冲并馈入到所述信号延迟链中进行传输；
    所述信号延迟链用于对被测信号进行延时传输，由多个延迟单元组成，且每个延迟单元的前端具有抽头，；
    所述触发器阵列用于对信号延迟链的各抽头状态进行锁存，并将锁存的抽头状态按照所述抽头的自然排序传递给所述连接网络；
    所述连接网络用于将接收到的抽头状态按照预先设定的连接关系进行变换，再传递给所述信号变化沿寻找和编码电路；
    所述信号变化沿寻找和编码电路用于寻找被锁存的在所述信号延迟链中传输的脉冲的变化沿，并根据所述变化沿的位置生成表示细时间戳的二进制码；
    所述时间戳输出电路用于根据信号变化沿寻找和编码电路输出的二进制码细时间戳和粗时钟计数器输出的粗时间戳一起换算成被测信号的到来时间戳并将其输出。
  2. 如权利要求1所述的基于FPGA的时间数字变换器，其特征在于，所述连接网络将接收到的抽头状态按照预先设定的连接关系进行的变换包括：将所述信号延迟链的各抽头进行重排序，确定一种将所述触发器阵列连接到所述信号变化沿寻找和编码电路的连接关系。
  3. 如权利要求2所述的基于FPGA的时间数字变换器，其特征在于，所述重排序包括：将0宽度延迟单元的抽头和下一个延迟单元的抽头位置互换。
  4. 如权利要求3所述的基于FPGA的时间数字变换器，其特征在于，所述重排序可重复多次进行，在一次调整顺序之后测量各延迟单元的延迟宽度，判断0宽度的延迟单元个数是否超过一个阈值，如果是，则再次重排序，直到0宽度延迟单元的个数不超过所述阈值。
  5. 如权利要求4所述的基于FPGA的时间数字变换器，其特征在于，所述测量各延迟单元的延迟宽度是采用码密度法测量各延迟单元的延迟宽度。
  6. 如权利要求1至5中任一项所述的基于FPGA的时间数字变换器，其特征在于，所述连接网络将接收到的抽头状态按照预先设定的连接关系进行的变换包括：对所述信号延迟链的各抽头进行抽取，确定一种将所述触发器阵列连接到所述信号变化沿寻找和编码电路的连接关系。
  7. 如权利要求6所述的基于FPGA的时间数字变换器，其特征在于，所述抽取的规则是：使基于所述信号延迟链所作的时间内插测量的积分非线性最小。
  8. 如权利要求7所述的基于FPGA的时间数字变换器，其特征在于，所述抽取为：先设定信号延迟链中被抽取后的总抽头数为R，然后根据系统时钟周期Tclock计算出抽取后形成的延迟单元组的理想延迟长度w：
    Figure PCTCN2015072862-appb-100001
    并根据该理想延迟长度w完成抽取。
  9. 如权利要求8所述的基于FPGA的时间数字变换器，其特征在于，抽取的是满足下述公式的抽头Sl，1≤l≤n：
    Figure PCTCN2015072862-appb-100002
    其中，设原始的各延迟单元的延迟宽度为B1、B2、B3、…、Bn，n为延迟单元的个数，原始的各个延迟单元的输出抽头分别记为S1、S2、S3、…、Sn，抽取后的抽头记为T1、T2、T3、…、TR，为了使上式成立需要增加一个量B0，并设定：B0＝0；对每一个给定的i，都会计算得到 一个满足上式的最小的l值，该最小的l值对应的抽头Sl就是抽取后的Ti。
  10. 如权利要求1所述的基于FPGA的时间数字变换器，其特征在于，所述信号变化沿寻找和编码电路根据从所述连接网络接收的抽头状态生成一个表示变化沿位置的温度计码，根据该温度计码生成用于表示变化沿位置的“one-hot”码，再将该“one-hot”码变换为表示时间戳的二进制码。
  11. 如权利要求10所述的基于FPGA的时间数字变换器，其特征在于，所述信号变化沿寻找和编码电路通过一个逐位移动的窗口将所述温度计码切分得到2N个窗口值，n＝2N，n为延迟单元的个数，所述窗口的位宽为m，m为自然数且2≤m≤2N，并通过依序排列所述窗口值所对应的真值得到与所述温度计码对应的“one-hot”码。
  12. 如权利要求11所述的基于FPGA的时间数字变换器，其特征在于，所有可能的窗口值与对应的真值之间转换的真值表存储在FPGA中的基本逻辑单元LUT中。
  13. 如权利要求12所述的基于FPGA的时间数字变换器，其特征在于，当所述信号变化沿寻找和编码电路用于寻找温度计码的下降沿时，在所述真值表中，只有最后一位是0、其余位均为1的窗口值对应的真值为1，其余窗口值对应的真值均为0；或者，只有最后一位是0、其余位均为1的窗口值对应的真值为0，其余窗口值对应的真值均为1。
  14. 如权利要求10所述的基于FPGA的时间数字变换器，其特征在于，所述变化沿寻找和编码电路对于用“1”表示的“one-hot”码，通过计算2N-1个“one-hot”码字的逻辑“或”运算来得到二进制码的每一位的编码；对于用“0”表示的“one-hot”码，通过计算2N-1个“one-hot”码字的逻辑“与”运算来得到二进制码的每一位的编码。
  15. 如权利要求14所述的基于FPGA的时间数字变换器，其特征在于，所述变化沿寻找和编码电路利用流水线结构组合使用FPGA的LUT实现所述逻辑“或”运算或者逻辑“与”运算，流水线的每一级是 一个或若干个并行的依靠LUT而实现的逻辑“或”运算或逻辑“与”运算。
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