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WO2016023303A1 - 阵列基板及其制造方法、显示装置 - Google Patents

阵列基板及其制造方法、显示装置 Download PDF

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Publication number
WO2016023303A1
WO2016023303A1 PCT/CN2014/092699 CN2014092699W WO2016023303A1 WO 2016023303 A1 WO2016023303 A1 WO 2016023303A1 CN 2014092699 W CN2014092699 W CN 2014092699W WO 2016023303 A1 WO2016023303 A1 WO 2016023303A1
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WIPO (PCT)
Prior art keywords
electrode
via hole
planarization layer
array substrate
thin film
Prior art date
Application number
PCT/CN2014/092699
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English (en)
French (fr)
Inventor
金熙哲
崔贤植
Original Assignee
京东方科技集团股份有限公司
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Priority to US14/769,931 priority Critical patent/US20160268316A1/en
Publication of WO2016023303A1 publication Critical patent/WO2016023303A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/0121—Operation of devices; Circuit arrangements, not otherwise provided for in this subclass
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/015—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on semiconductor elements having potential barriers, e.g. having a PN or PIN junction
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133357—Planarisation layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of manufacturing the same, and a display device.
  • the display device of the Advanced Super Dimension Switch (ADS) mode has many advantages such as wide viewing angle, high transmittance, high definition, etc., and thus becomes an important mode of the display device.
  • ADS Advanced Super Dimension Switch
  • FIG. 1 is a plan view of an array substrate of an ADS mode in the prior art; and FIG. 2 is a cross-sectional view taken along line A-A of FIG.
  • the array substrate includes a base substrate on which a gate line 2, a data line 11, and a thin film transistor 10 are formed.
  • the gate line 2 and the data line 11 define a pixel unit, and a first planarization layer 5 is formed over the gate line 2, the data line 11, and the thin film transistor 9.
  • a first electrode 7 is formed over the first planarization layer 5, and a first via 6 is formed on the first electrode 7 and the first planarization layer 5, and the first via 6 and the drain 4 of the thin film transistor 10 are formed. Corresponding.
  • the drain 4 includes a Via Hole Pad (41), and the first via 6 is located directly above the via disk 41.
  • a passivation layer 8 is formed over the first electrode 7 and in the first via hole 6, and a second via hole is formed on the passivation layer 8 in the first via hole 6 above the passivation layer 8 and
  • a second electrode 9 is formed in the second via, and the second electrode 9 is connected to the via disk 41 in the drain 4 of the thin film transistor.
  • the first planarization layer is for increasing the distance between the gate line 2, the data line 11, and the thin film transistor 10 and the first electrode to reduce the parasitic capacitance gate line 2, the data line 11, and the thin film transistor 10 and the first electrode Parasitic capacitance between.
  • a passivation layer is used to insulate between the first electrode and the second electrode.
  • the cross-sectional shape of the first via hole 6 formed is a funnel shape, and therefore, the first The cross-sectional area of the via 6 gradually increases from bottom to top.
  • the minimum cross-sectional area of the first via hole causes the maximum cross-sectional area of the first via hole to increase correspondingly, and in the pixel unit, the region of the largest cross-section of the first via hole is correspondingly provided with a light-shielding structure.
  • the district The pixel is not displayed in the domain, so as the maximum cross-sectional area of the first via increases, the aperture ratio of the pixel unit decreases, making it difficult to increase the resolution of the display device.
  • an array substrate includes: a substrate substrate; a gate line, a data line, and a thin film transistor formed over the substrate; a first planarization layer formed on the lining a via hole is formed in the first planarization layer above the bottom substrate, the gate line, the data line, and the thin film transistor, and a partial region of the via corresponds to a drain of the thin film transistor a first electrode formed over the first planarization layer and in the via hole, the first electrode being connected to the drain; a passivation layer formed over the first electrode; Two electrodes are formed over the passivation layer.
  • a second planarization layer is formed in the via hole, the second planarization layer covers the first electrode located in the via hole, and the passivation layer is located in the second flat Above the layer.
  • the material of the second planarization layer is an organic resin material.
  • the orthographic projection of the via on the substrate substrate falls into the area where the gate line is located.
  • an orthographic projection of the drain on the substrate substrate falls into a region where the gate line is located.
  • a display device includes: an array substrate, wherein the array substrate uses the array substrate described above.
  • a method for manufacturing an array substrate including:
  • a via hole is formed on the first planarization layer, and a partial region of the via hole is formed Corresponding to the drain of the thin film transistor;
  • a second electrode is formed over the passivation layer.
  • the step of forming a passivation layer over the first electrode further includes:
  • the step of forming a passivation layer over the first electrode includes:
  • the passivation layer is formed over the first electrode and the second planarization layer.
  • the step of forming a second planarization layer in the via includes:
  • the organic resin material is planarized to form the second planarization layer.
  • the orthographic projection of the via on the substrate substrate falls into the area where the gate line is located.
  • an orthographic projection of the drain on the substrate substrate falls into a region where the gate line is located.
  • FIG. 1 is a top plan view of an array substrate of an ADS mode in the prior art
  • Figure 2 is a cross-sectional view taken along line A-A of Figure 1;
  • FIG. 3 is a cross-sectional view of an array substrate according to Embodiment 1 of the present invention.
  • 4a to 4e are schematic diagrams showing the intermediate structure of the array substrate shown in FIG. 3 during the manufacturing process
  • FIG. 5 is a top plan view of an array substrate according to Embodiment 2 of the present invention.
  • Figure 6 is a cross-sectional view taken along line B-B of Figure 5;
  • FIG. 7a to 7e are schematic diagrams showing the intermediate structure of the array substrate shown in Fig. 6 during the manufacturing process.
  • the array substrate is an ADS mode array substrate, and the array substrate includes: a substrate substrate 1 , a gate line 2 , a data line 11 , a thin film transistor 10 , a first planarization layer 5 , and a first electrode 7 . Passivation layer 8 and second electrode 9.
  • the gate line 2, the data line 11 and the thin film transistor 10 are formed over the base substrate 1, and the first planarization layer 5 is formed over the gate line 2, the data line 11, and the thin film transistor 10 and the base substrate 1.
  • a via hole 12 is formed in the first planarization layer 5, and a partial region of the via hole 12 corresponds to the drain electrode 4 of the thin film transistor 10, and the first electrode 7 is formed above the first planarization layer 5 and in the via hole 12, The first electrode 7 is connected to the drain 4.
  • a passivation layer 8 is formed over the first electrode 7, and a second electrode 9 is formed over the passivation layer. It should be noted that the top view of FIG. 3 can be seen in FIG. 1 .
  • the first electrode 7 is a pixel electrode, and the pixel electrode is a plate electrode.
  • the second electrode 9 is a common electrode, which is a slit electrode.
  • the thin film transistor includes a gate, a gate insulating layer 3, an active layer, a source and a drain 4.
  • the gate is disposed in the same layer as the gate line 2, and the source and drain electrodes 4 are disposed in the same layer as the data line.
  • the via holes are not formed again on the passivation layer 8 in the via hole 12 formed by the first planarization layer 5, the minimum of the via holes 12 formed on the first planarization layer 5 is obtained.
  • the cross-sectional area can be correspondingly reduced, and the size of the via disk 41 in the drain 4 is also correspondingly reduced, and the maximum cross-sectional area of the via hole 12 can be correspondingly reduced, and the aperture ratio of the pixel unit is increased accordingly.
  • FIG. 4a to 4e are schematic diagrams showing the intermediate structure of the array substrate shown in Fig. 3 during the manufacturing process. As shown in FIG. 4a to FIG. 4e, the manufacturing method includes:
  • Step 101 Form a gate line, a data line, and a thin film transistor over the base substrate.
  • the gate line 2, the data line 11, and the thin film transistor 10 are formed over the substrate 1 by a plurality of patterning processes, which is consistent with the prior art and will not be described herein.
  • the size of the via disk 41 in the drain 4 of the thin film transistor 10 formed by the step 101 is smaller than that of the through-hole disk 41 of the prior art, and the via disk 41 is located in the pixel unit.
  • Step 102 forming a first planarization layer over the base substrate, the gate line, the data line, and the thin film transistor.
  • the first planarization layer is formed with a via hole, and a partial region of the via hole corresponds to a drain of the thin film transistor.
  • the gate line 2 and the data line 11 first on the substrate substrate 1, the gate line 2, and the data line 11 by a coating process Forming a layer of an organic resin material over the thin film transistor 10, then planarizing the layer of the organic resin material to form the first planarization layer 5, and then forming a via hole on the first planarization layer 5 by a patterning process 12.
  • the via 12 corresponds to the drain 4 of the thin film transistor. Specifically, the via hole is located directly above the via hole 41 in the drain.
  • Step 103 forming a first electrode above the first planarization layer and in the via, the first electrode being connected to the drain.
  • a first electrode 7 is formed over the first planarization layer 5 and in the via 12 by a patterning process, wherein the material of the first electrode 7 is a transparent and electrically conductive material, such as indium tin oxide (ITO). .
  • ITO indium tin oxide
  • Step 104 Form a passivation layer over the first electrode.
  • a passivation layer 8 is formed over the first electrode 7 by a coating process, wherein a portion of the passivation layer 8 is formed in the via hole 12, and the material of the passivation layer 8 may be silicon nitride or silicon oxide.
  • the passivation layer acts as an insulator.
  • Step 105 Form a second electrode over the passivation layer.
  • a second electrode 9 is formed over the passivation layer 8 by a patterning process, wherein the material of the second electrode 9 is a transparent and electrically conductive material such as ITO.
  • Embodiment 1 of the present invention provides an array substrate and a method of fabricating the same, wherein a first electrode in the array substrate is connected to a drain through a via, a passivation layer is formed on the first electrode, and a second electrode is formed in the passivation Above the layer.
  • a first electrode in the array substrate is connected to a drain through a via
  • a passivation layer is formed on the first electrode
  • a second electrode is formed in the passivation Above the layer.
  • FIG. 5 is a plan view of an array substrate according to a second embodiment of the present invention
  • FIG. 6 is a cross-sectional view taken along line B-B of FIG. 5.
  • the array substrate is an ADS mode array substrate
  • the array substrate includes: a substrate substrate 1, a gate line 2, a data line 11, a thin film transistor 10, a first planarization layer 5, and a first The electrode 7, the second planarization layer 13, the passivation layer 8, and the second electrode 9.
  • the gate line 2, the data line 11 and the thin film transistor 10 are formed over the base substrate 1, and the first planarization layer 5 is formed over the gate line 2, the data line 11 and the thin film transistor 10 and the base substrate 1, the first flat A via hole 12 is formed on the layer 5, and a partial region of the via hole 12 corresponds to the drain electrode 4 of the thin film transistor 10, first
  • the electrode 7 is formed above the first planarization layer 5 and in the via 12, the first electrode 7 is connected to the drain 4, and the second planarization layer 13 is formed in the via 12 and covers the first in the via 12
  • the electrode 7, the passivation layer 8 is formed above the first electrode 7 and above the second planarization layer 13, and the second electrode 9 is formed above the passivation layer.
  • the orthographic projection of the drain electrode 4 on the substrate substrate falls into the region where the gate line 2 is located.
  • the first electrode 7 is a pixel electrode, and the pixel electrode is a plate electrode.
  • the second electrode 9 is a common electrode, which is a slit electrode.
  • the difference between this embodiment and the first embodiment is that in the array substrate provided in this embodiment, the via holes on the first planarization layer are projected in the vertical direction (ie, the orthographic projection on the substrate substrate). Part of the area falls into the area where the gate line is located. Further, a second planarization layer 13 is formed in the via hole 12, and the second planarization layer 13 covers the first electrode 7 located in the via hole 12.
  • the technical solution of the present invention can reduce the minimum cross-sectional area of the via hole 12.
  • the minimum cross-sectional area of the via hole 12 is reduced, the position of the via hole 12 can be made to be no longer limited to the inside of the pixel unit.
  • the via hole 12 is disposed above the gate line 2, so that the area of the display area of the pixel unit can be effectively increased, and the aperture ratio of the pixel unit can be improved.
  • the via hole 12 is formed above the gate line 2, the size of the drain electrode 4 in the thin film transistor 10 can be correspondingly reduced (the via hole disk is omitted), and the same as shown in FIG.
  • the first electrode 7 is overlapped on the drain 4 (a portion of the first electrode 7 is located above the gate insulating layer 3, and a portion of the first electrode 7 is located above the drain 4), so that the size of the drain 4 can be obtained.
  • a further reduction is to reduce the overall volume of the thin film transistor. Due to the reduction in the volume of the thin film transistor, the resolution of the display device is facilitated.
  • the passivation layer 8 is formed over the first electrode 7 and above the second planarization layer 13. Therefore, the uneven structure at the via hole 12 can be avoided, and the occurrence of light leakage at the via hole 12 can be prevented.
  • the material of the second planarization layer 13 is an organic resin material.
  • the organic resin material has good fluidity and can be aggregated and filled in the via hole to facilitate subsequent planarization treatment.
  • the maximum cross-sectional area of the via holes in the array substrate provided by this embodiment is also smaller than the maximum cross-sectional area of the via holes in the array substrate provided in the first embodiment.
  • the via 12 of the provided array substrate is surrounded by the first planarization layer 5, the first electrode 7, the passivation layer 8, and the second electrode 9.
  • the via 12 of the array substrate provided by the present embodiment is only surrounded by the first planarization layer 5 and the first electrode 7 , so the height of the via 12 in the array substrate provided in this embodiment is smaller than that of the above embodiment.
  • the height of the via 12 in the array substrate provided is equal to the minimum cross-sectional area of the two vias 12, and the inclination angles of the inner walls of the vias 12 are equal.
  • the maximum cross-sectional area of the via hole 12 in the array substrate provided in this embodiment is smaller than the maximum cross-sectional area of the via hole 12 in the array substrate provided in the first embodiment, and thus, even in the array substrate provided in the embodiment
  • the aperture 12 is located in the pixel unit.
  • the aperture ratio of the array substrate provided in this embodiment is also greater than the aperture ratio of the array substrate provided in the first embodiment.
  • the manufacturing method includes:
  • Step 201 Form a gate line, a data line, and a thin film transistor over the base substrate.
  • step 201 is the same as the process of step 101 in the first embodiment. For details, refer to step 101 in the first embodiment. However, the size of the drain 4 of the thin film transistor 10 fabricated in step 201 is smaller than the size of the drain of the thin film transistor fabricated in step 101.
  • Step 202 forming a first planarization layer over the base substrate, the gate line, the data line, and the thin film transistor.
  • the first planarization layer is formed with a via hole, and a partial region of the via hole corresponds to a drain of the thin film transistor.
  • step 202 is the same as the process of step 102 in the first embodiment.
  • the via hole 12 formed by the step 202 projects in the vertical direction into the region where the gate line 2 is located, and due to the small size of the drain electrode 4, the partial region of the bottom portion of the via hole 4 and the gate insulating layer 3 connections.
  • Step 203 forming a first electrode above the first planarization layer and in the via, the first electrode being connected to the drain.
  • step 203 is the same as the process of step 203 in the first embodiment.
  • the first electrode 7 formed in step 203 is formed, the first electrode 7 in the via hole 12 is overlapped on the drain electrode 4, that is, a portion of the first electrode 7 is located above the gate insulating layer 3, and part of the first electrode 7 An electrode 7 is located above the drain 4.
  • Step 204 forming a second planarization layer in the via hole, and the second planarization layer is covered in the via hole The first electrode.
  • an organic resin material is first formed in the via hole 12 by a coating process. Since the organic resin material has good fluidity, it can be aggregated in the via hole 12; then the layer of the organic resin material is flattened. The second planarization layer 13 is formed to be filled, and the second planarization layer 13 is filled in the entire via hole 12.
  • Step 205 forming a passivation layer over the first electrode and the second planarization layer.
  • a passivation layer 8 is formed over the first electrode 7 and the second planarization layer 13 by a coating process, and the material of the passivation layer 8 may be silicon nitride or silicon oxide, and the passivation layer serves as an insulating layer. The role.
  • the passivation layer 8 formed in step 205 is located above the via 12.
  • Step 206 Form a second electrode over the passivation layer.
  • a second electrode 9 is formed over the passivation layer 8 by a patterning process, wherein the material of the second electrode 9 is a transparent and electrically conductive material such as ITO.
  • Embodiment 2 of the present invention provides an array substrate and a method of fabricating the same, wherein a first electrode in the array substrate is connected to a drain through a via, a second planarization layer is formed in the via hole, and a passivation layer is formed on the first Above the one electrode and the second planarization layer, the second electrode is formed over the passivation layer.
  • the formation on the first planarization layer is performed.
  • the minimum cross-sectional area of the via can be correspondingly reduced, and the maximum cross-sectional area of the via can be correspondingly reduced, and the aperture ratio of the pixel unit will increase accordingly.
  • the second via hole is disposed above the gate line, so that the via-hole structure in the drain can be omitted, so that the volume of the entire thin film transistor is reduced. Further, the aperture ratio of the pixel unit is further improved.
  • a third embodiment of the present invention provides a display device.
  • the display device includes an array substrate.
  • the array substrate is the array substrate provided in the first embodiment or the second embodiment.
  • the array substrate is the array substrate provided in the first embodiment or the second embodiment.
  • the display device provided in this embodiment may be any product or component having a display function, such as a liquid crystal display device, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a liquid crystal display device, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a third embodiment of the present invention provides a display device, where the display device includes: an array substrate, The first electrode in the array substrate is connected to the drain through the via, the passivation layer is formed above the first electrode, and the second electrode is formed above the passivation layer.
  • the via holes are not formed again on the passivation layer in the via formed by the first planarization layer, the minimum cross-sectional area of the via formed on the first planarization layer.
  • the maximum cross-sectional area of the via hole can be correspondingly reduced, and the aperture ratio of the pixel unit is increased, which facilitates the high resolution of the display device.

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Abstract

一种阵列基板及其制造方法、显示装置，阵列基板包括：衬底基板（1）、栅线（2）、数据线（11）、薄膜晶体管（10）形成在衬底基板（1）上方；第一平坦化层（5），形成在衬底基板（1）、栅线（2）、数据线（11）和薄膜晶体管（10）的上方，第一平坦化层（5）中形成有过孔（12），过孔（12）的部分区域与薄膜晶体管（10）的漏极（4）相对应；第一电极（7），形成在第一平坦化层（5）的上方和过孔（12）内，第一电极（7）与漏极（4）连接；钝化层（8）形成在第一电极（7）的上方，第二电极（9）形成在钝化层（8）的上方。

Description

阵列基板及其制造方法、显示装置 技术领域
本发明的实施例涉及阵列基板及其制造方法、显示装置。
背景技术
高级超维场转换(ADvanced Super Dimension Switch,简称ADS)模式的显示装置具有视角宽、透过率高、清晰度高等诸多优点，故成为显示装置的一种重要模式。
图1为现有技术中ADS模式的阵列基板的俯视图；图2为图1中A-A向的剖视图。如图1和图2所示，该阵列基板包括：衬底基板，在衬底基板1的上方形成有栅线2、数据线11和薄膜晶体管10。栅线2和数据线11限定出像素单元，在栅线2、数据线11和薄膜晶体管9的上方形成有第一平坦化层5。在第一平坦化层5的上方形成有第一电极7，在第一电极7和第一平坦化层5上形成有第一过孔6，第一过孔6与薄膜晶体管10的漏极4相对应。具体地，漏极4包括一通孔盘41(Via Hole Pad)，第一过孔6位于通孔盘41的正上方。在第一电极7的上方和第一过孔6内形成有钝化层8，在第一过孔6内的钝化层8上形成有第二过孔，在钝化层8的上方和第二过孔内形成有第二电极9，第二电极9与薄膜晶体管的漏极4中的通孔盘41连接。第一平坦化层用于增大栅线2、数据线11和薄膜晶体管10与第一电极之间的距离，以减小寄生电容栅线2、数据线11和薄膜晶体管10与第一电极之间的寄生电容。钝化层用于使第一电极和第二电极之间的绝缘。
需要说明的是，在利用构图工艺在第一电极7和第一平坦化层5上形成第一过孔6时，所形成的第一过孔6的截面形状为漏斗形，因此，该第一过孔6的横截面积由下至上逐渐增大。
在现有技术中，为保证能在位于第一过孔的底部的钝化层上能形成一定尺寸的第二过孔，往往需要将第一过孔的最小横截面积设置的较大。由于第一过孔的最小横截面积的增大会使得第一过孔的最大横截面积相应的增大，而在像素单元中，第一过孔的最大横截面的区域对应设置有遮光结构，该区 域不进行像素显示，因此随着第一过孔的最大横截面积的增大，像素单元的开口率会随之下降，从而使得显示装置难以高分辨率化。
发明内容
根据本发明的一个实施例提供了一种阵列基板，包括：衬底基板；栅线、数据线、薄膜晶体管，形成在所述衬底基板的上方；第一平坦化层，形成在所述衬底基板、所述栅线、所述数据线和所述薄膜晶体管的上方，所述第一平坦化层中形成有过孔，所述过孔的部分区域与所述薄膜晶体管的漏极相对应；第一电极，形成在所述第一平坦化层的上方和所述过孔内，所述第一电极与所述漏极连接；钝化层，形成在所述第一电极的上方；第二电极，形成在所述钝化层的上方。
在一个示例中，所述过孔内形成有第二平坦化层，所述第二平坦化层覆盖位于所述过孔内的所述第一电极，所述钝化层位于所述第二平坦化层的上方。
在一个示例中，所述第二平坦化层的材料为有机树脂材料。
在一个示例中，所述过孔在衬底基板上的正投影部分落入所述栅线所处的区域。
在一个示例中，所述漏极在所述衬底基板上的正投影落入所述栅线所处的区域。
根据本发明另一个实施例还提供了一种显示装置，包括：阵列基板，该阵列基板采用上述的阵列基板。
根据本发明的再一个实施例还提供了一种阵列基板的制造方法，包括：
在衬底基板的上方形成栅线、数据线和薄膜晶体管；
在所述衬底基板、所述栅线、所述数据线和所述薄膜晶体管的上方形成第一平坦化层，所述第一平坦化层上形成有过孔，所述过孔的部分区域与所述薄膜晶体管的漏极相对应；
在所述第一平坦化层的上方和所述过孔内形成第一电极，所述第一电极与所述漏极连接；
在所述第一电极的上方形成钝化层；
在所述钝化层的上方形成第二电极。
在一个示例中，所述在第一电极的上方形成钝化层的步骤之前还包括：
在所述过孔内形成第二平坦化层，所述第二平坦化层覆盖位于所述过孔内的所述第一电极；
所述在所述第一电极的上方形成钝化层的步骤包括：
在所述第一电极和所述第二平坦化层的上方形成所述钝化层。
在一个示例中，所述在所述过孔内形成第二平坦化层的步骤包括：
在所述过孔内形成有机树脂材料；
对所述有机树脂材料进行平坦化处理以形成所述第二平坦化层。
在一个示例中，所述过孔在衬底基板上的正投影落入所述栅线所处的区域。
在一个示例中，所述漏极在所述衬底基板上的正投影落入所述栅线所处的区域。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为现有技术中ADS模式的阵列基板的俯视图；
图2为图1中A-A向的剖视图；
图3为本发明实施例一提供的阵列基板的剖视图；
图4a～图4e为图3所示的阵列基板在制造过程中的中间结构示意图；
图5为本发明实施例二提供的阵列基板的俯视图；
图6为图5中B-B向的剖视图；
图7a～图7e为图6所示的阵列基板在制造过程中的中间结构示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例，都属于本发明保护的范围。
实施例一
图3为本发明实施例一提供的阵列基板的剖视图。如图3所示，该阵列基板为ADS模式的阵列基板，该阵列基板包括：衬底基板1、栅线2、数据线11、薄膜晶体管10、第一平坦化层5、第一电极7、钝化层8和第二电极9。栅线2、数据线11和薄膜晶体管10形成于衬底基板1的上方，第一平坦化层5形成于栅线2、数据线11和薄膜晶体管10和衬底基板1的上方。第一平坦化层5中形成有过孔12，过孔12的部分区域与薄膜晶体管10的漏极4相对应，第一电极7形成于第一平坦化层5的上方和过孔12内，第一电极7与漏极4连接。钝化层8形成于第一电极7的上方，第二电极9形成于钝化层的上方。需要说明的是，图3的俯视图可参见图1所示。
在本实施例中，第一电极7为像素电极，该像素电极为板状电极。第二电极9为公共电极，该公共电极为狭缝电极。
需要说明的是，该薄膜晶体管包括：栅极、栅极绝缘层3、有源层、源极和漏极4。栅极与栅线2同层设置，源极和漏极4与数据线同层设置。
在本实施例中，由于无需在第一平坦化层5所形成的过孔12内的钝化层8上再次形成过孔，因此在第一平坦化层5上所形成的过孔12的最小横截面积可相应减小，漏极4中的通孔盘41的尺寸也相应减小，该过孔12的最大横截面积也可相应减小，像素单元的开口率会随之上升。
图4a～图4e为图3所示的阵列基板在制造过程中的中间结构示意图。如图4a至图4e所示，该制造方法包括：
步骤101：在衬底基板的上方形成栅线、数据线和薄膜晶体管。
参见图4a，通过多次构图工艺以在衬底基板1的上方形成栅线2、数据线11和薄膜晶体管10，该过程与现有技术中的一致，此处不再赘述。
通过步骤101所形成薄膜晶体管10的漏极4中的通孔盘41的尺寸小于现有技术中的通孔盘41的尺寸，该通孔盘41位于像素单元内。
步骤102：在衬底基板、栅线、数据线和薄膜晶体管的上方形成第一平坦化层，第一平坦化层上形成有过孔，过孔的部分区域与薄膜晶体管的漏极相对应。
参见图4b和图4c，首先通过涂布工艺在衬底基板1、栅线2、数据线11 和薄膜晶体管10的上方形成一层有机树脂材料，然后对该层有机树脂材料进行平坦化处理以形成第一平坦化层5，再然后通过构图工艺以在第一平坦化层5上形成过孔12，该过孔12与薄膜晶体管的漏极4相对应。具体地，过孔位于漏极中通孔盘41的正上方。
步骤103：在第一平坦化层的上方和过孔内形成第一电极，第一电极与漏极连接。
参见图4d，通过构图工艺以在第一平坦化层5的上方和过孔12内形成第一电极7，其中第一电极7的材料为透明且导电的材料，例如：氧化铟锡(ITO)。
步骤104：在第一电极的上方形成钝化层。
参见图4e，通过涂布工艺以在第一电极7的上方形成钝化层8，其中部分钝化层8形成于过孔12内，钝化层8的材料可为氮化硅或氧化硅，钝化层起到绝缘的作用。
步骤105：在钝化层的上方形成第二电极。
参见图3，通过构图工艺以在钝化层8的上方形成第二电极9，其中第二电极9的材料为透明且导电的材料，例如：ITO。
本发明实施例一提供了一种阵列基板及其制造方法，该阵列基板中的第一电极通过过孔与漏极连接，钝化层形成于第一电极的上方，第二电极形成于钝化层的上方。在本发明的实施例中，由于无需在第一平坦化层所形成的过孔内的钝化层上再次形成过孔，因此在第一平坦化层上所形成的过孔的最小横截面积可相应减小，该过孔的最大横截面积也可相应减小，像素单元的开口率会随之上升。
实施例二
图5为本发明实施例二提供的阵列基板的俯视图，图6为图5中B-B向的剖视图。如图5和图6所示，该阵列基板为ADS模式的阵列基板，该阵列基板包括：衬底基板1、栅线2、数据线11、薄膜晶体管10、第一平坦化层5、第一电极7、第二平坦化层13、钝化层8和第二电极9。栅线2、数据线11和薄膜晶体管10形成于衬底基板1的上方，第一平坦化层5形成于栅线2、数据线11和薄膜晶体管10和衬底基板1的上方，第一平坦化层5上形成有过孔12，过孔12的部分区域与薄膜晶体管10的漏极4相对应，第一 电极7形成于第一平坦化层5的上方和过孔12内，第一电极7与漏极4连接，第二平坦化层13形成于过孔12内且覆盖位于过孔12内的第一电极7，钝化层8形成于第一电极7的上方和第二平坦化层13的上方，第二电极9形成于钝化层的上方。
例如，如图5所示，漏极4在衬底基板上的正投影落入栅线2所处的区域。
在本实施例中，第一电极7为像素电极，该像素电极为板状电极。第二电极9为公共电极，该公共电极为狭缝电极。
本实施例与上述实施例一的区别在于，在本实施例提供的阵列基板中，在第一平坦化层上的过孔在竖直方向上投影(即，在衬底基板上的正投影)部分落入所述栅线所处的区域。此外，在过孔12内还形成有第二平坦化层13，第二平坦化层13覆盖位于过孔12内的第一电极7。
通过上述实施例一的技术方案可知，本发明的技术方案可缩小过孔12的最小横截面积。在本实施例中，由于过孔12的最小横截面积的减小，从而可使得过孔12的位置不再限制于像素单元内。例如，该过孔12设置于栅线2的上方，从而可有效的增大像素单元的显示区域的面积，提升像素单元的开口率。需要说明的是，由于过孔12形成于栅线2的上方，此时薄膜晶体管10中漏极4的尺寸可相应减小(省去了通孔盘)，同时采用图6所示的这种将第一电极7搭接在漏极4方式(部分的第一电极7位于栅极绝缘层3的上方，部分的第一电极7位于漏极4的上方)，可使得漏极4的尺寸得到进一步的减小，即使得薄膜晶体管的整体体积减小。由于薄膜晶体管体积的减小，从而有利于显示装置的高分辨率化。
此外，在本实施例中，由于在过孔12内第一电极7的上方覆盖有第二平坦化层13，钝化层8形成于第一电极7的上方和第二平坦化层13的上方，从而可避免在过孔12处出现凹凸不平的结构，进而可防止在过孔12处的漏光现象的发生。
可选地，第二平坦化层13的材料为有机树脂材料。有机树脂材料的流动性好，可聚集填充于在过孔，方便后续的平坦化处理。
本实施例提供的阵列基板中的过孔的最大横截面积也小于实施例一提供的阵列基板中的过孔的最大横截面积。具体地，参见图3，上述实施例一中 提供的阵列基板的过孔12是由第一平坦化层5、第一电极7、钝化层8和第二电极9所围成。参见图6，本实施提供的阵列基板的过孔12仅由第一平坦化层5和第一电极7所围成，因此本实施例提供的阵列基板中的过孔12的高度小于上述实施例一提供的阵列基板中的过孔12的高度，在两个过孔12的最小横横截面积相等，且过孔12的内壁的倾斜角相等的前提下。本实施例提供的阵列基板中的过孔12的最大横截面积要小于上述实施例一提供的阵列基板中的过孔12的最大横截面积，因此，即便本实施例提供的阵列基板中的过孔12位于像素单元内，本实施例提供的阵列基板的开口率也大于上述实施例一提供阵列基板的开口率。
图7a～图7e为图6所示的阵列基板在制造过程中的中间结构示意图，如图7至图7e所示，该制造方法包括：
步骤201：在衬底基板的上方形成栅线、数据线和薄膜晶体管。
参见图7a，步骤201与上述实施例一中的步骤101的过程相同，具体可参见上述实施例一中的步骤101的内容。但是，通过步骤201制造出的薄膜晶体管10的漏极4的尺寸小于通过步骤101制造出的薄膜晶体管的漏极的尺寸。
步骤202：在衬底基板、栅线、数据线和薄膜晶体管的上方形成第一平坦化层，第一平坦化层上形成有过孔，过孔的部分区域与薄膜晶体管的漏极相对应。
参见图7b，步骤202与上述实施例一中的步骤102的过程相同，具体可参见上述实施例一中的步骤102的内容。但是，通过步骤202形成的过孔12在竖直方向上投影落入栅线2所处的区域，且由于漏极4的尺寸较小，使得过孔4的底部的部分区域与栅极绝缘层3连接。
步骤203：在第一平坦化层的上方和过孔内形成第一电极，第一电极与漏极连接。
参见图7c，步骤203与上述实施例一中的步骤203的过程相同，具体可参见上述实施例一中的步骤103的内容。但是，通过步骤203形成的第一电极7时，在过孔12内的第一电极7搭接在漏极4上，即部分的第一电极7位于栅极绝缘层3的上方，部分的第一电极7位于漏极4的上方。
步骤204：在过孔内形成第二平坦化层，第二平坦化层覆盖位于过孔内 的第一电极。
参见图7d，首先通过涂布工艺在过孔12内形成一层有机树脂材料，由于有机树脂材料有较好的流动性，因此可在过孔12内聚集；然后对该层有机树脂材料进行平坦化处理以形成第二平坦化层13，第二平坦化层13填充于整个过孔12。
步骤205：在第一电极和第二平坦化层的上方形成钝化层。
参见图7e，通过涂布工艺以在第一电极7和第二平坦化层13的上方形成钝化层8，钝化层8的材料可为氮化硅或氧化硅，钝化层起到绝缘的作用。
由于在步骤204中，第二平坦化层13填充于整个过孔12，因此在步骤205中形成的钝化层8位于过孔12的上方。
步骤206：在钝化层的上方形成第二电极。
参见图6，通过构图工艺以在钝化层8的上方形成第二电极9，其中第二电极9的材料为透明且导电的材料，如：ITO。
本发明实施例二提供了一种阵列基板及其制造方法，该阵列基板中的第一电极通过过孔与漏极连接，在过孔内形成有第二平坦化层，钝化层形成于第一电极和第二平坦化层的上方，第二电极形成于钝化层的上方。在本发明的实施例中，由于无需在第一平坦化层所形成的过孔内形成钝化层，且无需在钝化层上再次形成过孔，因此在第一平坦化层上所形成的过孔的最小横截面积可相应减小，该过孔的最大横截面积也可相应减小，像素单元的开口率会随之上升。此外，本实施例二相较于实施例一而言，本实施例二过孔设置于栅线的上方，因此可省去漏极中的通孔盘结构，使得整个薄膜晶体管的体积减小，进而使得像素单元的开口率得到进一步的提升。
实施例三
本发明实施例三提供了一种显示装置，该显示装置包括阵列基板，该阵列基板采用上述实施例一或实施二中提供的阵列基板，具体可参见上述实施例一或实施例二中的描述，此处不再赘述。
本实施例提供的显示装置可以为液晶显示装置、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本发明实施例三提供了一种显示装置，该显示装置包括：阵列基板，该 阵列基板中的第一电极通过过孔与漏极连接，钝化层形成于第一电极的上方，第二电极形成于钝化层的上方。在本发明的实施例中，由于无需在第一平坦化层所形成的过孔内的钝化层上再次形成过孔，因此在第一平坦化层上所形成的过孔的最小横截面积可相应减小，该过孔的最大横截面积也可相应减小，像素单元的开口率会随之上升，便于显示装置的高分辨率化。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。
本申请要求于2014年8月15日递交的中国专利申请第201410401878.6号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (11)

  1. 一种阵列基板，包括：
    衬底基板；
    栅线、数据线、薄膜晶体管，形成在所述衬底基板的上方；
    第一平坦化层，形成在所述衬底基板、所述栅线、所述数据线和所述薄膜晶体管的上方，所述第一平坦化层中形成有过孔，所述过孔的部分区域与所述薄膜晶体管的漏极相对应；
    第一电极，形成在所述第一平坦化层的上方和所述过孔内，所述第一电极与所述漏极连接；
    钝化层，形成在所述第一电极的上方；
    第二电极，形成在所述钝化层的上方。
  2. 根据权利要求1所述的阵列基板，其中，所述过孔内形成有第二平坦化层，所述第二平坦化层覆盖位于所述过孔内的所述第一电极，所述钝化层位于所述第二平坦化层的上方。
  3. 根据权利要求2所述的阵列基板，其中，所述第二平坦化层的材料为有机树脂材料。
  4. 根据权利要求1所述的阵列基板，其中，所述过孔在所述衬底基板上的正投影部分落入所述栅线所处的区域。
  5. 根据权利要求1或4所述的阵列基板，其中，所述漏极在所述衬底基板上的正投影落入所述栅线所处的区域。
  6. 一种显示装置，包括：如上述权利要求1-5中任一所述的阵列基板。
  7. 一种阵列基板的制造方法，包括：
    在衬底基板的上方形成栅线、数据线和薄膜晶体管；
    在所述衬底基板、所述栅线、所述数据线和所述薄膜晶体管的上方形成第一平坦化层，所述第一平坦化层上形成有过孔，所述过孔的部分区域与所述薄膜晶体管的漏极相对应；
    在所述第一平坦化层的上方和所述过孔内形成第一电极，所述第一电极与所述漏极连接；
    在所述第一电极的上方形成钝化层；
    在所述钝化层的上方形成第二电极。
  8. 根据权利要求7所述的阵列基板的制造方法，其中，所述在第一电极的上方形成钝化层的步骤之前还包括：
    在所述过孔内形成第二平坦化层，所述第二平坦化层覆盖位于所述过孔内的所述第一电极；
    所述在所述第一电极的上方形成钝化层的步骤包括：
    在所述第一电极和所述第二平坦化层的上方形成所述钝化层。
  9. 根据权利要求8所述的阵列基板的制造方法，其中，所述在所述过孔内形成第二平坦化层的步骤包括：
    在所述过孔内形成有机树脂材料；
    对所述有机树脂材料进行平坦化处理以形成所述第二平坦化层。
  10. 根据权利要求7中所述的阵列基板的制造方法，其中，所述过孔在衬底基板上的正投影部分落入所述栅线所处的区域。
  11. 根据权利要求7或10所述的阵列基板的制造方法，其中，所述漏极在所述衬底基板上的正投影落入所述栅线所处的区域。
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