WO2016013701A1

WO2016013701A1 - Broadcasting receiver and signal processor therefor

Info

Publication number: WO2016013701A1
Application number: PCT/KR2014/006768
Authority: WO
Inventors: 김연우; 이정은; 김진화; 이주호
Original assignee: 주식회사 레이믹스
Priority date: 2014-07-24
Filing date: 2014-07-24
Publication date: 2016-01-28
Also published as: KR20160012396A

Abstract

A broadcasting receiver that can simplify hardware and improve group delay characteristics by using an infinite impulse response (IIR) filter, and a signal processor therefor are disclosed. The signal processor for a broadcasting receiver comprises: a first signal processing unit for processing a digital signal and outputting an input digitised intermediate frequency signal for a digital TV; and a second signal processing unit for processing a digital signal and outputting an input digitised intermediate frequency signal for an analogue TV, wherein the respective first signal processing unit and the second signal processing unit process a signal using one or more IIR filters.

Description

Broadcast receivers and signal processors for broadcast receivers

The present invention relates to a broadcast receiver and a signal processor for the broadcast receiver, and more particularly, to a broadcast receiver and a signal processor for the broadcast receiver that can correspond to both an analog broadcast signal and a digital broadcast signal.

With one broadcast receiver, there is a need for a broadcast receiver that can respond to both analog TV signals and digital TV signals.

U.S. Patent No. 7,265,792 (hereinafter referred to as 'Primary Invention') discloses a television receiver capable of coping with both analog TV signals and digital TV signals. However, the digital signal processor (DSP) of the present invention performs signal processing using a finite impulse response (FIR) filter.

FIR filters require more coefficients to maintain the same performance as Infinite Impulse Response (IIR) filters, requiring larger multipliers and shift registers. do. Therefore, the signal processing using the FIR filter increases the complexity of hardware and requires a larger hardware configuration.

On the other hand, in the case of the IIR filter, unlike the FIR filter, it is possible to design a filter having the same performance as that of the FIR filter by using less co-election. However, in the case of the IIR filter, there is a problem in that there is a non-uniform group delay in the in-band frequency band.

In order to solve the group delay problem of the IIR filter, an additional design circuit for compensating for group delay using an Arbitrary Group Delay Equalizer (for example, All Pass Filter, APF) next to the IIR filter is additionally designed. To make the group delay as flat as possible. But for a system that requires a good, flat group delay, the order of APF must be high, making it difficult to apply in a real system.

Disclosure of Invention The present invention has an object of solving the above technical problem, and the object of the present invention is to provide a broadcast receiver and a signal processor for the broadcast receiver, which simplify the hardware and improve the group delay characteristics by using an IIR filter. There is this.

The broadcast receiver according to an exemplary embodiment of the present invention includes a signal processor that digitally processes and outputs an inputted digitized intermediate frequency signal using a plurality of Infinite Impulse Response (IIR) filters.

The signal processor may include a first signal processor configured to digitally process and output an input digitized intermediate frequency signal for digital TV, wherein the first signal processor comprises: a first filter for filtering the input digitized intermediate frequency signal; It characterized in that it comprises a filter unit.

Specifically, the first filter unit, the 1-1 IIR filter; And a 1-2 IIR filter connected to the 1-1 IIR filter through a memory.

That is, the first filter unit includes a 1-1 IIR filter, a 1-2 IIR filter, a 1-1 memory, and a 1-2 memory, wherein the digitized intermediate frequency signal is the 1-1 IIR filter. The first frequency of the first memory, the 1-2 IIR filter, and the 1-2 memory are input and output, or the digitized intermediate frequency signal is the 1-1 memory, the 1-2 IIR filter. And input and output in the order of the 1-2 memory and the 1-1 IIR filter.

Preferably, the 1-1 memory and the 1-2 memory are LIFO (Last-In First-Out) memory.

The signal processor may include a second signal processor configured to digitally process and output an inputted digitized intermediate frequency signal for analog TV, wherein the second signal processor may demodulate the inputted digitized intermediate frequency signal. Demodulator; And a second filter unit for filtering the demodulated signal by the demodulator.

Specifically, the second filter unit, the 2-1 IIR filter; And a 2-2 IIR filter connected through the 2-1 IIR filter and a memory.

That is, the second filter unit includes a 2-1 IIR filter, a 2-2 IIR filter, a 2-1 memory, and a 2-2 memory, wherein the signal demodulated by the demodulator is the second-1. A signal input and output in the order of an IIR filter, the 2-1 memory, the 2-2 IIR filter, and the 2-2 memory, or the signal demodulated by the demodulator is the 2-1 memory, the second It is characterized in that the input and output in the order of -2 IIR filter, the 2-2 memory and the 2-1 IIR filter. Preferably, the 2-1 memory and the 2-2 memory are LIFO (Last-In First-Out) memories.

According to the broadcast receiver and the signal processor for the broadcast receiver of the present invention, an IIR filter can be used to improve group delay characteristics while simplifying hardware.

1 is a block diagram of a broadcast receiver according to an embodiment of the present invention.

2 is a block diagram of a signal processor of the present invention.

3A and 3B are configuration diagrams of a first embodiment and a second embodiment of the first filter unit;

4A and 4B are configuration diagrams of a first embodiment and a second embodiment of the second filter unit;

5 is a characteristic diagram of filtering and group delay by coupling an IIR filter to the cascade of the present invention.

Hereinafter, a broadcast receiver and a signal processor for the broadcast receiver according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

The following examples of the present invention are intended to embody the present invention, but not to limit or limit the scope of the present invention. From the detailed description and examples of the present invention, those skilled in the art to which the present invention pertains can easily be interpreted as belonging to the scope of the present invention.

First, Figure 1 is a block diagram of a broadcast receiver 1000 according to an embodiment of the present invention.

As can be seen from Figure 1, the broadcast receiver 1000 according to an embodiment of the present invention, the frequency conversion circuit 100, IF amplification digitization circuit 200, the signal processor 300 and the signal output circuit ( 400).

The frequency conversion circuit 100 converts the input RF signal to have an intermediate frequency (IF). The RF signal input here is a signal for digital or analog television. The frequency conversion circuit 100 of the present invention may include a filter 120 and a mixer 130 implemented using a low noise amplifier (LNA) 110, a tracking filter, and a low pass filter. .

Next, the IF amplification digitizing circuit 200 includes a programmable gain amplifier (PGA, 210a, 210b) and an analog-to-digital converter (Analog to Digital Converter, ADC, 220a, 220b), and includes an input. It amplifies and digitizes the intermediate frequency signal.

The signal processor 300 of the present invention may be implemented by including a digital signal processor (DSP), and digitally process the digital signal into a signal of a digital TV format or an analog TV format according to a format of an inputted digitized intermediate frequency signal. It plays a role of printing. That is, the signal processor 300 of the present invention outputs an audio signal and a video signal in the form of digital signals, respectively, for the analog TV format signal. In addition, the signal processor 300 of the present invention outputs an I signal and a Q signal in digital form, respectively, for a digital TV format signal.

The signal output circuit 400 serves to output signals of various TV formats. The signal output circuit 400 according to the present invention uses an analog terminal to convert a TV signal in digital format by a first digital-to-analog converter 410 for converting an input digital signal into an analog signal and a low pass filter 420 for smoothing. Can be output via In addition, the signal output circuit 400 of the present invention can be output as an analog format TV signal through an analog terminal using a second digital-to-analog converter 430 that converts an input digital signal into an analog signal. Of course, each output terminal can output a signal in the form of a single or differential signal.

2 shows a block diagram of the signal processor 300 of the present invention.

As can be seen from FIG. 2, the signal processor 300 of the present invention includes a first signal processor 310 and a second signal processor 320.

When the inputted digitized intermediate frequency signal is a digital TV signal, the first signal processor 310 outputs the digital signal in a digital TV format. In addition, when the inputted digitized intermediate frequency signal is an analog TV signal, the second signal processor 320 performs a digital signal processing and outputs the digital signal in an analog TV format.

The first signal processor 310 of the present invention includes a first filter unit 312 for filtering an inputted digitized intermediate frequency signal.

3A and 3B show configuration diagrams of the first and second embodiments of the first filter unit 312, respectively. Here, the first filter unit 312 may use a channel selection filter (CSF) as an Infinite Impulse Response (IIR) filter.

In detail, the first filter unit 312 includes a 1-1 IIR filter F11 and a 1-1 IIR filter F12 connected to the 1-1 IIR filter F11 via a memory. In this case, the 1-2 delay IIR filter F12 having a memory connected to the front and rear ends compensates for the group delay of the 1-1 IIR filter F11.

In the first filter unit 312, the intermediate frequency signal digitized as shown in FIG. -2 may be configured to be input and output in the order of the memory M12. Alternatively, as illustrated in FIG. 3B, the first filter unit 312 may include the first-first memory M11, the first-first memory M11, the first-first IIR filter F12, and the second-first memory M12 as illustrated in FIG. 3B. ) And 1-1 IIR filter (F11) in order to be input and output. In this case, the 1-1 IIR filter F11 and the 1-2 IIR filter F12 may be used as I signal filters. In addition, the first-first memory M11 and the first-second memory M12 use a last-in first-out (LIFO) memory to finally output data in the original order.

In addition, the first filter unit 312 may use the first to third IIR filters F13 and the first to fourth IIR filters F14, which are IIR filters, as filters for Q signals. The 1-3 memory M13 and the 1-4 memory M14 use a last-in first-out memory to finally output data in the original order.

In addition, the 1-1 IIR filter F11, the 1-2 IIR filter F12, the 1-3 IIR filter F13, and the 1-4 IIR filter F14 may be configured. . In addition, the larger the size of the 1-1 memory (M11), the 1-2 memory (M12), the 1-3 memory (M13) and the 1-4 memory (M14), the group delay characteristics are improved, but the hardware The burden of the cost also increases, so it is desirable to select an appropriate size by trade off.

In detail, the second signal processor 320 includes a demodulator 321 for demodulating the input digitized intermediate frequency signal and a second filter unit 322 for filtering the demodulated signal by the demodulator 321. do. The demodulator 321 may be an example demodulator for VSB (Vestigial sideband).

4A and 4B show configuration diagrams of the first and second embodiments of the second filter unit 322, respectively.

Here, the second filter unit 322 uses an Infinite Impulse Response (IIR) filter as a low pass filter or a band pass filter. That is, the second filter unit 322 includes a 2-1 IIR filter F21 and a 2-2 IIR filter F22 connected to the 2-1 IIR filter F21 via a memory.

At this time, the 2-2 IIR filter F22 having a memory connected to the front and rear ends compensates for the group delay of the 2-1 IIR filter F21. As shown in FIG. 4A, the second filter unit 322 has a signal demodulated by the demodulator 321 in the 2-1 IIR filter F21, the 2-1 memory M21, and the 2-2 IIR filter F22. ) And 2-2 may be input and output in the order of the memory M22. Alternatively, as shown in FIG. 4B, the signal demodulated by the demodulator 321 is a 2-1 memory M21, a 2-2 IIR filter F22, a 2-2 memory M22, and a 2-1 IIR filter. Input and output in the order of (F21). At this time, the 2-1 IIR filter F21 and the 2-2 IIR filter F22 are used as filters for video signals. In addition, the second-first memory M21 and the second-second memory M22 use a last-in first-out (LIFO) memory to finally output data in the original order.

In addition, the second filter unit 322 filters the audio signal using the 2-3 IIR filter F23 and the 2-4 IIR filter F24 which are IIR filters. The 2-3 memory M23 and the 2-4 memory M24 use a last-in first-out memory to finally output data in the original order.

In addition, the 2-1 IIR filter F21, the 2-2 IIR filter F22, the 2-3 IIR filter F23, and the 2-4 IIR filter F24 may be configured. . In addition, as the size of the 2-1 memory M21, the 2-2 memory M22, the 2-3 memory M23, and the 2-4 memory M24 increases, the group delay characteristics are improved. The burden of the cost also increases, so it is desirable to select an appropriate size by trade off.

As described above, according to the broadcast receiver 1000 and the signal processor 300 for the broadcast receiver 1000 of the present invention, the role of canceling the group delay of the IIR filter by connecting the IIR filter to the cascade. Do it.

5 shows a characteristic diagram of filtering and group delay by connecting an IIR filter to a cascade of the present invention, respectively.

As can be seen from FIG. 5, the group delay canceling method of the present invention is for compensating the IIR filter F11 in which the memories M11 and M12 are connected before and after one IIR filter F11 and the IIR filter F12. Characterized in that the compensation portion. According to the present invention, the Arbitrary group delay method merely exhibits excellent filtering characteristics as two IIR filters are connected in series, as compared with simply canceling the group delay. Accordingly, the signal processor 300 may be implemented with smaller hardware than the FIR filter, and excellent signal characteristics may be obtained in a digital TV system, and performance of video and audio signals may be improved in an analog TV system.

Claims

And a signal processor using a plurality of Infinite Impulse Response (IIR) filters to digitally process and output an input digitized intermediate frequency signal.
The method of claim 1,

The signal processor,

And a first signal processor configured to digitally process and output an inputted digitized intermediate frequency signal for digital TV.

The first signal processor,

And a first filter for filtering an inputted digitized intermediate frequency signal.
The method of claim 2,

The first filter unit,

1-1 IIR filter; And

And a 1-2 IIR filter connected through the 1-1 IIR filter and a memory.
The method of claim 2,

The first filter unit includes a 1-1 IIR filter, a 1-2 IIR filter, a 1-1 memory, and a 1-2 memory,

The digitized intermediate frequency signal is input and output in the order of the 1-1 IIR filter, the 1-1 memory, the 1-2 IIR filter, and the 1-2 memory, or

The digitized intermediate frequency signal is input and output in the order of the 1-1 memory, the 1-2 IIR filter, the 1-2 memory and the 1-1 IIR filter.
The method of claim 4, wherein

And the first-first memory and the first-second memory are LIFO (last-in first-out) memory.
The method of claim 1,

The signal processor,

And a second signal processor configured to digitally process and output an inputted digitized intermediate frequency signal for analog TV.

The second signal processor,

A demodulator for demodulating an input digitized intermediate frequency signal; And

And a second filter unit for filtering the demodulated signal by the demodulator.
The method of claim 6,

The second filter unit,

2-1 IIR filter; And

And a 2-2 IIR filter connected through the 2-1 IIR filter and a memory.
The method of claim 6,

The second filter unit may include a 2-1 IIR filter, a 2-2 IIR filter, a 2-1 memory, and a 2-2 memory.

The signal demodulated by the demodulator is input and output in the order of the 2-1 IIR filter, the 2-1 memory, the 2-2 IIR filter, and the 2-2 memory, or

And a signal demodulated by the demodulator is input and output in the order of the 2-1 memory, the 2-2 IIR filter, the 2-2 memory, and the 2-1 IIR filter. .
The method of claim 8,

And the 2-1 memory and the 2-2 memory are LIFO (Last-In First-Out) memory.
A first signal processor for digitally processing and outputting an input digitized intermediate frequency signal for digital TV; And

And a second signal processor configured to digitally process and output an inputted digitized intermediate frequency signal for analog TV.

And the first signal processor and the second signal processor respectively process signals using at least one Infinite Impulse Response (IIR) filter.
The method of claim 10,

The first signal processor,

Includes; a first filter for filtering the input digitized intermediate frequency signal,

The first filter unit includes a 1-1 IIR filter, a 1-2 IIR filter, a 1-1 memory, and a 1-2 memory,

The digitized intermediate frequency signal is input and output in the order of the 1-1 IIR filter, the 1-1 memory, the 1-2 IIR filter, and the 1-2 memory, or

The digitized intermediate frequency signal is input and output in the order of the 1-1 memory, the 1-2 IIR filter, the 1-2 memory and the 1-1 IIR filter. Signal processor.
The method of claim 11,

And the first-first memory and the second-first memory are last-in first-out (LIFO) memories.
The method of claim 10,

The second signal processor,

A demodulator for demodulating an input digitized intermediate frequency signal; And

And a second filter unit for filtering the demodulated signal by the demodulator.

The second filter unit may include a 2-1 IIR filter, a 2-2 IIR filter, a 2-1 memory, and a 2-2 memory.

The signal demodulated by the demodulator is input and output in the order of the 2-1 IIR filter, the 2-1 memory, the 2-2 IIR filter, and the 2-2 memory, or

And a signal demodulated by the demodulator is input and output in the order of the 2-1 memory, the 2-2 IIR filter, the 2-2 memory, and the 2-1 IIR filter. Signal processor for.
The method of claim 13,

And the 2-1 memory and the 2-2 memory are last-in first-out (LIFO) memories.