WO2016062084A1

WO2016062084A1 - Power-off processing method and apparatus, and electronic device

Info

Publication number: WO2016062084A1
Application number: PCT/CN2015/079611
Authority: WO
Inventors: 颜志伟
Original assignee: 中兴通讯股份有限公司
Priority date: 2014-10-24
Filing date: 2015-05-22
Publication date: 2016-04-28
Also published as: CN105528308A

Abstract

Disclosed are a power-off processing method and apparatus, and an electronic device. The method comprises: detecting that an electronic device is powered off; and synchronizing data buffered by a buffer memory in the electronic device into a memory of the electronic device. The present invention solves the problem in the prior art that it is complex to prevent data in a memory from getting lost after an electronic device is powered off abnormally, so that the operation of preventing data in a memory from getting lost after an electronic device is powered off abnormally is simplified, the accuracy of the data in the memory is ensured and the user experience is improved.

Description

Power-down processing method, device and electronic device

Technical field

The present invention relates to the field of communications, and in particular, to a power-down processing method, apparatus, and electronic device.

Background technique

When the electronic device is working, there will be a situation in which the system is abnormally powered down. At this time, the user data stored in the memory will be lost. Therefore, it is desirable to have a certain device (such as a battery), and after the electronic device is abnormally powered down, it can continue to be The memory unit of the electronic device is powered to ensure that the data in the memory is not lost. In the process of the next system startup, the valid data stored in the memory is reused, and the implementation of the function is as simple as possible.

The memory power-down protection method currently adopted is basically implemented by an external non-volatile storage medium. In short, when the power of the device is about to be powered down, the data in the memory is transferred to the non-volatile storage medium. After the device is next started, the data in the non-volatile storage medium is copied to the memory again.

At present, the memory stick with the Error Correcting Code (ECC) function is very common. Although the ECC memory has certain checking and error correction capabilities during normal operation, the ECC does not automatically change when the device is restarted. To verify the existing data in the memory, it is obviously not feasible to use the ECC algorithm to verify the data in the memory by simply using the software method. The software can not directly read the existing ECC check value from the ECC memory and compare it with the calculated result. .

In the related art, the implementation method of making the data in the memory not lost after the electronic device is abnormally powered off is complicated, and the ECC does not automatically verify the existing data in the memory when the device is restarted, and an effective solution has not been proposed yet. Program.

Summary of the invention

The embodiment of the invention provides a method, a device, and an electronic device method and device for power-down processing, so as to at least solve the problem that the implementation method for preventing data in the memory from being lost after the abnormal power-off of the electronic device in the prior art is complicated, and ECC does not automatically check for problems with data already in memory at startup.

According to an embodiment of the present invention, a power down processing method is provided, including: detecting that an electronic device is powered down; synchronizing data buffered by the buffer memory in the electronic device into a memory of the electronic device.

In the embodiment of the present invention, the electronic device is powered off, and the electronic device is powered off normally, and the electronic device is powered off abnormally.

In the embodiment of the present invention, the memory is an error check and correction ECC memory.

In the embodiment of the present invention, after detecting that the electronic device is powered off, the flag bit for identifying whether the electronic device is abnormally powered down is set to be abnormally powered down.

In the embodiment of the present invention, after synchronizing data of the buffer memory cache in the electronic device into the memory of the electronic device, the method further includes: reading from the non-volatile memory for identifying the A flag indicating whether the electronic device is abnormally powered down; and when the flag indicates an abnormal power failure, the electronic device checks data in the ECC memory.

In the embodiment of the present invention, after the electronic device checks the data in the ECC memory through the ECC memory, the method includes: performing a check result obtained by performing ECC check on the data in the memory. The ECC check values stored in the memory are compared, and when the comparison result is consistent, it is confirmed that the data in the memory does not change. When the comparison result is inconsistent, it is confirmed that the data in the memory has occurred. Variety.

According to another embodiment of the present invention, there is also provided a power down processing apparatus, comprising: a detecting module configured to detect that the electronic device is powered down; and a synchronization module configured to buffer data of the buffer memory in the electronic device Synchronized into the memory of the electronic device.

In the embodiment of the present invention, the power-off condition of the electronic device detected by the detecting module includes one of the following: the electronic device is powered off normally, and the electronic device is abnormally powered down.

In the embodiment of the present invention, the device further includes: a setting module, configured to set a flag bit for identifying whether the electronic device is abnormally powered down to be abnormally powered down.

In an embodiment of the present invention, the apparatus further includes: a reading module configured to read, from the non-volatile memory, a flag bit for identifying whether the electronic device is abnormally powered down; the verification module is configured to be When the flag bit indicates an abnormal power failure, the electronic device checks data in the ECC memory.

In the embodiment of the present invention, the device further includes: a comparison module, configured to compare the verification result obtained by performing ECC check on the data in the memory with a pre-stored ECC check value in the memory; The first confirmation module is configured to confirm that the data in the memory does not change if the comparison result is consistent; The second confirmation module is set to confirm that the data in the memory has changed if the comparison result is inconsistent.

According to another embodiment of the present invention, there is also provided an electronic device comprising: a microprocessor controller, an ECC memory and a buffer memory; and a microprocessor controller configured to generate a control when the electronic device is detected to be powered down The buffer memory is configured to receive the control instruction and synchronize data buffered by the buffer memory into the ECC memory under the trigger of the control instruction.

In an embodiment of the invention, the electronic device further includes: a non-volatile memory, configured to store a flag bit for identifying whether the electronic device is abnormally powered down.

With the present invention, it is detected that the electronic device is powered down; the data buffered by the buffer memory in the electronic device is synchronized into the memory of the electronic device. The invention solves the problem that the implementation method of the data in the memory is not lost after the abnormal power-off of the electronic device in the prior art, and further, after the abnormal power-off of the electronic device, the operation of not losing the data in the memory is realized, and the memory is guaranteed. The correctness of the data enhances the user experience.

DRAWINGS

The drawings described herein are intended to provide a further understanding of the invention, and are intended to be a part of the invention. In the drawing:

1 is a flow chart of a power down processing method according to an embodiment of the present invention;

2 is a block diagram showing the structure of a power-down processing apparatus according to an embodiment of the present invention;

3 is a block diagram 1 of a power-down processing apparatus according to an embodiment of the present invention;

4 is a block diagram 2 of a power-down processing apparatus according to an embodiment of the present invention;

5 is a structural block diagram 3 of a power-down processing apparatus according to an embodiment of the present invention;

6 is a structural block diagram of an electronic device according to an embodiment of the present invention;

7 is a structural block diagram 1 of an electronic device according to an embodiment of the present invention;

8 is a block diagram of an apparatus involved in a power down processing method according to an embodiment of the present invention;

9 is a flowchart 1 of a power down processing method according to an embodiment of the present invention;

FIG. 10 is a flowchart of operations when an electronic device is restarted according to an embodiment of the present invention.

detailed description

The invention will be described in detail below with reference to the drawings in conjunction with the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments may be combined with each other without conflict.

In the embodiment, a power-down processing method is provided. FIG. 1 is a flowchart of a power-down processing method according to an embodiment of the present invention. As shown in FIG. 1, the process includes the following steps:

Step S102, detecting that the electronic device is powered off;

Step S104: Synchronize data buffered by the buffer memory in the electronic device into the memory of the electronic device.

Through the above steps, when the electronic device is powered off, the buffer memory synchronizes its cached data into the memory of the electronic device, and stores it through the non-volatile storage medium after the electronic device is powered down, compared to the prior art. The data is copied into the memory. The above steps solve the problem that the implementation method of the data in the memory is not lost after the electronic device is abnormally powered off, and the data in the memory is not realized after the electronic device is abnormally powered off. The lost operation is simple, ensuring the correctness of the data in the memory and improving the user experience. There may be multiple situations in which the electronic device is powered down. In a preferred embodiment, the electronic device is powered down, including the normal powering down of the electronic device or the abnormal power failure of the electronic device. The abnormal power-down of the electronic device means that the power is actively powered off due to non-human reasons, such as abnormal voltage and unplugged power.

In a preferred embodiment, the above memory is error checking and correcting ECC memory.

Since the electronic device may be powered off, there may be various cases. In a preferred embodiment, after detecting that the electronic device is powered off, the flag for identifying whether the electronic device is abnormally powered down is set to abnormal power-down. Thus, the situation in which the electronic device is powered off is separately identified. In another preferred embodiment, a flag for identifying whether the electronic device is abnormally powered down is read from the non-volatile memory, and the buffer memory in the electronic device is used if the flag indicates that the electronic device is abnormally powered down. After the cached data is synchronized into the memory of the electronic device, the electronic device verifies the data in the ECC memory.

In another preferred embodiment, after the electronic device checks the data in the ECC memory through the ECC memory, the verification result obtained by performing ECC check on the data in the memory is performed with the ECC check value pre-stored in the memory. In comparison, if the comparison result is consistent, it is confirmed that the data in the memory has not changed. At this time, after the electronic device is re-powered, the data in the memory is correct and can be used continuously; in the case where the comparison result is inconsistent , to confirm that the data in the memory has changed, in this case, you need to further judge the comparison If the difference is small, the data in the memory can be used continuously. If the difference is large, using the data in the memory will generate an error and cannot be used any more.

In the embodiment, a power-down processing device is also provided, which is used to implement the above-mentioned embodiments and preferred embodiments, and has not been described again. As used below, the term "module" may implement a combination of software and/or hardware of a predetermined function. Although the apparatus described in the following embodiments is preferably implemented in software, hardware, or a combination of software and hardware, is also possible and contemplated.

2 is a structural block diagram of a power-down processing apparatus according to an embodiment of the present invention. As shown in FIG. 2, the apparatus includes: a detecting module 22 configured to detect that the electronic device is powered off; and a synchronization module 24 configured to be in the electronic device. The data buffered by the buffer memory is synchronized into the memory of the electronic device.

In the embodiment of the present invention, the power-off condition of the electronic device detected by the detecting module 22 includes one of the following: the electronic device is powered off normally, and the electronic device is abnormally powered down.

In the embodiment of the present invention, the memory is an error check and corrects the ECC memory.

3 is a block diagram showing the structure of a power-down processing apparatus according to an embodiment of the present invention. As shown in FIG. 3, the apparatus further includes: a setting module 26, configured to set a flag for identifying whether the electronic device is abnormally powered down. Power down.

4 is a block diagram showing the structure of a power-down processing apparatus according to an embodiment of the present invention. As shown in FIG. 4, the apparatus further includes a reading module 28 configured to read from the non-volatile memory for identifying the electronic device. Whether the device is abnormally powered down or not; the verification module 30 is configured to verify the data in the ECC memory when the flag indicates abnormal power failure.

FIG. 5 is a structural block diagram 3 of a power-down processing apparatus according to an embodiment of the present invention. As shown in FIG. 5, the apparatus further includes: a comparison module 32 connected to the verification module 30, configured to perform data in the memory. The verification result obtained by the ECC check is compared with the pre-stored ECC check value in the memory; the first confirmation module 34 is set to confirm that the data in the memory does not change if the comparison result is consistent; the second confirmation module 36. Set to confirm that the data in the memory has changed if the comparison result is inconsistent.

6 is a structural block diagram of an electronic device according to an embodiment of the present invention. As shown in FIG. 6, the electronic device includes: a microprocessor controller 62, an ECC memory 64, and a buffer memory 66. The microprocessor controller 62 is configured to detect When the electronic device is powered down, a control command is generated; the buffer memory 66 is configured to receive the control command, and the data buffered by the buffer memory 66 is synchronized to the ECC memory 64 under the trigger of the control command. The buffer memory 66 may be part of the microprocessor controller 62, commonly referred to as a refresh cache, and integrated in a central processing unit (CPU).

FIG. 7 is a structural block diagram of an electronic device according to an embodiment of the present invention. As shown in FIG. 7, the electronic device further includes: a non-volatile memory 68 configured to store a flag for identifying whether the electronic device is abnormally powered down. .

The above-described problems existing in the related art will be described below in conjunction with the preferred embodiments, which combine the above-described embodiments and preferred embodiments thereof.

The preferred embodiment provides a memory power down protection method based on ECC memory characteristics. Several components of the method: the memory controller unit of the network processing chip used by the communication device can perform ECC check on the data in the memory, the battery that supplies power to the memory after the system is powered off, and the central processing unit (CPU) passes through the CPU bus. (local bus) external non-volatile random access memory (Non-Volatile Random Access Memory, NVRAM for short) storage system abnormal power-down flag (here can use any kind of storage medium that loses power without losing data) The communication device uses a memory module with an ECC function.

When the electronic device system is abnormally powered down, the hardware detects that the main power output voltage is abnormal, the processor chip receives the main power output abnormal interrupt, sends a memory self-refresh command through the memory controller, and sets the corresponding address in the NVRAM, hardware logic. Control turns on the battery and starts to supply power to the memory, after which the main power output fails.

When the electronic device restarts, during the cpu uboot boot phase, the abnormal power-down flag is read from the NVRAM. If the system abnormal power failure occurs before, the data ECC verification process is entered.

The preferred embodiment will be described in detail below with reference to the accompanying drawings.

Firstly, the method is based on certain hardware conditions, and the memory controller unit of the network processing chip used by the electronic device can perform ECC check on the data in the memory, and the used memory carries the ECC function, and the device block diagram related to the method is shown in FIG. 8 . Shown. The CPU is the core of the electronic device, and completes basic functions such as network protocol processing and message distribution. ECC memory, which stores programs and data when the electronic device is working properly. After the NVRAM is powered off, it can still maintain a kind of RAM. When the device is powered off abnormally, it will store a flag in the NVRAM. When the device restarts, the corresponding flag is read from the NVRAM to determine whether the last power failure occurred. It is abnormally powered down to distinguish this power-on process. The battery continues to supply power to the memory when the device is powered down, keeping the data in the memory intact.

When the device is powered off abnormally, the hardware detects that the main power voltage output is abnormal. FIG. 9 is a flowchart 1 of the power-down processing method according to the embodiment of the present invention. As shown in FIG. 9, the process includes the following steps:

Step S902, the power output is abnormal;

Step S904, entering an interrupt processing entry;

Step S906, the NVRAM performs identification, that is, sets the flag bit;

Step S908, refreshing the cache (cache), that is, refreshing the cache memory, and synchronizing the cached data into the memory;

Step S910, starting a memory self-refresh;

In step S912, the hardware boot battery is a memory battery.

Specifically, after detecting the abnormality, the hardware sends an interrupt signal to the CPU to trigger the device abnormal power-down interrupt. Then the software enters the interrupt process and triggers the interrupt handler function that is attached by request_irq. The interrupt handler mainly performs two tasks: Setting the corresponding flag bit in NVRAM indicates that the power failure is abnormal power failure of the device, and the device performs ECC check on the data in the memory at the next startup; 2. Refreshing the cache memory (cache) and starting the self-refresh memory Mode, refresh the cache is to synchronize the data in the cache to the memory, self-refresh (Self-Refresh) is used when there is no clock input, first execute the self-refresh command (REFS-EN) into the self-refresh mode, start the internal Refresh address counter counting and refresh operation, refresh control circuit provides refresh control at certain time intervals, Self-Refresh is usually used in power-saving mode, or sleep mode, which can consume less power and refresh cycle The shorter the power consumption is, the longer the refresh cycle is, as long as possible, in order to save power, but the cycle is too long, it is dangerous. Once it is not enough to keep the contents of the DRAM, it will be lost. For the NVRAM set operation, you can directly write the value to the fixed address. You can mount the NVRAM under the local bus of the CPU during design, and then select one byte of its corresponding address space as the flag. The value stored in the section is rewritten to 1. Refreshing the cache can use the way of writing values to the useless memory address. The memory size can directly cover the size of the cache. This is to ensure that the values in the cache are all synchronized to the memory during normal operation. While the software is processing the interrupt, the hardware logic turns on the battery switch and starts to supply power to the memory. After that, the main power fails and the electronic device loses power.

Since the memory is always powered by the battery during the power-down of the electronic device, the data in the memory is not lost. However, for software, it is still necessary to ensure the reliability of the data in the memory, or at least to determine whether the data has changed. This mainly depends on some operations performed when the device is powered on again.

When the electronic device is powered on again, the CPU uses uboot to boot. After uboot initializes the CPU's memory controller, it will go through a process as shown in Figure 10. The specific process is as follows:

Step S1002, the flag bit is read in the NVRAM, that is, after entering the process, the software first reads a flag indicating whether the device is abnormally powered down from the NVRAM, and the operation is the same as when the device is powered off, and the address corresponding to the flag bit does not change. One is a write operation and the other is a read operation.

Step S1004, determining whether the flag bit is set to 1, if the flag position is 1, indicating that the last power failure is abnormal power failure, the memory is powered by the battery during the power failure process, and the data needs to be verified, if the flag bit is not When set to 1, the process is skipped, and step S1012 is performed. If the flag bit is set to 1, step S1006 is performed. The method of setting the flag position 1 here is only one method for distinguishing whether it is an abnormal power failure, and the manner of judging the flag bit can be additionally selected. The series of operations to be performed after entering the data verification process mainly depend on the hardware characteristics of the CPU. The memory controller unit of the CPU we use here must be able to perform ECC check on the data in the memory. Here is a mips architecture CPU as an example to illustrate the process.

In step S1006, a start address and an end address are determined. Based on the characteristics of the CPU memory controller, first select the required memory space, and use the interval of the start address and the end address to indicate that the address value here is relative to the memory size, for example, the memory size is 2G, and the start address is 0. The end address is 1G, indicating that the first half of the memory is to be verified, not the physical space address 0~1G seen by the CPU.

Step S1008, the ECC check process, that is, performing a 64-byte ECC check. Later, a hardware module in the memory controller is used to verify the data. The module can read 64 bytes of data from the ddr3 memory supporting the ECC function, and calculate the ECC school corresponding to the data. The value is checked, and then the value is compared with the existing ECC check value read from the memory. If they are consistent, the data in the memory is considered to have not changed. If not, the value in the memory is changed. Since the module can only process 64 bytes of data at a time, if the size of the checked memory is greater than 64 bytes, it needs to be cycled from the start address to the end address. Each check completes 64 bytes and compares once. If there is a failure, The failure count (errcount) is incremented until all required memory is verified.

Step S1010, the errcount is written into the NVRAM, that is, after the verification is completed, the errcount is also written to a corresponding address in the NVRAM, and after the electronic device is completely powered on, the value is read from the NVRAM, and the software verifies the error according to the data. How much to decide whether the data stored in memory can continue to be used. From the process of data verification, we can see that this method mainly relies on the memory ECC check module of the CPU memory controller, especially it can complete the calculation of 64-byte data ECC check value and read the original ECC from the memory. The nature of the check value. Of course, the specific implementation of the method is not limited to the above description, for example, if a series of CPUs can complete the ECC check of the data in the memory, but not only can process 64 bytes of data at a time, the implementation of the method will be The corresponding modification, here is only based on the method description of a processor that has been applied.

In step S1012, the process ends.

In summary, the method adopted by the embodiment of the present invention saves the process of data movement. In the process of powering down the device, the data still exists in the device memory. And can learn from the characteristics of ECC memory to ensure separate memory The correctness of the data during power supply enables the data in the memory to be used normally after the device is restarted, which is also a key to the memory power-down protection function of the present invention.

It will be apparent to those skilled in the art that the various modules or steps of the present invention described above can be implemented by a general-purpose computing device that can be centralized on a single computing device or distributed across a network of multiple computing devices. Alternatively, they may be implemented by program code executable by the computing device such that they may be stored in the storage device by the computing device and, in some cases, may be different from the order herein. The steps shown or described are performed, or they are separately fabricated into individual integrated circuit modules, or a plurality of modules or steps thereof are fabricated as a single integrated circuit module. Thus, the invention is not limited to any specific combination of hardware and software.

The above description is only the preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes can be made to the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and scope of the present invention are intended to be included within the scope of the present invention.

Industrial applicability

The foregoing technical solution provided by the embodiment of the present invention can be used to detect that the electronic device is powered off during the power failure detection process of the electronic device, and synchronize the data buffered by the buffer memory in the electronic device into the memory of the electronic device. The invention solves the problem that the implementation method of the data in the memory is not lost after the abnormal power-off of the electronic device in the prior art, and further, after the abnormal power-off of the electronic device, the operation of not losing the data in the memory is realized, and the memory is guaranteed. The correctness of the data enhances the user experience.

Claims

A power-down processing method includes:

The electronic device is detected to be powered down;

Synchronizing data buffered by the buffer memory in the electronic device into a memory of the electronic device.
The method of claim 1, wherein the electronic device is powered down comprises one of the following:

The electronic device is powered off normally, and the electronic device is powered off abnormally.
The method of claim 2 wherein said memory is error checking and correcting ECC memory.
The method of claim 3, wherein detecting that the electronic device is powered down comprises:

A flag bit for identifying whether the electronic device is abnormally powered down is set to be abnormally powered down.
The method of claim 4, wherein after the data of the buffer memory cache in the electronic device is synchronized into the memory of the electronic device, the method further comprises:

Reading a flag for identifying whether the electronic device is abnormally powered down from a non-volatile memory;

The data in the ECC memory is verified when the flag bit indicates an abnormal power down.
The method according to claim 5, wherein after the data in the ECC memory is verified by the ECC memory, the method comprises:

Comparing the verification result obtained by performing ECC check on the data in the memory with the ECC check value pre-stored in the memory, and confirming that the data in the memory does not change if the comparison result is consistent When the comparison result is inconsistent, it is confirmed that the data in the memory has changed.
A power-down processing device includes:

a detection module configured to detect that the electronic device is powered off;

And a synchronization module configured to synchronize data buffered by the buffer memory in the electronic device into a memory of the electronic device.
The device according to claim 7, wherein the electronic device power-off condition detected by the detecting module comprises one of the following:

The electronic device is powered off normally, and the electronic device is powered off abnormally.
The apparatus of claim 8 wherein said memory is error checking and correcting ECC memory.
The apparatus of claim 9 wherein said apparatus further comprises:

The setting module sets a flag bit for identifying whether the electronic device is abnormally powered down to be abnormally powered down.
The device of claim 10, wherein the device further comprises:

a reading module configured to read, from the non-volatile memory, a flag bit for identifying whether the electronic device is abnormally powered down;

The verification module is configured to verify data in the ECC memory when the flag bit indicates abnormal power failure.
The apparatus of claim 11 wherein said apparatus further comprises:

a comparison module, configured to compare a verification result obtained by performing ECC check on the data in the memory with an ECC check value pre-stored in the memory;

The first confirmation module is configured to confirm that the data in the memory does not change if the comparison result is consistent;

The second confirmation module is configured to confirm that the data in the memory has changed if the comparison result is inconsistent.
An electronic device comprising: a micro processing controller, an ECC memory, and a buffer memory;

a microprocessor controller configured to generate a control command upon detecting that the electronic device is powered down;

The buffer memory is configured to receive the control instruction and synchronize data buffered by the buffer memory into the ECC memory under the trigger of the control instruction.
The electronic device of claim 13, wherein the electronic device further comprises:

A non-volatile memory is arranged to store a flag bit for identifying whether the electronic device is abnormally powered down.