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WO2015104808A1 - Power semiconductor device and power conversion device - Google Patents

Power semiconductor device and power conversion device Download PDF

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Publication number
WO2015104808A1
WO2015104808A1 PCT/JP2014/050182 JP2014050182W WO2015104808A1 WO 2015104808 A1 WO2015104808 A1 WO 2015104808A1 JP 2014050182 W JP2014050182 W JP 2014050182W WO 2015104808 A1 WO2015104808 A1 WO 2015104808A1
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WO
WIPO (PCT)
Prior art keywords
power semiconductor
insulating resin
ceramic
resin
insulating
Prior art date
Application number
PCT/JP2014/050182
Other languages
French (fr)
Japanese (ja)
Inventor
順平 楠川
英一 井出
円丈 露野
Original Assignee
株式会社日立製作所
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Filing date
Publication date
Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
Priority to PCT/JP2014/050182 priority Critical patent/WO2015104808A1/en
Publication of WO2015104808A1 publication Critical patent/WO2015104808A1/en

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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to a power semiconductor device used for a power conversion device such as an inverter device.
  • the needs for these power conversion devices include a reduction in cost, a reduction in installation area, and high reliability.
  • the power conversion device is composed of a power semiconductor device (power module) incorporating a power semiconductor element such as an IGBT (Insulated Gate Bipolar Transistor), as well as a number of components such as a control circuit, a bus bar, a coil, and a capacitor. Yes.
  • a technology for reducing the size and reliability of the power semiconductor device that is the main component of the power conversion device is important.
  • Al 2 O 3 aluminum oxide
  • AlN aluminum nitride
  • SiN silicon nitride
  • a conductive plate such as a copper foil is pasted on both sides via a brazing material. Then, the conductive plate is etched to form a circuit electrode and a back electrode, and a ceramic substrate with a circuit electrode is obtained.
  • solder (solder) paste is apply
  • a power semiconductor element is an element that switches a current of several amperes to several hundred amperes, and the element generates heat.
  • the quality of the heat generated by the element heat greatly affects the downsizing and reliability of the device.
  • heat generated by the power semiconductor element is dissipated from one surface of the element. Therefore, the heat dissipation performance is low, and there is a limit to the miniaturization and reliability of the power semiconductor device. For this reason, in recent years, power semiconductor devices having a double-sided cooling structure in which electrodes, insulating plates, and heat sinks are attached to both surfaces of the power semiconductor element to dissipate heat generated in the power semiconductor element from both surfaces of the element have been developed.
  • Patent Document 1 discloses a semiconductor device cooling structure in which a semiconductor device having a pair of heat sinks on both surfaces of a power semiconductor element and molded with resin almost entirely is in contact with a cooler via an insulating material.
  • Patent Document 2 includes two high thermal conductive insulating substrates which are provided so as to sandwich a semiconductor chip, and are provided with electrode patterns for bonding to the electrodes of the semiconductor chip on each sandwiching surface. The technology of the semiconductor device is disclosed.
  • Patent Document 3 discloses a power semiconductor element, a first heat radiating plate provided on one side of the power semiconductor element, a second heat radiating plate provided on a surface side opposite to the one surface, A technology of a power semiconductor module provided with a flow path through which a refrigerant flows so as to be in contact with the first and second heat radiating plates, respectively, is disclosed.
  • the present invention solves such a problem, and the object is to prevent peeling at the interface between the ceramic substrate (ceramic insulating substrate) and the insulating resin and to have high reliability.
  • a semiconductor device and a power conversion device are provided.
  • the present invention is configured as follows. That is, the power semiconductor device of the present invention includes a power semiconductor element, at least one ceramic insulating circuit board having a circuit electrode formed on a ceramic substrate, at least one electrode surface of the power semiconductor element, and the ceramic insulating circuit.
  • a second insulating resin having an adhesive strength higher than that of the first insulating resin.
  • the second insulating resin has an adhesive strength higher than that of the first insulating resin.
  • the present invention it is possible to provide a semiconductor device and a power conversion device that can prevent peeling at the interface between the ceramic substrate and the insulating resin and have high reliability.
  • FIG. 1 is a schematic plan view of a vicinity of main components of a power semiconductor device according to a first embodiment of the present invention as viewed from above. It is a figure which shows the cross-section of the power semiconductor device of a comparative example.
  • FIG. 1 is a diagram showing a cross-sectional structure of a power semiconductor device 10 according to the first embodiment of the present invention.
  • a ceramic substrate 2A, a circuit electrode 3A, and a back electrode 4A are provided to constitute a first ceramic insulating circuit substrate 23A.
  • the second ceramic insulating circuit board 23B is configured by including the ceramic substrate 2B, the circuit electrode 3B, and the back electrode 4B.
  • the heat generated by the first ceramic insulated circuit board 23A is radiated by the heat radiating base plate 19A and the heat conducting member 18A.
  • the heat radiating base plate 19B and the heat conducting member 18B are configured to radiate heat generated in the second ceramic insulated circuit board 23B.
  • the power semiconductor device 10 has a structure having a double-sided cooling structure. As shown in FIG. 1, the first ceramic insulated circuit board 23A and the second ceramic insulated circuit board 23B are arranged to face each other with the circuit electrodes 3A and the circuit electrodes 3B facing inward.
  • the power semiconductor element 11 made of IGBT or the like is connected to the first and second ceramic insulated circuit boards (23A and 23B) via a base 141 and solders 51A and 51B.
  • the power semiconductor element 12 is connected to the first and second ceramic insulated circuit boards (23A, 23B) via a pedestal 142, solders 52A, 52B, and the like.
  • the bus bars 8A, 8B, and 8G are connected to the power semiconductor element 11 and the first and second ceramic insulating circuit boards (23A and 23B) via solders 53A and 53B and wires 6G. .
  • the power semiconductor element 11 and the power semiconductor element 12 are separate chips as semiconductor chips.
  • the second insulating resin 17A is in contact with the circuit electrode 3A and the ceramic substrate 2A (ceramic insulating circuit substrate 23A) for insulation.
  • the second insulating resin 17B is in contact with the circuit electrode 3A and the ceramic substrate 2B (ceramic insulating circuit substrate 23A) for insulation.
  • the first insulating resin 16 includes second insulating resins 17A and 17B, ceramic insulating circuit boards 23A and 23B, power semiconductor elements 11 and 12, pedestals 141 and 142, and solders 51A, 51B, 52A, 52B, 53A, and 53B. Is covered and insulated.
  • the first insulating resin 16 covers and insulates part of the bus bars 8A, 8B, 8G.
  • circuit electrodes 3A and 3B have a notation that looks like a single metal body.
  • the circuit electrodes 3A and 3B are a plurality of circuit electrodes separated from each other to form an electric circuit. May be configured. Even when a plurality of circuit electrodes 3A and 3B are respectively formed, the plurality of circuit electrodes are formed on the same plane of the ceramic insulating circuit boards (23A and 23B). It is written in.
  • a ceramic insulated circuit board 23A is prepared in which a circuit electrode 3A is formed on one surface of a ceramic substrate 2A made of silicon nitride (SiN), and a back electrode 4A for heat dissipation is formed on the opposite surface.
  • a ceramic insulated circuit board 23B is prepared in which a circuit electrode 3B is formed on one surface of a ceramic substrate 2B made of silicon nitride (SiN), and a back electrode 4B for heat dissipation is formed on the opposite surface.
  • two ceramic insulating circuit boards (23A, 23B) on which the circuit electrodes (3A, 3B) and the back electrodes (4A, 4B) are formed are prepared.
  • a resin mainly composed of polyamideimide is applied to the whole. Then, the resin is cured at a predetermined temperature and time to form the second insulating resin (17A, 17B) on the ceramic insulating circuit boards (23A, 23B).
  • solders 51A, 52A, and 53A are formed at predetermined positions of the circuit electrode 3A of the ceramic insulating circuit board 23A located on the lower side of the first sheet. Then, on the solder (51A, 52A, 53A, etc.), the collector bus bar 8A, the control terminal bus bar 8G, and the power semiconductor element 11 are superimposed on the corresponding positions of the circuit electrode 3A, respectively. . (The actual configuration related to the notation of the control terminal bus bar 8G will be described later.) Then, by a reflow process through a reflow furnace (not shown), the first ceramic insulating circuit board 23A, the power semiconductor element 11, the collector bus bar 8A, and the control terminal bus bar 8G are joined. The gate terminal (not shown) and the control terminal bus bar 8G are connected by an aluminum thin wire 6G.
  • solder (51B, 52B, 53B, etc.) is formed at a predetermined position of the other ceramic insulated circuit board 23B, the emitter bus bar 8B and the base 141 are placed, and they are joined by a reflow process through a reflow furnace. . Then, solders 51B, 52B, 51C, and 52C are formed on the bases 141 and 142, and the emitter electrode (not shown) of the power semiconductor element 11 and the base 141 are formed so that the circuit electrodes 3B of the ceramic insulating circuit board 23B face each other. Align to match and join through reflow oven.
  • these joined circuit components are placed in a transfer mold (not shown), a molding material made of epoxy mold resin is injected, and a predetermined temperature and pressure are applied for a predetermined time.
  • the epoxy mold resin is thermally cured to form the first insulating resin 16 of the epoxy mold resin in which the entire power semiconductor element between the two ceramic insulated circuit boards 23A and 23B is insulated and sealed.
  • the back electrodes 4A, 4B of the two ceramic insulated circuit boards 23A, 23B and the heat radiating base plates 19A, 19B are joined via the heat conducting members 18A, 18B, thereby completing the power semiconductor device 10.
  • the first dielectric resin 16 had a relative dielectric constant of 4.0
  • the second dielectric resins 17A and 17B had a dielectric constant of 4.0.
  • the influence and effect of the difference between the relative dielectric constant of the first insulating resin 16 and the relative dielectric constant of the second insulating resins 17A and 17B will be described later.
  • FIG. 5 shows main components of the power semiconductor device 10 according to the first embodiment of the present invention (power semiconductor element 11, ceramic insulating circuit board 23A, heat radiation base plate 19A, circuit electrode 3A, control terminal bus bar 8G, collector. It is the schematic top view which looked at the neighborhood where bus bar 8A etc. are arranged from the upper surface. (FIG. 4 will be described later.) 5 is a diagram showing the relationship between the arrangement of the control terminal bus bar (control terminal) 8G and the collector bus bar 8A, and therefore, the illustration of the components other than those described above and the exact arrangement corresponding to FIG. 1 is omitted. ing.
  • the collector bus bar 8A and the control terminal bus bar 8G in FIG. 5 are located at the same height when viewed from the plane of the ceramic insulated circuit board 23A.
  • the control terminal bus bar 8G is hidden by the collector bus bar 8A and I can't show it. Therefore, in FIG. 1, in order to show that the control terminal bus bar 8G exists, for convenience, the control terminal bus bar 8G is shown at a position higher than the collector bus bar 8A. However, as described above, the control terminal bus bar 8G is the same height as the collector bus bar 8A, and a joining process or the like by solder (51A, 52A, 53A, etc.) is performed.
  • FIG. 2 is a diagram showing a cross-sectional structure of a power semiconductor device 10 according to the second embodiment of the present invention.
  • the difference in the cross-sectional structure of the power semiconductor device 10 in FIG. 1 is the volume of the second insulating resins 17A and 17B and the contact area with the ceramic insulating circuit boards 23A and 23B.
  • the volume of the second insulating resins 17A and 17B in FIG. 2 and the contact area with the ceramic insulating circuit boards 23A and 23B are both smaller than those of the second insulating resins 17A and 17B in FIG.
  • the power semiconductor device 10 of FIG. 2 differs from FIG. ⁇ 1> Predetermined temperature, pressure, and time based on a resin in which the second insulating resins 17A and 17B are mainly composed of a polyamideimide resin and an alumina filler having an average particle size of 5 ⁇ m is mixed in the polyamideimide resin at a weight ratio of 30 wt%. It is formed by curing with.
  • the ceramic substrates 2A and 2B are made of aluminum nitride (AlN).
  • the ceramic substrates 2A and 2B of the first embodiment are made of silicon nitride (SiN) as described above.
  • the power semiconductor device 10 of FIGS. Description is omitted.
  • the relative dielectric constant of the first insulating resin 16 of the completed power semiconductor device 10 is 4.0
  • the relative dielectric constant of the second insulating resins 17A and 17B is 6.2. .
  • the characteristics and features of the second embodiment of FIG. 2 different from those of the first embodiment of FIG. 1 will be described later.
  • FIG. 3 is a diagram showing a cross-sectional structure of a power semiconductor device 10 according to the third embodiment of the present invention.
  • the arrangement of the second insulating resins 17A and 17B is the arrangement of the second insulating resins 17A and 17B. That is, the ceramic substrates 2A and 2B applied to the end portions of the ceramic substrates 2A and 2B (ceramic insulating circuit substrates 23A and 23B) from a portion about 1 mm away from the peripheral ends of the circuit electrodes 3A and 3B of the ceramic insulating circuit substrates 23A and 23B. Second insulating resins 17A and 17B are respectively formed on the surfaces of
  • the power semiconductor device 10 of FIG. 1 differs from the power semiconductor device 10 of FIG. 1 in terms of material in that the second insulating resins 17A and 17B have a predetermined temperature and pressure based on a resin mainly composed of silicone. It is formed by curing with time. Except for the shapes and materials of the second insulating resins 17A and 17B, the power semiconductor device 10 of FIGS. 1 and 3 has the same shape, material, and manufacturing process, and therefore redundant description is omitted.
  • the first dielectric resin 16 of the completed power semiconductor device 10 has a relative dielectric constant of 4.0, and the second dielectric resins 17A and 17B have a dielectric constant of 2.8. .
  • the characteristics and features of the third embodiment of FIG. 3 different from those of the first and second embodiments of FIGS. 1 and 2 will be described later.
  • FIG. 6 is a diagram showing a cross-sectional structure of a power semiconductor device 20 of a comparative example. 6 differs from the power semiconductor device 10 according to the first embodiment of the present application shown in FIG. 1 in that the second insulating resins 17A and 17B in FIG. 1 are present in the comparative example shown in FIG. Is not to. Other components, materials, and manufacturing processes are the same. Therefore, the overlapping description is omitted.
  • the relative dielectric constant of the insulating resin (first insulating resin) of the completed power semiconductor device 20 of the comparative example was 4.0.
  • FIG. 7 is an enlarged view of the area S indicated by a broken line in FIG. Note that the shapes of the circuit electrode 3A and the back electrode 4A are described in a state closer to the actual state than FIG. 6, as will be described later.
  • the ceramic insulated circuit board (23A) includes a ceramic substrate 2A, a circuit electrode 3A, and a back electrode 4A.
  • the heat conducting member 18A and the heat radiating base plate 19A are joined to the back electrode 4A of the ceramic insulated circuit board (23A).
  • the power semiconductor element 12 is joined to the circuit electrode 3A of the ceramic insulated circuit board (23A) and the pedestal 142 via the solder 52A and the solder 52C, respectively.
  • the first insulating resin 16 made of epoxy mold resin insulates and seals the ceramic insulated circuit board (23A) and the power semiconductor element 12.
  • the circuit electrode 3 ⁇ / b> A and the back electrode 4 ⁇ / b> A have acute angles at the ends as indicated by the hatched lines. This acute angle shape is due to the nature of the chemical reaction when the circuit electrode 3A and the back electrode 4A are formed by chemical etching.
  • the power semiconductor element (11, 12: FIG. 6) is provided with a pair of high thermal conductivity ceramic substrates (2A, 2B: FIG. 6) on both sides, and almost the entire apparatus is resin molded (first insulating resin 16: FIG. 6)
  • first insulating resin 16 FIG. 6
  • tensile stress acts between the two ceramic substrates (2A, 2B: FIG. 6) due to curing shrinkage of the mold resin. This is the reason why 7) is likely to occur.
  • the ceramic substrate 2A is formed by sintering an inorganic powder material of silicon nitride. Even if aluminum oxide or aluminum nitride is used instead of silicon nitride, the interfacial peeling is performed in the same manner. 99 may occur.
  • FIG. 8A is a diagram showing the equipotential lines of the electric field in the ceramic substrate 2A and the first insulating resin 16 in the region S (FIGS. 6 and 7) of the comparative example.
  • an equipotential line of an electric field is shown by a plurality of curve groups of thin lines.
  • the electric field is most concentrated (the interval between equipotential lines is narrow). Become.
  • dielectric breakdown and partial discharge are most likely to occur in the vicinity of the maximum electric field strength.
  • the electric field characteristics of the comparative example shown in FIG. 8A are characteristics when an SiN substrate is used for the ceramic substrate 2A and an epoxy mold resin having a relative dielectric constant of 4.0 is used for the first insulating resin 16. Based on this comparative example, the maximum electric field strength in the comparative example is used as a reference in order to compare with the characteristics of Examples 1, 2, and 3 described below. In FIG. 8A, since the comparative example is used as a reference for comparison, “maximum electric field strength ratio 1” is described. In addition, about the other part and structure in FIG. 8A, since description overlaps, it abbreviate
  • FIG. 8B is a diagram showing electric field equipotential lines in the ceramic substrate 2A, the second insulating resin 17A, and the first insulating resin 16 in Example 1 according to the first embodiment of the present invention. Since the form and characteristics of the equipotential lines differ depending on the material of the insulating resin, FIG. The structure shown in FIG. 8B is different from the structure shown in FIG. 8A in that the second insulating resin 17A is provided. The second insulating resin 17A is provided at a location where the surface of the ceramic substrate 2A is not covered with the circuit electrode 3A. FIG. 8B corresponds to FIG. 1 describing the first embodiment.
  • the second insulating resin 17A is made of a material having higher adhesive strength to the ceramic substrate 2A than the first insulating resin 16 is. However, the relative dielectric constant of the second insulating resin 17A is 4.0, and the same dielectric constant as that of the first insulating resin 16 is used.
  • the form and characteristics of the equipotential lines of the electric field in the ceramic substrate 2A, the second insulating resin 17A, and the first insulating resin 16 in FIG. 8B are almost the same as those in FIG. 8A as the comparative example.
  • the electric field is most concentrated (the equipotential lines are narrow), and the maximum electric field strength is obtained. A ratio of 1 is obtained.
  • Other overlapping explanations are omitted.
  • FIG. 8C is a diagram showing electric field equipotential lines in the ceramic substrate 2A, the second insulating resin 17A, and the first insulating resin 16 in Example 2 according to the second embodiment of the present invention. Note that the form and characteristics of the equipotential lines differ depending on the material of the insulating resin, and therefore FIG.
  • the structure shown in FIG. 8C differs from the structure shown in FIG. 8B in that the length of the second insulating resin 17A in the direction in contact with the ceramic substrate 2A is shortened. 8C corresponds to FIG. 2 describing the second embodiment.
  • an AlN substrate is used as the ceramic substrate 2A.
  • the second insulating resin 17A is mainly composed of a polyamideimide resin, and is cured at a predetermined temperature, pressure, and time based on a resin in which an alumina filler having an average particle diameter of 5 ⁇ m is mixed in a polyamideimide resin at a weight ratio of 30 wt%. Is formed.
  • the relative dielectric constant of the first insulating resin 16 was 4.0
  • the relative dielectric constant of the second insulating resin 17A was 6.2.
  • FIG. 8D is a diagram showing electric field equipotential lines in the ceramic substrate 2A, the second insulating resin 17A, and the first insulating resin 16 in Example 3 according to the third embodiment of the present invention. Note that the form and characteristics of the equipotential lines differ depending on the material of the insulating resin, so FIG.
  • the structure shown in FIG. 8D is different from the structure shown in FIG. 8B in that the second insulating resin 17A is in contact only with the ceramic substrate 2A and away from the end of the circuit electrode 3A.
  • FIG. 8D corresponds to FIG. 3 describing the third embodiment.
  • a SiN substrate is used for the ceramic substrate 2A.
  • the second insulating resin 17A is formed by curing at a predetermined temperature, pressure, and time based on a resin mainly composed of silicone. At this time, the relative dielectric constant of the first insulating resin 16 was 4.0, whereas the relative dielectric constant of the second insulating resin 17A was 2.8.
  • the first, second, and third embodiments of the present application are provided with the second insulating resins 17A and 17B, and are intended to increase the adhesive strength between the ceramic substrate 2A and the ceramic surface.
  • FIG. 9 shows the shear between the ceramic substrate (2A, 2B) and the mold resin (first insulating resin 16) for Examples 1, 2, 3 and Comparative Examples according to the first, second, and third embodiments of the present invention. It is a figure which shows an intensity
  • the comparative example, Examples 1, 2, and 3 are shown in order from the left in the horizontal axis direction, and the vertical axis indicates the shear strength ratio (pu: unit method) with the comparative example being the reference value 1. Have taken.
  • the shear strength of Examples 1, 2, and 3 is higher than that of the comparative example, and the adhesive strength with the ceramic insulating plate is increased by forming the second insulating resin.
  • a solid silicon nitride (SiN) ceramic substrate is prepared, and a resin (second insulating resin) mainly composed of polyamideimide is provided on one surface thereof. It was applied and cured under predetermined conditions. After that, the mold is placed on the ceramic insulating plate, and the epoxy mold resin (first insulating resin) has a predetermined temperature, pressure and time, the bottom diameter is 5 mm, the top diameter is 4 mm, and the height is 3 mm. A trapezoidal cylindrical specimen was prepared.
  • a solid aluminum nitride (AlN) ceramic substrate was prepared, and one surface thereof was mainly composed of a polyamideimide resin.
  • a resin in which an alumina filler having an average particle diameter of 5 ⁇ m and a weight ratio of 30 wt% was mixed was applied and cured at a predetermined temperature and time to form a second insulating resin on the ceramic insulating plate.
  • the mold is placed on the ceramic insulating plate, and the epoxy mold resin (first insulating resin) has a predetermined temperature, pressure and time, the bottom diameter is 5 mm, the top diameter is 4 mm, and the height is 3 mm.
  • a trapezoidal cylindrical specimen was prepared.
  • a solid silicon nitride (SiN) ceramic insulating plate is prepared, and a resin mainly composed of silicone is applied to one surface thereof,
  • the second insulating resin was formed on the ceramic insulating plate by curing at a predetermined temperature and time. After that, the mold is placed on the ceramic insulating plate, and the epoxy mold resin (first insulating resin) has a predetermined temperature, pressure and time, the bottom diameter is 5 mm, the top diameter is 4 mm, and the height is 3 mm.
  • a trapezoidal cylindrical specimen was prepared.
  • a solid silicon nitride (SiN) ceramic insulating plate is prepared as a configuration corresponding to the comparative example, a mold is placed on the ceramic insulating plate, and an epoxy mold resin (first insulating resin) is used.
  • a trapezoidal cylindrical specimen having a bottom surface diameter of 5 mm, a top surface diameter of 4 mm, and a height of 3 mm was prepared at a predetermined temperature, pressure, and time.
  • FIG. 9 shows the result of the test described above.
  • the first, second, and third embodiments (Examples 1, 2, and 3) having the second insulating resin have higher shear strength than the comparative examples having no second insulating resin.
  • the height of the shear strength varies depending on the materials of the second insulating resin and the ceramic substrate.
  • Example 1 in which the ceramic substrate is made of SiN and the second insulating resin is made of polyamideimide resin has the highest shear strength.
  • Example 3 in which the ceramic substrate is made of SiN and the second insulating resin is made of a resin mainly composed of silicone, the shear strength is next high.
  • the ceramic substrate is AlN
  • the second insulating resin is mainly composed of a polyamideimide resin
  • the polyamideimide resin is composed of a resin in which an alumina filler having an average particle diameter of 5 ⁇ m is mixed in a weight ratio of 30 wt%.
  • (2nd Embodiment) is a result lower than Example 1 and Example 3 about shear strength.
  • Example 1-3 has the second insulating resin that has a stronger adhesion to the ceramic substrate than the first insulating resin. This is considered to be the reason why the shear strength is increased. Moreover, it is thought that the difference in shear strength ratio is mainly caused by the difference in the material of the second insulating resin.
  • the collector lead (collector bus bar 8A, FIG. 1), emitter lead (emitter bus bar 8B, FIG. 1), and control terminal (control terminal bus bar) of the power semiconductor device (10, FIG. 1) are used. 8G, FIG. 1) was set to the same potential.
  • FIG. 10 is a diagram illustrating a result of performing a temperature cycle test on Examples 1, 2, 3 and the comparative example, and measuring a partial discharge voltage of the power semiconductor device every predetermined cycle.
  • the horizontal axis represents the cumulative number (cycle) of temperature cycle tests
  • the vertical axis represents the partial discharge start voltage at each temperature cycle.
  • the characteristic line 1000 represents a comparative example
  • the characteristic line 1001 represents Example 1
  • the characteristic line 1002 represents Example 2
  • the characteristic line 1003 represents Example 3.
  • ⁇ Temperature cycle test result of comparative example> As shown by the characteristic line 1000 in FIG. 10, in the comparative example, it was about 6 kVrms before the temperature cycle test, and no partial discharge occurred at less than 6 kVrms. However, after 200 cycles (cumulative number) of the temperature cycle test, the partial discharge start voltage was about 5.3 kVrms, and thereafter the partial discharge start voltage decreased with the progress of the test cycle. The reason why the partial discharge start voltage is lowered is that the adhesion between the ceramic substrates 2A and 2B and the epoxy mold resin which is the first insulating resin is peeled off to cause interface peeling, and partial discharge is generated at the peeling portion.
  • Example 1 ⁇ Results of temperature cycle test of Example 1> As shown by the characteristic line 1001 in FIG. 10, in Example 1, partial discharge did not occur at less than 6 kVrms before the temperature cycle test. And even after 1000 cycles (cumulative number) of the temperature cycle test, the occurrence of partial discharge was not seen at less than 6 kVrms. Note that the maximum electric field strength ratio of the electric field concentration portion in the comparative example of FIG. 8A is 1, and the maximum electric field strength ratio of the electric field concentration portion in the embodiment 1 of FIG. Thus, from the viewpoint of the maximum electric field strength, the partial discharge start voltage decreases in the comparative example (characteristic line 1000) in the temperature cycle test shown in FIG. In Example 1 (characteristic line 1001), the partial discharge start voltage is maintained.
  • Example 1 The reason why the comparative example deteriorates faster than Example 1 is that the second insulating resin is not present in the comparative example, so the first insulating resin 16 (FIGS. 7 and 8A) and the ceramic substrate 2A (FIGS. 7 and 8A) Peeling (interfacial peeling 99, FIG. 7) occurred, and as the cumulative number of temperature cycles increased, the peeling increased and the partial discharge start voltage decreased.
  • Example 1 since the second insulating resin 17A (FIG. 8B) is more firmly bonded to the ceramic substrate 2A than the first insulating resin 16 (FIG. 8B), peeling does not occur and partial discharge is caused. The starting voltage does not decrease.
  • Example 2 ⁇ Results of temperature cycle test of Example 2> As shown by the characteristic line 1002 in FIG. 10, in Example 2, the partial discharge start voltage was about 7.2 kVrms from the time before the temperature cycle test until the cumulative number of temperature cycles was about 400 times.
  • the second insulating resin 17A As described above, as the second insulating resin 17A (FIG. 8C), a polyamideimide resin is mainly used, and an alumina filler having an average particle diameter of 5 ⁇ m is added to the polyamideimide resin at a weight ratio of 30 wt%. A mixed resin is used.
  • Example 3 ⁇ Results of temperature cycle test of Example 3> As shown by the characteristic line 1003 in FIG. 10, in Example 3, the partial discharge start voltage was about 6.4 kVrms from before the temperature cycle test until the cumulative number of temperature cycles was about 800 times. This temperature cycle partial discharge start voltage (about 6.4 kVrms) is between the partial discharge start voltage of the comparative example and Example 1 (about 6 kVrms) and the partial discharge start voltage of Example 2 (about 7.2 kVrms). The value is shown. In the structure of Example 3, the maximum electric field strength ratio of the electric field concentration portion in FIG. 8D is 0.99, and the maximum electric field strength ratio of the comparative example of FIG. 8A and FIG. This corresponds to the value of the maximum electric field strength ratio of Example 2 in FIG. 8C being between 0.88.
  • Example 1-3 ⁇ Results of Temperature Cycle Test and Shear Strength Test of Example 1-3>
  • the second insulating resin 17A having an adhesive strength stronger than that of the first insulating resin 16 and having an appropriate relative dielectric constant is provided. It can be seen that the reliability is improved in the reliability test by the temperature cycle test. This improvement in reliability is achieved by the second insulating resin 17A (polyamideimide resin, silicone resin, etc.) having excellent adhesion to the ceramic between the ceramic substrate 2A and the first insulating resin 16 (epoxy mold resin). This is because interfacial peeling is prevented.
  • Example 2 had the highest partial discharge start voltage from 0 to 1000 times, followed by Example 3 and then Example 1. Met.
  • Example 1 had the strongest shear strength, followed by Example 3 and then Example 2.
  • the order of these desirable properties does not necessarily match between the shear strength test of FIG. 9 and the partial cycle start voltage temperature cycle test of FIG. That is, the selection of the optimal structure and material of the second insulating resin 17A differs depending on whether priority is given to the strength characteristic of the shear strength or the reliability by the temperature cycle test. Furthermore, various characteristics are exhibited not only by the second insulating resin 17A but also by the material and structure of the first insulating resin 16 and the ceramic substrate 2A.
  • FIG. 4 is a diagram showing a cross-sectional structure of a power semiconductor device 40 according to the fourth embodiment of the present invention.
  • a ceramic insulated circuit board 23S is configured by including a ceramic substrate 2A, a circuit electrode 3A, and a back electrode 4A.
  • the heat generating base plate 19A and the heat conducting member 18A are configured to radiate heat generated in the ceramic insulated circuit board 23S.
  • the power semiconductor device 40 has a structure having a single-sided cooling structure.
  • the power semiconductor element 11 made of IGBT or the like is connected to the ceramic insulating circuit board 23S through the solder 5A.
  • the external terminal 113 is connected to the power semiconductor element 11 and the ceramic insulating circuit board 23S via leads (bus bars) 8L, solder 57, circuit electrodes 3A, and wires 6W.
  • a second insulating resin 17A made of polyamideimide resin is provided in contact with the ceramic substrate 2A and the circuit electrode 3A.
  • the power semiconductor element 11 and the ceramic insulated circuit board 23S are insulated and sealed with the first insulating resin 16 made of epoxy mold resin.
  • the power semiconductor element 11 and the ceramic insulating circuit board 23S which are insulated and sealed are accommodated.
  • the second insulating resin 17A made of the polyamideimide resin is provided, so that the first and second embodiments are provided. Similar to the embodiment (Examples 1 and 2), there is an effect of improving reliability in a shear strength test, a temperature cycle test, and the like.
  • the second insulating resin has been described as a resin mainly composed of polyamideimide, a resin in which an alumina filler having an average particle size of 5 ⁇ m is mixed in a polyamideimide resin with a weight ratio of 30 wt%, and a resin mainly composed of silicone. A resin may be applied.
  • the first insulating resin has been described as an epoxy mold resin, but the effect of including the second insulating resin in the power semiconductor device in any case of a transfer mold resin or a potting resin mainly composed of an epoxy resin. There is.
  • the material of the ceramic substrate the case where the inorganic powder material such as aluminum nitride and silicon nitride is produced by sintering has been described, but the case where the ceramic substrate is produced using aluminum oxide also includes the above-mentioned second insulation in the power semiconductor device. There is an effect when a resin is provided.
  • the power semiconductor device includes the second insulating resin.
  • the power semiconductor device to a wide gap device, SiC (Silicon Carbide, Silicon Carbide) or GaN (gallium Nitride, GaN) semiconductor devices using such and Ga 2 O 3 (gallium oxide, gallium oxide) But it has the same effect.
  • a power conversion device including the power semiconductor device of the present invention described above can be configured. At this time, high reliability can be secured in the factor resulting from the power semiconductor device as the power conversion device.

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Abstract

This power semiconductor device is provided with: a power semiconductor element (11); at least one ceramic insulating circuit board (23A) wherein a circuit electrode (3A) is formed on a ceramic substrate (2A); a first insulating resin (16) that seals the power semiconductor element (11) and the circuit electrode (3A) of the ceramic substrate (2A), in a state wherein at least one electrode surface of the power semiconductor element (11) and the circuit electrode (3A) of the ceramic insulating circuit board (23A) are electrically connected to each other; and a second insulating resin (17A), which is provided at least on a part between the ceramic substrate board (2A) and the first insulating resin (16), and which has higher bonding strength to a ceramic of the ceramic substrate (2A) than the first insulating resin (16).

Description

パワー半導体装置および電力変換装置Power semiconductor device and power conversion device
　本発明は、インバータ装置等の電力変換装置に使用されるパワー半導体装置等に関する。 The present invention relates to a power semiconductor device used for a power conversion device such as an inverter device.
　近年、地球規模での環境汚染問題や資源問題がクローズアップされており、資源の有効活用、省エネルギー化の推進、地球温暖化ガスの排出抑制が重要なテーマとなっている。
　そのため、電力を利用する分野においては、インバータ装置を代表とする電力変換装置が、各種家電製品をはじめ、産業機器、鉄道、ハイブリッド自動車（ＨＥＶ）等の自動車、電力、社会インフラ関連機器に幅広く応用展開され、電力変換装置の需要は堅調な拡大をみせている。
　また、東日本大震災による脱原子力発電の国内世論を受けて、風力発電等の再生可能エネルギー分野における電力変換装置の急速な拡大が見込まれている。 In recent years, environmental pollution problems and resource problems on a global scale have been highlighted, and effective utilization of resources, promotion of energy saving, and suppression of emission of global warming gas have become important themes.
Therefore, in the field of using electric power, power converters represented by inverter devices are widely applied to various home appliances, automobiles such as industrial equipment, railways, and hybrid vehicles (HEV), electric power, and social infrastructure equipment. As a result, the demand for power converters is growing steadily.
In addition, in response to the domestic public opinion of denuclear power generation caused by the Great East Japan Earthquake, rapid expansion of power converters in the field of renewable energy such as wind power generation is expected.
　これら電力変換装置におけるニーズとしては、低コスト化とともに、設置面積の小スペース化、高信頼化が挙げられる。電力変換装置は、ＩＧＢＴ（Insulated Gate Bipolar Transistor）等のパワー半導体素子を内蔵したパワー半導体装置（パワーモジュール）の他、制御回路、バスバー（bus bar）、コイル、コンデンサ等の数多く部品から構成されている。
　前記の電力変換装置の低コスト化、小型化、高信頼化には、電力変換装置の主構成部品であるパワー半導体装置の小型化、高信頼化の技術が重要である。
　従来から使用されているパワー半導体装置においては、酸化アルミニウム（Ａｌ２Ｏ３）、窒化アルミニウム（ＡｌＮ）、窒化珪素（ＳｉＮ）等の材料を焼結してできたセラミック基板（セラミック絶縁基板）の両面に、ろう材を介して銅箔等の導体板を貼り付ける。そして、この導体板をエッチングすることにより回路電極と裏面電極を形成し、回路電極付きのセラミック基板を得る。 The needs for these power conversion devices include a reduction in cost, a reduction in installation area, and high reliability. The power conversion device is composed of a power semiconductor device (power module) incorporating a power semiconductor element such as an IGBT (Insulated Gate Bipolar Transistor), as well as a number of components such as a control circuit, a bus bar, a coil, and a capacitor. Yes.
In order to reduce the cost, size, and reliability of the power conversion device, a technology for reducing the size and reliability of the power semiconductor device that is the main component of the power conversion device is important.
In the power semiconductor device which has been used conventionally, aluminum oxide (Al 2 O 3), aluminum nitride (AlN), a ceramic substrate Deki by sintering a material such as silicon nitride (SiN) (ceramic insulating substrate) A conductive plate such as a copper foil is pasted on both sides via a brazing material. Then, the conductive plate is etched to form a circuit electrode and a back electrode, and a ceramic substrate with a circuit electrode is obtained.
　そして、前記のセラミック基板の回路電極上に、はんだ（半田）ペーストを塗布し、パワー半導体素子を載せ、リフロー炉を通してリフローすることにより、回路電極とパワー半導体素子を接合する。
　そして、パワー半導体素子の電極とセラミック基板の回路電極との間をアルミ細線等でワイヤー接続し、その後、放熱金属ベース板とセラミック絶縁基板の裏面電極とを半田等により接合する。
　そして、セラミック基板の回路電極と金属端子を接合、放熱金属ベースの周囲に樹脂ケースを配置させ、最後にシリコーンゲルでパワー半導体素子を絶縁封止してパワー半導体装置が完成する。 And a solder (solder) paste is apply | coated on the circuit electrode of the said ceramic substrate, a power semiconductor element is mounted, and a circuit electrode and a power semiconductor element are joined by reflowing through a reflow furnace.
Then, a wire connection is made between the electrode of the power semiconductor element and the circuit electrode of the ceramic substrate with an aluminum thin wire or the like, and then the heat-dissipating metal base plate and the back electrode of the ceramic insulating substrate are joined by soldering or the like.
Then, the circuit electrode of the ceramic substrate and the metal terminal are joined, a resin case is disposed around the heat radiating metal base, and finally the power semiconductor element is insulated and sealed with silicone gel to complete the power semiconductor device.
　パワー半導体素子は、数アンペア～数百アンペアの電流をスイッチングする素子であり、素子の発熱が伴う。この素子発熱の放熱の良し悪しが装置の小型化と信頼性に大きく影響する。従来構造の多くのパワー半導体装置においては、パワー半導体素子の発熱を素子の片側の面から放熱していた。そのため放熱性能が低く、パワー半導体装置の小型化と信頼性に限界があった。
　このため、近年ではパワー半導体素子の両面に電極、絶縁板、放熱板を取り付け、パワー半導体素子で発生した熱を素子の両面から放熱する両面冷却構造のパワー半導体装置が開発されている。 A power semiconductor element is an element that switches a current of several amperes to several hundred amperes, and the element generates heat. The quality of the heat generated by the element heat greatly affects the downsizing and reliability of the device. In many power semiconductor devices having a conventional structure, heat generated by the power semiconductor element is dissipated from one surface of the element. Therefore, the heat dissipation performance is low, and there is a limit to the miniaturization and reliability of the power semiconductor device.
For this reason, in recent years, power semiconductor devices having a double-sided cooling structure in which electrodes, insulating plates, and heat sinks are attached to both surfaces of the power semiconductor element to dissipate heat generated in the power semiconductor element from both surfaces of the element have been developed.
　特許文献１には、パワー半導体素子の両面に一対の放熱板を備え、装置のほぼ全体を樹脂でモールドした半導体装置が、絶縁材を介して冷却器と接触している半導体装置の冷却構造の技術が開示されている。
　また、特許文献２には、半導体チップを挟むように設けられ、各挟む側の面に前記半導体チップの電極に接合するための電極パターンが配設された２枚の高熱伝導性絶縁基板を備えた半導体装置の技術が開示されている。
　また、特許文献３には、パワー半導体素子とその一方の面の側に設けられた第１の放熱板と、前記一方の面の反対側の面側に設けられた第２の放熱板と、前記第１と第２の放熱板にそれぞれ接するように冷媒を通流させる流路を備えたパワー半導体モジュールの技術が開示されている。 Patent Document 1 discloses a semiconductor device cooling structure in which a semiconductor device having a pair of heat sinks on both surfaces of a power semiconductor element and molded with resin almost entirely is in contact with a cooler via an insulating material. Technology is disclosed.
Further, Patent Document 2 includes two high thermal conductive insulating substrates which are provided so as to sandwich a semiconductor chip, and are provided with electrode patterns for bonding to the electrodes of the semiconductor chip on each sandwiching surface. The technology of the semiconductor device is disclosed.
Patent Document 3 discloses a power semiconductor element, a first heat radiating plate provided on one side of the power semiconductor element, a second heat radiating plate provided on a surface side opposite to the one surface, A technology of a power semiconductor module provided with a flow path through which a refrigerant flows so as to be in contact with the first and second heat radiating plates, respectively, is disclosed.
特許第４００７３０４号公報Japanese Patent No. 4007034 特許第４２８５４７０号公報Japanese Patent No. 4285470 特許第４５８６０８７号公報Japanese Patent No. 4586087
　しかしながら、後記する比較例の図６に示すパワー半導体素子の両面に一対の高熱伝導性のセラミック基板を備え、ほぼ全体を絶縁樹脂でモールドした半導体装置においては、セラミック基板のセラミック表面とエポキシモールド樹脂（第一絶縁樹脂）との接着強度が低いという問題点があった。
　また、このように接着強度が低いと、後記する比較例の図７に示すように、セラミック絶縁基板のセラミック表面とモールド樹脂との間で界面剥離を生じる可能性があった。
　また、このような界面剥離が発生した場合、セラミック基板の回路電極とセラミック基板のパワー半導体素子を搭載する側の反対側の面に形成してある裏面電極との間で電流のリーク不良となる可能性があった。 However, in a semiconductor device in which a pair of high thermal conductivity ceramic substrates are provided on both sides of the power semiconductor element shown in FIG. 6 of the comparative example to be described later and almost entirely molded with an insulating resin, the ceramic surface of the ceramic substrate and the epoxy mold resin There was a problem that the adhesive strength with (first insulating resin) was low.
In addition, when the adhesive strength is low as described above, there is a possibility that interface peeling occurs between the ceramic surface of the ceramic insulating substrate and the mold resin, as shown in FIG.
In addition, when such interface peeling occurs, a current leakage defect occurs between the circuit electrode of the ceramic substrate and the back electrode formed on the surface of the ceramic substrate opposite to the side on which the power semiconductor element is mounted. There was a possibility.
　また、パワー半導体素子に加わる電圧が高い場合には、界面剥離で空気の絶縁破壊、いわゆる部分放電（コロナ放電）を発生させ、絶縁部を劣化させるという可能性があった。
　なお、この界面剥離は、両面冷却構造のパワー半導体装置のみならず、片面冷却構造のパワー半導体装置においても、エポキシ樹脂のような弾性率の高い樹脂で封止する場合には、同様に生じる可能性があった。
　また、特許文献１－３においては、前記のような放熱に対する各種の対策はあるものの、セラミック基板とモールド樹脂との接着強度が低く、界面剥離や、リーク不良や、部分放電による絶縁部の劣化等の信頼性上の問題点が生ずる可能性があった。 In addition, when the voltage applied to the power semiconductor element is high, there is a possibility that the insulation is deteriorated by causing an insulation breakdown of the air, that is, a so-called partial discharge (corona discharge) due to interface peeling.
This interfacial delamination can occur not only in a power semiconductor device having a double-sided cooling structure but also in a power semiconductor device having a single-sided cooling structure when sealed with a resin having a high elastic modulus such as an epoxy resin. There was sex.
In Patent Documents 1-3, although there are various countermeasures against heat dissipation as described above, the adhesive strength between the ceramic substrate and the mold resin is low, interface peeling, leakage failure, and deterioration of the insulating portion due to partial discharge. There is a possibility that a problem of reliability such as the above will occur.
　そこで、本発明は、このような課題を解決するものであって、その目的とするところは、セラミック基板（セラミック絶縁基板）と絶縁樹脂との界面での剥離を防止し、高い信頼性を有する半導体装置、および電力変換装置を提供することにある。 Therefore, the present invention solves such a problem, and the object is to prevent peeling at the interface between the ceramic substrate (ceramic insulating substrate) and the insulating resin and to have high reliability. A semiconductor device and a power conversion device are provided.
　前記の課題を解決するために、本発明を以下のように構成した。
　すなわち、本発明のパワー半導体装置は、パワー半導体素子と、セラミック基板上に回路電極を形成した少なくとも１枚のセラミック絶縁回路基板と、前記パワー半導体素子の少なくとも一方の電極面と、前記セラミック絶縁回路基板の回路電極とを電気的に接合された状態にて、前記パワー半導体素子と前記セラミック基板の回路電極とを封止する第一絶縁樹脂と、前記セラミック基板と前記第一絶縁樹脂との間の少なくとも一部分に、前記セラミック基板のセラミックとの接着強度が前記第一絶縁樹脂よりも高い接着強度を有する第二絶縁樹脂と、を備えることを特徴とする。
　また、その他の手段は、発明を実施するための形態のなかで説明する。 In order to solve the above problems, the present invention is configured as follows.
That is, the power semiconductor device of the present invention includes a power semiconductor element, at least one ceramic insulating circuit board having a circuit electrode formed on a ceramic substrate, at least one electrode surface of the power semiconductor element, and the ceramic insulating circuit. A first insulating resin that seals the power semiconductor element and the circuit electrode of the ceramic substrate in a state where the circuit electrode of the substrate is electrically bonded, and between the ceramic substrate and the first insulating resin And a second insulating resin having an adhesive strength higher than that of the first insulating resin. The second insulating resin has an adhesive strength higher than that of the first insulating resin.
Other means will be described in the embodiment for carrying out the invention.
　本発明によれば、セラミック基板と絶縁樹脂との界面での剥離を防止し、高い信頼性を有する半導体装置、および電力変換装置を提供することができる。 According to the present invention, it is possible to provide a semiconductor device and a power conversion device that can prevent peeling at the interface between the ceramic substrate and the insulating resin and have high reliability.
本発明の第１実施形態に係るパワー半導体装置の断面構造を示す図である。It is a figure showing the section structure of the power semiconductor device concerning a 1st embodiment of the present invention. 本発明の第２実施形態に係るパワー半導体装置の断面構造を示す図である。It is a figure which shows the cross-section of the power semiconductor device which concerns on 2nd Embodiment of this invention. 本発明の第３実施形態に係るパワー半導体装置の断面構造を示す図である。It is a figure which shows the cross-section of the power semiconductor device which concerns on 3rd Embodiment of this invention. 本発明の第４実施形態に係るパワー半導体装置の断面構造を示す図である。It is a figure which shows the cross-section of the power semiconductor device which concerns on 4th Embodiment of this invention. 本発明の第１実施形態に係るパワー半導体装置の主な構成要素が配置された近傍を上面からみた概略の平面図である。1 is a schematic plan view of a vicinity of main components of a power semiconductor device according to a first embodiment of the present invention as viewed from above. 比較例のパワー半導体装置の断面構造を示す図である。It is a figure which shows the cross-section of the power semiconductor device of a comparative example. 図６の破線の領域を拡大して示す図である。It is a figure which expands and shows the area | region of the broken line of FIG. 比較例の符号Ｓの領域のセラミック基板と第一絶縁樹脂における電界の等電位線を示す図である。It is a figure which shows the equipotential line of the electric field in the ceramic substrate and 1st insulating resin of the area | region of the code | symbol S of a comparative example. 本発明の実施例１におけるセラミック基板と第二絶縁樹脂と第一絶縁樹脂における電界の等電位線を示す図である。It is a figure which shows the equipotential line of the electric field in the ceramic substrate in Example 1 of this invention, 2nd insulating resin, and 1st insulating resin. 本発明の実施例２におけるセラミック基板と第二絶縁樹脂と第一絶縁樹脂における電界の等電位線を示す図である。It is a figure which shows the equipotential line of the electric field in the ceramic substrate in Example 2 of this invention, 2nd insulating resin, and 1st insulating resin. 本発明の実施例３におけるセラミック基板と第二絶縁樹脂と第一絶縁樹脂における電界の等電位線を示す図である。It is a figure which shows the equipotential line of the electric field in the ceramic substrate in Example 3 of this invention, 2nd insulating resin, and 1st insulating resin. 本発明の実施例１、２、３と比較例について、セラミック基板とモールド樹脂とのせん断強度試験結果を示す図である。It is a figure which shows the shear strength test result of a ceramic substrate and mold resin about Examples 1, 2, and 3 and a comparative example of this invention. 本発明の実施例１、２、３と比較例に対し、温度サイクル試験を実施し、所定サイクル毎にパワー半導体装置の部分放電電圧を測定した結果を示す図である。It is a figure which shows the result of having implemented the temperature cycle test with respect to Example 1, 2, 3 and comparative example of this invention, and measuring the partial discharge voltage of the power semiconductor device for every predetermined cycle.
　以下に本願の発明を実施するための形態（以下、「実施形態」と称す）を、図面を参照して説明する。 Hereinafter, modes for carrying out the invention of the present application (hereinafter referred to as “embodiments”) will be described with reference to the drawings.
（第１実施形態）
　図１は、本発明の第１実施形態に係るパワー半導体装置１０の断面構造を示す図である。 (First embodiment)
FIG. 1 is a diagram showing a cross-sectional structure of a power semiconductor device 10 according to the first embodiment of the present invention.
＜パワー半導体装置の構成の概要＞
　まず、パワー半導体装置１０の構成の概要について説明する。
　図１において、セラミック基板２Ａと回路電極３Ａと裏面電極４Ａとを備えて第１のセラミック絶縁回路基板２３Ａが構成されている。同様に、セラミック基板２Ｂと回路電極３Ｂと裏面電極４Ｂとを備えて第２のセラミック絶縁回路基板２３Ｂが構成されている。
　また、放熱ベース板１９Ａと熱伝導部材１８Ａによって、前記の第１のセラミック絶縁回路基板２３Ａで発生する熱を放熱する構成となっている。
　同様に、放熱ベース板１９Ｂと熱伝導部材１８Ｂによって、前記の第２のセラミック絶縁回路基板２３Ｂで発生する熱を放熱する構成となっている。
　この放熱ベース板１９Ａ、１９Ｂと熱伝導部材１８Ａ、１８Ｂを有することによって、パワー半導体装置１０は、両面冷却構造を有する構造となっている。
　なお、図１に示されるように、第１のセラミック絶縁回路基板２３Ａと第２のセラミック絶縁回路基板２３Ｂは、回路電極３Ａと回路電極３Ｂの側を内側に向けて対向配置されている。 <Overview of power semiconductor device configuration>
First, the outline of the configuration of the power semiconductor device 10 will be described.
In FIG. 1, a ceramic substrate 2A, a circuit electrode 3A, and a back electrode 4A are provided to constitute a first ceramic insulating circuit substrate 23A. Similarly, the second ceramic insulating circuit board 23B is configured by including the ceramic substrate 2B, the circuit electrode 3B, and the back electrode 4B.
Further, the heat generated by the first ceramic insulated circuit board 23A is radiated by the heat radiating base plate 19A and the heat conducting member 18A.
Similarly, the heat radiating base plate 19B and the heat conducting member 18B are configured to radiate heat generated in the second ceramic insulated circuit board 23B.
By having the heat radiating base plates 19A and 19B and the heat conducting members 18A and 18B, the power semiconductor device 10 has a structure having a double-sided cooling structure.
As shown in FIG. 1, the first ceramic insulated circuit board 23A and the second ceramic insulated circuit board 23B are arranged to face each other with the circuit electrodes 3A and the circuit electrodes 3B facing inward.
　また、ＩＧＢＴ等で構成されているパワー半導体素子１１は、台座１４１や半田５１Ａ、５１Ｂ等を介して、前記の第１、第２のセラミック絶縁回路基板（２３Ａ、２３Ｂ）に接続されている。
　同様に、パワー半導体素子１２は、台座１４２や半田５２Ａ、５２Ｂ等を介して、前記の第１、第２のセラミック絶縁回路基板（２３Ａ、２３Ｂ）に接続されている。
　また、バスバー８Ａ、８Ｂ、８Ｇは、半田５３Ａ、５３Ｂやワイヤー６Ｇを介して、前記のパワー半導体素子１１や前記の第１、第２のセラミック絶縁回路基板（２３Ａ、２３Ｂ）に接続されている。
　なお、パワー半導体素子１１とパワー半導体素子１２は、半導体チップとしては、別チップである。 The power semiconductor element 11 made of IGBT or the like is connected to the first and second ceramic insulated circuit boards (23A and 23B) via a base 141 and solders 51A and 51B.
Similarly, the power semiconductor element 12 is connected to the first and second ceramic insulated circuit boards (23A, 23B) via a pedestal 142, solders 52A, 52B, and the like.
The bus bars 8A, 8B, and 8G are connected to the power semiconductor element 11 and the first and second ceramic insulating circuit boards (23A and 23B) via solders 53A and 53B and wires 6G. .
The power semiconductor element 11 and the power semiconductor element 12 are separate chips as semiconductor chips.
　また、第二絶縁樹脂１７Ａは、回路電極３Ａとセラミック基板２Ａ（セラミック絶縁回路基板２３Ａ）に接触して絶縁している。第二絶縁樹脂１７Ｂは、回路電極３Ａとセラミック基板２Ｂ（セラミック絶縁回路基板２３Ａ）に接触して絶縁している。
　また、第一絶縁樹脂１６は、第二絶縁樹脂１７Ａ、１７Ｂとセラミック絶縁回路基板２３Ａ、２３Ｂとパワー半導体素子１１、１２と台座１４１、１４２と半田５１Ａ、５１Ｂ、５２Ａ、５２Ｂ、５３Ａ、５３Ｂとを被覆して絶縁している。また、第一絶縁樹脂１６は、バスバー８Ａ、８Ｂ、８Ｇの一部を被覆して絶縁している。 The second insulating resin 17A is in contact with the circuit electrode 3A and the ceramic substrate 2A (ceramic insulating circuit substrate 23A) for insulation. The second insulating resin 17B is in contact with the circuit electrode 3A and the ceramic substrate 2B (ceramic insulating circuit substrate 23A) for insulation.
The first insulating resin 16 includes second insulating resins 17A and 17B, ceramic insulating circuit boards 23A and 23B, power semiconductor elements 11 and 12, pedestals 141 and 142, and solders 51A, 51B, 52A, 52B, 53A, and 53B. Is covered and insulated. The first insulating resin 16 covers and insulates part of the bus bars 8A, 8B, 8G.
　また、第１、第２のセラミック絶縁回路基板（２３Ａ、２３Ｂ）には、パワー半導体素子１１、１２以外にも、他の半導体チップ、ＩＣチップ、また抵抗、コンデンサ、コイル等の回路部品が搭載されてパワー半導体装置、または電力変換装置を構成することもある。ただし、周知であるので、それら他の回路部品を図示することは省略している。
　また、図１において、回路電極３Ａ、３Ｂは、単一の金属体のようにも見える表記をしているが、実際には、電気回路を構成するために互いに隔離された複数の回路電極で構成されていることがある。回路電極３Ａ、３Ｂがそれぞれ複数で構成されている場合でも、それらの複数の回路電極がセラミック絶縁回路基板（２３Ａ、２３Ｂ）の同一平面に形成されているため、図１ではあたかも連続体のように表記されている。 In addition to the power semiconductor elements 11 and 12, other semiconductor chips, IC chips, and circuit components such as resistors, capacitors, and coils are mounted on the first and second ceramic insulated circuit boards (23A and 23B). Thus, a power semiconductor device or a power conversion device may be configured. However, since these are well-known, illustration of these other circuit components is omitted.
In FIG. 1, the circuit electrodes 3A and 3B have a notation that looks like a single metal body. However, in actuality, the circuit electrodes 3A and 3B are a plurality of circuit electrodes separated from each other to form an electric circuit. May be configured. Even when a plurality of circuit electrodes 3A and 3B are respectively formed, the plurality of circuit electrodes are formed on the same plane of the ceramic insulating circuit boards (23A and 23B). It is written in.
＜パワー半導体装置の製作工程の概要＞
　次に、図１のパワー半導体装置１０の製作工程の概要について説明する。
　まず、窒化珪素（ＳｉＮ）からなるセラミック基板２Ａの一方の面に回路電極３Ａと、その反対側の面に放熱用の裏面電極４Ａを形成したセラミック絶縁回路基板２３Ａを用意する。同様に、窒化珪素（ＳｉＮ）からなるセラミック基板２Ｂの一方の面に回路電極３Ｂと、その反対側の面に放熱用の裏面電極４Ｂを形成したセラミック絶縁回路基板２３Ｂを用意する。つまり、前記の回路電極（３Ａ、３Ｂ）と裏面電極（４Ａ、４Ｂ）を形成したセラミック絶縁回路基板（２３Ａ、２３Ｂ）を２枚準備する。
　前記の２枚のセラミック絶縁回路基板（２３Ａ、２３Ｂ）の回路電極（３Ａ、３Ｂ）の周囲からセラミック絶縁回路基板（２３Ａ、２３Ｂ）の端部にかけるセラミック絶縁回路基板（２３Ａ、２３Ｂ）の表面全体にポリアミドイミドを主体とする樹脂を塗布する。そして、所定の温度、時間で前記の樹脂を硬化させ、セラミック絶縁回路基板（２３Ａ、２３Ｂ）上に第二絶縁樹脂（１７Ａ、１７Ｂ）を形成する。 <Outline of manufacturing process of power semiconductor device>
Next, the outline of the manufacturing process of the power semiconductor device 10 of FIG. 1 will be described.
First, a ceramic insulated circuit board 23A is prepared in which a circuit electrode 3A is formed on one surface of a ceramic substrate 2A made of silicon nitride (SiN), and a back electrode 4A for heat dissipation is formed on the opposite surface. Similarly, a ceramic insulated circuit board 23B is prepared in which a circuit electrode 3B is formed on one surface of a ceramic substrate 2B made of silicon nitride (SiN), and a back electrode 4B for heat dissipation is formed on the opposite surface. That is, two ceramic insulating circuit boards (23A, 23B) on which the circuit electrodes (3A, 3B) and the back electrodes (4A, 4B) are formed are prepared.
Surfaces of the ceramic insulating circuit boards (23A, 23B) extending from the periphery of the circuit electrodes (3A, 3B) of the two ceramic insulating circuit boards (23A, 23B) to the ends of the ceramic insulating circuit boards (23A, 23B). A resin mainly composed of polyamideimide is applied to the whole. Then, the resin is cured at a predetermined temperature and time to form the second insulating resin (17A, 17B) on the ceramic insulating circuit boards (23A, 23B).
　そして、１枚目の下側に位置するセラミック絶縁回路基板２３Ａの回路電極３Ａの所定の位置に半田５１Ａ、５２Ａ、５３Ａを形成する。そして、その半田（５１Ａ、５２Ａ、５３Ａ等）の上に、コレクタバスバー８Ａと制御端子のバスバー８Ｇ、さらにパワー半導体素子１１をコレクタ電極（不図示）がそれぞれ回路電極３Ａの該当する位置に重ね合わせる。（なお、制御端子のバスバー８Ｇの表記に関する実際の構成については、後記する。）
　そして、リフロー炉（不図示）を通すリフローの工程により、１枚目のセラミック絶縁回路基板２３Ａとパワー半導体素子１１、コレクタバスバー８Ａ、制御端子のバスバー８Ｇを接合する。
　そして、ゲート端子（不図示）と制御端子のバスバー８Ｇ間をアルミ細線のワイヤー６Ｇで接続する。 Then, solders 51A, 52A, and 53A are formed at predetermined positions of the circuit electrode 3A of the ceramic insulating circuit board 23A located on the lower side of the first sheet. Then, on the solder (51A, 52A, 53A, etc.), the collector bus bar 8A, the control terminal bus bar 8G, and the power semiconductor element 11 are superimposed on the corresponding positions of the circuit electrode 3A, respectively. . (The actual configuration related to the notation of the control terminal bus bar 8G will be described later.)
Then, by a reflow process through a reflow furnace (not shown), the first ceramic insulating circuit board 23A, the power semiconductor element 11, the collector bus bar 8A, and the control terminal bus bar 8G are joined.
The gate terminal (not shown) and the control terminal bus bar 8G are connected by an aluminum thin wire 6G.
　その後、もう１枚のセラミック絶縁回路基板２３Ｂの所定の位置に半田（５１Ｂ、５２Ｂ、５３Ｂ等）を形成し、エミッタバスバー８Ｂと台座１４１を載せ、リフロー炉を通すリフローの工程によりそれらを接合する。
　そして、台座１４１、１４２の上に半田５１Ｂ、５２Ｂ、５１Ｃ、５２Ｃを形成し、セラミック絶縁回路基板２３Ｂの回路電極３Ｂが向き合う形でパワー半導体素子１１のエミッタ電極（不図示）と台座１４１とが一致するように位置合わせし、リフロー炉を通して接合する。 Thereafter, solder (51B, 52B, 53B, etc.) is formed at a predetermined position of the other ceramic insulated circuit board 23B, the emitter bus bar 8B and the base 141 are placed, and they are joined by a reflow process through a reflow furnace. .
Then, solders 51B, 52B, 51C, and 52C are formed on the bases 141 and 142, and the emitter electrode (not shown) of the power semiconductor element 11 and the base 141 are formed so that the circuit electrodes 3B of the ceramic insulating circuit board 23B face each other. Align to match and join through reflow oven.
　そして、それら接合された回路部品をトランスファーモールドの金型（不図示）に配置し、エポキシモールド樹脂からなるモールド材を注入し、所定の温度、圧力を所定の時間加える。この工程により、エポキシモールド樹脂が熱硬化して、２枚のセラミック絶縁回路基板２３Ａ、２３Ｂの間にあるパワー半導体素子全体が絶縁封止されるエポキシモールド樹脂の第一絶縁樹脂１６を形成する。
　その後、２枚のセラミック絶縁回路基板２３Ａ、２３Ｂの裏面電極４Ａ、４Ｂと放熱ベース板１９Ａ、１９Ｂを熱伝導部材１８Ａ、１８Ｂを介して接合し、パワー半導体装置１０を完成させる。なお、完成したパワー半導体装置１０の第一絶縁樹脂１６の比誘電率は４.０、第二絶縁樹脂１７Ａ、１７Ｂの比誘電率は４．０であった。
　この第一絶縁樹脂１６の比誘電率と第二絶縁樹脂１７Ａ、１７Ｂの比誘電率との相違の影響、効果については、後記する。 Then, these joined circuit components are placed in a transfer mold (not shown), a molding material made of epoxy mold resin is injected, and a predetermined temperature and pressure are applied for a predetermined time. Through this process, the epoxy mold resin is thermally cured to form the first insulating resin 16 of the epoxy mold resin in which the entire power semiconductor element between the two ceramic insulated circuit boards 23A and 23B is insulated and sealed.
Thereafter, the back electrodes 4A, 4B of the two ceramic insulated circuit boards 23A, 23B and the heat radiating base plates 19A, 19B are joined via the heat conducting members 18A, 18B, thereby completing the power semiconductor device 10. In the completed power semiconductor device 10, the first dielectric resin 16 had a relative dielectric constant of 4.0, and the second dielectric resins 17A and 17B had a dielectric constant of 4.0.
The influence and effect of the difference between the relative dielectric constant of the first insulating resin 16 and the relative dielectric constant of the second insulating resins 17A and 17B will be described later.
＜制御端子の構造の補足＞
　なお、図１における制御端子のバスバー８Ｇとコレクタのバスバー（コレクタバスバー）８Ａとの構造上の関係について補足説明する。
　図５は、本発明の第１実施形態に係るパワー半導体装置１０の主な構成要素（パワー半導体素子１１、セラミック絶縁回路基板２３Ａ、放熱ベース板１９Ａ、回路電極３Ａ、制御端子のバスバー８Ｇ、コレクタバスバー８Ａ等）が配置された近傍を上面からみた概略の平面図である。（図４については後記する。）
　なお、図５は、制御端子のバスバー（制御端子）８Ｇとコレクタバスバー８Ａとの配置の関連を示す図であるので、前記以外の構成要素や図１と対応する正確な配置の図示を省略している。
　図５におけるコレクタバスバー８Ａと制御端子のバスバー８Ｇは、セラミック絶縁回路基板２３Ａを平面とみて、この平面からの高さが、同一の高さに位置している。 <Supplement of control terminal structure>
A supplementary description will be given of the structural relationship between the control terminal bus bar 8G and the collector bus bar (collector bus bar) 8A in FIG.
FIG. 5 shows main components of the power semiconductor device 10 according to the first embodiment of the present invention (power semiconductor element 11, ceramic insulating circuit board 23A, heat radiation base plate 19A, circuit electrode 3A, control terminal bus bar 8G, collector. It is the schematic top view which looked at the neighborhood where bus bar 8A etc. are arranged from the upper surface. (FIG. 4 will be described later.)
5 is a diagram showing the relationship between the arrangement of the control terminal bus bar (control terminal) 8G and the collector bus bar 8A, and therefore, the illustration of the components other than those described above and the exact arrangement corresponding to FIG. 1 is omitted. ing.
The collector bus bar 8A and the control terminal bus bar 8G in FIG. 5 are located at the same height when viewed from the plane of the ceramic insulated circuit board 23A.
　このコレクタバスバー８Ａと制御端子のバスバー８Ｇが同一の高さにあることを、図１の断面図において、そのまま表記すると、制御端子のバスバー８Ｇは、コレクタバスバー８Ａに隠れてしまい、その配置状況を示せない。
　そのため、図１においては、制御端子のバスバー８Ｇが存在していることを示すために、便宜的に、制御端子のバスバー８Ｇをコレクタバスバー８Ａよりも高い位置に表記している。しかし前記したように、制御端子のバスバー８Ｇはコレクタバスバー８Ａと同じ高さで、半田（５１Ａ、５２Ａ、５３Ａ等）による接合工程等が行われる。 If the collector bus bar 8A and the control terminal bus bar 8G are at the same height in the sectional view of FIG. 1, the control terminal bus bar 8G is hidden by the collector bus bar 8A and I can't show it.
Therefore, in FIG. 1, in order to show that the control terminal bus bar 8G exists, for convenience, the control terminal bus bar 8G is shown at a position higher than the collector bus bar 8A. However, as described above, the control terminal bus bar 8G is the same height as the collector bus bar 8A, and a joining process or the like by solder (51A, 52A, 53A, etc.) is performed.
（第２実施形態）
　図２は、本発明の第２実施形態に係るパワー半導体装置１０の断面構造を示す図である。
　図２において、図１のパワー半導体装置１０の断面構造において異なるのは、第二絶縁樹脂１７Ａ、１７Ｂの容積であり、またセラミック絶縁回路基板２３Ａ、２３Ｂとの接触面積である。図２における第二絶縁樹脂１７Ａ、１７Ｂの容積、およびセラミック絶縁回路基板２３Ａ、２３Ｂとの接触面積は、ともに図１における第二絶縁樹脂１７Ａ、１７Ｂに比較して小さくなっている。 (Second Embodiment)
FIG. 2 is a diagram showing a cross-sectional structure of a power semiconductor device 10 according to the second embodiment of the present invention.
2, the difference in the cross-sectional structure of the power semiconductor device 10 in FIG. 1 is the volume of the second insulating resins 17A and 17B and the contact area with the ceramic insulating circuit boards 23A and 23B. The volume of the second insulating resins 17A and 17B in FIG. 2 and the contact area with the ceramic insulating circuit boards 23A and 23B are both smaller than those of the second insulating resins 17A and 17B in FIG.
　また、図２のパワー半導体装置１０において、図１と材質の観点から異なるのは、
 <1> 第二絶縁樹脂１７Ａ、１７Ｂが、ポリアミドイミド樹脂を主体とし、ポリアミドイミド樹脂中に平均粒径５μｍのアルミナフィラーを重量比３０ｗｔ％で混合した樹脂を基に所定の温度、圧力、時間で硬化させて形成されたものである。
 <2> セラミック基板２Ａ、２Ｂが窒化アルミニウム（ＡｌＮ）からなることである。なお、第１実施形態のセラミック基板２Ａ、２Ｂは、前記したように窒化珪素（ＳｉＮ）からなる。
　これらの第二絶縁樹脂１７Ａ、１７Ｂの形状および材質と、セラミック基板２Ａ、２Ｂの材質以外は、図１と図２のパワー半導体装置１０において、同一の形状、材質、製造工程であるので重複する説明は省略する。
　なお、図２の第２実施形態において、完成したパワー半導体装置１０の第一絶縁樹脂１６の比誘電率は４．０、第二絶縁樹脂１７Ａ、１７Ｂの比誘電率は６．２であった。
　図２の第２実施形態が図１の第１実施形態と異なる特性、特徴については後記する。 Further, the power semiconductor device 10 of FIG. 2 differs from FIG.
<1> Predetermined temperature, pressure, and time based on a resin in which the second insulating resins 17A and 17B are mainly composed of a polyamideimide resin and an alumina filler having an average particle size of 5 μm is mixed in the polyamideimide resin at a weight ratio of 30 wt%. It is formed by curing with.
<2> The ceramic substrates 2A and 2B are made of aluminum nitride (AlN). The ceramic substrates 2A and 2B of the first embodiment are made of silicon nitride (SiN) as described above.
Except for the shape and material of the second insulating resins 17A and 17B and the material of the ceramic substrates 2A and 2B, the power semiconductor device 10 of FIGS. Description is omitted.
In the second embodiment of FIG. 2, the relative dielectric constant of the first insulating resin 16 of the completed power semiconductor device 10 is 4.0, and the relative dielectric constant of the second insulating resins 17A and 17B is 6.2. .
The characteristics and features of the second embodiment of FIG. 2 different from those of the first embodiment of FIG. 1 will be described later.
（第３実施形態）
　図３は、本発明の第３実施形態に係るパワー半導体装置１０の断面構造を示す図である。
　図３において、図１のパワー半導体装置１０の断面構造と異なるのは、第二絶縁樹脂１７Ａ、１７Ｂの配置である。
　すなわち、セラミック絶縁回路基板２３Ａ、２３Ｂの回路電極３Ａ、３Ｂの周囲端部から約１ｍｍ離れた部分からセラミック基板２Ａ、２Ｂ（セラミック絶縁回路基板２３Ａ、２３Ｂ）の端部にかけるセラミック基板２Ａ、２Ｂの表面にそれぞれ第二絶縁樹脂１７Ａ、１７Ｂを形成している。 (Third embodiment)
FIG. 3 is a diagram showing a cross-sectional structure of a power semiconductor device 10 according to the third embodiment of the present invention.
In FIG. 3, what is different from the cross-sectional structure of the power semiconductor device 10 of FIG. 1 is the arrangement of the second insulating resins 17A and 17B.
That is, the ceramic substrates 2A and 2B applied to the end portions of the ceramic substrates 2A and 2B (ceramic insulating circuit substrates 23A and 23B) from a portion about 1 mm away from the peripheral ends of the circuit electrodes 3A and 3B of the ceramic insulating circuit substrates 23A and 23B. Second insulating resins 17A and 17B are respectively formed on the surfaces of
　また、図３のパワー半導体装置１０において、図１のパワー半導体装置１０と材質の観点から異なるのは、第二絶縁樹脂１７Ａ、１７Ｂが、シリコーンを主体とする樹脂を基に所定の温度、圧力、時間で硬化させて形成されたものである。
　これらの第二絶縁樹脂１７Ａ、１７Ｂの形状および材質以外は、図１と図３のパワー半導体装置１０において、同一の形状、材質、製造工程であるので重複する説明は省略する。
　なお、図３の第２実施形態において、完成したパワー半導体装置１０の第一絶縁樹脂１６の比誘電率は４．０、第二絶縁樹脂１７Ａ、１７Ｂの比誘電率は２．８であった。
　図３の第３実施形態が図１、図２の第１、第２実施形態と異なる特性、特徴については後記する。 3 differs from the power semiconductor device 10 of FIG. 1 in terms of material in that the second insulating resins 17A and 17B have a predetermined temperature and pressure based on a resin mainly composed of silicone. It is formed by curing with time.
Except for the shapes and materials of the second insulating resins 17A and 17B, the power semiconductor device 10 of FIGS. 1 and 3 has the same shape, material, and manufacturing process, and therefore redundant description is omitted.
In the second embodiment shown in FIG. 3, the first dielectric resin 16 of the completed power semiconductor device 10 has a relative dielectric constant of 4.0, and the second dielectric resins 17A and 17B have a dielectric constant of 2.8. .
The characteristics and features of the third embodiment of FIG. 3 different from those of the first and second embodiments of FIGS. 1 and 2 will be described later.
＜比較例について＞
　次に、パワー半導体装置の比較例について説明する。この比較例のパワー半導体装置と、本願の第１、第２、第３実施形態のパワー半導体装置とを比較することにより、本願の特徴を明確にする。
　図６は、比較例のパワー半導体装置２０の断面構造を示す図である。
　図６に示す比較例において、図１に示す本願の第１実施形態に係るパワー半導体装置１０と異なるのは、図１における第二絶縁樹脂１７Ａ、１７Ｂが図６に示す比較例においては、存在しないことである。
　その他の構成要素、材質、製造工程は同一である。そのため重複する説明は省略する。
　なお、比較例の完成したパワー半導体装置２０の絶縁樹脂（第一絶縁樹脂）の比誘電率は４．０であった。 <About Comparative Example>
Next, a comparative example of the power semiconductor device will be described. The characteristics of the present application will be clarified by comparing the power semiconductor device of this comparative example with the power semiconductor devices of the first, second, and third embodiments of the present application.
FIG. 6 is a diagram showing a cross-sectional structure of a power semiconductor device 20 of a comparative example.
6 differs from the power semiconductor device 10 according to the first embodiment of the present application shown in FIG. 1 in that the second insulating resins 17A and 17B in FIG. 1 are present in the comparative example shown in FIG. Is not to.
Other components, materials, and manufacturing processes are the same. Therefore, the overlapping description is omitted.
The relative dielectric constant of the insulating resin (first insulating resin) of the completed power semiconductor device 20 of the comparative example was 4.0.
《比較例の問題点》
　次に、この比較例の問題点について説明する。この比較例の構造においては、セラミック基板と絶縁樹脂間の剥離発生や絶縁耐圧の問題がある。これらの問題に関連して、セラミック基板と絶縁樹脂（モールド樹脂）との間のせん断強度試験と、信頼性試験としての温度サイクル試験とを実施した。これらについて順に説明する。 《Problems of comparative example》
Next, problems of this comparative example will be described. In the structure of this comparative example, there are problems of delamination between the ceramic substrate and the insulating resin and withstand voltage. In relation to these problems, a shear strength test between the ceramic substrate and the insulating resin (mold resin) and a temperature cycle test as a reliability test were performed. These will be described in order.
《セラミック基板と絶縁樹脂間の剥離発生について》
　まず、セラミック基板と絶縁樹脂間の剥離発生について説明する。
　図７は、図６の破線で示した符号Ｓの領域を拡大して示す図である。なお、回路電極３Ａと裏面電極４Ａの形状については、後記するように、図６よりも実際に近い状態で表記している。
　図７において、セラミック絶縁回路基板（２３Ａ）は、セラミック基板２Ａと回路電極３Ａと裏面電極４Ａとを備えて構成されている。
　熱伝導部材１８Ａと放熱ベース板１９Ａは、セラミック絶縁回路基板（２３Ａ）の裏面電極４Ａと接合されている。
　パワー半導体素子１２は、半田５２Ａと半田５２Ｃをそれぞれ介して、セラミック絶縁回路基板（２３Ａ）の回路電極３Ａ、および台座１４２とそれぞれ接合している。
　また、エポキシモールド樹脂からなる第一絶縁樹脂１６は、セラミック絶縁回路基板（２３Ａ）やパワー半導体素子１２を絶縁して封止している。
　なお、図７において、回路電極３Ａと裏面電極４Ａは端部において、斜線で示したように鋭角の形状になる。この鋭角の形状になるのは、回路電極３Ａと裏面電極４Ａが化学エッチングで形成する場合に、化学反応の性質によるものである。 <Occurrence of peeling between ceramic substrate and insulating resin>
First, the occurrence of peeling between the ceramic substrate and the insulating resin will be described.
FIG. 7 is an enlarged view of the area S indicated by a broken line in FIG. Note that the shapes of the circuit electrode 3A and the back electrode 4A are described in a state closer to the actual state than FIG. 6, as will be described later.
In FIG. 7, the ceramic insulated circuit board (23A) includes a ceramic substrate 2A, a circuit electrode 3A, and a back electrode 4A.
The heat conducting member 18A and the heat radiating base plate 19A are joined to the back electrode 4A of the ceramic insulated circuit board (23A).
The power semiconductor element 12 is joined to the circuit electrode 3A of the ceramic insulated circuit board (23A) and the pedestal 142 via the solder 52A and the solder 52C, respectively.
The first insulating resin 16 made of epoxy mold resin insulates and seals the ceramic insulated circuit board (23A) and the power semiconductor element 12.
In FIG. 7, the circuit electrode 3 </ b> A and the back electrode 4 </ b> A have acute angles at the ends as indicated by the hatched lines. This acute angle shape is due to the nature of the chemical reaction when the circuit electrode 3A and the back electrode 4A are formed by chemical etching.
　この図７に示した構造において、セラミック基板２Ａのセラミック表面と第一絶縁樹脂１６との接着強度が低くなると、セラミック基板２Ａのセラミック表面と第一絶縁樹脂１６（モールド樹脂、エポキシモールド樹脂）との間で界面剥離９９を生じる可能性がある。
　このような界面剥離９９が発生した場合、セラミック絶縁回路基板（２３Ａ：図６）の回路電極３Ａと反対側の面に形成してある裏面電極４Ａとの間で電流のリーク不良となる可能性がある。また、パワー半導体素子１２に加わる電圧が高い場合には、界面剥離で空気の絶縁破壊、いわゆる部分放電（コロナ放電）を発生させ、絶縁部（第一絶縁樹脂１６等）を劣化させるという可能性がある。 In the structure shown in FIG. 7, when the adhesive strength between the ceramic surface of the ceramic substrate 2A and the first insulating resin 16 decreases, the ceramic surface of the ceramic substrate 2A and the first insulating resin 16 (mold resin, epoxy mold resin) There is a possibility that interfacial debonding 99 occurs.
When such interface peeling 99 occurs, there is a possibility of current leakage failure with the back electrode 4A formed on the surface opposite to the circuit electrode 3A of the ceramic insulated circuit board (23A: FIG. 6). There is. In addition, when the voltage applied to the power semiconductor element 12 is high, there is a possibility that the insulation separation (the first insulating resin 16 or the like) may be deteriorated by causing an insulation breakdown of the air due to interface separation, so-called partial discharge (corona discharge). There is.
　なお、パワー半導体素子（１１、１２：図６）の両面に一対の高熱伝導性のセラミック基板（２Ａ、２Ｂ：図６）を備え、装置のほぼ全体を樹脂モールド（第一絶縁樹脂１６：図６）した半導体装置（２０：図６）においては、モールド樹脂の硬化収縮によって２枚のセラミック基板（２Ａ、２Ｂ：図６）の間に引っ張り応力が働くことも、この界面剥離（９９：図７）を生じやすくさせる理由である。
　また、図６および図７において、セラミック基板２Ａは、窒化珪素の無機粉末材料を焼結して形成したものであるが、窒化珪素の代わりに酸化アルミニウムや窒化アルミニウムを用いても同様に界面剥離９９を生じる可能性がある。 The power semiconductor element (11, 12: FIG. 6) is provided with a pair of high thermal conductivity ceramic substrates (2A, 2B: FIG. 6) on both sides, and almost the entire apparatus is resin molded (first insulating resin 16: FIG. 6) In the semiconductor device (20: FIG. 6), tensile stress acts between the two ceramic substrates (2A, 2B: FIG. 6) due to curing shrinkage of the mold resin. This is the reason why 7) is likely to occur.
6 and 7, the ceramic substrate 2A is formed by sintering an inorganic powder material of silicon nitride. Even if aluminum oxide or aluminum nitride is used instead of silicon nitride, the interfacial peeling is performed in the same manner. 99 may occur.
《セラミック基板と絶縁樹脂間の電界強度について》
　次に、セラミック絶縁回路基板２３Ａのセラミック基板２Ａと回路電極３Ａに接触する第一絶縁樹脂１６または第二絶縁樹脂１７Ａとの電界強度（もしくは絶縁耐圧）の関係について説明する。
　これら電界強度が第１、第２、第３実施形態および比較例において、どのような相違があるかを、図８Ａ～図８Ｄを参照して次に説明する。 《Electric field strength between ceramic substrate and insulating resin》
Next, the relationship of the electric field strength (or withstand voltage) between the ceramic substrate 2A of the ceramic insulated circuit substrate 23A and the first insulating resin 16 or the second insulating resin 17A in contact with the circuit electrode 3A will be described.
Next, how these electric field intensities differ in the first, second and third embodiments and the comparative example will be described with reference to FIGS. 8A to 8D.
<比較例の最大電界強度>
　図８Ａは、前記の比較例の符号Ｓの領域（図６、図７）のセラミック基板２Ａと第一絶縁樹脂１６における電界の等電位線を示す図である。
　図８Ａにおいて、細線による複数の曲線群で示したのが、電界の等電位線である。
　図８Ａにおいては、回路電極３Ａの端部とセラミック基板２Ａと第一絶縁樹脂１６とが一点で接触する近傍において、電界が最も集中（等電位線の間隔が狭い）し、最大の電界強度となる。また、絶縁破壊や部分放電は、この最大の電界強度を示す付近で起こる可能性が最も高い。 <Maximum electric field strength of comparative example>
FIG. 8A is a diagram showing the equipotential lines of the electric field in the ceramic substrate 2A and the first insulating resin 16 in the region S (FIGS. 6 and 7) of the comparative example.
In FIG. 8A, an equipotential line of an electric field is shown by a plurality of curve groups of thin lines.
In FIG. 8A, in the vicinity where the end of the circuit electrode 3A, the ceramic substrate 2A, and the first insulating resin 16 are in contact with each other at one point, the electric field is most concentrated (the interval between equipotential lines is narrow). Become. In addition, dielectric breakdown and partial discharge are most likely to occur in the vicinity of the maximum electric field strength.
　なお、図８Ａに示した比較例の電界の特性は、セラミック基板２ＡにＳｉＮ基板、第一絶縁樹脂１６に比誘電率４．０のエポキシモールド樹脂を用いた場合の特性である。
　この比較例を基準として、次に説明する実施例１、２、３の各前記の特性と比較するために、比較例における最大電界強度を基準とする。図８Ａでは、比較例を比較の基準としているので、「最大電界強度比１」と記載している。
　なお、図８Ａにおけるその他の部分、構造については、説明が重複するので省略する。 The electric field characteristics of the comparative example shown in FIG. 8A are characteristics when an SiN substrate is used for the ceramic substrate 2A and an epoxy mold resin having a relative dielectric constant of 4.0 is used for the first insulating resin 16.
Based on this comparative example, the maximum electric field strength in the comparative example is used as a reference in order to compare with the characteristics of Examples 1, 2, and 3 described below. In FIG. 8A, since the comparative example is used as a reference for comparison, “maximum electric field strength ratio 1” is described.
In addition, about the other part and structure in FIG. 8A, since description overlaps, it abbreviate | omits.
<実施例１の最大電界強度>
　図８Ｂは、本発明の第１実施形態による実施例１におけるセラミック基板２Ａと第二絶縁樹脂１７Ａと第一絶縁樹脂１６における電界の等電位線を示す図である。なお、等電位線の形態、特性については、絶縁樹脂の材質によって異なるので図８Ｂは、実施例１として表記する。
　図８Ｂに示した構造が、図８Ａに示した構造に対して異なるのは、第二絶縁樹脂１７Ａを備えていることである。第二絶縁樹脂１７Ａは、セラミック基板２Ａの表面が回路電極３Ａに覆われていない箇所に備えられている。また、図８Ｂは第１実施形態を記載した図１に対応している。
　第二絶縁樹脂１７Ａは、第一絶縁樹脂１６よりもセラミック基板２Ａへの接着強度が高い材質を用いている。ただし、第二絶縁樹脂１７Ａの比誘電率は４．０であり、第一絶縁樹脂１６の比誘電率と同じものを用いている。 <Maximum electric field strength of Example 1>
FIG. 8B is a diagram showing electric field equipotential lines in the ceramic substrate 2A, the second insulating resin 17A, and the first insulating resin 16 in Example 1 according to the first embodiment of the present invention. Since the form and characteristics of the equipotential lines differ depending on the material of the insulating resin, FIG.
The structure shown in FIG. 8B is different from the structure shown in FIG. 8A in that the second insulating resin 17A is provided. The second insulating resin 17A is provided at a location where the surface of the ceramic substrate 2A is not covered with the circuit electrode 3A. FIG. 8B corresponds to FIG. 1 describing the first embodiment.
The second insulating resin 17A is made of a material having higher adhesive strength to the ceramic substrate 2A than the first insulating resin 16 is. However, the relative dielectric constant of the second insulating resin 17A is 4.0, and the same dielectric constant as that of the first insulating resin 16 is used.
　そのため、図８Ｂのセラミック基板２Ａと第二絶縁樹脂１７Ａと第一絶縁樹脂１６における電界の等電位線の形態、特性は、比較例としての図８Ａと概ね同一の結果が得られている。
　なお、図８Ｂにおいては、回路電極３Ａの端部とセラミック基板２Ａと第二絶縁樹脂１７Ａとが一点で接触する近傍において、電界が最も集中（等電位線の間隔が狭い）し、最大電界強度比１が得られている。
　また、その他の重複する説明は省略する。 Therefore, the form and characteristics of the equipotential lines of the electric field in the ceramic substrate 2A, the second insulating resin 17A, and the first insulating resin 16 in FIG. 8B are almost the same as those in FIG. 8A as the comparative example.
In FIG. 8B, in the vicinity where the end of the circuit electrode 3A, the ceramic substrate 2A, and the second insulating resin 17A contact at one point, the electric field is most concentrated (the equipotential lines are narrow), and the maximum electric field strength is obtained. A ratio of 1 is obtained.
Other overlapping explanations are omitted.
<実施例２の最大電界強度>
　図８Ｃは、本発明の第２実施形態による実施例２におけるセラミック基板２Ａと第二絶縁樹脂１７Ａと第一絶縁樹脂１６における電界の等電位線を示す図である。なお、等電位線の形態、特性については、絶縁樹脂の材質によって異なるので図８Ｃは、実施例２として表記する。
　図８Ｃに示した構造が、図８Ｂに示した構造に対して異なるのは、第二絶縁樹脂１７Ａのセラミック基板２Ａと接する方向における長さが短くなったことである。なお、図８Ｃは第２実施形態を記載した図２に対応している。
　また、図８Ｃにおいて、セラミック基板２ＡにＡｌＮ基板が用いられている。
　また、第二絶縁樹脂１７Ａは、ポリアミドイミド樹脂を主体とし、ポリアミドイミド樹脂中に平均粒径５μｍのアルミナフィラーを重量比３０ｗｔ％で混合した樹脂を基に所定の温度、圧力、時間で硬化させて形成されたものである。 <Maximum electric field strength of Example 2>
FIG. 8C is a diagram showing electric field equipotential lines in the ceramic substrate 2A, the second insulating resin 17A, and the first insulating resin 16 in Example 2 according to the second embodiment of the present invention. Note that the form and characteristics of the equipotential lines differ depending on the material of the insulating resin, and therefore FIG.
The structure shown in FIG. 8C differs from the structure shown in FIG. 8B in that the length of the second insulating resin 17A in the direction in contact with the ceramic substrate 2A is shortened. 8C corresponds to FIG. 2 describing the second embodiment.
In FIG. 8C, an AlN substrate is used as the ceramic substrate 2A.
The second insulating resin 17A is mainly composed of a polyamideimide resin, and is cured at a predetermined temperature, pressure, and time based on a resin in which an alumina filler having an average particle diameter of 5 μm is mixed in a polyamideimide resin at a weight ratio of 30 wt%. Is formed.
　このとき、第一絶縁樹脂１６の比誘電率が４．０に対して、第二絶縁樹脂１７Ａの比誘電率は６．２であった。
　図８Ｃにおいて、回路電極３Ａの端部とセラミック基板２Ａと第二絶縁樹脂１７Ａとが一点で接触する近傍において、電界が最も集中（等電位線の間隔が狭い）し、最大電界強度比０．８８が得られている。
　すなわち、図８Ｃのような構造においては、第二絶縁樹脂１７Ａの比誘電率（ε２＝６．２）が第一絶縁樹脂１６の比誘電率（ε１＝４．０）よりも高い場合には、回路電極３Ａの端部とセラミック基板２Ａと第二絶縁樹脂１７Ａとが一点で接触する近傍の電界強度は、緩和される。
　また、その他の重複する説明は省略する。 At this time, the relative dielectric constant of the first insulating resin 16 was 4.0, whereas the relative dielectric constant of the second insulating resin 17A was 6.2.
In FIG. 8C, in the vicinity where the end of the circuit electrode 3A, the ceramic substrate 2A, and the second insulating resin 17A contact at one point, the electric field is most concentrated (the equipotential lines are narrow), and the maximum electric field strength ratio is 0. 88 is obtained.
That is, in the structure as shown in FIG. 8C, the relative dielectric constant (ε 2 = 6.2) of the second insulating resin 17A is higher than the relative dielectric constant (ε 1 = 4.0) of the first insulating resin 16. The electric field strength in the vicinity where the end of the circuit electrode 3A, the ceramic substrate 2A, and the second insulating resin 17A contact at one point is relaxed.
Other overlapping explanations are omitted.
<実施例３の最大電界強度>
　図８Ｄは、本発明の第３実施形態による実施例３におけるセラミック基板２Ａと第二絶縁樹脂１７Ａと第一絶縁樹脂１６における電界の等電位線を示す図である。なお、等電位線の形態、特性については、絶縁樹脂の材質によって異なるので図８Ｄは、実施例３として表記する。
　図８Ｄに示した構造が、図８Ｂに示した構造に対して異なるのは、第二絶縁樹脂１７Ａが、セラミック基板２Ａとのみ接触し、回路電極３Ａの端部からは離れていることである。また、図８Ｄは第３実施形態を記載した図３に対応している。
　また、図８Ｄにおいて、セラミック基板２ＡにＳｉＮ基板が用いられている。また、第二絶縁樹脂１７Ａが、シリコーンを主体とする樹脂を基に所定の温度、圧力、時間で硬化させて形成されたものである。
　このとき、第一絶縁樹脂１６の比誘電率が４．０に対して、第二絶縁樹脂１７Ａの比誘電率は２．８であった。 <Maximum electric field strength of Example 3>
FIG. 8D is a diagram showing electric field equipotential lines in the ceramic substrate 2A, the second insulating resin 17A, and the first insulating resin 16 in Example 3 according to the third embodiment of the present invention. Note that the form and characteristics of the equipotential lines differ depending on the material of the insulating resin, so FIG.
The structure shown in FIG. 8D is different from the structure shown in FIG. 8B in that the second insulating resin 17A is in contact only with the ceramic substrate 2A and away from the end of the circuit electrode 3A. . FIG. 8D corresponds to FIG. 3 describing the third embodiment.
In FIG. 8D, a SiN substrate is used for the ceramic substrate 2A. The second insulating resin 17A is formed by curing at a predetermined temperature, pressure, and time based on a resin mainly composed of silicone.
At this time, the relative dielectric constant of the first insulating resin 16 was 4.0, whereas the relative dielectric constant of the second insulating resin 17A was 2.8.
　図８Ｄにおいて、回路電極３Ａの端部とセラミック基板２Ａと第一絶縁樹脂１６とが一点で接触する近傍において、電界が最も集中し、最大電界強度比０．９９が得られている。
　すなわち、図８Ｄのような構造においては、第二絶縁樹脂１７Ａの比誘電率（ε２＝２．８）が第一絶縁樹脂１６の比誘電率（ε１＝４．０）よりも低い場合には、回路電極３Ａの端部とセラミック基板２Ａとが一点で接触する近傍の電界強度は、緩和される。 In FIG. 8D, the electric field is most concentrated near the end of the circuit electrode 3A, the ceramic substrate 2A, and the first insulating resin 16 at one point, and a maximum electric field strength ratio of 0.99 is obtained.
That is, in the structure as shown in FIG. 8D, the relative dielectric constant (ε 2 = 2.8) of the second insulating resin 17A is lower than the relative dielectric constant (ε 1 = 4.0) of the first insulating resin 16. First, the electric field strength in the vicinity where the end of the circuit electrode 3A and the ceramic substrate 2A are in contact at one point is relaxed.
　実施例２の図８Ｃと実施例３の図８Ｄとを比較すると、第二絶縁樹脂１７Ａを回路電極３Ａの端部に対して、何処に配置するかによって、最大電界強度への影響が異なることがわかる。
　つまり、図８Ｃのように、回路電極３Ａの端部とセラミック基板２Ａとの接点における電界が最も集中する箇所において、第二絶縁樹脂１７Ａを接触される場合には、（ε２＞ε１）の条件で電界の集中が緩和される。これに対して、第二絶縁樹脂１７Ａが離れている場合には、（ε１＞ε２）の条件で電界の集中が緩和される。 Comparing FIG. 8C of Example 2 and FIG. 8D of Example 3, the influence on the maximum electric field strength differs depending on where the second insulating resin 17A is arranged with respect to the end of the circuit electrode 3A. I understand.
That is, as shown in FIG. 8C, when the second insulating resin 17A is brought into contact at a place where the electric field at the contact point between the end of the circuit electrode 3A and the ceramic substrate 2A is most concentrated, (ε 2 > ε 1 ). The concentration of the electric field is relaxed under the conditions of On the other hand, when the second insulating resin 17A is separated, the concentration of the electric field is relaxed under the condition of (ε 1 > ε 2 ).
《セラミック基板とモールド絶縁樹脂とのせん断強度試験》
　本願の第１、第２、第３実施形態は、第二絶縁樹脂１７Ａ、１７Ｂを備えて、セラミック基板２Ａのセラミック表面との接着強度を高くすることを意図したものである。
　次に、本願の第１、第２、第３実施形態がどの程度、効果があるかを比較例とともに調べるために、セラミック基板２Ａとモールド絶縁樹脂（第一絶縁樹脂１６）とのせん断強度試験を行った結果を図９に示す。 <Shear strength test between ceramic substrate and mold insulating resin>
The first, second, and third embodiments of the present application are provided with the second insulating resins 17A and 17B, and are intended to increase the adhesive strength between the ceramic substrate 2A and the ceramic surface.
Next, in order to examine the effectiveness of the first, second, and third embodiments of the present application together with a comparative example, a shear strength test between the ceramic substrate 2A and the mold insulating resin (first insulating resin 16). The result of performing is shown in FIG.
　図９は、本発明の第１、第２、第３実施形態による実施例１、２、３と比較例について、セラミック基板（２Ａ、２Ｂ）とモールド樹脂（第一絶縁樹脂１６）とのせん断強度試験結果を示す図である。
　図９において、横軸方向に左から順に、比較例、実施例１、２、３について示し、縦軸には、比較例を基準値１としたせん断強度比（ｐ．ｕ．：単位法)をとっている。
　図９からわかるように、実施例１、２、３のせん断強度は比較例より高く、セラミック絶縁板との接着強度が第二絶縁樹脂を形成することで高くなっている。 FIG. 9 shows the shear between the ceramic substrate (2A, 2B) and the mold resin (first insulating resin 16) for Examples 1, 2, 3 and Comparative Examples according to the first, second, and third embodiments of the present invention. It is a figure which shows an intensity | strength test result.
9, the comparative example, Examples 1, 2, and 3 are shown in order from the left in the horizontal axis direction, and the vertical axis indicates the shear strength ratio (pu: unit method) with the comparative example being the reference value 1. Have taken.
As can be seen from FIG. 9, the shear strength of Examples 1, 2, and 3 is higher than that of the comparative example, and the adhesive strength with the ceramic insulating plate is increased by forming the second insulating resin.
　具体的には以下の方法で本発明の効果を検証した。
<1>　第１実施形態に相当する構成（実施例１）として、無垢の窒化珪素（ＳｉＮ）セラミック基板を準備し、その一方の面にポリアミドイミドを主体とする樹脂（第二絶縁樹脂）を塗布し、所定の条件にて硬化させた。
　その後、モールド金型をセラミック絶縁板上に配置し、エポキシモールド樹脂（第一絶縁樹脂）を所定の温度、圧力、時間で、底面の直径が５ｍｍ、上面の直径が４ｍｍ、高さ３ｍｍである台形円柱の試験片を作製した。 Specifically, the effect of the present invention was verified by the following method.
<1> As a configuration corresponding to the first embodiment (Example 1), a solid silicon nitride (SiN) ceramic substrate is prepared, and a resin (second insulating resin) mainly composed of polyamideimide is provided on one surface thereof. It was applied and cured under predetermined conditions.
After that, the mold is placed on the ceramic insulating plate, and the epoxy mold resin (first insulating resin) has a predetermined temperature, pressure and time, the bottom diameter is 5 mm, the top diameter is 4 mm, and the height is 3 mm. A trapezoidal cylindrical specimen was prepared.
<2>　次に、第２実施形態に相当する構成（実施例２）として、無垢の窒化アルミニウム（ＡｌＮ）セラミック基板を準備し、その一方の面にポリアミドイミド樹脂を主体とし、ポリアミドイミド樹脂中に平均粒径５μｍのアルミナフィラーを、重量比３０ｗｔ％を混合した樹脂を塗布し、所定の温度、時間で硬化させセラミック絶縁板上に第二絶縁樹脂を形成した。
　その後、モールド金型をセラミック絶縁板上に配置し、エポキシモールド樹脂（第一絶縁樹脂）を所定の温度、圧力、時間で、底面の直径が５ｍｍ、上面の直径が４ｍｍ、高さ３ｍｍである台形円柱の試験片を作製した。 <2> Next, as a configuration corresponding to the second embodiment (Example 2), a solid aluminum nitride (AlN) ceramic substrate was prepared, and one surface thereof was mainly composed of a polyamideimide resin. A resin in which an alumina filler having an average particle diameter of 5 μm and a weight ratio of 30 wt% was mixed was applied and cured at a predetermined temperature and time to form a second insulating resin on the ceramic insulating plate.
After that, the mold is placed on the ceramic insulating plate, and the epoxy mold resin (first insulating resin) has a predetermined temperature, pressure and time, the bottom diameter is 5 mm, the top diameter is 4 mm, and the height is 3 mm. A trapezoidal cylindrical specimen was prepared.
<3>　次に、第３実施形態に相当する構成（実施例３）として、無垢の窒化珪素（ＳｉＮ）セラミック絶縁板を準備し、その一方の面にシリコーンを主体とする樹脂を塗布し、所定の温度、時間で硬化させセラミック絶縁板上に第二絶縁樹脂を形成した。
　その後、モールド金型をセラミック絶縁板上に配置し、エポキシモールド樹脂（第一絶縁樹脂）を所定の温度、圧力、時間で、底面の直径が５ｍｍ、上面の直径が４ｍｍ、高さ３ｍｍである台形円柱の試験片を作製した。 <3> Next, as a configuration corresponding to the third embodiment (Example 3), a solid silicon nitride (SiN) ceramic insulating plate is prepared, and a resin mainly composed of silicone is applied to one surface thereof, The second insulating resin was formed on the ceramic insulating plate by curing at a predetermined temperature and time.
After that, the mold is placed on the ceramic insulating plate, and the epoxy mold resin (first insulating resin) has a predetermined temperature, pressure and time, the bottom diameter is 5 mm, the top diameter is 4 mm, and the height is 3 mm. A trapezoidal cylindrical specimen was prepared.
<4>　最後に、比較例に相当する構成として、無垢の窒化珪素（ＳｉＮ）セラミック絶縁板を準備し、モールド金型をセラミック絶縁板上に配置し、エポキシモールド樹脂（第一絶縁樹脂）を所定の温度、圧力、時間で、底面の直径が５ｍｍ、上面の直径が４ｍｍ、高さ３ｍｍである台形円柱の試験片を作製した。 <4> Finally, a solid silicon nitride (SiN) ceramic insulating plate is prepared as a configuration corresponding to the comparative example, a mold is placed on the ceramic insulating plate, and an epoxy mold resin (first insulating resin) is used. A trapezoidal cylindrical specimen having a bottom surface diameter of 5 mm, a top surface diameter of 4 mm, and a height of 3 mm was prepared at a predetermined temperature, pressure, and time.
　また、せん断強度の測定は、接合強度試験機を用いて、プローブをセラミック絶縁板の表面に平行となるように移動させて、試験片側面に当て、徐々に荷重を増加させて試験片が絶縁基板から剥離または破壊された時の荷重を測定した。
　以上による試験の結果が前記した図９である。
　なお、前記したように、第二絶縁樹脂を有する第１、第２、第３実施形態（実施例１、２、３）は、第二絶縁樹脂のない比較例より、せん断強度は高い。それとともに、第二絶縁樹脂およびセラミック基板の材質によってもせん断強度の高さは、異なる。 For the measurement of shear strength, use a bond strength tester to move the probe so that it is parallel to the surface of the ceramic insulating plate and place it on the side of the test piece, and gradually increase the load to insulate the test piece. The load when peeled or broken from the substrate was measured.
FIG. 9 shows the result of the test described above.
As described above, the first, second, and third embodiments (Examples 1, 2, and 3) having the second insulating resin have higher shear strength than the comparative examples having no second insulating resin. At the same time, the height of the shear strength varies depending on the materials of the second insulating resin and the ceramic substrate.
　図９に示すように、セラミック基板がＳｉＮで、第二絶縁樹脂がポリアミドイミド樹脂で構成されている実施例１（第１実施形態）が最もせん断強度は高い。
　また、セラミック基板がＳｉＮで、第二絶縁樹脂がシリコーンを主体とする樹脂で構成されている実施例３（第３実施形態）が、次に、せん断強度は高い。
　また、セラミック基板がＡｌＮで、第二絶縁樹脂がポリアミドイミド樹脂を主体とし、ポリアミドイミド樹脂中に平均粒径５μｍのアルミナフィラーを、重量比３０ｗｔ％を混合した樹脂で構成されている実施例２（第２実施形態）は、せん断強度については、実施例１、実施例３よりは低い結果となっている。
　これらは、比較例は第一絶縁樹脂のみで第二絶縁樹脂がないのに対し、実施例１－３は、セラミック基板に対する接着力が第一絶縁樹脂よりも強い第二絶縁樹脂を有していることがせん断強度を高める理由であると考えられる。また、主として、第二絶縁樹脂の材質の相違により、せん断強度比の差異が生じていると考えられる。 As shown in FIG. 9, Example 1 (first embodiment) in which the ceramic substrate is made of SiN and the second insulating resin is made of polyamideimide resin has the highest shear strength.
Further, in Example 3 (third embodiment) in which the ceramic substrate is made of SiN and the second insulating resin is made of a resin mainly composed of silicone, the shear strength is next high.
In addition, the ceramic substrate is AlN, the second insulating resin is mainly composed of a polyamideimide resin, and the polyamideimide resin is composed of a resin in which an alumina filler having an average particle diameter of 5 μm is mixed in a weight ratio of 30 wt%. (2nd Embodiment) is a result lower than Example 1 and Example 3 about shear strength.
In the comparative example, only the first insulating resin is present and the second insulating resin is not present. On the other hand, Example 1-3 has the second insulating resin that has a stronger adhesion to the ceramic substrate than the first insulating resin. This is considered to be the reason why the shear strength is increased. Moreover, it is thought that the difference in shear strength ratio is mainly caused by the difference in the material of the second insulating resin.
《温度サイクル毎の部分放電試験》
　実施例１、２、３（第１、第２、第３実施形態）、および、比較例に対し、本発明の効果を検証するために、パワー半導体装置の温度サイクル試験（ΔＴ＝１６５度）を実施した。そして各温度サイクルについて部分放電試験を実施することで、セラミック基板と絶縁樹脂間の剥離発生を検証した。
　部分放電試験は、部分放電試験器にてパワー半導体装置（１０、図１）のコレクタリード（コレクタバスバー８Ａ、図１）、エミッタリード（エミッタバスバー８Ｂ、図１）、制御端子（制御端子のバスバー８Ｇ、図１）を同電位とした。
　そして、これらとセラミック基板２Ａ、２Ｂ（セラミック絶縁回路基板２３Ａ、２３Ｂ）の裏面電極４Ａ、４Ｂとの間に交流電圧を印加した。そして、徐々に電圧上昇させ、部分放電の電荷量が１０ｐＣを超えた時の電圧を部分放電開始電圧とした。 《Partial discharge test for each temperature cycle》
In order to verify the effects of the present invention against Examples 1, 2, and 3 (first, second, and third embodiments) and the comparative example, a power semiconductor device temperature cycle test (ΔT = 165 degrees) Carried out. And by performing the partial discharge test about each temperature cycle, peeling generation | occurrence | production between a ceramic substrate and insulating resin was verified.
In the partial discharge test, the collector lead (collector bus bar 8A, FIG. 1), emitter lead (emitter bus bar 8B, FIG. 1), and control terminal (control terminal bus bar) of the power semiconductor device (10, FIG. 1) are used. 8G, FIG. 1) was set to the same potential.
Then, an AC voltage was applied between these and the back electrodes 4A and 4B of the ceramic substrates 2A and 2B (ceramic insulation circuit substrates 23A and 23B). Then, the voltage was gradually increased, and the voltage when the charge amount of partial discharge exceeded 10 pC was taken as the partial discharge start voltage.
　図１０は、実施例１、２、３と比較例に対し、温度サイクル試験を実施し、所定サイクル毎にパワー半導体装置の部分放電電圧を測定した結果を示す図である。
　図１０において、横軸は温度サイクル試験の累積回数（サイクル）、縦軸は各温度サイクル時点での部分放電開始電圧を表している。
　なお、特性線１０００は比較例を、特性線１００１は実施例１を、特性線１００２は実施例２を、特性線１００３は実施例３を示している。 FIG. 10 is a diagram illustrating a result of performing a temperature cycle test on Examples 1, 2, 3 and the comparative example, and measuring a partial discharge voltage of the power semiconductor device every predetermined cycle.
In FIG. 10, the horizontal axis represents the cumulative number (cycle) of temperature cycle tests, and the vertical axis represents the partial discharge start voltage at each temperature cycle.
The characteristic line 1000 represents a comparative example, the characteristic line 1001 represents Example 1, the characteristic line 1002 represents Example 2, and the characteristic line 1003 represents Example 3.
<比較例の温度サイクル試験結果>
　図１０の特性線１０００に示すように、比較例においては、温度サイクル試験前の時点では約６ｋＶｒｍｓであって、６ｋＶｒｍｓ未満で部分放電の発生はなかった。しかし、温度サイクル試験を２００サイクル（累積回数）経過後、部分放電開始電圧は約５．３ｋＶｒｍｓとなり、その後試験サイクルの経過と伴に部分放電開始電圧が低下した。
　この部分放電開始電圧が低下したのは、セラミック基板２Ａ、２Ｂと第一絶縁樹脂であるエポキシモールド樹脂間の接着が剥がれ、界面剥離を生じ、その剥離部で部分放電が発生したためである。 <Temperature cycle test result of comparative example>
As shown by the characteristic line 1000 in FIG. 10, in the comparative example, it was about 6 kVrms before the temperature cycle test, and no partial discharge occurred at less than 6 kVrms. However, after 200 cycles (cumulative number) of the temperature cycle test, the partial discharge start voltage was about 5.3 kVrms, and thereafter the partial discharge start voltage decreased with the progress of the test cycle.
The reason why the partial discharge start voltage is lowered is that the adhesion between the ceramic substrates 2A and 2B and the epoxy mold resin which is the first insulating resin is peeled off to cause interface peeling, and partial discharge is generated at the peeling portion.
<実施例１の温度サイクル試験結果>
　図１０の特性線１００１に示すように、実施例１では、温度サイクル試験前の時点では６ｋＶｒｍｓ未満で部分放電の発生はなかった。そして、温度サイクル試験を１０００サイクル（累積回数）経過後も６ｋＶｒｍｓ未満で部分放電の発生は見られなかった。
　なお、図８Ａの比較例における前記した電界集中部の最大電界強度比が１であり、かつ図８Ｂの、実施例１における前記した電界集中部の最大電界強度比も同じ１である。
　このように最大電界強度の観点では、実施例１と比較例では、同じ条件でありながら、図１０に示した温度サイクル試験においては、比較例（特性線１０００）では部分放電開始電圧が低下し、実施例１（特性線１００１）では部分放電開始電圧が維持されているという結果が得られている。 <Results of temperature cycle test of Example 1>
As shown by the characteristic line 1001 in FIG. 10, in Example 1, partial discharge did not occur at less than 6 kVrms before the temperature cycle test. And even after 1000 cycles (cumulative number) of the temperature cycle test, the occurrence of partial discharge was not seen at less than 6 kVrms.
Note that the maximum electric field strength ratio of the electric field concentration portion in the comparative example of FIG. 8A is 1, and the maximum electric field strength ratio of the electric field concentration portion in the embodiment 1 of FIG.
Thus, from the viewpoint of the maximum electric field strength, the partial discharge start voltage decreases in the comparative example (characteristic line 1000) in the temperature cycle test shown in FIG. In Example 1 (characteristic line 1001), the partial discharge start voltage is maintained.
　比較例が実施例１よりも劣化が早く起こる理由は、比較例では第二絶縁樹脂がないため、第一絶縁樹脂１６（図７、図８Ａ）とセラミック基板２Ａ（図７、図８Ａ）との間で剥離（界面剥離９９、図７）が発生し、温度サイクルの累積回数の増加とともに、その剥離が拡大し、部分放電開始電圧が低下したものである。
　これに対し、実施例１では、第二絶縁樹脂１７Ａ（図８Ｂ）が第一絶縁樹脂１６（図８Ｂ）よりも、セラミック基板２Ａに強固に接着しているため、剥離が生じず、部分放電開始電圧は低下しない。 The reason why the comparative example deteriorates faster than Example 1 is that the second insulating resin is not present in the comparative example, so the first insulating resin 16 (FIGS. 7 and 8A) and the ceramic substrate 2A (FIGS. 7 and 8A) Peeling (interfacial peeling 99, FIG. 7) occurred, and as the cumulative number of temperature cycles increased, the peeling increased and the partial discharge start voltage decreased.
On the other hand, in Example 1, since the second insulating resin 17A (FIG. 8B) is more firmly bonded to the ceramic substrate 2A than the first insulating resin 16 (FIG. 8B), peeling does not occur and partial discharge is caused. The starting voltage does not decrease.
<実施例２の温度サイクル試験結果>
　図１０の特性線１００２に示すように、実施例２では、温度サイクル試験前から温度サイクルの累積回数が４００回程度まで、部分放電開始電圧は約７．２ｋＶｒｍｓであった。
　これは、実施例２では、前記したように、第二絶縁樹脂１７Ａ（図８Ｃ）として、ポリアミドイミド樹脂を主体とし、ポリアミドイミド樹脂中に平均粒径５μｍのアルミナフィラーを、重量比３０ｗｔ％を混合した樹脂を用いている。
　そのため、第二絶縁樹脂１７Ａの比誘電率は、ε２＝６．２となり、第一絶縁樹脂１６の比誘電率（ε１＝４．０）よりも高く、電界集中部の最大電界強度比０．８８と緩和されている。
　この電界集中部の最大電界強度が緩和されたために、図１０において、実施例２は、特性線１００２に示すように、比較例の特性線１０００や実施例１の特性線１００１よりも、高い部分放電開始電圧が得られている。 <Results of temperature cycle test of Example 2>
As shown by the characteristic line 1002 in FIG. 10, in Example 2, the partial discharge start voltage was about 7.2 kVrms from the time before the temperature cycle test until the cumulative number of temperature cycles was about 400 times.
In Example 2, as described above, as the second insulating resin 17A (FIG. 8C), a polyamideimide resin is mainly used, and an alumina filler having an average particle diameter of 5 μm is added to the polyamideimide resin at a weight ratio of 30 wt%. A mixed resin is used.
Therefore, the relative dielectric constant of the second insulating resin 17A is ε 2 = 6.2, which is higher than the relative dielectric constant (ε 1 = 4.0) of the first insulating resin 16, and the maximum electric field strength ratio of the electric field concentration portion. Relaxed to 0.88.
Since the maximum electric field strength of the electric field concentration portion has been relaxed, in FIG. 10, as shown by a characteristic line 1002, Example 2 is higher than the characteristic line 1000 of the comparative example and the characteristic line 1001 of Example 1. The discharge start voltage is obtained.
<実施例３の温度サイクル試験結果>
　図１０の特性線１００３に示すように、実施例３では、温度サイクル試験前から温度サイクルの累積回数が８００回程度まで、部分放電開始電圧は約６．４ｋＶｒｍｓであった。
　この温度サイクル部分放電開始電圧（約６．４ｋＶｒｍｓ）が、比較例および実施例１の部分放電開始電圧（約６ｋＶｒｍｓ）と、実施例２の部分放電開始電圧（約７．２ｋＶｒｍｓ）との間の値を示した。
　これは、実施例３の構造においては、図８Ｄにおける電界集中部の最大電界強度比が０．９９であって、図８Ａの比較例、および、図８Ｂ実施例１の最大電界強度比が１と、図８Ｃの実施例２の最大電界強度比が０．８８との間の値であることに対応している。 <Results of temperature cycle test of Example 3>
As shown by the characteristic line 1003 in FIG. 10, in Example 3, the partial discharge start voltage was about 6.4 kVrms from before the temperature cycle test until the cumulative number of temperature cycles was about 800 times.
This temperature cycle partial discharge start voltage (about 6.4 kVrms) is between the partial discharge start voltage of the comparative example and Example 1 (about 6 kVrms) and the partial discharge start voltage of Example 2 (about 7.2 kVrms). The value is shown.
In the structure of Example 3, the maximum electric field strength ratio of the electric field concentration portion in FIG. 8D is 0.99, and the maximum electric field strength ratio of the comparative example of FIG. 8A and FIG. This corresponds to the value of the maximum electric field strength ratio of Example 2 in FIG. 8C being between 0.88.
＜実施例１－３の温度サイクル試験とせん断強度試験の結果について＞
　実施例１－３（第１－第３実施形態）のように、セラミック基板２Ａに対する接着力が第一絶縁樹脂１６よりも強く、かつ適切な比誘電率の第二絶縁樹脂１７Ａを備えることにより、温度サイクル試験による信頼性試験において、信頼度が向上していることがわかる。
　この信頼度の向上は、セラミック基板２Ａと第一絶縁樹脂１６（エポキシモールド樹脂）との間に、セラミックとの接着性に優れている第二絶縁樹脂１７Ａ（ポリアミドイミド樹脂、シリコーン樹脂等）が界面剥離を防止したためである。
　なお、図１０に示した部分放電開始電圧の温度サイクル試験では、０回～１０００回において、実施例２が部分放電開始電圧が最も高く、次に実施例３、その次に実施例１の順番であった。 <Results of Temperature Cycle Test and Shear Strength Test of Example 1-3>
As in Example 1-3 (first to third embodiments), the second insulating resin 17A having an adhesive strength stronger than that of the first insulating resin 16 and having an appropriate relative dielectric constant is provided. It can be seen that the reliability is improved in the reliability test by the temperature cycle test.
This improvement in reliability is achieved by the second insulating resin 17A (polyamideimide resin, silicone resin, etc.) having excellent adhesion to the ceramic between the ceramic substrate 2A and the first insulating resin 16 (epoxy mold resin). This is because interfacial peeling is prevented.
In the temperature cycle test of the partial discharge start voltage shown in FIG. 10, Example 2 had the highest partial discharge start voltage from 0 to 1000 times, followed by Example 3 and then Example 1. Met.
　一方、前記した図９に示したせん断強度の試験においては、実施例１がせん断強度が最も強く、次に実施例３、その次に実施例２の順番であった。
　これらの望ましいと考えられる特性の順番は、図９のせん断強度の試験と図１０の部分放電開始電圧の温度サイクル試験とでは、一致するとはかぎらない。
　すなわち、せん断強度の強さの特性を優先するか、温度サイクル試験による信頼性を優先するかによって、第二絶縁樹脂１７Ａの最適な構造や材質の選択が異なってくる。
　さらには、第二絶縁樹脂１７Ａのみならず、第一絶縁樹脂１６やセラミック基板２Ａの材質や構造によっても、様々な特性を示す。 On the other hand, in the shear strength test shown in FIG. 9, Example 1 had the strongest shear strength, followed by Example 3 and then Example 2.
The order of these desirable properties does not necessarily match between the shear strength test of FIG. 9 and the partial cycle start voltage temperature cycle test of FIG.
That is, the selection of the optimal structure and material of the second insulating resin 17A differs depending on whether priority is given to the strength characteristic of the shear strength or the reliability by the temperature cycle test.
Furthermore, various characteristics are exhibited not only by the second insulating resin 17A but also by the material and structure of the first insulating resin 16 and the ceramic substrate 2A.
（その他の実施形態）
　以上、本発明の実施形態について図面を参照して詳述したが、本発明はこれら実施形態およびその変形に限定されるものではなく、本発明の要旨を逸脱しない範囲の設計変更等があってもよく、以下にその例をあげる。 (Other embodiments)
As mentioned above, although embodiment of this invention was explained in full detail with reference to drawings, this invention is not limited to these embodiment and its deformation | transformation, There exists a design change etc. of the range which does not deviate from the summary of this invention. Well, here are some examples:
《片面冷却構造のパワー半導体装置への適用》
　第１、第２、第３実施形態においては、両面冷却構造のパワー半導体装置１０（図１、図２、図３）を説明したが、本発明の第二絶縁樹脂を備えることにより、信頼性を向上させる技術は、片面冷却構造のパワー半導体装置へ適用することもできる。
　図４は、本発明の第４実施形態に係るパワー半導体装置４０の断面構造を示す図である。
　図４において、セラミック基板２Ａと回路電極３Ａと裏面電極４Ａを備えてセラミック絶縁回路基板２３Ｓが構成されている。
　また、放熱ベース板１９Ａと熱伝導部材１８Ａとによって、前記のセラミック絶縁回路基板２３Ｓで発生する熱を放熱する構成となっている。
　この放熱ベース板１９Ａと熱伝導部材１８Ａを有することによって、パワー半導体装置４０は、片面冷却構造を有する構造となっている。 << Application of single-sided cooling structure to power semiconductor devices >>
In the first, second, and third embodiments, the power semiconductor device 10 (FIGS. 1, 2, and 3) having a double-sided cooling structure has been described. However, by including the second insulating resin of the present invention, reliability is improved. The technique for improving the above can also be applied to a power semiconductor device having a single-sided cooling structure.
FIG. 4 is a diagram showing a cross-sectional structure of a power semiconductor device 40 according to the fourth embodiment of the present invention.
In FIG. 4, a ceramic insulated circuit board 23S is configured by including a ceramic substrate 2A, a circuit electrode 3A, and a back electrode 4A.
Further, the heat generating base plate 19A and the heat conducting member 18A are configured to radiate heat generated in the ceramic insulated circuit board 23S.
By having the heat radiating base plate 19A and the heat conducting member 18A, the power semiconductor device 40 has a structure having a single-sided cooling structure.
　また、ＩＧＢＴ等で構成されているパワー半導体素子１１は、半田５Ａを介して、前記のセラミック絶縁回路基板２３Ｓに接続されている。
　また、外部端子１１３は、リード（バスバー）８Ｌ、半田５７、回路電極３Ａ、ワイヤー６Ｗを介して、前記のパワー半導体素子１１や前記のセラミック絶縁回路基板２３Ｓに接続されている。
　また、セラミック基板２Ａと回路電極３Ａとに接触して、ポリアミドイミド樹脂からなる第二絶縁樹脂１７Ａが備えられている。また、エポキシモールド樹脂からなる第一絶縁樹脂１６によって、パワー半導体素子１１およびセラミック絶縁回路基板２３Ｓを絶縁封止する。
　また、樹脂ケース１１１のなかに、絶縁封止されたパワー半導体素子１１およびセラミック絶縁回路基板２３Ｓ等が納められる。
　この片面冷却構造のパワー半導体装置４０においても、エポキシモールド樹脂からなる第一絶縁樹脂１６以外に、前記のポリアミドイミド樹脂からなる第二絶縁樹脂１７Ａが備えられているので、第１、第２実施形態（実施例１、２）と同様に、せん断強度試験や温度サイクル試験等における信頼性が向上する効果がある。 The power semiconductor element 11 made of IGBT or the like is connected to the ceramic insulating circuit board 23S through the solder 5A.
The external terminal 113 is connected to the power semiconductor element 11 and the ceramic insulating circuit board 23S via leads (bus bars) 8L, solder 57, circuit electrodes 3A, and wires 6W.
Further, a second insulating resin 17A made of polyamideimide resin is provided in contact with the ceramic substrate 2A and the circuit electrode 3A. Further, the power semiconductor element 11 and the ceramic insulated circuit board 23S are insulated and sealed with the first insulating resin 16 made of epoxy mold resin.
In addition, in the resin case 111, the power semiconductor element 11 and the ceramic insulating circuit board 23S which are insulated and sealed are accommodated.
Also in the power semiconductor device 40 of this single-side cooling structure, in addition to the first insulating resin 16 made of epoxy mold resin, the second insulating resin 17A made of the polyamideimide resin is provided, so that the first and second embodiments are provided. Similar to the embodiment (Examples 1 and 2), there is an effect of improving reliability in a shear strength test, a temperature cycle test, and the like.
《第二絶縁樹脂の材質》
　第二絶縁樹脂として、ポリアミドイミドを主体とする樹脂、ポリアミドイミド樹脂中に平均粒径５μｍのアルミナフィラーを重量比３０ｗｔ％を混合した樹脂、シリコーンを主体とする樹脂として説明したが、ポリイミドを主体とする樹脂を適用してもよい。 <Material of second insulating resin>
The second insulating resin has been described as a resin mainly composed of polyamideimide, a resin in which an alumina filler having an average particle size of 5 μm is mixed in a polyamideimide resin with a weight ratio of 30 wt%, and a resin mainly composed of silicone. A resin may be applied.
《第一絶縁樹脂の材質》
　第一絶縁樹脂としては、エポキシモールド樹脂として説明したが、エポキシ樹脂を主体とするトランスファーモールドレジン、あるいはポッティングレジンのいずれの場合でも、パワー半導体装置に前記の第二絶縁樹脂を備えた場合の効果がある。 <Material of first insulating resin>
The first insulating resin has been described as an epoxy mold resin, but the effect of including the second insulating resin in the power semiconductor device in any case of a transfer mold resin or a potting resin mainly composed of an epoxy resin. There is.
《セラミック基板の材質》
　セラミック基板の材質としては、窒化アルミニウム、窒化珪素等の無機粉末材料を焼結して作製した場合について説明したが、酸化アルミニウムを用いて作製した場合についても、パワー半導体装置に前記の第二絶縁樹脂を備えた場合の効果がある。 <Material of ceramic substrate>
As the material of the ceramic substrate, the case where the inorganic powder material such as aluminum nitride and silicon nitride is produced by sintering has been described, but the case where the ceramic substrate is produced using aluminum oxide also includes the above-mentioned second insulation in the power semiconductor device. There is an effect when a resin is provided.
《パワー半導体素子》
　パワー半導体素子としてＩＧＢＴを用いる場合について、説明したが、ＩＧＢＴに限らない。例えば、バイポーラトランジスタ（bipolar transistor）やＢｉＣＭＯＳ（Bipolar Complementary Metal Oxide Semiconductor）やＭＯＳＦＥＴ（metal oxide silicon field effect transistor）やスーパー ジャンクション ＭＯＳＦＥＴを用いた場合においても、パワー半導体装置に前記の第二絶縁樹脂を備えた場合に同様の効果がある。
　また、前記のパワー半導体素子をワイドギャップデバイスとするために、ＳｉＣ（Silicon Carbide、炭化ケイ素）やＧａＮ（gallium nitride、窒化ガリウム）やＧａ２Ｏ３（gallium oxide、酸化ガリウム）など用いた半導体デバイスでも同様の効果がある。 《Power semiconductor element》
Although the case where IGBT was used as a power semiconductor element was demonstrated, it is not restricted to IGBT. For example, even when a bipolar transistor (Bipolar transistor), BiCMOS (Bipolar Complementary Metal Oxide Semiconductor), MOSFET (metal oxide silicon field effect transistor), or super junction MOSFET is used, the power semiconductor device includes the second insulating resin. Have the same effect.
Also, the power semiconductor device to a wide gap device, SiC (Silicon Carbide, Silicon Carbide) or GaN (gallium Nitride, GaN) semiconductor devices using such and Ga 2 O 3 (gallium oxide, gallium oxide) But it has the same effect.
《電力変換装置》
　前記した本発明のパワー半導体装置を含んでなる電力変換装置を構成することができる。このとき、電力変換装置としてもパワー半導体装置に起因する要因において、高い信頼性を確保できる。 《Power conversion device》
A power conversion device including the power semiconductor device of the present invention described above can be configured. At this time, high reliability can be secured in the factor resulting from the power semiconductor device as the power conversion device.
　１０、２０、４０　　パワー半導体装置
　１１、１２　　パワー半導体素子
　１６　　第一絶縁樹脂
　１７Ａ、１７Ｂ　　第二絶縁樹脂
　１８Ａ、１８Ｂ　　熱伝導部材
　１９Ａ、１９Ｂ　　放熱ベース板
　１１１　　樹脂ケース
　１１３　　外部端子
　１４１、１４２　　台座
　２Ａ、２Ｂ　　セラミック基板
　２３Ａ、２３Ｂ、２３Ｓ　　セラミック絶縁回路基板
　３Ａ、３Ｂ　　回路電極
　４Ａ、４Ｂ　　裏面電極
　５１Ａ、５１Ｂ、５１Ｃ、５２Ａ、５２Ｂ、５２Ｃ、５７　　半田
　６Ｇ、６Ｗ　　ワイヤー
　８Ａ　　バスバー、コレクタバスバー
　８Ｂ　　バスバー、エミッタバスバー
　８Ｇ　　バスバー、制御端子のバスバー、（制御端子）
　８Ｌ　　バスバー、リード
　９９　　界面剥離 10, 20, 40 Power semiconductor device 11, 12 Power semiconductor element 16 First insulating resin 17A, 17B Second insulating resin 18A, 18B Thermal conductive member 19A, 19B Heat radiation base plate 111 Resin case 113 External terminal 141, 142 Base 2A, 2B Ceramic substrate 23A, 23B, 23S Ceramic insulated circuit substrate 3A, 3B Circuit electrode 4A, 4B Back electrode 51A, 51B, 51C, 52A, 52B, 52C, 57 Solder 6G, 6W Wire 8A Bus bar, collector bus bar 8B bus bar, emitter bus bar 8G bus bar, control terminal bus bar, (control terminal)
8L bus bar, lead 99 interface peeling

Claims (8)

  1. 　パワー半導体素子と、
    　セラミック基板上に回路電極を形成した少なくとも１枚のセラミック絶縁回路基板と、
    　前記パワー半導体素子の少なくとも一方の電極面と、前記セラミック絶縁回路基板の回路電極とを電気的に接合された状態にて、前記パワー半導体素子と前記セラミック基板の回路電極とを封止する第一絶縁樹脂と、
    　前記セラミック基板と前記第一絶縁樹脂との間の少なくとも一部分に、前記セラミック基板のセラミックとの接着強度が前記第一絶縁樹脂よりも高い接着強度を有する第二絶縁樹脂と、
    を備えることを特徴とするパワー半導体装置。     A power semiconductor element;
    At least one ceramic insulated circuit board having circuit electrodes formed on the ceramic board;
    First sealing the power semiconductor element and the circuit electrode of the ceramic substrate in a state in which at least one electrode surface of the power semiconductor element and the circuit electrode of the ceramic insulating circuit board are electrically bonded. Insulating resin;
    At least a portion between the ceramic substrate and the first insulating resin, a second insulating resin having an adhesive strength with the ceramic of the ceramic substrate higher than that of the first insulating resin;
    A power semiconductor device comprising:
  2. 　請求項１において、
    　前記第一絶縁樹脂が、エポキシ樹脂主体とするトランスファーモールドレジン、またはポッティングレジンのいずれかであること特徴とするパワー半導体装置。     In claim 1,
    The power semiconductor device, wherein the first insulating resin is a transfer mold resin or a potting resin mainly composed of an epoxy resin.
  3. 　請求項１または請求項２において、
    　前記第二絶縁樹脂が、ポリアミドイミドを主体とする樹脂、またはポリイミドを主体とする樹脂、またはシリコーンを主体とする樹脂のいずれかであること特徴とするパワー半導体装置。     In claim 1 or claim 2,
    The power semiconductor device, wherein the second insulating resin is any one of a resin mainly composed of polyamideimide, a resin mainly composed of polyimide, or a resin mainly composed of silicone.
  4. 　請求項１において、
    　前記第二絶縁樹脂と前記セラミック絶縁回路基板の回路電極の少なくとも一部分が接触して配置されていることを特徴とするパワー半導体装置。     In claim 1,
    The power semiconductor device, wherein the second insulating resin and at least a part of a circuit electrode of the ceramic insulating circuit board are in contact with each other.
  5. 　請求項４において、
    　前記第二絶縁樹脂の比誘電率が前記第一絶縁樹脂の比誘電率よりも大きいことを特徴とするパワー半導体装置。     In claim 4,
    A power semiconductor device characterized in that the relative dielectric constant of the second insulating resin is larger than the relative dielectric constant of the first insulating resin.
  6. 　請求項１において、
    　前記第二絶縁樹脂と前記セラミック絶縁回路基板の回路電極とが離れて配置されていることを特徴とするパワー半導体装置。     In claim 1,
    The power semiconductor device, wherein the second insulating resin and the circuit electrode of the ceramic insulating circuit board are arranged apart from each other.
  7. 　請求項６において、
    　前記第二絶縁樹脂の比誘電率が前記第一絶縁樹脂の比誘電率よりも小さいことを特徴とするパワー半導体装置。     In claim 6,
    A power semiconductor device, wherein the relative dielectric constant of the second insulating resin is smaller than the relative dielectric constant of the first insulating resin.
  8. 　パワー半導体素子と、
    　セラミック基板上に回路電極を形成した少なくとも１枚のセラミック絶縁回路基板と、
    　前記パワー半導体素子の少なくとも一方の電極面と、前記セラミック絶縁回路基板の回路電極とを電気的に接合された状態にて、前記パワー半導体素子と前記セラミック基板の回路電極とを封止する第一絶縁樹脂と、
    　前記セラミック基板と前記第一絶縁樹脂との間の少なくとも一部分に、前記セラミック基板のセラミックとの接着強度が前記第一絶縁樹脂よりも高い接着強度を有する第二絶縁樹脂と、
    を備えてなるパワー半導体装置を含んでなる電力変換装置。     A power semiconductor element;
    At least one ceramic insulated circuit board having circuit electrodes formed on the ceramic board;
    First sealing the power semiconductor element and the circuit electrode of the ceramic substrate in a state in which at least one electrode surface of the power semiconductor element and the circuit electrode of the ceramic insulating circuit board are electrically bonded. Insulating resin;
    At least a portion between the ceramic substrate and the first insulating resin, a second insulating resin having an adhesive strength with the ceramic of the ceramic substrate higher than that of the first insulating resin;
    A power conversion device comprising a power semiconductor device comprising:
PCT/JP2014/050182 2014-01-09 2014-01-09 Power semiconductor device and power conversion device WO2015104808A1 (en)

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EP3300463A1 (en) * 2016-09-26 2018-03-28 Hitachi Power Semiconductor Device, Ltd. Semiconductor device
WO2020136459A1 (en) * 2018-12-28 2020-07-02 федеральное государственное бюджетное научное учреждение "Научно-производственный комплекс "Технологический центр" Methods for manufacturing three-dimensional electronic modules, three-dimensional electronic modules
CN116798882A (en) * 2023-08-22 2023-09-22 哈尔滨工业大学（威海） Manufacturing method of power module with double-sided heat dissipation structure

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JP2000091472A (en) * 1998-09-10 2000-03-31 Toshiba Corp Semiconductor device
JP2005116602A (en) * 2003-10-03 2005-04-28 Denki Kagaku Kogyo Kk Circuit board and its manufacturing method
JP2006032617A (en) * 2004-07-15 2006-02-02 Hitachi Ltd Semiconductor power module
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EP3300463A1 (en) * 2016-09-26 2018-03-28 Hitachi Power Semiconductor Device, Ltd. Semiconductor device
WO2020136459A1 (en) * 2018-12-28 2020-07-02 федеральное государственное бюджетное научное учреждение "Научно-производственный комплекс "Технологический центр" Methods for manufacturing three-dimensional electronic modules, three-dimensional electronic modules
CN116798882A (en) * 2023-08-22 2023-09-22 哈尔滨工业大学（威海） Manufacturing method of power module with double-sided heat dissipation structure
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