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WO2015019677A1 - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method Download PDF

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Publication number
WO2015019677A1
WO2015019677A1 PCT/JP2014/063565 JP2014063565W WO2015019677A1 WO 2015019677 A1 WO2015019677 A1 WO 2015019677A1 JP 2014063565 W JP2014063565 W JP 2014063565W WO 2015019677 A1 WO2015019677 A1 WO 2015019677A1
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WO
WIPO (PCT)
Prior art keywords
metal
bonding
semiconductor chip
wiring
purity
Prior art date
Application number
PCT/JP2014/063565
Other languages
French (fr)
Japanese (ja)
Inventor
宮本　健二
中川　成幸
南部　俊和
Original Assignee
日産自動車株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日産自動車株式会社 filed Critical 日産自動車株式会社
Priority to JP2015530729A priority Critical patent/JP6260941B2/en
Publication of WO2015019677A1 publication Critical patent/WO2015019677A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H01L2224/83805—Soldering or alloying involving forming a eutectic alloy at the bonding interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
    • H01L23/473—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing liquids

Definitions

  • the present invention relates to a semiconductor device in which a semiconductor chip and a wiring metal are joined, and further to a semiconductor device in which such a semiconductor device is disposed on a base plate such as a cooling body via an insulating ceramic substrate.
  • the present invention relates to a manufacturing method and a semiconductor device manufactured by such a method.
  • Recent semiconductor devices particularly semiconductor devices called high power modules having a large current density, are required to be usable even in a high temperature environment. Therefore, in a mounting structure of a semiconductor device, a joint having excellent high temperature durability when held at a high temperature or subjected to a high temperature thermal cycle is strongly desired. From the viewpoint of environmental protection, a Pb (lead) -free joining technique is essential.
  • solder is widely used for bonding for mounting such semiconductor devices, but the operating temperature is the melting point of the solder (for example, It is limited to about 200 ° C. or less. Also, for example, in a joint where the electrode is Cu, a Cu—Sn brittle intermetallic compound layer is formed at the interface, resulting in poor high-temperature durability. Therefore, various attempts have been made to ensure the high temperature durability of the joint.
  • a low-temperature bonding method has been proposed in which active surface energy of metal nanoparticles is used to agglomerate and bond at low temperatures. If this bonding method is used, the bonded interface after agglomeration becomes a bulk metal, and therefore has excellent high temperature durability.
  • a noble metal such as Au (gold) is used as the metal nanoparticle, and the surface of the metal nanoparticle is modified with an organic substance, resulting in a structure in which the particles are agglomerated, and the organic substance is a bonding process. Since the gas is sometimes gasified and remains, voids are present in the joint, resulting in large variations in joint strength.
  • an insert material containing a metal such as Zn (zinc) that causes a eutectic reaction with the base metal from the viewpoint of eliminating the influence on the bonding quality caused by the oxide film formed on the bonding surface and forming a sound bonded portion.
  • a metal such as Zn (zinc) that causes a eutectic reaction with the base metal
  • bonding is performed by causing a eutectic reaction at the bonding interface by pressurizing and heating in a state of interposing between the bonding surfaces. That is, by generating a eutectic reaction between the base metal and the insert material, the oxide film on the surface of the base material can be removed and discharged together with the generated eutectic reaction melt from the joint surface.
  • the yield point is lowered by increasing the purity of the wiring metal, and thermal stress is generated based on the difference in thermal expansion coefficient between the semiconductor chip and the wiring metal.
  • the concavo-convex structure remains on the joint surface, and the metal in the insert material contained in the solidified eutectic reaction liquid phase remaining on the concavo-convex bottom is on the wiring metal side. It has been found that it may spread. Then, it has been found that when such metal diffusion occurs, the purity of the wiring metal decreases, the thermal stress increases due to an increase in the yield point, and the elongation decreases, which may impair durability reliability.
  • the present invention has been made in view of the above problems in the conventional bonding technology applied to the mounting structure of a semiconductor device.
  • the present inventors have formed a metal atom diffusion prevention layer made of, for example, Ni or TiN on the surface of the bonding surface of the wiring metal made of high purity Al. As a result, the present inventors have found that the above problems can be solved, and have completed the present invention.
  • the bonding surface is mainly composed of at least one selected from the group consisting of Al, Cu, Ag, and Au.
  • the bonding surface is mainly composed of at least one selected from the group consisting of Al, Cu, Ag, and Au.
  • the bonding surface is mainly composed of at least one selected from the group consisting of Al, Cu, Ag, and Au.
  • the insert material is interposed, the semiconductor chip and the wiring metal are heated while being relatively pressurized, and the eutectic reaction melt generated at the bonding interface is discharged together with the oxide film, Without even wherein the bonding the metal A and a high-purity Al which constitutes the bonding surface of the semiconductor chip and the interconnect metal in some direct.
  • the semiconductor device of the present invention is formed by bonding a semiconductor chip and a wiring metal, and the semiconductor chip has at least one selected from the group consisting of Al, Cu, Ag and Au as a main component.
  • the wiring metal is made of high-purity Al and has a metal atom diffusion prevention layer on or inside the bonding surface, and constitutes the bonding surface of the semiconductor chip and the wiring metal.
  • Metal A and high-purity Al are directly bonded at at least a part of the bonding interface, Zn eutectic composition around the direct bonding part, and at least one metal other than Au contained in Al and metal A It is characterized by the presence of effluents containing the oxides.
  • the diffusion preventing layer for preventing the diffusion of metal atoms is formed on the surface or inside of the bonding surface of the wiring metal made of high purity Al. Therefore, even if the eutectic reaction liquid phase coagulum remains at the bottom of the concavo-convex structure of the joint surface, the metal atoms in the coagulum do not diffuse to the wiring metal side, and the yield is reduced due to the decrease in the purity of the wiring metal. It is possible to prevent an increase in point, a decrease in elongation, and an increase in thermal stress, and the durability reliability of the apparatus is improved.
  • (A)-(e) is process drawing which shows roughly the joining process of the semiconductor chip and wiring metal by the manufacturing method of the semiconductor device of this invention.
  • (A)-(c) is a perspective view which shows the example of the shape of the uneven structure formed in a junction part in the manufacturing method of the semiconductor device of this invention. It is a schematic sectional drawing which shows the structure of the semiconductor chip which comprises one side of the semiconductor device by the manufacturing method of this invention.
  • (A)-(d) is a schematic sectional drawing which shows the example which formed the diffusion prevention layer in the surface of a joining surface in the manufacturing method of the semiconductor device of this invention.
  • (A)-(d) is a schematic sectional drawing which shows the example which formed the diffusion prevention layer in the inside of a joining surface in the manufacturing method of the semiconductor device of this invention.
  • (A)-(d) is a schematic sectional drawing which respectively shows the embodiment of the semiconductor device by the manufacturing method of this invention. It is a schematic sectional drawing explaining the structure of the semiconductor device used for the Example of this invention.
  • % means mass percentage unless otherwise specified.
  • metal A mainly composed of at least one selected from the group consisting of Al, Cu, Ag and Au, and high-purity Al.
  • at least one of the joint surfaces is provided with unevenness for breaking the oxide film on the joint surface.
  • a metal atom diffusion preventing layer is formed on the surface or inside of the bonding surface of the wiring metal.
  • an insert material containing Zn as a metal that causes a eutectic reaction with at least one metal other than Au contained in Al and the metal A is interposed between both joint surfaces.
  • “high purity Al” means that containing 99.0% or more of Al.
  • the semiconductor chip and the wiring metal are relatively pressurized and heated, and the oxide film formed on the bonding surface is broken by the unevenness so that the metal A of the semiconductor chip and the wiring metal and the insert material are in contact with each other.
  • the eutectic reaction of the metal contained in the metal A and the Al contained in the wiring metal and the metal contained in the insert material is caused at the bonding interface.
  • the eutectic reaction melt is discharged together with the oxide film, and the metal A and the wiring metal of the semiconductor chip are directly bonded at at least a part of the bonding interface, so that the semiconductor chip and the wiring metal are firmly bonded.
  • the metal atoms in the solidified material are prevented by the diffusion preventing layer. Since diffusion to the wiring metal is prevented, the yield point of the wiring metal does not increase and the elongation does not decrease, and the durability reliability of the device can be improved.
  • Melting due to the eutectic reaction occurs when the composition of the interdiffusion region formed by mutual diffusion of two or more metals becomes the eutectic composition. A phase is formed.
  • the melting point of Al is 660 ° C.
  • the melting point of Zn is 419.5 ° C.
  • this eutectic metal melts at 382 ° C. which is lower than the respective melting points. Therefore, when the clean surfaces of both metals are brought into contact and heated to 382 ° C. or higher, a reaction (eutectic melting) occurs and Al-95% Zn has a eutectic composition, but the eutectic reaction itself is independent of the alloy components. It is a constant change, and the composition of the insert material only increases or decreases the amount of eutectic reaction.
  • the neighboring oxide film is crushed and decomposed by the formation of a liquid phase by the eutectic reaction, and further, eutectic melting spreads to the entire surface, thereby expanding and promoting the oxide film breakage, and lowering the oxide film on the joint surface at a low temperature. Since it is removed at (eutectic temperature), the metal A and the metal B can be directly joined without going through the brazing material layer. Therefore, the strength is ensured by the direct joining of the metal A and Al not containing Pb, so that even when kept at a high temperature, a brittle intermetallic compound layer and a Kirkendall void are not generated, and an excellent high temperature durability is achieved.
  • the semiconductor device provided with the provided Pb-free junction can be manufactured.
  • the eutectic composition is spontaneously achieved by interdiffusion, there is no need to control the composition, and the essential condition is that a low-melting eutectic reaction occurs between the base material (metal A, Al) and the metal contained in the insert material. Is to generate. At this time, it is necessary to cause eutectic reaction between the metal contained in the metal A of the semiconductor chip, Al of the wiring metal, and the metal contained in the insert material on the joint surface. It is necessary to heat to the higher eutectic temperature.
  • 1 (a) to 1 (e) are process diagrams for explaining a bonding process between a semiconductor chip and a wiring metal in a method of manufacturing a semiconductor device according to the present invention.
  • the formation of the diffusion preventing layer is omitted from this figure because it is not directly involved in the bonding process.
  • the insert material 4 is disposed between the wiring metal 2 and the semiconductor chip 3.
  • the wiring metal 2 is made of high-purity Al, and fine unevenness R is formed in advance on the joint surface, and a diffusion prevention layer (see FIG. (Not shown) is formed.
  • a metal layer 3c containing, for example, Al, Cu, or Ag as a main component is formed as a metal A on the bonding surface of the semiconductor chip 3 by plating, sputtering, or the like. Note that oxide films 2f and 3f are formed on the surfaces of the wiring metal 2 and the metal layer 3c.
  • the selection range of the metal A a pure metal selected from the group consisting of Al, Cu, Ag and Au, and various metals including an alloy between these metals can be adopted.
  • Joining that is, using an Al-based material eliminates the starting point of the degradation reaction at the interface, so that joining with higher durability reliability is possible.
  • the “same material” as used herein means a metal containing Al as a main component, and is not necessarily the same high-purity Al as the wiring metal 2.
  • the shape of the unevenness R formed on the joint surface of the wiring metal 2 is not limited as long as it has a function of concentrating stress and promoting the destruction of the oxide film.
  • FIG. ) To (c) can be employed. That is, as shown in FIG. 2 (a), if the convex-convex tip is made to be a substantially flat surface as a trapezoidal cross-sectional concavo-convex structure, the stress concentration means can be easily formed even if the stress concentration level is slightly reduced. Costs can be reduced.
  • FIG. 2B it is also possible to adopt a concavo-convex structure in which triangular prisms are arranged in parallel, whereby the convex tip of the concavo-convex structure becomes linear, and the stress concentration degree is increased. This can enhance the effect of breaking the oxide film.
  • FIG. 2 (c) it is possible to adopt a concavo-convex structure in which square pyramids are juxtaposed in the vertical and horizontal directions. Thus, the breaking performance of the oxide film can be improved.
  • the shape of the unevenness R is not particularly limited as long as it has a function of concentrating stress and promoting the destruction of the oxide film as described above. It is also possible to make the tip of the convex part such as a shape a curved surface. Needless to say, the smaller the radius of curvature of the curved surface, the more the stress concentration becomes more prominent, and the oxide film is easily broken.
  • Such unevenness R can be formed by, for example, cutting, grinding, plastic processing (roller processing), laser processing, electric discharge processing, etching processing, lithography, etc., and the formation method is particularly limited. It is not a thing. Of these processing methods, plastic processing enables formation at a very low cost.
  • the dimensions and shape of the fine irregularities are an aspect ratio (height / width): 0.001 or more, a pitch: 1 ⁇ m or more, and preferably an aspect ratio of 0.1 or more and a pitch: 10 ⁇ m or more.
  • the semiconductor chip 3 is provided with the metal layer 3c made of metal A on the joint surface side as described above.
  • the semiconductor chip body 3 made of SiC, Si, GaN, etc.
  • An adhesion layer 3a and a barrier layer 3b can be interposed between the layers 3c.
  • the barrier layer 3b has a function of preventing the components of the metal layer 3c from diffusing into the chip body, and Ni (nickel), Pt—Ir (platinum-iridium), or the like can be applied.
  • the adhesion layer 3a has a function of improving the adhesion between the barrier layer 3b and the chip body 3, and for example, Ti (titanium), Cr (chromium), or the like can be used.
  • the insert material 4 is made of Zn, which is a metal that causes a eutectic reaction with at least one metal element of Al, Cu, and Ag and Al contained in the wiring metal, other than Au contained in the metal A.
  • Zn is a metal that causes a eutectic reaction with at least one metal element of Al, Cu, and Ag and Al contained in the wiring metal, other than Au contained in the metal A.
  • a metal (pure zinc or zinc alloy) containing Zn as a main component is used.
  • an alloy containing Zn and Al, Mg, Cu, Ag, and Sn as a main component for example, an alloy containing Zn and Al as main components, Zn, Al, and Mg
  • An alloy containing a main component or an alloy containing Zn, Al, and Cu as main components can also be used. That is, the eutectic temperature of the alloy system containing Zn and Al is low (382 ° C. for the Zn—Al based alloy and 330 ° C. for the Zn—Al—Mg based alloy). Both members can be joined by removing the oxide film that hinders the joining from the joining interface without inducing.
  • the insert material 4 can contain metal contained in the metal A constituting the bonding surface of the semiconductor chip 3 and Al contained in the wiring metal, and the reactivity between the insert material and the member to be joined is improved. In addition, it is desirable for improving the affinity of the bonding interface.
  • the thickness of the insert material 4 is desirably 20 ⁇ m or more and 200 ⁇ m or less.
  • the thickness of the insert material 4 is less than 20 ⁇ m, the oxide film is not sufficiently discharged, the sealing performance of the joint portion is lowered, and oxidation progresses during joining and the strength characteristics of the joint portion are lowered.
  • it exceeds 200 ⁇ m a high pressurizing force may be required for discharging the surplus portion, or the residual pressure at the interface may increase and the joint performance may be deteriorated.
  • the “main component” in the metal A or the insert material means that the total content of these metal components is 80% or more.
  • the semiconductor chip 3 and the wiring metal 2 are relatively pressurized, brought into close contact via the insert material 4, and heating is started while further pressing.
  • the stress at the portion where the tip of the convex portion of the concavo-convex R contacts abruptly increases locally, and the oxide film 3f of the metal layer 3c is mechanically formed without increasing the applied pressure so much. Is destroyed and the new surface is exposed.
  • the oxide film 2f at the tip of the fine irregularities 2r is also destroyed, and the new surface of the wiring metal 2 is exposed.
  • a eutectic reaction occurs between the metal layer 3c and the metal element in the wiring metal 2, respectively.
  • a eutectic melt phase is generated.
  • the eutectic melting range extends to the entire bonding interface, so that the metal layer 3c and the oxide films 3f and 2f of the wiring metal 2 are removed from the surface. As shown in FIG. The 2f fragments are dispersed in the eutectic melt phase.
  • the eutectic reaction melt is discharged from the bonding interface, and most of the fragments of the oxide films 3f and 2f dispersed in the liquid phase are eutectic. It is extruded together with the melt from the bonding interface, and the new surfaces of the metal layer 3c and the wiring metal 2 are exposed, and the diffusion reaction of the component elements contained therein occurs at the bonding interface.
  • bonding between the wiring metal 2 and the metal layer 3c of the semiconductor chip 3 that is, direct bonding between the metal A and Al is achieved.
  • a small amount of mixture containing eutectic reaction product, oxide film, metal derived from insert material, etc. may remain at the bonding interface, but as long as the metal-to-metal direct bonding portion is formed, the strength It will not be a problem. Moreover, such a residue contributes to electric conduction and heat conduction.
  • FIG. 1 shows an example in which the unevenness R is formed on the wiring metal 2 side
  • the present invention is not limited to this, and the formation position of the fine unevenness is as described above.
  • it can be provided on both of the bonding surfaces. By forming it on both surfaces, it is possible to increase the breakdown starting point of the oxide film.
  • the form of foil It is desirable to sandwich between the two materials.
  • the bonding of the wiring metal 2 and the semiconductor chip 3 in the manufacturing method of the present invention can be performed in an inert gas atmosphere, but can be performed in the air without any trouble.
  • it is possible to carry out in vacuum but not only vacuum equipment is required, but also the vacuum gauge and gate valve may be damaged by melting of the insert material. Therefore, it is advantageous in terms of cost.
  • means for heating or maintaining the bonding portion within a predetermined temperature range is not particularly limited.
  • high-frequency heating, infrared heating, heater heating, or the like can be used.
  • a combined method can be employed.
  • the speed is high because the interface is oxidized and the discharge of the melt is lowered and the strength is lowered. This tendency occurs particularly in the case of bonding in the atmosphere.
  • the pressurizing force at the time of joining can be reduced by forming the unevenness R, and therefore the pressurizing force at the time of joining is preferably set to 1 MPa or more and 30 MPa or less. That is, when the pressure is less than 1 MPa, the oxide film cannot be destroyed or the eutectic reaction product or the oxide film fragments can be sufficiently discharged from the joint surface. If the pressure exceeds 30 MPa, the semiconductor chip 2 may be damaged. by.
  • FIG. 4 is a schematic cross-sectional view illustrating the function of the diffusion preventing layer in the method for manufacturing a semiconductor device of the present invention.
  • a wiring metal 2 and a semiconductor chip 3 are prepared, and an insert material 4 is disposed therebetween.
  • the wiring metal 2 is made of high-purity Al as described above, and fine irregularities R are formed in advance on the joint surface, and a metal atom diffusion prevention layer L is further formed on the surface.
  • a metal atom diffusion prevention layer L is further formed on the surface.
  • the diffusion preventing layer L any material of Ni, TiN, WN, TiWN, and PtIr can be used, and can be formed by vapor deposition or sputtering.
  • a metal layer 3c made of the above-described metal A (a metal mainly composed of at least one of Al, Cu, Ag, and Au) is formed by plating, sputtering, or the like. .
  • An oxide film 3f is formed on the surface of the metal layer 3c.
  • the oxide film 3f of the metal layer 3c is mechanically broken as described above, and this The eutectic reaction generated at the fracture portion expands to the bonding surface, and the oxide film 3f is broken and discharged from the bonding surface together with the eutectic melt.
  • the metal layer 3c and the wiring metal 2 are directly joined with the bottom of the unevenness R left, and a piece of the oxide film 3f is formed on the bottom of the unevenness R. It remains dispersed in the eutectic melt phase Em.
  • FIG. 4C shows the state of the bonding interface immediately after bonding, and the residue Es at the bottom of the unevenness R is solidified in a state in which the eutectic melt phase Em entrains the oxide film 3f.
  • metal atoms, typically Zn, contained in the residue Es diffuse into the metal layer 3c.
  • the diffusion preventing layer L becomes an obstacle, the diffusion of metal atoms is prevented. Therefore, a decrease in the elongation of the wiring metal 2 and an increase in thermal stress can be avoided, and the durability reliability of the semiconductor device can be improved.
  • FIG. 5 shows an example in which a metal atom diffusion preventing layer L is formed inside the joint surface of the wiring metal 2.
  • the diffusion preventing layer L is formed inside the bonding surface (position just below the surface) and the outermost surface of the bonding surface is high-purity Al
  • an oxide film (aluminum oxide) 2f is formed on the surface (FIG. 5 (a)), except that the diffusion of metal atoms after standing at high temperature extends to the range from the surface of the wiring metal 2 to the diffusion prevention layer L (see FIG. 5 (d)). There is no change.
  • the structure of the semiconductor device manufactured by the manufacturing method of the present invention is a semiconductor device in which a semiconductor chip and a wiring metal are joined, and the semiconductor chip is at least selected from the group consisting of Al, Cu, Ag, and Au.
  • a metal A mainly composed of one kind is provided on the bonding surface, the wiring metal is made of high-purity Al, and has a metal atom diffusion prevention layer on the surface or inside of the bonding surface.
  • the metal A and the high-purity Al constituting the bonding surface are directly bonded at least at a part of the bonding interface, and the eutectic composition of Zn around the direct bonding portion and Al and other than Au contained in the metal A Exhausts containing at least one metal oxide are present (see FIG. 1 (e)).
  • the “eutectic composition of Zn” is a composition obtained by eutectic reaction of Zn contained in the insert material, at least one metal other than Au contained in the metal A, and Al of the wiring metal.
  • the “oxide” is a fragment of the oxide film formed on the surfaces of the metal A and the wiring metal (high purity Al).
  • the wiring metal can be disposed on an insulating ceramic substrate, and the ceramic substrate is attached to a base plate (cooling body or the like) via a back metal provided on the surface of the ceramic substrate on the side opposite to the semiconductor chip.
  • a bonded structure can also be used.
  • the same manufacturing method and bonding structure as the above-described bonding of the semiconductor chip and the wiring metal can be employed for bonding the back metal and the base plate.
  • the back metal when joining the back metal provided on the anti-semiconductor chip side of the insulating ceramic substrate onto the base plate, the back metal is made of high-purity Al, and the joining surface of the base plate is made of Al, Cu, Ag and It is made of metal B mainly composed of at least one selected from the group consisting of Au, and at least one of the two joint surfaces is provided with unevenness for breaking the oxide film on the joint surface, As a metal that causes a eutectic reaction with Al and at least one metal other than Au contained in the metal B between the bonding surfaces after forming a diffusion preventing layer of metal atoms on the surface or inside of the bonding surface The back metal and the base plate are heated while relatively pressurizing the insert material containing And discharged together with oxide film, bonded directly to a high-purity Al metal B constituting the bonding surface of the back metal and the base plate in at least a part of the bonding interface.
  • the wiring metal is disposed on the insulating ceramic substrate, and the back metal provided on the side of the insulating ceramic substrate opposite to the semiconductor chip is bonded on the base plate.
  • the metal is made of high-purity Al and has a diffusion preventing layer for metal atoms on the surface or inside of the bonding surface, and the base plate is mainly composed of at least one selected from the group consisting of Al, Cu, Ag and Au.
  • the high-purity Al and metal B constituting the back surface metal and the base plate joint surface are directly joined at least at a part of the joint interface, and Zn is shared around the direct joint portion.
  • the crystal composition and the discharge containing at least one oxide of metal other than Au contained in Al and the metal A are interposed.
  • the metal B constituting the bonding surface of the base plate may be a material different from the metal A constituting the bonding surface of the semiconductor chip, but it is desirable to use the same kind of material.
  • FIGS. 6A to 6D are schematic cross-sectional views showing several examples of embodiments of a semiconductor device according to the manufacturing method of the present invention.
  • a semiconductor device 1 shown in FIG. 6A includes a bus bar in which a wiring metal 2 made of high-purity Al is arranged on one side of an insulating ceramic substrate 12 on a cooling body (heat sink) 11.
  • the semiconductor chip 3 is bonded to the wiring metal 2 and fixed.
  • the semiconductor chip 3 includes a metal layer 3c made of the metal A on the bonding surface, and the metal layer 3c of the semiconductor chip 3 and the wiring metal 2 are directly bonded by the method described above. Yes.
  • a semiconductor device 1 shown in FIG. 6B includes a wiring metal 2 made of high-purity Al on the upper surface side of the insulating ceramic substrate 12 in the drawing, and a back metal 5 also made of high-purity Al on the lower surface side in the drawing.
  • a cooling body 11 is provided on the back metal side of the ceramic substrate 12. Then, the wiring metal 2 (high purity Al) on the upper surface side and the semiconductor chip 3 having the metal layer 3c made of the metal A on the bonding surface are bonded by the above method, and the back surface metal 5 (high purity Al) on the lower surface side.
  • the cooling body 11 (metal B) is similarly joined.
  • the semiconductor device 1 shown in FIG. 6C shows an example of a double-sided mounting type semiconductor device, whereas FIGS. 6A and 6B are single-sided mountings.
  • a bus bar provided with a wiring metal 2 made of high-purity Al is disposed on one side of an insulating ceramic substrate 12 along with a cooling body 11 on the upper and lower sides of a semiconductor chip 3 provided with a metal layer 3c.
  • the metal layer 3c made of metal A provided on the upper and lower surfaces of the semiconductor chip 3 and the wiring metal 2 made of high-purity Al of the bus bar are directly bonded by the above-described method.
  • the semiconductor device 1 shown in FIG. 6D uses a ceramic substrate 12 having a wiring metal 2 and a back metal 5 both made of high-purity Al on both surfaces of an insulating ceramic substrate 12. It is a double-sided mounting type. That is, as shown in FIG. 6C, the back surface metal 5 (high-purity Al) and the cooling body 11 (metal B) disposed on the back surface side of the ceramic substrate 12 are joined by the method of the present invention.
  • the structure is substantially the same as the form.
  • FIG. 7 is a schematic cross-sectional view showing a state before bonding of the semiconductor device of the present invention (however, the insert material 4 is omitted).
  • the semiconductor chip 3 shown in the figure has a metal layer 3c made of metal A on the bonding surface. I have.
  • the metal layer 3c can also be formed via an adhesion layer 3a or a barrier layer 3b as shown in FIG.
  • the insulating ceramic substrate 12 includes a wiring metal 2 made of high-purity Al on the upper surface side in the drawing, and a back metal 5 also made of high-purity Al on the lower surface side in the drawing. Concavities and convexities R are formed on the surface of the metal 5 (bonding surface between the semiconductor chip 3 and a base plate 11 described later).
  • the base plate (cooling body) 11 is made of metal B, and unevenness R is similarly formed on the joint surface with the back surface metal 5. At this time, the unevenness R may be formed by only one of the back metal 5 and the base plate 11. A diffusion prevention layer L is formed on the uneven surface of the wiring metal 2 and the back metal 5.
  • the semiconductor device bonded in this way has the metal atom diffusion prevention layer L formed on the surfaces of the wiring metal 2 and the back surface metal 5, even if the unevenness R remains on the bonding surface, it is exposed to a high temperature environment. Even so, diffusion from the solidified portion of the uneven portion to the wiring metal 2 and the back metal 5 is prevented. Therefore, the original mechanical performance of the wiring metal 2 and the back surface metal 5 can be maintained, and the durability reliability of the semiconductor device can be improved.
  • Example 1 (A) Semiconductor chip After depositing Ti / Ni / Ag by vapor deposition on the back surface of an SiC diode (semiconductor chip 3) having a size of 1.66 ⁇ 1.52 ⁇ 0.36 mm, Al is deposited on the deposition surface. (Metal A) was sputtered to a thickness of 6 ⁇ m to form a metal layer 3c, which was used as a bonding surface.
  • Base plate A plate material having a thickness of 1.0 mm made of industrial pure aluminum (metal B) defined as A1070 in JIS H 4000 was used as the base plate 11. Then, a unidirectional groove having a height of 0.1 mm and a pitch of 0.1 mm was formed on the surface (bonding surface with the back surface metal 5) by using a diamond tool, thereby forming the unevenness R.
  • metal B industrial pure aluminum
  • Example 2 The same operation as in Example 1 above, except that a 0.1 mm thick foil strip made of a Zn-4.0% Al-2.0% Cu alloy produced by a rapid cooling single roll method was used as the insert material. By repeating the above, the respective joining surfaces were joined to obtain the semiconductor device of Example 2.
  • Example 3 By repeating the same operation as in Example 1 above, except that Ti / Ni / Ag is formed by vapor deposition on the back surface of the SiC diode of the above size (semiconductor chip 3) and the bonding surface is Ag. The respective joining surfaces were joined to obtain the semiconductor device of Example 3.
  • Example 4 Except for forming the diffusion prevention layer L by sputtering WN on the outermost surfaces of the wiring metal 2 and the back surface metal 5, the same operation as in Example 1 is repeated to join the respective bonding surfaces. A semiconductor device of Example 4 was obtained.
  • Comparative Example 1 By repeating the same operation as in Example 1 without forming a diffusion prevention layer on the bonding surface of the wiring metal 2 and the back surface metal 5, the respective bonding surfaces are bonded to obtain the semiconductor device of Comparative Example 1. It was.

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Abstract

At the time of bonding a wiring metal (2), which is formed of high purity Al, and a semiconductor chip (3) by providing recesses and projections (R) on a bonding surface of the semiconductor chip (3), said bonding surface being formed of a metal (A) (Al, Ag or the like) and/or on a bonding surface of the wiring metal (2), and by generating eutectic reaction between an insertion material, which is provided between the bonding surfaces, and the bonding materials to be bonded, a metallic atom diffusion prevention layer (L) formed of Ni, TiN, WN or the like is previously formed on a surface of the bonding surface of the wiring metal (2).

Description

半導体装置の製造方法Manufacturing method of semiconductor device
　本発明は、半導体チップと配線金属とを接合して成る半導体装置、さらには、このような半導体装置を絶縁性セラミックス基板を介して、冷却体のようなベースプレート上に配置して成る半導体装置の製造方法と、このような方法により製造された半導体装置に関するものである。 The present invention relates to a semiconductor device in which a semiconductor chip and a wiring metal are joined, and further to a semiconductor device in which such a semiconductor device is disposed on a base plate such as a cooling body via an insulating ceramic substrate. The present invention relates to a manufacturing method and a semiconductor device manufactured by such a method.
　近年の半導体装置、特に、大電流密度の所謂ハイパワーモジュールと称する半導体装置においては、高温環境下でも使用可能であることが要求されている。
　そのため、半導体装置の実装構造においては、高温に保持されたり、高温熱サイクルを受けたりした場合の高温耐久性に優れた接合部が強く望まれている。また、環境保全の観点からすると、Ｐｂ（鉛）フリーの接合技術が必須となっている。 2. Description of the Related Art Recent semiconductor devices, particularly semiconductor devices called high power modules having a large current density, are required to be usable even in a high temperature environment.
Therefore, in a mounting structure of a semiconductor device, a joint having excellent high temperature durability when held at a high temperature or subjected to a high temperature thermal cycle is strongly desired. From the viewpoint of environmental protection, a Pb (lead) -free joining technique is essential.
　このような半導体装置の実装のための接合には、現状では、Ｓｎ（錫）－Ａｇ（銀）－Ｃｕ（銅）系のはんだが広く使われているが、使用温度がはんだの融点（例えば２００℃程度）以下に制限される。また、例えば、電極がＣｕである接合部においては、界面にＣｕ－Ｓｎ系の脆い金属間化合物層が生成し、高温耐久性に乏しいものとなる。
　そのため、接合部の高温耐久性を確保するために、いろいろな試みがなされている。 Currently, Sn (tin) -Ag (silver) -Cu (copper) -based solder is widely used for bonding for mounting such semiconductor devices, but the operating temperature is the melting point of the solder (for example, It is limited to about 200 ° C. or less. Also, for example, in a joint where the electrode is Cu, a Cu—Sn brittle intermetallic compound layer is formed at the interface, resulting in poor high-temperature durability.
Therefore, various attempts have been made to ensure the high temperature durability of the joint.
　例えば、金属ナノ粒子の活性な表面エネルギーを利用して、低温にて凝集、接合する低温接合工法が提案されている。この接合工法を用いれば、凝集した後の接合界面はバルク金属となるため、優れた高温耐久性を有する。しかし、金属ナノ粒子として、Ａｕ（金）のような貴金属を用い、このような金属ナノ粒子の表面に有機物を修飾したような構造をとるため、粒子が凝集した構造となり、しかも有機物が接合プロセス時にガス化して、残存することから接合部にはボイドが存在するため、継手強度のバラツキの大きいものとなる。 For example, a low-temperature bonding method has been proposed in which active surface energy of metal nanoparticles is used to agglomerate and bond at low temperatures. If this bonding method is used, the bonded interface after agglomeration becomes a bulk metal, and therefore has excellent high temperature durability. However, a noble metal such as Au (gold) is used as the metal nanoparticle, and the surface of the metal nanoparticle is modified with an organic substance, resulting in a structure in which the particles are agglomerated, and the organic substance is a bonding process. Since the gas is sometimes gasified and remains, voids are present in the joint, resulting in large variations in joint strength.
　また、高温はんだとしてはこの他に、Ａｕ系の組成を有するものとして、Ａｕ－Ｇｅ（ゲルマニウム）系などのはんだがあるが、これらも、貴金属であるＡｕを用いているため、コスト的な問題ばかりでなく、接合界面に金属間化合物層を生成したり、カーケンダルボイドを生成したりするため、長期的な信頼性に問題がある。 In addition to this, there are Au-Ge (germanium) -based solders as other high-temperature solders that have an Au-based composition, but these also use a noble metal Au, which is a cost problem. In addition, since an intermetallic compound layer is generated at the bonding interface or a Kirkendall void is generated, there is a problem in long-term reliability.
　一方、接合面に生成された酸化皮膜による接合品質に対する影響を排除し、健全な接合部を形成する観点から、母材金属と共晶反応を生ずるＺｎ（亜鉛）のような金属を含むインサート材を接合面間に介在させた状態で加圧、加熱することにより、接合界面に共晶反応を生じさせて接合することが知られている。すなわち、母材金属とインサート材との間に共晶反応を生じさせることによって、母材表面の酸化皮膜を除去し、生じた共晶反応溶融物と共に接合面から排出することが可能になる。
　このとき、母材金属とインサート材との直接的な接触を促進し、共晶反応の起点を早期に形成して、上記接合プロセスをより円滑なものとするべく、酸化皮膜を破壊するための凹凸構造を接合面に形成することが提案されている（引用文献１参照）。 On the other hand, an insert material containing a metal such as Zn (zinc) that causes a eutectic reaction with the base metal from the viewpoint of eliminating the influence on the bonding quality caused by the oxide film formed on the bonding surface and forming a sound bonded portion. It is known that bonding is performed by causing a eutectic reaction at the bonding interface by pressurizing and heating in a state of interposing between the bonding surfaces. That is, by generating a eutectic reaction between the base metal and the insert material, the oxide film on the surface of the base material can be removed and discharged together with the generated eutectic reaction melt from the joint surface.
At this time, the direct contact between the base metal and the insert material is promoted, the starting point of the eutectic reaction is formed at an early stage, and the oxide film is destroyed in order to make the joining process smoother. It has been proposed to form a concavo-convex structure on the joint surface (see cited document 1).
日本国特開２０１３－７８７９３号公報Japanese Unexamined Patent Publication No. 2013-78793
　このような接合方法を半導体装置における半導体チップと配線金属に適用するにあたっては、配線金属の純度を上げることによって降伏点を下げ、半導体チップと配線金属間の熱膨張係数差に基づく熱応力の発生を少なくし、半導体装置の耐久信頼性の向上を図るようにしていた。
　しかしながら、使用環境状態や凹凸構造の形状によっては、凹凸構造が接合面に残存し、凹凸底部に残留する共晶反応液相の凝固物中に含まれるインサート材中の金属が配線金属の側に拡散することがあることが判明した。そして、このような金属の拡散が生じると配線金属の純度が下がり、降伏点の上昇による熱応力の増大、伸びの低下が生じ、耐久信頼性が損なわれる可能性があることが判った。 When such a bonding method is applied to a semiconductor chip and wiring metal in a semiconductor device, the yield point is lowered by increasing the purity of the wiring metal, and thermal stress is generated based on the difference in thermal expansion coefficient between the semiconductor chip and the wiring metal. In order to improve the durability and reliability of the semiconductor device.
However, depending on the use environment and the shape of the concavo-convex structure, the concavo-convex structure remains on the joint surface, and the metal in the insert material contained in the solidified eutectic reaction liquid phase remaining on the concavo-convex bottom is on the wiring metal side. It has been found that it may spread. Then, it has been found that when such metal diffusion occurs, the purity of the wiring metal decreases, the thermal stress increases due to an increase in the yield point, and the elongation decreases, which may impair durability reliability.
　本発明は、半導体装置の実装構造に適用される従来の接合技術における上記課題に鑑みてなされたものであって、その目的とするところは、接合界面に凹凸構造が残存したとしても、この中に含まれる金属の拡散を防止し、もって装置の耐久信頼性を確保することができる半導体装置の製造方法を提供することにある。また、このような製造方法による耐久性に優れた半導体装置を提供することにある。 The present invention has been made in view of the above problems in the conventional bonding technology applied to the mounting structure of a semiconductor device. The object of the present invention is that even if a concavo-convex structure remains at the bonding interface, It is an object of the present invention to provide a method of manufacturing a semiconductor device that can prevent diffusion of metal contained in the semiconductor device and thereby ensure durability reliability of the device. Another object of the present invention is to provide a semiconductor device having excellent durability by such a manufacturing method.
　本発明者らは、上記目的を達成すべく、鋭意検討を重ねた結果、高純度Ａｌから成る配線金属の接合面の表面に、例えば、ＮｉやＴｉＮなどから成る金属原子の拡散防止層を形成することによって、上記課題が解決できることを見出し、本発明を完成するに到った。 As a result of intensive studies to achieve the above object, the present inventors have formed a metal atom diffusion prevention layer made of, for example, Ni or TiN on the surface of the bonding surface of the wiring metal made of high purity Al. As a result, the present inventors have found that the above problems can be solved, and have completed the present invention.
　すなわち、本発明は上記知見に基づくものであって、本発明の半導体装置の製造方法においては、接合面がＡｌ、Ｃｕ、Ａｇ及びＡｕから成る群より選ばれた少なくとも１種を主成分とする金属Ａから成る半導体チップと、高純度Ａｌから成る配線金属とを接合するに際して、上記両接合面の少なくとも一方に接合面の酸化皮膜を破壊するための凹凸を設けると共に、上記配線金属の接合面の表面又は内部に金属原子の拡散防止層を形成した上で、両接合面間にＡｌと上記金属Ａに含まれるＡｕ以外の少なくとも１種の金属とそれぞれ共晶反応を生じる金属としてＺｎを含むインサート材を介在させ、上記半導体チップと配線金属を相対的に加圧しつつ加熱し、接合界面に生じた共晶反応溶融物を上記酸化皮膜と共に排出して、接合界面の少なくとも一部において上記半導体チップ及び配線金属の接合面を構成する金属Ａと高純度Ａｌとを直接接合することを特徴とする。 That is, the present invention is based on the above knowledge, and in the semiconductor device manufacturing method of the present invention, the bonding surface is mainly composed of at least one selected from the group consisting of Al, Cu, Ag, and Au. When joining the semiconductor chip made of metal A and the wiring metal made of high-purity Al, at least one of the joint surfaces is provided with irregularities for breaking the oxide film on the joint surface, and the joint surface of the wiring metal In addition, a metal atom diffusion prevention layer is formed on the surface or the inside of ZnO, and Zn is contained as a metal that causes a eutectic reaction with Al and at least one metal other than Au contained in the metal A between both joint surfaces. The insert material is interposed, the semiconductor chip and the wiring metal are heated while being relatively pressurized, and the eutectic reaction melt generated at the bonding interface is discharged together with the oxide film, Without even wherein the bonding the metal A and a high-purity Al which constitutes the bonding surface of the semiconductor chip and the interconnect metal in some direct.
　　また、本発明の半導体装置は、半導体チップと配線金属とが接合されて成るものであって、上記半導体チップはＡｌ、Ｃｕ、Ａｇ及びＡｕから成る群より選ばれた少なくとも１種を主成分とする金属Ａを接合面に備え、上記配線金属は高純度Ａｌから成ると共に、該接合面の表面又は内部に金属原子の拡散防止層を有し、これら半導体チップ及び配線金属の接合面を構成する金属Ａと高純度Ａｌとが接合界面の少なくとも一部において直接接合され、当該直接接合部の周囲にＺｎの共晶組成物と、Ａｌ及び上記金属Ａに含まれるＡｕ以外の少なくとも１種の金属の酸化物を含む排出物が介在していることを特徴としている。 The semiconductor device of the present invention is formed by bonding a semiconductor chip and a wiring metal, and the semiconductor chip has at least one selected from the group consisting of Al, Cu, Ag and Au as a main component. The wiring metal is made of high-purity Al and has a metal atom diffusion prevention layer on or inside the bonding surface, and constitutes the bonding surface of the semiconductor chip and the wiring metal. Metal A and high-purity Al are directly bonded at at least a part of the bonding interface, Zn eutectic composition around the direct bonding part, and at least one metal other than Au contained in Al and metal A It is characterized by the presence of effluents containing the oxides.
　本発明によれば、高純度Ａｌから成る配線金属の接合面の表面又は内部に金属原子の拡散を防止する拡散防止層を形成している。したがって、接合面の凹凸構造の底部に共晶反応液相の凝固物が残留していたとしても、凝固物中の金属原子が配線金属側へ拡散することがなく、配線金属の純度低下による降伏点の上昇、伸びの低下、熱応力の増大を防止することができ、装置の耐久信頼性が向上する。 According to the present invention, the diffusion preventing layer for preventing the diffusion of metal atoms is formed on the surface or inside of the bonding surface of the wiring metal made of high purity Al. Therefore, even if the eutectic reaction liquid phase coagulum remains at the bottom of the concavo-convex structure of the joint surface, the metal atoms in the coagulum do not diffuse to the wiring metal side, and the yield is reduced due to the decrease in the purity of the wiring metal. It is possible to prevent an increase in point, a decrease in elongation, and an increase in thermal stress, and the durability reliability of the apparatus is improved.
（ａ）～（ｅ）は本発明の半導体装置の製造方法による半導体チップと配線金属との接合過程を概略的に示す工程図である。(A)-(e) is process drawing which shows roughly the joining process of the semiconductor chip and wiring metal by the manufacturing method of the semiconductor device of this invention. （ａ）～（ｃ）は本発明の半導体装置の製造方法において接合部に形成する凹凸構造の形状例を示す斜視図である。(A)-(c) is a perspective view which shows the example of the shape of the uneven structure formed in a junction part in the manufacturing method of the semiconductor device of this invention. 本発明の製造方法による半導体装置の一方を構成する半導体チップの構造を示す概略断面図である。It is a schematic sectional drawing which shows the structure of the semiconductor chip which comprises one side of the semiconductor device by the manufacturing method of this invention. （ａ）～（ｄ）は本発明の半導体装置の製造方法における拡散防止層を接合面の表面に形成した例を示す概略断面図である。(A)-(d) is a schematic sectional drawing which shows the example which formed the diffusion prevention layer in the surface of a joining surface in the manufacturing method of the semiconductor device of this invention. （ａ）～（ｄ）は本発明の半導体装置の製造方法における拡散防止層を接合面の内部に形成した例を示す概略断面図である。(A)-(d) is a schematic sectional drawing which shows the example which formed the diffusion prevention layer in the inside of a joining surface in the manufacturing method of the semiconductor device of this invention. （ａ）～（ｄ）は本発明の製造方法による半導体装置の実施形態例を示すそれぞれ概略断面図である。(A)-(d) is a schematic sectional drawing which respectively shows the embodiment of the semiconductor device by the manufacturing method of this invention. 本発明の実施例に用いた半導体装置の構成を説明する概略断面図である。It is a schematic sectional drawing explaining the structure of the semiconductor device used for the Example of this invention.
　以下に、本発明の半導体装置の製造方法について、さらに詳細、かつ具体的に説明する。なお、本明細書において「％」は、特記しない限り、質量百分率を意味するものとする。 Hereinafter, the semiconductor device manufacturing method of the present invention will be described in more detail and specifically. In the present specification, “%” means mass percentage unless otherwise specified.
　本発明の半導体装置の製造方法においては、Ａｌ、Ｃｕ、Ａｇ及びＡｕから成る群より選ばれた少なくとも１種を主成分とする金属Ａから成る接合面を備えた半導体チップと、高純度Ａｌから成る配線金属とを接合するに際して、両接合面の少なくとも一方に接合面の酸化皮膜を破壊するための凹凸を設ける。また、上記配線金属の接合面の表面又は内部に金属原子の拡散防止層を形成しておく。そして、両接合面間にＡｌと上記金属Ａに含まれるＡｕ以外の少なくとも１種の金属とそれぞれ共晶反応を生じる金属としてＺｎを含むインサート材を介在させる。
　なお、本発明において、「高純度Ａｌ」とは、Ａｌを９９．０％以上含有するものを意味する。
In the method for manufacturing a semiconductor device of the present invention, a semiconductor chip having a bonding surface made of metal A mainly composed of at least one selected from the group consisting of Al, Cu, Ag and Au, and high-purity Al. When joining the wiring metal to be formed, at least one of the joint surfaces is provided with unevenness for breaking the oxide film on the joint surface. Further, a metal atom diffusion preventing layer is formed on the surface or inside of the bonding surface of the wiring metal. Then, an insert material containing Zn as a metal that causes a eutectic reaction with at least one metal other than Au contained in Al and the metal A is interposed between both joint surfaces.
In the present invention, “high purity Al” means that containing 99.0% or more of Al.
　この状態で、半導体チップと配線金属を相対的に加圧すると共に加熱し、接合面に形成されている酸化皮膜を凹凸により破壊して、半導体チップの金属Ａ及び配線金属とインサート材とをそれぞれ接触させ、接合界面に金属Ａに含まれる金属及び配線金属中のＡｌとインサート材に含まれる金属との共晶反応を生じさせる。
　そして、この共晶反応溶融物を酸化皮膜と共に排出して、接合界面の少なくとも一部において上記半導体チップの金属Ａと配線金属とを直接接合し、半導体チップと配線金属が強固に接合される。 In this state, the semiconductor chip and the wiring metal are relatively pressurized and heated, and the oxide film formed on the bonding surface is broken by the unevenness so that the metal A of the semiconductor chip and the wiring metal and the insert material are in contact with each other. The eutectic reaction of the metal contained in the metal A and the Al contained in the wiring metal and the metal contained in the insert material is caused at the bonding interface.
Then, the eutectic reaction melt is discharged together with the oxide film, and the metal A and the wiring metal of the semiconductor chip are directly bonded at at least a part of the bonding interface, so that the semiconductor chip and the wiring metal are firmly bonded.
　このようにして接合された半導体装置においては、接合面に凹凸構造が残存し、その中に共晶反応液相の凝固物が残留していたとしても、拡散防止層によって凝固物中の金属原子の配線金属へ拡散が阻止されるので、配線金属の降伏点が上昇したり、伸びが低下したりすることがなく、装置の耐久信頼性を向上させることができる。 In the semiconductor device bonded in this way, even if a concavo-convex structure remains on the bonding surface and solidified material in the eutectic reaction liquid phase remains therein, the metal atoms in the solidified material are prevented by the diffusion preventing layer. Since diffusion to the wiring metal is prevented, the yield point of the wiring metal does not increase and the elongation does not decrease, and the durability reliability of the device can be improved.
　共晶反応による溶融は、２種以上の金属が相互拡散して生じた相互拡散域の組成が共晶組成となった場合に生じ、保持温度が共晶温度以上であれば共晶反応により液相が形成される。例えば、Ｚｎ－Ａｌ系合金の場合、Ａｌの融点は６６０℃、Ｚｎの融点は４１９．５℃であり、この共晶金属はそれぞれの融点より低い３８２℃にて溶融する。
　したがって、両金属の清浄面を接触させ、３８２℃以上に加熱保持すると反応（共晶溶融）が生じ、Ａｌ－９５％Ｚｎが共晶組成となるが、共晶反応自体は合金成分に無関係な一定の変化であり、インサート材の組成は共晶反応の量を増減するに過ぎない。 Melting due to the eutectic reaction occurs when the composition of the interdiffusion region formed by mutual diffusion of two or more metals becomes the eutectic composition. A phase is formed. For example, in the case of a Zn—Al alloy, the melting point of Al is 660 ° C., the melting point of Zn is 419.5 ° C., and this eutectic metal melts at 382 ° C. which is lower than the respective melting points.
Therefore, when the clean surfaces of both metals are brought into contact and heated to 382 ° C. or higher, a reaction (eutectic melting) occurs and Al-95% Zn has a eutectic composition, but the eutectic reaction itself is independent of the alloy components. It is a constant change, and the composition of the insert material only increases or decreases the amount of eutectic reaction.
　一方、一般的な金属材料の表面には酸化皮膜が存在するが、接合過程における加圧によって、凹凸の先端に応力が集中するため、比較的低い加圧力によって、チップへのダメージを与えることなく酸化皮膜を破壊することができる。そして、この破壊部を介して半導体チップの金属Ａと配線金属（Ａｌ）のそれぞれとインサート材とが接触し、これらの間に共晶反応が生じる。 On the other hand, there is an oxide film on the surface of a general metal material, but stress is concentrated on the tip of the unevenness due to pressurization in the joining process, so the chip is not damaged by a relatively low pressure. The oxide film can be destroyed. Then, each of the metal A and the wiring metal (Al) of the semiconductor chip and the insert material come into contact with each other through the fracture portion, and a eutectic reaction occurs between them.
　共晶反応による液相の生成によって近傍の酸化皮膜が破砕、分解され、さらに共晶溶融が全面に拡がっていくことによって、酸化皮膜破壊が拡大し、促進され、接合面の酸化皮膜が低温度（共晶温度）で除去されるので、ろう材層を介することなく、金属Ａと金属Ｂとのダイレクトな接合が可能となる。
　したがって、Ｐｂが含まれない金属ＡとＡｌとの直接接合によって強度が確保されることから、高温保持した場合にも脆い金属間化合物層やカーケンダルボイドを生成せず、優れた高温耐久性を備えたＰｂフリーの接合部を備えた半導体装置を製造することができる。 The neighboring oxide film is crushed and decomposed by the formation of a liquid phase by the eutectic reaction, and further, eutectic melting spreads to the entire surface, thereby expanding and promoting the oxide film breakage, and lowering the oxide film on the joint surface at a low temperature. Since it is removed at (eutectic temperature), the metal A and the metal B can be directly joined without going through the brazing material layer.
Therefore, the strength is ensured by the direct joining of the metal A and Al not containing Pb, so that even when kept at a high temperature, a brittle intermetallic compound layer and a Kirkendall void are not generated, and an excellent high temperature durability is achieved. The semiconductor device provided with the provided Pb-free junction can be manufactured.
　共晶組成は相互拡散によって自発的達成されるため、組成のコントロールは必要なく、必須条件は母材（金属Ａ、Ａｌ）とインサート材に含まれる金属の間に、低融点の共晶反応が生成することである。
　このとき、接合面には、半導体チップの金属Ａに含まれる金属と配線金属のＡｌと、インサート材に含まれる金属との共晶反応をそれぞれ生じさせることが必要であり、そのためには、両共晶温度の高い方の温度に加熱する必要がある。 Since the eutectic composition is spontaneously achieved by interdiffusion, there is no need to control the composition, and the essential condition is that a low-melting eutectic reaction occurs between the base material (metal A, Al) and the metal contained in the insert material. Is to generate.
At this time, it is necessary to cause eutectic reaction between the metal contained in the metal A of the semiconductor chip, Al of the wiring metal, and the metal contained in the insert material on the joint surface. It is necessary to heat to the higher eutectic temperature.
　図１（ａ）～（ｅ）は、本発明による半導体装置の製造方法における半導体チップと配線金属の接合プロセスについて説明する工程図である。なお、拡散防止層の形成については、接合プロセスに直接関与しないことから、この図からは省略している。 1 (a) to 1 (e) are process diagrams for explaining a bonding process between a semiconductor chip and a wiring metal in a method of manufacturing a semiconductor device according to the present invention. The formation of the diffusion preventing layer is omitted from this figure because it is not directly involved in the bonding process.
　まず、図１（ａ）に示すように、配線金属２と半導体チップ３の間に、インサート材４を配置する。
　このとき、配線金属２は、高純度Ａｌから成るものであって、その接合面には、予め微細な凹凸Ｒが形成してあると共に、その表面には、後述するように拡散防止層（図示せず）が形成されている。一方、半導体チップ３の接合面には、金属Ａとして、例えばＡｌ、ＣｕあるいはＡｇを主成分とする金属層３ｃがめっきやスパッタリングなどによって形成されている。なお、これら配線金属２や金属層３ｃの表面には、酸化皮膜２ｆ、３ｆが生成している。 First, as shown in FIG. 1A, the insert material 4 is disposed between the wiring metal 2 and the semiconductor chip 3.
At this time, the wiring metal 2 is made of high-purity Al, and fine unevenness R is formed in advance on the joint surface, and a diffusion prevention layer (see FIG. (Not shown) is formed. On the other hand, a metal layer 3c containing, for example, Al, Cu, or Ag as a main component is formed as a metal A on the bonding surface of the semiconductor chip 3 by plating, sputtering, or the like. Note that oxide films 2f and 3f are formed on the surfaces of the wiring metal 2 and the metal layer 3c.
　ここで、金属Ａの選択範囲としては、Ａｌ、Ｃｕ、Ａｇ及びＡｕから成る群から選ばれる純金属や、これら金属間の合金を含む種々の金属を採用することができるが、同種材同士の接合、すなわちＡｌ系材料とした方が界面の劣化反応の起点がなくなるため、耐久信頼性のより高い接合が可能となる。なお、ここで言う「同種材」とは、Ａｌを主成分とする金属であることを意味し、必ずしも配線金属２と同じ高純度Ａｌである必要はない。 Here, as the selection range of the metal A, a pure metal selected from the group consisting of Al, Cu, Ag and Au, and various metals including an alloy between these metals can be adopted. Joining, that is, using an Al-based material eliminates the starting point of the degradation reaction at the interface, so that joining with higher durability reliability is possible. The “same material” as used herein means a metal containing Al as a main component, and is not necessarily the same high-purity Al as the wiring metal 2.
　上記配線金属２の接合面に形成する凹凸Ｒの形状としては、応力を集中させて、酸化皮膜の破壊を促進させる機能さえあれば、その形状や数に制限はなく、例えば、図２（ａ）～（ｃ）に示すようなものを採用することができる。
　すなわち、図２（ａ）に示すように、台形状断面の凹凸構造として、凸部先端を略平面とすれば、応力集中度は若干低下するとしても、応力集中手段の形成が容易となり、加工費を削減することができる。 The shape of the unevenness R formed on the joint surface of the wiring metal 2 is not limited as long as it has a function of concentrating stress and promoting the destruction of the oxide film. For example, FIG. ) To (c) can be employed.
That is, as shown in FIG. 2 (a), if the convex-convex tip is made to be a substantially flat surface as a trapezoidal cross-sectional concavo-convex structure, the stress concentration means can be easily formed even if the stress concentration level is slightly reduced. Costs can be reduced.
　また、図２（ｂ）に示すように、三角柱を並列させたような凹凸構造を採用することも可能であり、これによって、凹凸構造の凸部先端が線状のものとなり、応力集中度を高めて、酸化皮膜の破断効果を向上させることができる。
　さらに、図２（ｃ）に示すように、四角錐を縦横方向に並列させた凹凸構造を採用することもでき、凹凸構造の凸部先端が点状となることから、さらに応力集中度を高めて、酸化皮膜の破断性能を向上させることができる。 In addition, as shown in FIG. 2B, it is also possible to adopt a concavo-convex structure in which triangular prisms are arranged in parallel, whereby the convex tip of the concavo-convex structure becomes linear, and the stress concentration degree is increased. This can enhance the effect of breaking the oxide film.
Furthermore, as shown in FIG. 2 (c), it is possible to adopt a concavo-convex structure in which square pyramids are juxtaposed in the vertical and horizontal directions. Thus, the breaking performance of the oxide film can be improved.
　凹凸Ｒの形状としては、上記したように、応力を集中させて、酸化皮膜の破壊を促進させる機能さえあれば、特に限定されることはなく、上記の他には、波形やかまぼこ形、半球状など凸部先端を曲面とすることも可能である。なお、当該曲面の曲率半径は、小さいほど応力集中が顕著なものとなって、酸化皮膜が破壊し易くなることは言うまでもない。 As described above, the shape of the unevenness R is not particularly limited as long as it has a function of concentrating stress and promoting the destruction of the oxide film as described above. It is also possible to make the tip of the convex part such as a shape a curved surface. Needless to say, the smaller the radius of curvature of the curved surface, the more the stress concentration becomes more prominent, and the oxide film is easily broken.
　このような凹凸Ｒは、例えば、切削加工、研削加工、塑性加工（ローラ加工）、レーザ加工、放電加工、エッチング加工、リソグラフィーなどによって形成することができ、その形成方法としては、特に限定されるものではない。これら加工方法のうち、塑性加工によれば、非常に低コストで形成が可能である。
　なお、微細凹凸の寸法、形状としては、アスペクト比（高さ／幅）：０．００１以上、ピッチ：１μｍ以上で、望ましくはアスペクト比０．１以上、ピッチ：１０μｍ以上である。 Such unevenness R can be formed by, for example, cutting, grinding, plastic processing (roller processing), laser processing, electric discharge processing, etching processing, lithography, etc., and the formation method is particularly limited. It is not a thing. Of these processing methods, plastic processing enables formation at a very low cost.
The dimensions and shape of the fine irregularities are an aspect ratio (height / width): 0.001 or more, a pitch: 1 μm or more, and preferably an aspect ratio of 0.1 or more and a pitch: 10 μm or more.
　一方、半導体チップ３は、上記したように接合面側に、金属Ａから成る金属層３ｃを備えているが、図３に示すように、ＳｉＣやＳｉ、ＧａＮなどから成る半導体チップ本体３と金属層３ｃの間に、密着層３ａ及びバリヤ層３ｂを介在させることができる。 On the other hand, the semiconductor chip 3 is provided with the metal layer 3c made of metal A on the joint surface side as described above. However, as shown in FIG. 3, the semiconductor chip body 3 made of SiC, Si, GaN, etc. An adhesion layer 3a and a barrier layer 3b can be interposed between the layers 3c.
　バリヤ層３ｂは、金属層３ｃの成分がチップ本体内に拡散するのを防止する機能を有し、Ｎｉ（ニッケル）やＰｔ－Ｉｒ（白金－イリジウム）などを適用することができる。
　一方、密着層３ａは、上記バリヤ層３ｂとチップ本体３との密着性を向上させる機能を有し、例えば、Ｔｉ（チタン）、Ｃｒ（クロム）などを用いることができる。 The barrier layer 3b has a function of preventing the components of the metal layer 3c from diffusing into the chip body, and Ni (nickel), Pt—Ir (platinum-iridium), or the like can be applied.
On the other hand, the adhesion layer 3a has a function of improving the adhesion between the barrier layer 3b and the chip body 3, and for example, Ti (titanium), Cr (chromium), or the like can be used.
　インサート材４は、上記金属Ａに含まれるＡｕ以外、すなわちＡｌ、Ｃｕ及びＡｇのうちの少なくとも１種の金属元素と、配線金属に含まれるＡｌのそれぞれと共晶反応を生じる金属であるＺｎを含むものであって、例えば、Ｚｎを主成分とする金属（純亜鉛、亜鉛合金）が用いられる。 The insert material 4 is made of Zn, which is a metal that causes a eutectic reaction with at least one metal element of Al, Cu, and Ag and Al contained in the wiring metal, other than Au contained in the metal A. For example, a metal (pure zinc or zinc alloy) containing Zn as a main component is used.
　また、Ｚｎと、Ａｌ、Ｍｇ、Ｃｕ、Ａｇ及びＳｎから成る群より選ばれた少なくとも１種の金属を主成分とする合金、例えばＺｎとＡｌを主成分とする合金、ＺｎとＡｌとＭｇを主成分とする合金、ＺｎとＡｌとＣｕを主成分とする合金を用いることもできる。
　すなわち、ＺｎとＡｌを含む合金系の共晶温度は低く（Ｚｎ－Ａｌ系合金では３８２℃、Ｚｎ－Ａｌ－Ｍｇ系合金では３３０℃）、このような低い温度で、母材の軟化や変形を惹起することなく、接合を阻害する酸化皮膜を接合界面から除去して、両部材を接合することができる。 Further, an alloy containing Zn and Al, Mg, Cu, Ag, and Sn as a main component, for example, an alloy containing Zn and Al as main components, Zn, Al, and Mg An alloy containing a main component or an alloy containing Zn, Al, and Cu as main components can also be used.
That is, the eutectic temperature of the alloy system containing Zn and Al is low (382 ° C. for the Zn—Al based alloy and 330 ° C. for the Zn—Al—Mg based alloy). Both members can be joined by removing the oxide film that hinders the joining from the joining interface without inducing.
　さらに、インサート材４には、半導体チップ３の接合面を構成する金属Ａに含まれる金属や、配線金属に含まれるＡｌを含有させることができ、インサート材と被接合部材との反応性の向上や、接合界面の親和性の向上のためから望ましい。 Furthermore, the insert material 4 can contain metal contained in the metal A constituting the bonding surface of the semiconductor chip 3 and Al contained in the wiring metal, and the reactivity between the insert material and the member to be joined is improved. In addition, it is desirable for improving the affinity of the bonding interface.
　上記インサート材４の厚さとしては、２０μｍ以上、２００μｍ以下とすることが望ましい。
　インサート材４の厚さが２０μｍに満たない場合、酸化皮膜の排出が不十分となったり、接合部のシール性が低下し、接合中に酸化が進み接合部の強度特性を低下させたりする。一方、２００μｍを超えると、余剰部分の排出のために高い加圧力が必要となったり、界面への残存が多くなり、継ぎ手性能を低下させたりすることがある。 The thickness of the insert material 4 is desirably 20 μm or more and 200 μm or less.
When the thickness of the insert material 4 is less than 20 μm, the oxide film is not sufficiently discharged, the sealing performance of the joint portion is lowered, and oxidation progresses during joining and the strength characteristics of the joint portion are lowered. On the other hand, if it exceeds 200 μm, a high pressurizing force may be required for discharging the surplus portion, or the residual pressure at the interface may increase and the joint performance may be deteriorated.
　なお、本発明においては、金属Ａやインサート材における「主成分」とは、それら金属成分の含有量が合計で８０％以上であることを意味するものとする。 In the present invention, the “main component” in the metal A or the insert material means that the total content of these metal components is 80% or more.
　そして、図１（ａ）に示した状態で、半導体チップ３と配線金属２を相対的に加圧して、これらをインサート材４を介して密着させ、さらに加圧しながら加熱を開始する。
　すると、図１（ｂ）に示すように、凹凸Ｒの凸部先端が接触した部位の応力が局所的に急激に上昇し、加圧力をさほど増すことなく、金属層３ｃの酸化被膜３ｆが機械的に破壊され、新生面が露出する。また、酸化被膜３ｆと共に、微細凹凸２ｒ先端の酸化皮膜２ｆも破壊され、配線金属２の新生面が露出する。 Then, in the state shown in FIG. 1A, the semiconductor chip 3 and the wiring metal 2 are relatively pressurized, brought into close contact via the insert material 4, and heating is started while further pressing.
Then, as shown in FIG. 1 (b), the stress at the portion where the tip of the convex portion of the concavo-convex R contacts abruptly increases locally, and the oxide film 3f of the metal layer 3c is mechanically formed without increasing the applied pressure so much. Is destroyed and the new surface is exposed. In addition to the oxide film 3f, the oxide film 2f at the tip of the fine irregularities 2r is also destroyed, and the new surface of the wiring metal 2 is exposed.
　金属層３ｃ及び配線金属２とインサート材４の間で拡散が生じ、共晶反応が発生する温度に到達すると、金属層３ｃ及び配線金属２中の金属元素との間にそれぞれ共晶反応が生じ、共晶溶融相が発生する。
　そして、この共晶溶融範囲が接合界面全体に拡がっていくことにより、金属層３ｃ及び配線金属２の酸化被膜３ｆ、２ｆが表面から除去され、図１（ｃ）に示すように、酸化皮膜３ｆ、２ｆの欠片が共晶溶融相中に分散する。 When diffusion occurs between the metal layer 3c and the wiring metal 2 and the insert material 4 and reaches a temperature at which a eutectic reaction occurs, a eutectic reaction occurs between the metal layer 3c and the metal element in the wiring metal 2, respectively. A eutectic melt phase is generated.
The eutectic melting range extends to the entire bonding interface, so that the metal layer 3c and the oxide films 3f and 2f of the wiring metal 2 are removed from the surface. As shown in FIG. The 2f fragments are dispersed in the eutectic melt phase.
　続く加圧によって、図１（ｄ）に示すように、共晶反応溶融物が接合界面から排出され、この液相中に分散されていた酸化皮膜３ｆ、２ｆの欠片もその大部分が共晶溶融物と共に接合界面から押し出され、金属層３ｃ及び配線金属２の新生面がそれぞれ露出し、接合界面にこれらに含まれる成分元素の拡散反応が生じる。
　これによって、図１（ｅ）に示すように、配線金属２と半導体チップ３の金属層３ｃとの接合、すなわち金属ＡとＡｌとの直接的な接合が達成される。このとき、共晶反応生成物や酸化皮膜、インサート材に由来する金属などを含む微量の混合物が接合界面に残存することがあり得るが、金属同士の直接接合部が形成されている限り、強度上の問題となることはない。また、このような残存物は、電気伝導や熱伝導に寄与することになる。 By subsequent pressurization, as shown in FIG. 1 (d), the eutectic reaction melt is discharged from the bonding interface, and most of the fragments of the oxide films 3f and 2f dispersed in the liquid phase are eutectic. It is extruded together with the melt from the bonding interface, and the new surfaces of the metal layer 3c and the wiring metal 2 are exposed, and the diffusion reaction of the component elements contained therein occurs at the bonding interface.
As a result, as shown in FIG. 1 (e), bonding between the wiring metal 2 and the metal layer 3c of the semiconductor chip 3, that is, direct bonding between the metal A and Al is achieved. At this time, a small amount of mixture containing eutectic reaction product, oxide film, metal derived from insert material, etc. may remain at the bonding interface, but as long as the metal-to-metal direct bonding portion is formed, the strength It will not be a problem. Moreover, such a residue contributes to electric conduction and heat conduction.
　なお、図１においては、凹凸Ｒを配線金属２の側に形成した例を示したが、これに限定されることはなく、微細凹凸の形成位置については、上記のように配線金属２と半導体チップ３の接合面の一方に形成するほか、接合面の両方に設けることができる。両面に形成することによって、酸化皮膜の破壊起点をより多くすることができる。 Although FIG. 1 shows an example in which the unevenness R is formed on the wiring metal 2 side, the present invention is not limited to this, and the formation position of the fine unevenness is as described above. In addition to being formed on one of the bonding surfaces of the chip 3, it can be provided on both of the bonding surfaces. By forming it on both surfaces, it is possible to increase the breakdown starting point of the oxide film.
　また、上記では、薄板上のインサート材４を配線金属２の上に載置しただけの例を示したが、組成や形状（厚さ）などに関する選択の自由度が高いことから、箔の形態で両材料の間に挟み込むことが望ましい。
　この他に、めっきやパウダーデポジション法によって、インサート材金属を配線金属２や半導体チップ３の一方あるいは両方の接合面に予め被覆しておくことも可能であり、この場合には、被覆によって酸化皮膜の生成を防止できる。 Moreover, although the example which only mounted the insert material 4 on a thin plate on the wiring metal 2 was shown above, since the freedom degree of selection regarding a composition, a shape (thickness), etc. is high, the form of foil It is desirable to sandwich between the two materials.
In addition, it is also possible to preliminarily coat the joint surface of one or both of the wiring metal 2 and the semiconductor chip 3 by plating or a powder deposition method. Formation of a film can be prevented.
　本発明の製造方法における配線金属２と半導体チップ３の上記接合は、不活性ガス雰囲気で行うこともできるが、大気中でも何ら支障なく行うことができる。
　もちろん、真空中で行うことも可能であるが、真空設備が必要となるばかりでなく、インサート材の溶融により真空計やゲートバルブを損傷する可能性があるので、大気中で行うことが設備面からもコスト的にも有利である。 The bonding of the wiring metal 2 and the semiconductor chip 3 in the manufacturing method of the present invention can be performed in an inert gas atmosphere, but can be performed in the air without any trouble.
Of course, it is possible to carry out in vacuum, but not only vacuum equipment is required, but also the vacuum gauge and gate valve may be damaged by melting of the insert material. Therefore, it is advantageous in terms of cost.
　本発明における上記接合において、接合部を所定の温度範囲に加熱したり、維持したりするための手段としては、特に限定されることはなく、例えば、高周波加熱や赤外線加熱、ヒータ加熱あるいはこれらを組み合わせた方法を採用することができる。また、治具によって加圧状態に固定し、治具と共にろう付け炉内に保持するといった方法を用いることも可能である。 In the above-described bonding according to the present invention, means for heating or maintaining the bonding portion within a predetermined temperature range is not particularly limited. For example, high-frequency heating, infrared heating, heater heating, or the like can be used. A combined method can be employed. Moreover, it is also possible to use a method of fixing in a pressurized state with a jig and holding it in a brazing furnace together with the jig.
　上記接合温度への昇温速度については、遅い場合には、界面が酸化されて溶融物の排出性が低下して、強度が低下する原因となることがあるため、速い方が望ましい。特に大気中の接合の場合には、この傾向がある。 As for the rate of temperature rise to the above-mentioned bonding temperature, it is desirable that the speed is high because the interface is oxidized and the discharge of the melt is lowered and the strength is lowered. This tendency occurs particularly in the case of bonding in the atmosphere.
　一方、本発明の製造方法においては、凹凸Ｒの形成によって、接合時の加圧力を低減することができることから、接合時の加圧力については、１ＭＰａ以上、３０ＭＰａ以下とすることが望ましい。
　すなわち、１ＭＰａに満たない場合は、酸化皮膜の破壊や、共晶反応物や酸化皮膜欠片の接合面からの排出が十分にできず、３０ＭＰａを超えると半導体チップ２が損傷する可能性があることによる。 On the other hand, in the manufacturing method of the present invention, the pressurizing force at the time of joining can be reduced by forming the unevenness R, and therefore the pressurizing force at the time of joining is preferably set to 1 MPa or more and 30 MPa or less.
That is, when the pressure is less than 1 MPa, the oxide film cannot be destroyed or the eutectic reaction product or the oxide film fragments can be sufficiently discharged from the joint surface. If the pressure exceeds 30 MPa, the semiconductor chip 2 may be damaged. by.
　図４は、本発明の半導体装置の製造方法における拡散防止層の機能を説明する概略断面図である。
　まず、図４（ａ）に示すように、配線金属２と半導体チップ３を準備し、これらの間にインサート材４を配置する。 FIG. 4 is a schematic cross-sectional view illustrating the function of the diffusion preventing layer in the method for manufacturing a semiconductor device of the present invention.
First, as shown in FIG. 4A, a wiring metal 2 and a semiconductor chip 3 are prepared, and an insert material 4 is disposed therebetween.
　ここで、配線金属２は、前述したように高純度Ａｌから成り、その接合面には、予め微細な凹凸Ｒが形成してあり、その表面には、さらに金属原子の拡散防止層Ｌが形成されている。なお、上記拡散防止層Ｌとしては、Ｎｉ、ＴｉＮ、ＷＮ、ＴｉＷＮ及びＰｔＩｒのうちのいずれかの材料を用いることができ、蒸着やスパッタリングなどによって成膜することができる。
　一方、半導体チップ３の接合面には、上記した金属Ａ（Ａｌ、Ｃｕ、Ａｇ及びＡｕから成る少なくとも１種を主成分とする金属）から成る金属層３ｃがめっきやスパッタリングなどによって形成されている。なお、金属層３ｃの表面には、酸化皮膜３ｆが生成している。 Here, the wiring metal 2 is made of high-purity Al as described above, and fine irregularities R are formed in advance on the joint surface, and a metal atom diffusion prevention layer L is further formed on the surface. Has been. As the diffusion preventing layer L, any material of Ni, TiN, WN, TiWN, and PtIr can be used, and can be formed by vapor deposition or sputtering.
On the other hand, on the bonding surface of the semiconductor chip 3, a metal layer 3c made of the above-described metal A (a metal mainly composed of at least one of Al, Cu, Ag, and Au) is formed by plating, sputtering, or the like. . An oxide film 3f is formed on the surface of the metal layer 3c.
　そして、間にインサート材４を介在させた配線金属２と半導体チップ３を相対的に加圧すると共に加熱すると、先に説明したように、金属層３ｃの酸化被膜３ｆが機械的に破壊され、この破壊部分で生じた共晶反応が接合面に拡大し、酸化被膜３ｆが破壊され、共晶溶融物と共に接合面から排出される。
　その結果、図４（ｂ）に示すように、金属層３ｃと配線金属２とが凹凸Ｒの底部を残した状態に直接的に接合され、凹凸Ｒの底部には、酸化皮膜３ｆの欠片が共晶溶融相Ｅｍの中に分散した状態に残留する。 When the wiring metal 2 and the semiconductor chip 3 with the insert material 4 interposed therebetween are relatively pressurized and heated, the oxide film 3f of the metal layer 3c is mechanically broken as described above, and this The eutectic reaction generated at the fracture portion expands to the bonding surface, and the oxide film 3f is broken and discharged from the bonding surface together with the eutectic melt.
As a result, as shown in FIG. 4B, the metal layer 3c and the wiring metal 2 are directly joined with the bottom of the unevenness R left, and a piece of the oxide film 3f is formed on the bottom of the unevenness R. It remains dispersed in the eutectic melt phase Em.
　図４（ｃ）は、接合直後の接合界面の状態を示すものであって、凹凸Ｒの底部の残留物Ｅｓは、共晶溶融相Ｅｍが酸化皮膜３ｆを巻き込んだ状態に凝固している。
　このような接合部が高温環境に放置されると、図４（ｄ）に示すように、残留物Ｅｓの中に含まれる金属原子、代表的にはＺｎが金属層３ｃに拡散するものの、配線金属２の側には、拡散防止層Ｌが障害となるため、金属原子の拡散が阻止される。そのため、配線金属２の伸びの低下や熱応力の増大を回避することができ、半導体装置の耐久信頼性を向上させることができる。 FIG. 4C shows the state of the bonding interface immediately after bonding, and the residue Es at the bottom of the unevenness R is solidified in a state in which the eutectic melt phase Em entrains the oxide film 3f.
When such a junction is left in a high temperature environment, as shown in FIG. 4D, metal atoms, typically Zn, contained in the residue Es diffuse into the metal layer 3c. On the metal 2 side, since the diffusion preventing layer L becomes an obstacle, the diffusion of metal atoms is prevented. Therefore, a decrease in the elongation of the wiring metal 2 and an increase in thermal stress can be avoided, and the durability reliability of the semiconductor device can be improved.
　図５は、金属原子の拡散防止層Ｌを配線金属２の接合面の内部に形成した例を示すものである。
　この場合、拡散防止層Ｌが接合面の内部（表面直下位置）に形成され、接合面の最表面が高純度Ａｌであることから、その表面に酸化皮膜（酸化アルミニウム）２ｆが形成され（図５（ａ）参照）、高温放置後の金属原子の拡散が、配線金属２の表面から拡散防止層Ｌまでの範囲に及ぶ（図５（ｄ）参照）こと以外は、基本的に図４と変わりはない。
FIG. 5 shows an example in which a metal atom diffusion preventing layer L is formed inside the joint surface of the wiring metal 2.
In this case, since the diffusion preventing layer L is formed inside the bonding surface (position just below the surface) and the outermost surface of the bonding surface is high-purity Al, an oxide film (aluminum oxide) 2f is formed on the surface (FIG. 5 (a)), except that the diffusion of metal atoms after standing at high temperature extends to the range from the surface of the wiring metal 2 to the diffusion prevention layer L (see FIG. 5 (d)). There is no change.
　本発明の製造方法により製造された半導体装置の構造は、半導体チップと配線金属とが接合されて成る半導体装置であって、半導体チップはＡｌ、Ｃｕ、Ａｇ及びＡｕから成る群より選ばれた少なくとも１種を主成分とする金属Ａを接合面に備え、上記配線金属は高純度Ａｌから成ると共に、接合面の表面又は内部に金属原子の拡散防止層を有し、これら半導体チップ及び配線金属の接合面を構成する金属Ａと高純度Ａｌとが接合界面の少なくとも一部において直接接合され、当該直接接合部の周囲にＺｎの共晶組成物と、Ａｌ及び上記金属Ａに含まれるＡｕ以外の少なくとも１種の金属の酸化物を含む排出物が介在していることになる（図１（ｅ）参照）。 The structure of the semiconductor device manufactured by the manufacturing method of the present invention is a semiconductor device in which a semiconductor chip and a wiring metal are joined, and the semiconductor chip is at least selected from the group consisting of Al, Cu, Ag, and Au. A metal A mainly composed of one kind is provided on the bonding surface, the wiring metal is made of high-purity Al, and has a metal atom diffusion prevention layer on the surface or inside of the bonding surface. The metal A and the high-purity Al constituting the bonding surface are directly bonded at least at a part of the bonding interface, and the eutectic composition of Zn around the direct bonding portion and Al and other than Au contained in the metal A Exhausts containing at least one metal oxide are present (see FIG. 1 (e)).
　なお、ここで、「Ｚｎの共晶組成物」とは、インサート材に含まれるＺｎと、金属Ａに含まれるＡｕ以外の少なくとも１種の金属と及び配線金属のＡｌの共晶反応による組成物、また「酸化物」については、上記金属Ａ及び配線金属（高純度Ａｌ）の表面に生成していた酸化皮膜の欠片ということになる。
　また、接合条件、すなわち、加圧力、接合温度、微細凹凸形状、インサート材の成分、量などの調整により、凹凸構造の底部の残存を可及的に減らすことができ、断続的な接合を全面的な直接接合に近づけることができる。 Here, the “eutectic composition of Zn” is a composition obtained by eutectic reaction of Zn contained in the insert material, at least one metal other than Au contained in the metal A, and Al of the wiring metal. In addition, the “oxide” is a fragment of the oxide film formed on the surfaces of the metal A and the wiring metal (high purity Al).
In addition, by adjusting the joining conditions, that is, pressure, joining temperature, fine uneven shape, composition and amount of insert material, etc., the bottom of the uneven structure can be reduced as much as possible, and intermittent joining can be performed on the entire surface. It can be approximated to direct bonding.
　本発明においては、上記配線金属を絶縁性セラミックス基板上に配置することができ、このセラミックス基板の反半導体チップ側の面に備えた裏面金属を介して、セラミックス基板をベースプレート（冷却体など）に接合した構造とすることもできる。
　このとき、上記裏面金属とベースプレートとの接合にも、上記した半導体チップと配線金属の接合と同様の製造方法や接合構造を採用することができる。 In the present invention, the wiring metal can be disposed on an insulating ceramic substrate, and the ceramic substrate is attached to a base plate (cooling body or the like) via a back metal provided on the surface of the ceramic substrate on the side opposite to the semiconductor chip. A bonded structure can also be used.
At this time, the same manufacturing method and bonding structure as the above-described bonding of the semiconductor chip and the wiring metal can be employed for bonding the back metal and the base plate.
　すなわち、上記絶縁性セラミックス基板の反半導体チップ側に備えた裏面金属をベースプレート上に接合するに際して、上記裏面金属を高純度Ａｌから成るものすると共に、上記ベースプレートの接合面をＡｌ、Ｃｕ、Ａｇ及びＡｕから成る群より選ばれた少なくとも１種を主成分とする金属Ｂから成るものとし、上記両接合面の少なくとも一方に接合面の酸化皮膜を破壊するための凹凸を設けると共に、上記裏面金属の接合面の表面又は内部に金属原子の拡散防止層を形成した上で、両接合面間にＡｌと上記金属Ｂに含まれるＡｕ以外の少なくとも１種の金属とそれぞれ共晶反応を生じる金属としてＺｎを含むインサート材を介在させ、上記裏面金属とベースプレートを相対的に加圧しつつ加熱し、接合界面に生じた共晶反応溶融物を上記酸化皮膜と共に排出して、接合界面の少なくとも一部において上記裏面金属及びベースプレートの接合面を構成する高純度Ａｌと金属Ｂとを直接接合する。 That is, when joining the back metal provided on the anti-semiconductor chip side of the insulating ceramic substrate onto the base plate, the back metal is made of high-purity Al, and the joining surface of the base plate is made of Al, Cu, Ag and It is made of metal B mainly composed of at least one selected from the group consisting of Au, and at least one of the two joint surfaces is provided with unevenness for breaking the oxide film on the joint surface, As a metal that causes a eutectic reaction with Al and at least one metal other than Au contained in the metal B between the bonding surfaces after forming a diffusion preventing layer of metal atoms on the surface or inside of the bonding surface The back metal and the base plate are heated while relatively pressurizing the insert material containing And discharged together with oxide film, bonded directly to a high-purity Al metal B constituting the bonding surface of the back metal and the base plate in at least a part of the bonding interface.
　このようにして製造された半導体装置は、上記配線金属が絶縁性セラミックス基板上に配置され、該絶縁性セラミックス基板の反半導体チップ側に備えた裏面金属がベースプレート上に接合されており、上記裏面金属は高純度Ａｌから成ると共に、その接合面の表面又は内部に金属原子の拡散防止層を有し、上記ベースプレートはＡｌ、Ｃｕ、Ａｇ及びＡｕから成る群より選ばれた少なくとも１種を主成分とする金属Ｂを接合面に備え、これら裏面金属及びベースプレートの接合面を構成する高純度Ａｌと金属Ｂとが接合界面の少なくとも一部において直接接合され、当該直接接合部の周囲にＺｎの共晶組成物と、Ａｌ及び上記金属Ａに含まれるＡｕ以外の少なくとも１種の金属の酸化物を含む排出物が介在している構造となる。 In the semiconductor device manufactured in this way, the wiring metal is disposed on the insulating ceramic substrate, and the back metal provided on the side of the insulating ceramic substrate opposite to the semiconductor chip is bonded on the base plate. The metal is made of high-purity Al and has a diffusion preventing layer for metal atoms on the surface or inside of the bonding surface, and the base plate is mainly composed of at least one selected from the group consisting of Al, Cu, Ag and Au. The high-purity Al and metal B constituting the back surface metal and the base plate joint surface are directly joined at least at a part of the joint interface, and Zn is shared around the direct joint portion. The crystal composition and the discharge containing at least one oxide of metal other than Au contained in Al and the metal A are interposed.
　すなわち、裏面金属の接合面の表面又は内部に、金属原子の拡散防止層が形成されているので、接合面に共晶反応液相の凝固物が残留したとしても、凝固物中の金属原子の配線金属へ拡散が阻止され、裏面金属の伸びが低下したり、熱応力が増したりすることがなく、半導体装置の耐久信頼性が向上する。
　なお、ベースプレートの接合面を構成する金属Ｂについては、上記半導体チップの接合面を構成する金属Ａと異なる材料であってもよいが、同種材を用いることが望ましい。 That is, since a diffusion preventing layer of metal atoms is formed on the surface or inside of the bonding surface of the back surface metal, even if solidified material of the eutectic reaction liquid phase remains on the bonding surface, the metal atoms in the solidified material Diffusion to the wiring metal is prevented, the elongation of the back surface metal does not decrease, and the thermal stress does not increase, thereby improving the durability reliability of the semiconductor device.
The metal B constituting the bonding surface of the base plate may be a material different from the metal A constituting the bonding surface of the semiconductor chip, but it is desirable to use the same kind of material.
　図６（ａ）～（ｄ）は、本発明の製造方法による半導体装置の実施形態の数例を示す概略断面図である。
　第1の実施形態として、図６（ａ）に示す半導体装置１は、冷却体（ヒートシンク）１１上に、絶縁性セラミックス基板１２の片面側に高純度Ａｌから成る配線金属２を配置したバスバーが固定され、その配線金属２に半導体チップ３が接合された構造を備えている。そして、上記半導体チップ３は、その接合面に上記金属Ａから成る金属層３ｃを備えており、半導体チップ３の金属層３ｃと配線金属２とが上記した方法により直接接合された構造となっている。 FIGS. 6A to 6D are schematic cross-sectional views showing several examples of embodiments of a semiconductor device according to the manufacturing method of the present invention.
As a first embodiment, a semiconductor device 1 shown in FIG. 6A includes a bus bar in which a wiring metal 2 made of high-purity Al is arranged on one side of an insulating ceramic substrate 12 on a cooling body (heat sink) 11. The semiconductor chip 3 is bonded to the wiring metal 2 and fixed. The semiconductor chip 3 includes a metal layer 3c made of the metal A on the bonding surface, and the metal layer 3c of the semiconductor chip 3 and the wiring metal 2 are directly bonded by the method described above. Yes.
　図６（ｂ）に示す半導体装置１は、絶縁性セラミックス基板１２の図中上面側に高純度Ａｌから成る配線金属２を備え、図中下面側に同じく高純度Ａｌから成る裏面金属５を備えたセラミックス基板１２の裏面金属側に冷却体１１を備えている。そして、上面側の配線金属２（高純度Ａｌ）と、接合面に金属Ａから成る金属層３ｃを備えた半導体チップ３が上記下方法によって接合され、下面側の裏面金属５（高純度Ａｌ）と冷却体１１（金属Ｂ）が同様に接合された構造となっている。 A semiconductor device 1 shown in FIG. 6B includes a wiring metal 2 made of high-purity Al on the upper surface side of the insulating ceramic substrate 12 in the drawing, and a back metal 5 also made of high-purity Al on the lower surface side in the drawing. A cooling body 11 is provided on the back metal side of the ceramic substrate 12. Then, the wiring metal 2 (high purity Al) on the upper surface side and the semiconductor chip 3 having the metal layer 3c made of the metal A on the bonding surface are bonded by the above method, and the back surface metal 5 (high purity Al) on the lower surface side. The cooling body 11 (metal B) is similarly joined.
　図６（ｃ）に示す半導体装置１は、図６（ａ）及び（ｂ）が片側実装であったのに対し、両面実装タイプの半導体装置の例を示すものであって、両面に金属Ａから成る金属層３ｃを備えた半導体チップ３の上下に、絶縁性セラミックス基板１２の片面側に高純度Ａｌから成る配線金属２を備えたバスバーが冷却体１１と共に配置されている。半導体チップ３の上下両面に備えた金属Ａから成る金属層３ｃとバスバーの高純度Ａｌから成る配線金属２が上記した方法により直接接合された構造となっている。 The semiconductor device 1 shown in FIG. 6C shows an example of a double-sided mounting type semiconductor device, whereas FIGS. 6A and 6B are single-sided mountings. A bus bar provided with a wiring metal 2 made of high-purity Al is disposed on one side of an insulating ceramic substrate 12 along with a cooling body 11 on the upper and lower sides of a semiconductor chip 3 provided with a metal layer 3c. The metal layer 3c made of metal A provided on the upper and lower surfaces of the semiconductor chip 3 and the wiring metal 2 made of high-purity Al of the bus bar are directly bonded by the above-described method.
　第４の実施形態として、図６（ｄ）に示す半導体装置１は、絶縁性セラミックス基板１２の両面に、共に高純度Ａｌから成る配線金属２と裏面金属５を備えたセラミックス基板１２を用いた両面実装タイプのものである。すなわち、セラミックス基板１２の裏面側に配置した裏面金属５（高純度Ａｌ）と冷却体１１（金属Ｂ）とが本発明の方法によって接合されていること以外は、図６（ｃ）に示した形態と実質的に同様の構造となっている。 As a fourth embodiment, the semiconductor device 1 shown in FIG. 6D uses a ceramic substrate 12 having a wiring metal 2 and a back metal 5 both made of high-purity Al on both surfaces of an insulating ceramic substrate 12. It is a double-sided mounting type. That is, as shown in FIG. 6C, the back surface metal 5 (high-purity Al) and the cooling body 11 (metal B) disposed on the back surface side of the ceramic substrate 12 are joined by the method of the present invention. The structure is substantially the same as the form.
　図７は、本発明の半導体装置の接合前の状態を示す概略断面図（但し、インサート材４は省略）であって、図に示す半導体チップ３は接合面に金属Ａから成る金属層３ｃを備えている。なお、上記金属層３ｃは、図３に示したように、密着層３ａやバリヤ層３ｂを介して形成することもできる。
　一方、絶縁性セラミックス基板１２は、図中上面側に高純度Ａｌから成る配線金属２を備え、図中下面側に同じく高純度Ａｌから成る裏面金属５を備えており、これら配線金属２及び裏面金属５の表面（半導体チップ３及び後述するベースプレート１１との接合面）には凹凸Ｒが形成されている。 FIG. 7 is a schematic cross-sectional view showing a state before bonding of the semiconductor device of the present invention (however, the insert material 4 is omitted). The semiconductor chip 3 shown in the figure has a metal layer 3c made of metal A on the bonding surface. I have. The metal layer 3c can also be formed via an adhesion layer 3a or a barrier layer 3b as shown in FIG.
On the other hand, the insulating ceramic substrate 12 includes a wiring metal 2 made of high-purity Al on the upper surface side in the drawing, and a back metal 5 also made of high-purity Al on the lower surface side in the drawing. Concavities and convexities R are formed on the surface of the metal 5 (bonding surface between the semiconductor chip 3 and a base plate 11 described later).
　ベースプレート（冷却体）１１は、金属Ｂから成り、その裏面金属５との接合面には、同様に凹凸Ｒが形成されている。このとき、凹凸Ｒの形成は、裏面金属５及びベースプレート１１のいずれか一方だけでもよい。
　なお、上記配線金属２及び裏面金属５の凹凸表面上には、拡散防止層Ｌが成膜されている。 The base plate (cooling body) 11 is made of metal B, and unevenness R is similarly formed on the joint surface with the back surface metal 5. At this time, the unevenness R may be formed by only one of the back metal 5 and the base plate 11.
A diffusion prevention layer L is formed on the uneven surface of the wiring metal 2 and the back metal 5.
　そして、上記半導体チップ３と配線金属２の間と、裏面金属５とベースプレート１１の間に、Ｚｎを含有するインサート材（図示せず）を介在させた状態で、これらを加圧すると共に、加熱することによって、これらの間が接合される。
　こうして接合された半導体装置は、配線金属２及び裏面金属５の表面に金属原子の拡散防止層Ｌが形成されているため、接合面に凹凸Ｒが残存したとしても、また、高温環境に曝されたとしても、凹凸残存部の凝固物から配線金属２及び裏面金属５への拡散が防止される。したがって、配線金属２及び裏面金属５の本来の機械的性能を維持することができ、半導体装置の耐久信頼性を向上させることができる。 And while inserting the insert material (not shown) containing Zn between the said semiconductor chip 3 and the wiring metal 2, and between the back surface metal 5 and the baseplate 11, these are pressurized and heated. By doing so, they are joined.
Since the semiconductor device bonded in this way has the metal atom diffusion prevention layer L formed on the surfaces of the wiring metal 2 and the back surface metal 5, even if the unevenness R remains on the bonding surface, it is exposed to a high temperature environment. Even so, diffusion from the solidified portion of the uneven portion to the wiring metal 2 and the back metal 5 is prevented. Therefore, the original mechanical performance of the wiring metal 2 and the back surface metal 5 can be maintained, and the durability reliability of the semiconductor device can be improved.
　以下、本発明を実施例に基づいて具体的に説明する。なお、文中の符号については、図７に対応するものである。 Hereinafter, the present invention will be specifically described based on examples. In addition, about the code | symbol in a sentence, it respond | corresponds to FIG.
〔実施例１〕
（ａ）半導体チップ
　１．６６×１．５２×０．３６ｍｍのサイズのＳｉＣダイオード（半導体チップ３）の裏面に、Ｔｉ／Ｎｉ／Ａｇを蒸着により成膜した後、この成膜面上にＡｌ（金属Ａ）を６μｍの厚さにスパッタリングして金属層３ｃを形成し、接合面とした。  [Example 1]
(A) Semiconductor chip After depositing Ti / Ni / Ag by vapor deposition on the back surface of an SiC diode (semiconductor chip 3) having a size of 1.66 × 1.52 × 0.36 mm, Al is deposited on the deposition surface. (Metal A) was sputtered to a thickness of 6 μm to form a metal layer 3c, which was used as a bonding surface.
（ｂ）絶縁性セラミックス基板
　ＡｌＮから成る厚さ０．６４ｍｍのセラミック基板１２の両面に、純度９９．９９％の高純度アルミニウムから成る厚さ０．５ｍｍの配線金属２と、同じく高純度アルミニウム（金属Ｂ）から成る厚さ０．５ｍｍの裏面金属５をそれぞれ形成した。
　そして、上記配線金属２及び裏面金属５には、その表面には、凹凸Ｒとして、ダイヤモンド工具を用いた切削加工によって、高さ０．１ｍｍ、ピッチ０．１ｍｍの一方向溝を形成した。さらに、スパッタリングにより、その表面にＮｉ層を５μｍの厚さに成膜し、拡散防止層Ｌとした。 (B) Insulating ceramic substrate On both sides of a 0.64 mm thick ceramic substrate 12 made of AlN, a 0.5 mm thick wiring metal 2 made of high purity aluminum having a purity of 99.99% and a high purity aluminum ( Back metal 5 having a thickness of 0.5 mm made of metal B) was formed.
Then, the wiring metal 2 and the back metal 5 were formed with unidirectional grooves having a height of 0.1 mm and a pitch of 0.1 mm on the surfaces thereof as the unevenness R by cutting using a diamond tool. Further, a Ni layer having a thickness of 5 μm was formed on the surface by sputtering to form a diffusion preventing layer L.
（ｃ）ベースプレート
　ＪＩＳ　Ｈ　４０００に、Ａ１０７０として規定される工業用純アルミニウム（金属Ｂ）から成る厚さ１．０ｍｍの板材をベースプレート１１とした。そして、その表面（裏面金属５との接合面）に、ダイヤモンド工具を用いた切削加工により、高さ０．１ｍｍ、ピッチ０．１ｍｍの一方向溝を形成し、凹凸Ｒとした。 (C) Base plate A plate material having a thickness of 1.0 mm made of industrial pure aluminum (metal B) defined as A1070 in JIS H 4000 was used as the base plate 11. Then, a unidirectional groove having a height of 0.1 mm and a pitch of 0.1 mm was formed on the surface (bonding surface with the back surface metal 5) by using a diamond tool, thereby forming the unevenness R.
（ｄ）接合
　次に、半導体チップ３と配線金属２の接合面間と、裏面金属５とベースプレート１１の接合面間に、急冷単ロール法によって作製したＺｎ－３．５％Ａｌ－２．５％Ｍｇ合金から成る厚さ０．１ｍｍの箔帯をそれぞれインサート材として挟んだ。
　そして、赤外線加熱方式の拡散接合装置により、５ＭＰａの加圧力の下で、４００℃に１分間保持することによって、配線金属２と半導体チップ３、裏面金属５とベースプレート１１をそれぞれ接合して、実施例１の半導体装置を得た。 (D) Joining Next, Zn-3.5% Al-2.5 produced by a quenching single roll method between the joining surfaces of the semiconductor chip 3 and the wiring metal 2 and between the joining surfaces of the back metal 5 and the base plate 11. Each 0.1 mm thick foil strip made of% Mg alloy was sandwiched as an insert material.
Then, the wiring metal 2 and the semiconductor chip 3, and the back metal 5 and the base plate 11 are respectively joined by holding at 400 ° C. for 1 minute under a pressure of 5 MPa by an infrared heating type diffusion bonding apparatus. The semiconductor device of Example 1 was obtained.
〔実施例２〕
　インサート材として、急冷単ロール法によって作製したＺｎ－４．０％Ａｌ－２．０％Ｃｕ合金から成る厚さ０．１ｍｍの箔帯を用いたこと以外は、上記実施例１と同様の操作を繰り返すことによって、それぞれの接合面を接合して、実施例２の半導体装置を得た。 [Example 2]
The same operation as in Example 1 above, except that a 0.1 mm thick foil strip made of a Zn-4.0% Al-2.0% Cu alloy produced by a rapid cooling single roll method was used as the insert material. By repeating the above, the respective joining surfaces were joined to obtain the semiconductor device of Example 2.
〔実施例３〕
　上記サイズのＳｉＣダイオード（半導体チップ３）の裏面に、Ｔｉ／Ｎｉ／Ａｇを蒸着により成膜し、接合面をＡｇとしたこと以外は）、上記実施例１と同様の操作を繰り返すことによって、それぞれの接合面を接合して、実施例３の半導体装置を得た。 Example 3
By repeating the same operation as in Example 1 above, except that Ti / Ni / Ag is formed by vapor deposition on the back surface of the SiC diode of the above size (semiconductor chip 3) and the bonding surface is Ag. The respective joining surfaces were joined to obtain the semiconductor device of Example 3.
〔実施例４〕
　配線金属２及び裏面金属５の最表面にＷＮをスパッタリング成膜して、拡散防止層Ｌとしたこと以外は、上記実施例１と同様の操作を繰り返すことによって、それぞれの接合面を接合し、実施例４の半導体装置を得た。 Example 4
Except for forming the diffusion prevention layer L by sputtering WN on the outermost surfaces of the wiring metal 2 and the back surface metal 5, the same operation as in Example 1 is repeated to join the respective bonding surfaces. A semiconductor device of Example 4 was obtained.
〔比較例１〕
　配線金属２及び裏面金属５の接合面に拡散防止層を形成することなく、上記実施例１と同様の操作を繰り返すことによって、それぞれの接合面を接合して、比較例１の半導体装置を得た。 [Comparative Example 1]
By repeating the same operation as in Example 1 without forming a diffusion prevention layer on the bonding surface of the wiring metal 2 and the back surface metal 5, the respective bonding surfaces are bonded to obtain the semiconductor device of Comparative Example 1. It was.
〔評価試験〕　　
　上記実施例及び比較例によって得られた半導体装置を３００℃に保持した恒温槽中に、それぞれ３０００時間保持した後、下記方法によって電気抵抗率及び熱伝導率をそれぞれ測定し、接合部の電気伝導性及び熱伝導性を評価した。
　その結果を表１に示す。 〔Evaluation test〕
The semiconductor devices obtained by the above examples and comparative examples were held in a thermostat held at 300 ° C. for 3000 hours, respectively, and then the electrical resistivity and thermal conductivity were measured by the following methods, respectively. And thermal conductivity were evaluated.
The results are shown in Table 1.
（ａ）電気抵抗率
　比較例の場合、バリヤ層がないため恒温槽中での保持によりZｎが配線金属のAl中に拡散するため、電気抵抗率は大きく増加しているが、本発明の場合は拡散が防止されるため、高純度アルミの高い電気伝導率が維持された。

（ｂ）熱伝導率
　比較例の場合、バリヤ層がないため恒温槽中での保持によりZｎが配線金属のAl中に拡散するため、熱伝導率は大幅に低下しているが、本発明の場合は拡散が抑制されるため、高純度アルミの高い熱伝導率が維持された。 (A) Electric resistivity In the case of the comparative example, since there is no barrier layer, Zn is diffused in Al of the wiring metal by holding in the thermostat, so that the electric resistivity is greatly increased. Because diffusion is prevented, high electrical conductivity of high purity aluminum was maintained.

(B) Thermal conductivity In the case of the comparative example, since there is no barrier layer, Zn is diffused into Al of the wiring metal by holding in the thermostat, so that the thermal conductivity is greatly reduced. In some cases, diffusion was suppressed, and the high thermal conductivity of high-purity aluminum was maintained.
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001
　　１　半導体装置
　　２　配線金属（高純度Ａｌ）
　　Ｒ　凹凸
　　Ｌ　拡散防止層
　　２ｆ　酸化皮膜
　　３　半導体チップ
　　３ｃ　金属層（金属Ａ）
　　３ｆ　酸化皮膜
　　４　インサート材
　　５　裏面金属（高純度Ａｌ）
　１１　ベースプレート（金属Ｂ）
　１２　絶縁性セラミックス基材 1 Semiconductor device 2 Wiring metal (high purity Al)
R Concavity and convexity L Diffusion prevention layer 2f Oxide film 3 Semiconductor chip 3c Metal layer (metal A)
3f Oxide film 4 Insert material 5 Back metal (high purity Al)
11 Base plate (Metal B)
12 Insulating ceramic substrate

Claims (15)

  1. 　接合面がＡｌ、Ｃｕ、Ａｇ及びＡｕから成る群より選ばれた少なくとも１種を主成分とする金属Ａから成る半導体チップと、高純度Ａｌから成る配線金属とを接合するに際して、
    　上記両接合面の少なくとも一方に接合面の酸化皮膜を破壊するための凹凸を設けると共に、上記配線金属の接合面の表面又は内部に金属原子の拡散防止層を形成した上で、両接合面間にＡｌと上記金属Ａに含まれるＡｕ以外の少なくとも１種の金属とそれぞれ共晶反応を生じる金属としてＺｎを含むインサート材を介在させ、上記半導体チップと配線金属を相対的に加圧しつつ加熱し、接合界面に生じた共晶反応溶融物を上記酸化皮膜と共に排出して、接合界面の少なくとも一部において上記半導体チップ及び配線金属の接合面を構成する金属Ａと高純度Ａｌとを直接接合することを特徴とする半導体装置の製造方法。     When joining a semiconductor chip made of metal A mainly composed of at least one selected from the group consisting of Al, Cu, Ag, and Au, and a wiring metal made of high-purity Al.
    At least one of the joint surfaces is provided with concavities and convexities for destroying the oxide film on the joint surface, and a metal atom diffusion prevention layer is formed on or inside the joint surface of the wiring metal. An insert material containing Zn as a metal that causes eutectic reaction with at least one metal other than Au contained in Al and the metal A is interposed between the semiconductor chip and the wiring metal and heated while relatively pressurizing the semiconductor chip and the wiring metal. The eutectic reaction melt generated at the bonding interface is discharged together with the oxide film, and the metal A constituting the bonding surface of the semiconductor chip and the wiring metal and the high-purity Al are directly bonded at least at a part of the bonding interface. A method for manufacturing a semiconductor device.
  2. 　上記インサート材がＺｎを主成分とする金属であることを特徴とする請求項１に記載の接合方法。 The joining method according to claim 1, wherein the insert material is a metal containing Zn as a main component.
  3. 　上記インサート材がＺｎと、Ａｌ、Ｍｇ、Ｃｕ、Ａｇ及びＳｎから成る群より選ばれた少なくとも１種の金属を主成分とする合金であることを特徴とする請求項１又は２に記載の接合方法。 The joining according to claim 1 or 2, wherein the insert material is an alloy mainly composed of Zn and at least one metal selected from the group consisting of Al, Mg, Cu, Ag, and Sn. Method.
  4. 上記インサート材がＺｎ及びＡｌを主成分とする合金であることを特徴とする請求項３に記載の接合方法。 The joining method according to claim 3, wherein the insert material is an alloy mainly composed of Zn and Al.
  5. 　上記インサート材がＺｎ、Ａｌ及びＭｇを主成分とする合金であることを特徴とする請求項３に記載の接合方法。 The joining method according to claim 3, wherein the insert material is an alloy containing Zn, Al, and Mg as main components.
  6. 　上記インサート材がＺｎ、Ａｌ及びＣｕを主成分とする合金であることを特徴とする請求項３に記載の接合方法。 4. The joining method according to claim 3, wherein the insert material is an alloy mainly composed of Zn, Al, and Cu.
  7. 　上記金属原子の拡散防止層がＮｉ、ＴｉＮ、ＷＮ、ＴｉＷＮ又はＰｔＩｒから成ることを特徴とする請求項１～６のいずれか１つの項に記載の接合方法。 The bonding method according to any one of claims 1 to 6, wherein the metal atom diffusion prevention layer is made of Ni, TiN, WN, TiWN, or PtIr.
  8. 　上記金属ＡがＡｌを主成分とする金属から成ることを特徴とする請求項１～７のいずれか１つの項に記載の接合方法。 The joining method according to any one of claims 1 to 7, wherein the metal A is made of a metal mainly composed of Al.
  9. 　上記インサート材の厚さが２０～２００μｍであることを特徴とする請求項１～８のいずれか１つの項に記載の接合方法。 The joining method according to any one of claims 1 to 8, wherein the thickness of the insert material is 20 to 200 µm.
  10. 　配線金属が絶縁性セラミックス基板上に配置されていることを特徴とする請求項１～９のいずれか１つの項に記載の製造方法。 The method according to any one of claims 1 to 9, wherein the wiring metal is disposed on an insulating ceramic substrate.
  11. 　上記絶縁性セラミックス基板の反半導体チップ側に備えた裏面金属をベースプレート上に接合するに際して、上記裏面金属を高純度Ａｌから成るものすると共に、上記ベースプレートの接合面をＡｌ、Ｃｕ、Ａｇ及びＡｕから成る群より選ばれた少なくとも１種を主成分とする金属Ｂから成るものとし、上記両接合面の少なくとも一方に接合面の酸化皮膜を破壊するための凹凸を設けると共に、上記裏面金属の接合面の表面又は内部に金属原子の拡散防止層を形成した上で、両接合面間にＡｌと上記金属Ｂに含まれるＡｕ以外の少なくとも１種の金属とそれぞれ共晶反応を生じる金属としてＺｎを含むインサート材を介在させ、上記裏面金属とベースプレートを相対的に加圧しつつ加熱し、接合界面に生じた共晶反応溶融物を上記酸化皮膜と共に排出して、接合界面の少なくとも一部において上記裏面金属及びベースプレートの接合面を構成する高純度Ａｌと金属Ｂとを直接接合することを特徴とする請求項１０に記載の製造方法。 When joining the back metal provided on the anti-semiconductor chip side of the insulating ceramic substrate on the base plate, the back metal is made of high-purity Al, and the joint surface of the base plate is made of Al, Cu, Ag and Au. It is made of a metal B mainly composed of at least one selected from the group consisting of: and at least one of the joint surfaces is provided with unevenness for breaking the oxide film on the joint surface, and the joint surface of the back metal In addition, a metal atom diffusion prevention layer is formed on the surface or inside of the metal, and Zn is included as a metal that causes a eutectic reaction with Al and at least one metal other than Au contained in the metal B between the two joint surfaces. The eutectic reaction melt generated at the bonding interface is heated by relatively pressing the back metal and the base plate with an insert material interposed therebetween. Together discharged method according to claim 10, characterized in that the direct bonding a high-purity Al metal B constituting the bonding surface of the back metal and the base plate in at least a part of the bonding interface.
  12. 　接合面がＡｌ、Ｃｕ、Ａｇ及びＡｕから成る群より選ばれた少なくとも１種を主成分とする金属Ａから成る半導体チップと、高純度Ａｌから成る配線金属とを接合した半導体装置であって、
    　上記両接合面の少なくとも一方に接合面の酸化皮膜を破壊するための凹凸を設けると共に、上記配線金属の接合面の表面又は内部に金属原子の拡散防止層を形成した上で、両接合面間にＡｌと上記金属Ａに含まれるＡｕ以外の少なくとも１種の金属とそれぞれ共晶反応を生じる金属としてＺｎを含むインサート材を介在させ、上記半導体チップと配線金属を相対的に加圧しつつ加熱し、接合界面に生じた共晶反応溶融物を上記酸化皮膜と共に排出して、接合界面の少なくとも一部において上記半導体チップ及び配線金属の接合面を構成する金属Ａと高純度Ａｌとを直接接合して成ることを特徴とする半導体装置。     A semiconductor device in which a bonding surface is formed by bonding a semiconductor chip made of metal A mainly composed of at least one selected from the group consisting of Al, Cu, Ag, and Au, and a wiring metal made of high-purity Al.
    At least one of the joint surfaces is provided with concavities and convexities for destroying the oxide film on the joint surface, and a metal atom diffusion prevention layer is formed on or inside the joint surface of the wiring metal. An insert material containing Zn as a metal that causes eutectic reaction with at least one metal other than Au contained in Al and the metal A is interposed between the semiconductor chip and the wiring metal and heated while relatively pressurizing the semiconductor chip and the wiring metal. The eutectic reaction melt generated at the bonding interface is discharged together with the oxide film, and the metal A constituting the bonding surface of the semiconductor chip and the wiring metal and the high-purity Al are directly bonded at least at a part of the bonding interface. A semiconductor device comprising:
  13. 　半導体チップと配線金属とが接合されて成る半導体装置であって、
    　上記半導体チップはＡｌ、Ｃｕ、Ａｇ及びＡｕから成る群より選ばれた少なくとも１種を主成分とする金属Ａを接合面に備え、上記配線金属は高純度Ａｌから成ると共に、その接合面の表面又は内部に金属原子の拡散防止層を有し、
    　これら半導体チップ及び配線金属の接合面を構成する金属Ａと高純度Ａｌとが接合界面の少なくとも一部において直接接合され、当該直接接合部の周囲にＺｎの共晶組成物と、Ａｌ及び上記金属Ａに含まれるＡｕ以外の少なくとも１種の金属の酸化物を含む排出物が介在していることを特徴とする半導体装置。     A semiconductor device formed by bonding a semiconductor chip and a wiring metal,
    The semiconductor chip is provided with a metal A mainly composed of at least one selected from the group consisting of Al, Cu, Ag and Au, and the wiring metal is made of high-purity Al, and the surface of the bond surface Or a metal atom diffusion prevention layer inside,
    The metal A and the high-purity Al constituting the bonding surface of the semiconductor chip and the wiring metal are directly bonded at at least a part of the bonding interface, and the eutectic composition of Zn, Al and the metal are formed around the direct bonding portion. A semiconductor device characterized in that an emission containing an oxide of at least one metal other than Au contained in A is interposed.
  14. 　上記配線金属が絶縁性セラミックス基板上に配置され、該絶縁性セラミックス基板の反半導体チップ側に備えた裏面金属がベースプレート上に接合されており、
    　上記裏面金属は高純度Ａｌから成り、上記ベースプレートは接合面にＡｌ、Ｃｕ、Ａｇ及びＡｕから成る群より選ばれた少なくとも１種を主成分とする金属Ｂを備え、
    　上記両接合面の少なくとも一方に接合面の酸化皮膜を破壊するための凹凸を設けると共に、上記裏面金属の接合面の表面又は内部に金属原子の拡散防止層を形成した上で、両接合面間にＡｌと上記金属Ａに含まれるＡｕ以外の少なくとも１種の金属とそれぞれ共晶反応を生じる金属としてＺｎを含むインサート材を介在させ、上記裏面金属とベースプレートを相対的に加圧しつつ加熱し、接合界面に生じた共晶反応溶融物を上記酸化皮膜と共に排出して、接合界面の少なくとも一部において上記裏面金属及びベースプレートの接合面を構成する高純度Ａｌと金属Ｂとを直接接合して成ることを特徴とする請求項１２又は１３に記載の半導体装置。     The wiring metal is disposed on an insulating ceramic substrate, and a back metal provided on the anti-semiconductor chip side of the insulating ceramic substrate is bonded on the base plate,
    The back metal is made of high-purity Al, and the base plate is provided with a metal B mainly composed of at least one selected from the group consisting of Al, Cu, Ag and Au on the joint surface,
    At least one of the joint surfaces is provided with concavities and convexities for destroying the oxide film on the joint surface, and a diffusion preventing layer for metal atoms is formed on the surface or inside of the joint surface of the back metal. An insert material containing Zn as a metal that causes a eutectic reaction with at least one kind of metal other than Au and Al contained in the metal A, and heating the back metal and the base plate while relatively pressurizing them, The eutectic reaction melt generated at the bonding interface is discharged together with the oxide film, and the high-purity Al and metal B constituting the bonding surface of the back metal and the base plate are directly bonded at least at a part of the bonding interface. The semiconductor device according to claim 12, wherein the semiconductor device is a semiconductor device.
  15. 　上記配線金属が絶縁性セラミックス基板上に配置され、該絶縁性セラミックス基板の反半導体チップ側に備えた裏面金属がベースプレート上に接合されており、
    　上記裏面金属は高純度Ａｌから成ると共に、その接合面の表面又は内部に金属原子の拡散防止層を有し、上記ベースプレートはＡｌ、Ｃｕ、Ａｇ及びＡｕから成る群より選ばれた少なくとも１種を主成分とする金属Ｂを接合面に備え、
    　これら裏面金属及びベースプレートの接合面を構成する高純度Ａｌと金属Ｂとが接合界面の少なくとも一部において直接接合され、当該直接接合部の周囲にＺｎの共晶組成物と、Ａｌ及び上記金属Ａに含まれるＡｕ以外の少なくとも１種の金属の酸化物を含む排出物が介在していることを特徴とする請求項１２又は１３に記載の半導体装置。     The wiring metal is disposed on an insulating ceramic substrate, and a back metal provided on the anti-semiconductor chip side of the insulating ceramic substrate is bonded on the base plate,
    The back metal is made of high-purity Al, and has a metal atom diffusion prevention layer on the surface or inside of the joint surface. The base plate is made of at least one selected from the group consisting of Al, Cu, Ag and Au. A metal B as a main component is provided on the joint surface,
    High-purity Al and metal B constituting the joining surface of the back metal and the base plate are directly joined at at least a part of the joining interface, and the eutectic composition of Zn, Al, and the metal A around the direct joining part. 14. The semiconductor device according to claim 12, wherein an emission containing at least one metal oxide other than Au contained in the metal is interposed.
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