Nothing Special   »   [go: up one dir, main page]

WO2015012159A1 - D/a converter - Google Patents

D/a converter Download PDF

Info

Publication number
WO2015012159A1
WO2015012159A1 PCT/JP2014/068812 JP2014068812W WO2015012159A1 WO 2015012159 A1 WO2015012159 A1 WO 2015012159A1 JP 2014068812 W JP2014068812 W JP 2014068812W WO 2015012159 A1 WO2015012159 A1 WO 2015012159A1
Authority
WO
WIPO (PCT)
Prior art keywords
switch
capacitor
converter
reference voltage
closed
Prior art date
Application number
PCT/JP2014/068812
Other languages
French (fr)
Japanese (ja)
Inventor
潤一 斉藤
博喜 佐藤
Original Assignee
アルプス電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by アルプス電気株式会社 filed Critical アルプス電気株式会社
Publication of WO2015012159A1 publication Critical patent/WO2015012159A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0602—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic
    • H03M1/0604—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic at one point, i.e. by adjusting a single reference value, e.g. bias or gain error
    • H03M1/0607—Offset or drift compensation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/74—Simultaneous conversion
    • H03M1/80—Simultaneous conversion using weighted impedances
    • H03M1/802—Simultaneous conversion using weighted impedances using capacitors, e.g. neuron-mos transistors, charge coupled devices
    • H03M1/804—Simultaneous conversion using weighted impedances using capacitors, e.g. neuron-mos transistors, charge coupled devices with charge redistribution

Definitions

  • the present invention relates to a high-precision D / A converter that converts a digital signal into an analog voltage.
  • D / A converts the signal output from such a delta-sigma modulator with low noise
  • a switched-capacitor type D / A converter (digital to analog converter) suitable for a fine process technology is used.
  • the D / A converter disclosed in Patent Document 1 performs D / A conversion using two positive and negative reference voltages and a plurality of capacitors.
  • FIG. 10 is a circuit diagram showing a D / A converter 900 described in Patent Document 1.
  • the left terminals of the capacitive elements C901 to C90e are connected to the reference voltage Vr + or Vr ⁇ by the operation of the switches SUG1 to SUGe.
  • Each C90e holds a charge corresponding to the reference voltage.
  • the terminals on the left side of the capacitive elements C90f to C90i are connected to the reference potentials Vr +, Vr ⁇ , or the ground potential, and the capacitive elements C90f to C90i hold charges corresponding to the reference voltages, respectively. To do.
  • the capacitive elements C901 to C90e are connected in parallel between the output terminal (output potential OUT) and the inverting input terminal of the operational amplifier 100. Further, when the clock ⁇ 902 becomes high level, among the switches SUGf to SUGi, the switch connected to the reference potential Vr + or Vr ⁇ is opened, and the switch connected to the ground potential is closed. As a result, the charges held in the capacitive elements C90f to C90i while the clock ⁇ 901 is at the high level are transferred, that is, integrated to the feedback capacitive element Cfb of the operational amplifier 100.
  • the switched capacitor type D / A converter uses capacitors such as the capacitive elements C901 to C90e in the configuration for outputting the voltage, so the charge accumulated when the digital signal is zero is ignored. This could cause an error in the analog voltage output.
  • This invention solves the subject mentioned above, and aims at providing a highly accurate D / A converter.
  • a D / A converter includes a first switch connected to a first reference voltage, a second switch connected to a second reference voltage, the first switch, and the second switch.
  • a third switch connected to the third reference voltage, a first capacitor connected to the first switch, the second switch, and the third switch, and connected to the first capacitor
  • a fourth switch connected to a third reference voltage; a fifth switch connected to the first capacitor and the fourth switch; an operational amplifier connected to the fifth switch;
  • a fifth switch and a second capacitor connected to the operational amplifier, and when the input digital signal with polarity is 0, the first switch is closed and the second switch is opened And the first switch is open Is characterized in that the control of switching the, and when the second switch is closed is performed.
  • the D / A converter of the present invention when the input digital signal with polarity is 0, the number of times the first switch is closed and the second switch is opened, and the first switch It is preferable that the first switch and the second switch are controlled so that the difference between the number of times of opening and closing the second switch is minimized.
  • the difference between the number of times when the positive output is generated by the first reference voltage and the case where the negative output is output by the second reference voltage is small. Therefore, the output is further close to zero.
  • the first switch and the second switch are alternately closed when the input digital signal with polarity is zero.
  • the digital signal when the digital signal is 0, the case where a positive output is generated by the first reference voltage and the case where a negative output is generated by the second reference voltage are alternately repeated.
  • the output is stable and close to 0.
  • the first switch and the second switch are controlled to open and close by a code that can be regarded as random. It may be.
  • the D / A converter includes a sixth switch inserted to connect the first switch and the second switch, the third switch and the first capacitor.
  • the first switch and the second switch are preferably controlled by a control line so that one is closed and the other is opened.
  • the sixth switch if the sixth switch is open, it can be opened even if either the first switch or the second switch is closed, so only one control line is required. Since the sixth switch can be controlled so that a current flows when necessary, low power consumption and high accuracy can be achieved.
  • the D / A converter includes: a first control line that controls the first switch; and a second control line that controls the second switch; It is preferable that all of the second control lines are opened or controlled so that one of them is closed.
  • the first switch and the second switch can be controlled to flow current when necessary, so that low power consumption and high accuracy can be achieved.
  • the first capacitor is preferably a variable capacitor formed by connecting a plurality of switched capacitors each having a seventh switch, an eighth switch, and a third capacitor. .
  • 2 is an equivalent circuit diagram of a capacitor with a switch
  • (a) is an equivalent circuit diagram of a capacitor with a switch connected to a first reference voltage
  • (b) is an equivalent circuit diagram of a capacitor with a switch connected to a second reference voltage.
  • FIG. 1 is a circuit diagram of a main part showing a D / A converter 10 according to an embodiment of the present invention.
  • FIG. 2 is a circuit diagram of a main part showing the D / A converter 10 including a specific example of a variable capacitor.
  • FIG. 3 is an equivalent circuit diagram of a capacitor with a switch, FIG. 3 (a) is an equivalent circuit diagram of a capacitor with a switch connected to the first reference voltage, and FIG. 3 (b) is a second reference circuit. It is an equivalent circuit diagram of the capacitor with a switch CU connected to the voltage Vr2.
  • the D / A converter 10 is a switched capacitor type D / A converter using an operational amplifier (operational amplifier) in which an output terminal and an inverting input terminal are connected via a capacitor.
  • the D / A converter 10 according to the present embodiment has a function of converting a signed digital signal in which a sign indicating polarity is added to a digital signal into a unipolar analog signal. Specifically, for example, a signed digital signal in which the most significant of 4-bit digital signals (0000) to (1111) is assigned to positive / negative polarity data (1 for positive, 0 for negative), After conversion, an analog voltage such as 1V to 3V is output.
  • the digital value of (0111) is the maximum value of the negative polarity
  • the digital value of (1111) is the maximum value of the positive polarity
  • the digital value of (1000) is the minimum value of the positive polarity ( Zero)
  • the digital value of (0000) is the minimum negative polarity value (zero).
  • the digital value of (0111) and the digital value of (1111) have the same absolute value.
  • the digital value of (1000) and the digital value of (0000) are substantially the same zero value although code data is given by quantization.
  • the analog voltage converted into an analog signal is output with a maximum value on the negative side of 1V, a minimum value (zero) on the negative and positive sides of 2V, and a maximum value on the positive side of 3V.
  • the main part of the D / A converter 10 includes a first switch SW1 connected to the first reference voltage Vr1 and a second switch connected to the second reference voltage Vr2. 2 switch SW2 and a third switch SW3 connected to the third reference voltage Vr3.
  • the first capacitor C1 whose capacitance value is variable corresponding to the digital value that is the input data
  • the fourth switch SW4 connected to the third reference voltage Vr3, the first capacitor C1 and the fourth capacitor
  • a fifth switch SW5 connected to the switch SW4.
  • An operational amplifier OP1 connected to the fifth switch SW5 and a second capacitor C2 connected to the fifth switch SW5 and the operational amplifier OP1 are provided.
  • a sixth switch SW6 is provided so as to connect the first switch SW1 and the second switch SW2, the third switch SW3 and the first capacitor C1.
  • the first switch SW1 and the second switch SW2 are controlled by the control line SCL so that one is closed and the other is opened.
  • the first switch SW1 and the second switch SW2 have a complementary relationship in which only one of them is closed.
  • the switches (SW3 to SW6) other than the first switch SW1 and the second switch SW2 are controlled to be opened and closed by the clock ⁇ 1 and the clock ⁇ 2.
  • the third reference voltage Vr3 is a ground potential.
  • the first reference voltage Vr1 is a voltage having the same magnitude and a different polarity as the second reference voltage Vr2.
  • the non-inverting input terminal of the operational amplifier OP1 is connected to the third reference voltage Vr3, which is the ground potential in this embodiment.
  • the power supply circuit and the control circuit for controlling the opening and closing of the switches are controlled so as to obtain a circuit operation described later. Further, other switches and capacitors are added so as to include a reset circuit for setting an initial value of the analog voltage output, an integration circuit with gain, an incomplete integration circuit, and the like. It is omitted in the description. Note that the circuit of the D / A converter 10 including such a power supply circuit or the like is provided as a semiconductor integrated circuit as a single unit or a system including other circuits, and is used in an electronic device or the like.
  • the D / A converter 10 determines whether the input data is positive or negative by the control circuit, and is connected to the first reference voltage Vr1 when the positive sign is 1 as described above.
  • the first switch SW1 to be closed is closed.
  • the second switch SW2 connected to the second reference voltage Vr2 is closed.
  • the positive sign is 1
  • the second switch SW2 is opened
  • the negative sign is 0, the first switch SW1 is opened.
  • One of the first switch SW1 and the second switch SW2 is closed and the other is opened.
  • control signal Din is generated by the control circuit to determine the absolute value of the input data and determine the size of the first capacitor C1 so that the capacitance value is proportional to the absolute value.
  • the D / A converter 10 is controlled to perform the following switching operation and outputs an analog voltage. For example, when (1010) is input, as described above, the first switch SW1 is closed and the second switch SW2 is opened. Then, during the period when the clock ⁇ 1 is at a high level, the third switch SW3 is opened, the fourth switch SW4 is closed, the fifth switch SW5 is opened, and the sixth switch SW6 is closed. As a result, the first capacitor C1 adjusted by the control signal Din is charged so as to become the first reference voltage Vr1.
  • the fourth switch SW4 and the sixth switch SW6 are opened, and the third switch SW3 and the fifth switch SW5 are closed.
  • the charge charged in the first capacitor C1 is transferred to the second capacitor C2.
  • An integration operation for accumulating charges in the second capacitor C2 is obtained, and the output voltage of the operational amplifier OP1 is determined according to the capacitance ratio between the first capacitor C1 and the second capacitor C2.
  • the capacitance value of the first capacitor C1 is variable corresponding to the digital value that is input data. More specifically, as shown in FIG. 2, the main part of the D / A converter 10 of the present embodiment includes a switch including a seventh switch SW7, an eighth switch SW8, and a third capacitor C3. This is a circuit including a variable capacitor in which n capacitors CU are connected in parallel. The n switched capacitors CU are selected from 0 to n, and the combined capacitance value of the parallel connection can be set in a staircase pattern.
  • the control circuit calculates the absolute value of the input data, and the effective number of the switched capacitor CU is varied by the control signal Din so that the capacitance value is proportional to the absolute value. . That is, switch control for closing the seventh switch SW7 and opening the eighth switch SW8 is performed on the effective number of switched capacitors CU proportional to the absolute value of the input data based on the control signal Din. If the seventh switch SW7 is closed and the eighth switch SW8 is opened based on the control signal Din, the switch-enabled capacitor CU is validated. In this state, the fourth switch SW4 is set to the third reference voltage Vr3. When connected to the third capacitor C3, the third capacitor C3 is charged. If the seventh switch SW7 is opened and the eighth switch SW8 is closed, the third capacitor C3 has both sides of the eighth switch SW8 and the fourth switch SW4 connected to the third reference voltage Vr3. Therefore, the capacitor CU with a switch is invalidated.
  • the equivalent circuit of the switched capacitor CU is a three-terminal circuit composed of a resistor and a capacitor.
  • the seventh switch SW7 is opened and the eighth switch SW8 is closed, the seventh switch SW7 is a high resistance off resistance Roff, and the eighth switch SW8 is a low resistance on resistance Ron.
  • is there. 3 corresponds to one switch, but an equivalent circuit to which a switch such as the sixth switch SW6 is connected can be represented by a series-connected resistor. Therefore, if the resistance value of FIG. 3 is replaced with the resistance value of the combined resistance, the following description is the same.
  • FIG. 3A when the first reference voltage Vr1 is applied to the seventh switch SW7, the third capacitor C3 is divided by the following equation via the off-resistance Roff. The charged voltage Voff1 is charged.
  • Voff1 (Vr1-Vr3) ⁇ Ron / (Roff + Ron)
  • the third capacitor C3 is expressed by the following equation via the off-resistance Roff. Is charged to a voltage Voff2 divided into two.
  • Voff2 (Vr2-Vr3) ⁇ Ron / (Roff + Ron)
  • the third reference voltage Vr3 is a ground potential.
  • the voltage Voff1 and the voltage Voff2 are numerical values having the same magnitude and different polarities.
  • the first switch SW1 when the input digital signal with polarity is zero, the first switch SW1 is closed and the second switch SW2 is opened, and the first switch SW1 is opened and the second switch SW1 is opened. Control is performed to switch between when the switch SW2 is closed. At this time, the difference between the number of times the first switch SW1 is closed and the second switch SW2 is opened and the number of times the first switch SW1 is opened and the second switch SW2 is closed is minimized. Thus, the first switch SW1 and the second switch SW2 are controlled. Specifically, this will be described below.
  • FIG. 4 is an explanatory diagram showing a driving method in the first example of the D / A converter 10 according to the embodiment of the present invention.
  • FIG. 5 is an explanatory diagram showing a driving method in the second embodiment.
  • FIG. 6 is an explanatory diagram showing a driving method in a comparative example. 4 to 6, Din is a signal (1 or 0) for selecting the switched capacitor CU, SCL is a polarity sign (1 or 0), Vin is a charging voltage of the third capacitor C3, and the horizontal axis Is the time axis.
  • Din is a signal (1 or 0) for selecting the switched capacitor CU
  • SCL is a polarity sign (1 or 0)
  • Vin is a charging voltage of the third capacitor C3
  • the horizontal axis Is the time axis.
  • the third capacitor C3 is charged to the voltage Voff2.
  • the state in which the first switch SW1 and the second switch SW2 are selected immediately before is continued. For this reason, the charge accumulated in the state of the voltage Voff1 is continuously transferred, or the charge accumulated in the state of the voltage Voff2 is continuously transferred and output, so that a large error occurs.
  • the polarity of the state in which the data is zero is stored before that, and the polarity of the inverted polarity Control to switch between the first switch SW1 and the second switch SW2 is performed so that That is, when the input digital signal with polarity is zero, the first switch so that the difference between the number of times the first switch SW1 is closed and the number of times the second switch SW2 is closed is minimized.
  • SW1 and the second switch SW2 are alternately closed.
  • the first switch SW1 and the second switch SW2 are random. Opening and closing is controlled by a sign that can be considered as According to this configuration, when the digital signal is 0, a positive output is generated in the state of the voltage Voff1 by the first reference voltage Vr1, and a negative output is generated in the state of the voltage Voff2 by the second reference voltage Vr2. Are repeated at random, and averaged to produce an output close to zero.
  • the first switch SW1 when the input digital signal with polarity is zero, the first switch SW1 is closed and the second switch SW2 is opened, and the first switch SW1. Is opened and the second switch SW2 is closed.
  • the digital signal when the digital signal is zero, switching is performed between a case where a positive output is generated by the first reference voltage Vr1 and a case where a negative output is generated by the second reference voltage Vr2.
  • the error accumulated in either state is canceled out, and the output is close to zero.
  • the first switch SW1 and the second switch SW2 are controlled so that the difference between the number of times the switch SW1 is opened and the second switch SW2 is closed is minimized.
  • the first switch SW1 and the second switch SW2 are alternately closed when the input digital signal with polarity is zero. According to this configuration, when the digital signal is zero, the case where a positive output is generated by the first reference voltage Vr1 and the case where a negative output is generated by the second reference voltage Vr2 are alternately repeated. Therefore, the output is stable and close to zero.
  • the opening / closing is controlled by a code that allows the first switch SW1 and the second switch SW2 to be regarded as random. You may make it do.
  • the digital signal when the digital signal is zero, a case where a positive output is generated by the first reference voltage Vr1 and a case where a negative output is generated by the second reference voltage Vr2 are randomly repeated. Therefore, the output is close to zero.
  • the D / A converter 10 of this embodiment includes a sixth switch SW6, and the first switch SW1 and the second switch SW2 are controlled by the control line SCL so that one is closed and the other is opened.
  • the According to this configuration if the sixth switch SW6 is open, it can be opened even if either the first switch SW1 or the second switch SW2 is closed, so only one control line SCL is required. . Since the sixth switch SW6 can control the current to flow when necessary, low power consumption and high accuracy can be achieved.
  • the first capacitor C1 is formed by connecting a plurality of switched capacitors CU including a seventh switch SW7, an eighth switch SW8, and a third capacitor C3 in parallel.
  • Variable capacity since it is a variable capacitor having the first switch SW1 and the second switch SW2 as inputs, complicated control is not required, and low power consumption and high accuracy can be achieved.
  • the number of switch-attached capacitors CU connected in parallel may be increased.
  • the capacitance value of the third capacitor varies individually due to manufacturing variations of the switched capacitor CU, if a different switched capacitor CU is selected for each clock ⁇ 1, integrated analog The influence of the voltage on the output error can be reduced. By controlling in this way, higher accuracy can be achieved.
  • FIG. 7 is a circuit diagram of a main part showing a D / A converter 20 of a second modification including a specific example of a variable capacitor.
  • the sixth switch SW6 as shown in FIG. 2 is not inserted in the main part of the D / A converter 20 of the second modified example.
  • the other parts are the same as the main part of the D / A converter 10 including the specific example of the variable capacitor shown in FIG.
  • the control circuit obtains the absolute value of the input data, and the effective number of the switched capacitor CU is varied so that the capacitance value is proportional to the absolute value.
  • the D / A converter 20 of the second modified example determines whether the input data is positive or negative by the control circuit, and when the polarity is positive sign 1, at the timing when the clock ⁇ 1 becomes high level, The first switch SW1 connected to the first reference voltage Vr1 is closed. When the polarity is a negative sign 0, the second switch SW2 connected to the second reference voltage Vr2 is closed at the timing when the clock ⁇ 1 becomes high level. When the positive sign is 1, the second switch SW2 is opened, and when the negative sign is 0, the first switch SW1 is opened. At this time, the first switch SW1 and the second switch SW2 are in a complementary relationship in which only one of them is closed.
  • the main part of the D / A converter 20 of the second modified example controls to close the first switch SW1 or the second switch SW2 at the timing when the clock ⁇ 1 becomes high level, and the sixth switch SW6. 2 is the same as the main part of the D / A converter 10 including the specific example of the variable capacitor shown in FIG.
  • the D / A converter 20 according to the second modified example has a difference between the number of times the first switch SW1 is closed and the number of times the second switch SW2 is closed when the input digital signal with polarity is zero.
  • the first switch SW1 and the second switch SW2 are controlled at the timing when the clock ⁇ 1 becomes high level.
  • the first reference voltage Vr1 is controlled so as to reduce the difference in the number of times between the case where a positive output is made and the case where a negative output is made by the second reference voltage Vr2. Therefore, the error accumulated in one of the states is canceled out.
  • FIG. 8 is a circuit diagram of a main part showing a D / A converter 30 according to a third modification of the embodiment of the present invention.
  • FIG. 9 is a circuit diagram of a main part showing a D / A converter 30 of a third modification including a specific example of a variable capacitor.
  • the main part of the D / A converter 30 of the third modified example is the first control line SL1 for controlling the first switch SW11 connected to the first reference voltage Vr1.
  • a second control line SL2 for controlling the second switch SW12 connected to the second reference voltage Vr2.
  • the first control line SL1 and the second control line SL2 are controlled such that either one is opened or one is closed.
  • a control signal for closing the first switch SW11 is transmitted to the first control line SL1 by a control circuit (not shown) when the input data is positive. Further, when the input data is negative, a control signal for closing the second switch SW12 is transmitted to the second control line SL2 while the clock ⁇ 1 is at a high level. In other states, the first switch SW11 and the second switch SW12 are controlled to be open. The first switch SW11 and the second switch SW12 are directly connected to the third switch SW3 and the first capacitor C1, and the sixth switch SW6 as shown in FIGS. 1 and 2 is not inserted. .
  • the absolute value of the input data is obtained by the control circuit, and the effective number of the capacitance CU with the switch is varied so that the capacitance value is proportional to the absolute value.
  • the first switch is set so that the difference between the number of times the first switch SW11 is closed and the number of times the second switch SW2 is closed is minimized.
  • SW11 and the second switch SW12 are controlled. According to this configuration, the error of outputting zero is canceled out, and the first switch SW11 and the second switch SW12 can be controlled to flow current when necessary, so that low power consumption and high accuracy can be achieved. can do.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

The main section of this D/A converter (10) is equipped with a first switch (SW1) which is connected to a first reference voltage (Vr1), a second switch (SW2) which is connected to a second reference voltage (Vr2), and a third switch (SW3) which is connected to a third reference voltage (Vr3). The A/D converter is also equipped with a first capacitor (C1), a fourth switch (SW4) which is connected to the third reference voltage (Vr3), and a fifth switch (SW5) which is connected to the first capacitor (C1) and the fourth switch (SW4). In addition, the D/A converter is also equipped with an operational amplifier (OP1) which is connected to the fifth switch (SW5) and a second capacitor (C2) which is connected to the fifth switch (SW5) and the operational amplifier (OP1). When an input digital signal with polarity is zero, control is performed so as to switch between a case wherein the first switch (SW1) is closed and the second switch (SW2) is opened and a case wherein the first switch (SW1) is opened and the second switch (SW2) is closed. Consequently, a high-precision D/A converter is provided.

Description

Ｄ／Ａ変換器D / A converter
　本発明は、デジタル信号をアナログ電圧に変換する高精度なＤ／Ａ変換器に関する。 The present invention relates to a high-precision D / A converter that converts a digital signal into an analog voltage.
　デジタル信号をアナログ電圧に変換する方式は数多く提案されているが、近年では、精度および回路規模の観点から、オーバーサンプリングを用い、ノイズシェーピング機能をもつデルタシグマ変調器が多用されている。これは、オーバーサンプリング部とデルタシグマ変調部分がデジタル回路で構成されるため、近年の微細プロセス技術に適合しており、高速動作やサイズ縮小が見込めるためである。また別の理由は、デジタル回路以後のアナログ回路部分の要求、たとえば、真にデジタルからアナログへ変換する部分のビット幅・階調が小さくて済むことや、後置されるローパスフィルタ特性が緩和されるためである。 Many schemes for converting a digital signal into an analog voltage have been proposed, but in recent years, from the viewpoint of accuracy and circuit scale, a delta-sigma modulator using oversampling and having a noise shaping function is frequently used. This is because the oversampling part and the delta-sigma modulation part are composed of digital circuits, so that it is compatible with recent fine process technology and high speed operation and size reduction can be expected. Another reason is that the requirements of the analog circuit part after the digital circuit, for example, the bit width and gradation of the part that truly converts from digital to analog can be reduced, and the low-pass filter characteristics that are placed downstream are alleviated. Because.
　このようなデルタシグマ変調器から出力される信号を低ノイズでＤ／Ａ変換するため、微細プロセス技術に適合したスイッチト・キャパシタ型のＤ／Ａ変換器（ｄｉｇｉｔａｌ　ｔｏ　ａｎａｌｏｇ　ｃｏｎｖｅｒｔｅｒ）が使用されている。例えば、特許文献１に開示されたＤ／Ａ変換器では、正負の２つの基準電圧と複数のキャパシタを用いてＤ／Ａ変換を行う。 In order to D / A convert the signal output from such a delta-sigma modulator with low noise, a switched-capacitor type D / A converter (digital to analog converter) suitable for a fine process technology is used. Yes. For example, the D / A converter disclosed in Patent Document 1 performs D / A conversion using two positive and negative reference voltages and a plurality of capacitors.
　図１０は、特許文献１に記載されたＤ／Ａ変換器９００を示す回路図である。 FIG. 10 is a circuit diagram showing a D / A converter 900 described in Patent Document 1.
　クロック供給部２００から供給されるクロックφ９０１がハイレベルである期間に、スイッチＳＵＧ１～ＳＵＧｅの動作によって、容量素子Ｃ９０１～Ｃ９０ｅの左側の端子が基準電圧Ｖｒ＋又はＶｒ－に接続され、容量素子Ｃ９０１～Ｃ９０ｅはそれぞれ基準電圧に対応する電荷を保持する。また、スイッチＳＵＧｆ～ＳＵＧｉの動作によって、容量素子Ｃ９０ｆ～Ｃ９０ｉの左側の端子が基準電位Ｖｒ＋、Ｖｒ－、又は接地電位に接続され、容量素子Ｃ９０ｆ～Ｃ９０ｉは、それぞれ基準電圧に応じた電荷を保持する。 During the period when the clock φ901 supplied from the clock supply unit 200 is at the high level, the left terminals of the capacitive elements C901 to C90e are connected to the reference voltage Vr + or Vr− by the operation of the switches SUG1 to SUGe. Each C90e holds a charge corresponding to the reference voltage. Further, by the operation of the switches SUGf to SUGi, the terminals on the left side of the capacitive elements C90f to C90i are connected to the reference potentials Vr +, Vr−, or the ground potential, and the capacitive elements C90f to C90i hold charges corresponding to the reference voltages, respectively. To do.
　クロックφ９０２がハイレベルになると、容量素子Ｃ９０１～Ｃ９０ｅが、演算増幅器１００の出力端子（出力電位ＯＵＴ）と反転入力端子との間に並列に接続される。また、クロックφ９０２がハイレベルになると、スイッチＳＵＧｆ～ＳＵＧｉのうち、基準電位Ｖｒ＋又はＶｒ－に接続されるスイッチは開状態となり、接地電位に接続されるスイッチは閉状態となる。これによって、容量素子Ｃ９０ｆ～Ｃ９０ｉに、クロックφ９０１がハイレベルである期間に保持された電荷が、演算増幅器１００の帰還容量素子Ｃｆｂに転送つまり、積分される。 When the clock φ902 becomes high level, the capacitive elements C901 to C90e are connected in parallel between the output terminal (output potential OUT) and the inverting input terminal of the operational amplifier 100. Further, when the clock φ902 becomes high level, among the switches SUGf to SUGi, the switch connected to the reference potential Vr + or Vr− is opened, and the switch connected to the ground potential is closed. As a result, the charges held in the capacitive elements C90f to C90i while the clock φ901 is at the high level are transferred, that is, integrated to the feedback capacitive element Cfb of the operational amplifier 100.
　その結果、容量素子Ｃ９０１～Ｃ９０ｅ及び帰還容量素子Ｃｆｂの間で、電荷の分配が起こり、出力電位ＯＵＴの最大振幅をより大きくすることができる。 As a result, charge distribution occurs between the capacitive elements C901 to C90e and the feedback capacitive element Cfb, and the maximum amplitude of the output potential OUT can be further increased.
特開２００３－２６４４６４号公報JP 2003-264464 A
　しかしながら、スイッチト・キャパシタ型のＤ／Ａ変換器は、電圧を出力する構成に、容量素子Ｃ９０１～Ｃ９０ｅ等の容量を使用しているため、デジタル信号がゼロのときに蓄積される電荷が無視できず、アナログ電圧出力に誤差を生じてしまう可能性があった。 However, the switched capacitor type D / A converter uses capacitors such as the capacitive elements C901 to C90e in the configuration for outputting the voltage, so the charge accumulated when the digital signal is zero is ignored. This could cause an error in the analog voltage output.
　本発明は、上述した課題を解決するものであり、高精度なＤ／Ａ変換器を提供することを目的とする。 This invention solves the subject mentioned above, and aims at providing a highly accurate D / A converter.
　本発明のＤ／Ａ変換器は、第１の基準電圧に接続する第１のスイッチと、第２の基準電圧に接続する第２のスイッチと、前記第１のスイッチ及び前記第２のスイッチに接続され第３の基準電圧に接続する第３のスイッチと、前記第１のスイッチ、前記第２のスイッチ及び前記第３のスイッチに接続された第１の容量と、前記第１の容量に接続され第３の基準電圧に接続された第４のスイッチと、前記第１の容量及び前記第４のスイッチに接続された第５のスイッチと、前記第５のスイッチに接続されたオペアンプと、前記第５のスイッチと前記オペアンプに接続された第２の容量とを備え、入力された極性付きデジタル信号が０のとき、前記第１のスイッチが閉じられ、前記第２のスイッチが開放される場合と、前記第１のスイッチが開放され、前記第２のスイッチが閉じられる場合と、を切り替える制御が行われることを特徴とする。 A D / A converter according to the present invention includes a first switch connected to a first reference voltage, a second switch connected to a second reference voltage, the first switch, and the second switch. A third switch connected to the third reference voltage, a first capacitor connected to the first switch, the second switch, and the third switch, and connected to the first capacitor A fourth switch connected to a third reference voltage; a fifth switch connected to the first capacitor and the fourth switch; an operational amplifier connected to the fifth switch; A fifth switch and a second capacitor connected to the operational amplifier, and when the input digital signal with polarity is 0, the first switch is closed and the second switch is opened And the first switch is open Is characterized in that the control of switching the, and when the second switch is closed is performed.
　この構成によれば、デジタル信号がゼロのとき、第１の基準電圧によって、正の出力がされる場合と、第２の基準電圧によって負の出力がされる場合と、を切り替えるので、いずれか一方の状態で蓄積される誤差が相殺され、ゼロに近い出力となる。 According to this configuration, when the digital signal is zero, switching is performed between a case where a positive output is generated by the first reference voltage and a case where a negative output is generated by the second reference voltage. The error accumulated in one state is canceled out and the output is close to zero.
　また本発明のＤ／Ａ変換器において、入力された極性付きデジタル信号が０のときに、前記第１のスイッチが閉じられ、前記第２のスイッチが開放される回数と、前記第１のスイッチが開放され、前記第２のスイッチが閉じられる回数と、の差が最小となるように前記第１のスイッチと前記第２のスイッチとが制御されることが好ましい。 In the D / A converter of the present invention, when the input digital signal with polarity is 0, the number of times the first switch is closed and the second switch is opened, and the first switch It is preferable that the first switch and the second switch are controlled so that the difference between the number of times of opening and closing the second switch is minimized.
　この構成によれば、デジタル信号が０のとき、第１の基準電圧によって、正の出力がされる場合と、第２の基準電圧によって負の出力がされる場合との回数の差が小さくなるように制御されるので、更にゼロに近い出力となる。 According to this configuration, when the digital signal is 0, the difference between the number of times when the positive output is generated by the first reference voltage and the case where the negative output is output by the second reference voltage is small. Therefore, the output is further close to zero.
　本発明のＤ／Ａ変換器において、入力された極性付きデジタル信号がゼロのときに、前記第１のスイッチと前記第２のスイッチとが交互に閉じられることが好ましい。 In the D / A converter of the present invention, it is preferable that the first switch and the second switch are alternately closed when the input digital signal with polarity is zero.
　この構成によれば、デジタル信号が０のとき、第１の基準電圧によって、正の出力がされる場合と、第２の基準電圧によって負の出力がされる場合とが交互に繰り返されるので、安定して０に近い出力となる。 According to this configuration, when the digital signal is 0, the case where a positive output is generated by the first reference voltage and the case where a negative output is generated by the second reference voltage are alternately repeated. The output is stable and close to 0.
　本発明のＤ／Ａ変換器において、入力された極性付きデジタル信号がゼロのときに、前記第１のスイッチと前記第２のスイッチとがランダムとみなすことができる符号により開閉を制御されるようにしてもよい。 In the D / A converter of the present invention, when the input digital signal with polarity is zero, the first switch and the second switch are controlled to open and close by a code that can be regarded as random. It may be.
　この構成によれば、デジタル信号がゼロのとき、第１の基準電圧によって、正の出力がされる場合と、第２の基準電圧によって負の出力がされる場合とがランダムに繰り返されるので、ゼロに近い出力となる。 According to this configuration, when the digital signal is zero, a case where a positive output is generated by the first reference voltage and a case where a negative output is generated by the second reference voltage are randomly repeated. The output is close to zero.
　本発明のＤ／Ａ変換器において、前記第１のスイッチ及び前記第２のスイッチと、前記第３のスイッチ及び前記第１の容量と、を接続するように挿入された第６のスイッチを備え、前記第１のスイッチと前記第２のスイッチとは、一方が閉じ他方が開放されるように制御線で制御されることが好ましい。 In the D / A converter according to the present invention, the D / A converter includes a sixth switch inserted to connect the first switch and the second switch, the third switch and the first capacitor. The first switch and the second switch are preferably controlled by a control line so that one is closed and the other is opened.
この構成によれば、第６のスイッチが開いていれば、第１のスイッチ及び第２のスイッチのいずれか一方が閉じていても開放されるので、制御線が１つで済む。第６のスイッチで必要なときに電流を流すように制御できるので、低消費電力で、高精度にすることができる。 According to this configuration, if the sixth switch is open, it can be opened even if either the first switch or the second switch is closed, so only one control line is required. Since the sixth switch can be controlled so that a current flows when necessary, low power consumption and high accuracy can be achieved.
　本発明のＤ／Ａ変換器において、前記第１のスイッチを制御する第１の制御線と、前記第２のスイッチを制御する第２の制御線と、を備え、前記第１の制御線と前記第２の制御線とがいずれも開放されているか、いずれか一方が閉じるように制御されていることが好ましい。 In the D / A converter of the present invention, the D / A converter includes: a first control line that controls the first switch; and a second control line that controls the second switch; It is preferable that all of the second control lines are opened or controlled so that one of them is closed.
　この構成によれば、第１のスイッチ及び第２のスイッチを必要なときに電流を流すように制御できるので、低消費電力で、高精度にすることができる。 According to this configuration, the first switch and the second switch can be controlled to flow current when necessary, so that low power consumption and high accuracy can be achieved.
　本発明のＤ／Ａ変換器において、第１の容量は、第７のスイッチ、第８のスイッチ及び第３の容量を備えたスイッチ付き容量が複数並列接続されてなる可変容量であることが好ましい。 In the D / A converter of the present invention, the first capacitor is preferably a variable capacitor formed by connecting a plurality of switched capacitors each having a seventh switch, an eighth switch, and a third capacitor. .
　この構成によれば、第１のスイッチ及び第２のスイッチを入力とする可変容量であるので、複雑な制御を必要とせず、低消費電力で、高精度にすることができる。 According to this configuration, since it is a variable capacitor having the first switch and the second switch as inputs, complicated control is not required, and low power consumption and high accuracy can be achieved.
　本発明によれば、デジタル信号がゼロのとき、正の出力がされる場合と負の出力がされる場合とを切り替えるので、誤差が相殺され、高精度なＤ／Ａ変換器を提供することができる。 According to the present invention, when a digital signal is zero, switching between a case where a positive output is made and a case where a negative output is made is made, so that an error is canceled and a highly accurate D / A converter is provided. Can do.
本発明の実施形態のＤ／Ａ変換器を示す主要部の回路図である。It is a circuit diagram of the principal part which shows the D / A converter of the embodiment of the present invention. 可変容量の具体的事例を含むＤ／Ａ変換器を示す主要部の回路図である。It is a circuit diagram of the principal part which shows the D / A converter containing the specific example of a variable capacity | capacitance. スイッチ付き容量の等価回路図であり、（ａ）は第１の基準電圧に接続されたスイッチ付き容量の等価回路図であり、（ｂ）は第２の基準電圧に接続されたスイッチ付き容量の等価回路図である。2 is an equivalent circuit diagram of a capacitor with a switch, (a) is an equivalent circuit diagram of a capacitor with a switch connected to a first reference voltage, and (b) is an equivalent circuit diagram of a capacitor with a switch connected to a second reference voltage. It is an equivalent circuit diagram. 本発明の実施形態のＤ／Ａ変換器の第１実施例における駆動方法を示す説明図である。It is explanatory drawing which shows the drive method in the 1st Example of the D / A converter of embodiment of this invention. 第２実施例における駆動方法を示す説明図である。It is explanatory drawing which shows the drive method in 2nd Example. 比較例における駆動方法を示す説明図である。It is explanatory drawing which shows the drive method in a comparative example. 可変容量の具体的事例を含む第２変形例のＤ／Ａ変換器を示す主要部の回路図である。It is a circuit diagram of the principal part which shows the D / A converter of the 2nd modification containing the specific example of a variable capacity | capacitance. 第３変形例のＤ／Ａ変換器を示す主要部の回路図である。It is a circuit diagram of the principal part which shows the D / A converter of a 3rd modification. 可変容量の具体的事例を含む第３変形例のＤ／Ａ変換器を示す主要部の回路図である。It is a circuit diagram of the principal part which shows the D / A converter of the 3rd modification containing the specific example of a variable capacity | capacitance. 従来のＤ／Ａ変換器を示す回路図である。It is a circuit diagram which shows the conventional D / A converter.
　以下、本発明の実施の形態について図面を用いて詳細に説明する。なお、分かりやすいように、図面は寸法を適宜変更している。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. For easy understanding, the dimensions of the drawings are appropriately changed.
　図１は、本発明の実施形態のＤ／Ａ変換器１０を示す主要部の回路図である。図２は、可変容量の具体的事例を含むＤ／Ａ変換器１０を示す主要部の回路図である。図３は、スイッチ付き容量の等価回路図であり、図３（ａ）は第１の基準電圧に接続されたスイッチ付き容量の等価回路図であり、図３（ｂ）は、第２の基準電圧Ｖｒ２に接続されたスイッチ付き容量ＣＵの等価回路図である。 FIG. 1 is a circuit diagram of a main part showing a D / A converter 10 according to an embodiment of the present invention. FIG. 2 is a circuit diagram of a main part showing the D / A converter 10 including a specific example of a variable capacitor. FIG. 3 is an equivalent circuit diagram of a capacitor with a switch, FIG. 3 (a) is an equivalent circuit diagram of a capacitor with a switch connected to the first reference voltage, and FIG. 3 (b) is a second reference circuit. It is an equivalent circuit diagram of the capacitor with a switch CU connected to the voltage Vr2.
　本発明の実施形態のＤ／Ａ変換器１０は、出力端子と反転入力端子とが容量を介して接続されたオペアンプ（演算増幅器）を用いたスイッチト・キャパシタ型Ｄ／Ａ変換器である。本実施形態のＤ／Ａ変換器１０は、デジタル信号に極性を示す符号が付いた符号付きデジタル信号を片極性のアナログ信号に変換する機能を有している。具体的には、例えば、４ビットのデジタル信号（００００）～（１１１１）の最上位を正負の極性データ（正の場合に１、負の場合に０）に割り当てた符号付きデジタル信号であり、変換後は１Ｖ～３Ｖ等のアナログ電圧を出力する。この場合、（０１１１）のデジタル値は負側の極性の最大値、（１１１１）のデジタル値が正側の極性の最大値であり、（１０００）のデジタル値は正側の極性の最小値（ゼロ）であり、（００００）のデジタル値が負側の極性の最小値（ゼロ）である。なお、（０１１１）のデジタル値及び（１１１１）のデジタル値は、絶対値が同じ大きさである。（１０００）のデジタル値及び（００００）のデジタル値は、量子化により符号データが付与されているが、実質的に同じゼロの値である。アナログ信号に変換されたアナログ電圧は、負側の最大値が１Ｖ、負側及び正側の最小値（ゼロ）が２Ｖ、正側の最大値が３Ｖで出力される。 The D / A converter 10 according to the embodiment of the present invention is a switched capacitor type D / A converter using an operational amplifier (operational amplifier) in which an output terminal and an inverting input terminal are connected via a capacitor. The D / A converter 10 according to the present embodiment has a function of converting a signed digital signal in which a sign indicating polarity is added to a digital signal into a unipolar analog signal. Specifically, for example, a signed digital signal in which the most significant of 4-bit digital signals (0000) to (1111) is assigned to positive / negative polarity data (1 for positive, 0 for negative), After conversion, an analog voltage such as 1V to 3V is output. In this case, the digital value of (0111) is the maximum value of the negative polarity, the digital value of (1111) is the maximum value of the positive polarity, and the digital value of (1000) is the minimum value of the positive polarity ( Zero), and the digital value of (0000) is the minimum negative polarity value (zero). Note that the digital value of (0111) and the digital value of (1111) have the same absolute value. The digital value of (1000) and the digital value of (0000) are substantially the same zero value although code data is given by quantization. The analog voltage converted into an analog signal is output with a maximum value on the negative side of 1V, a minimum value (zero) on the negative and positive sides of 2V, and a maximum value on the positive side of 3V.
　本発明の実施形態のＤ／Ａ変換器１０の主要部は、図１に示すように、第１の基準電圧Ｖｒ１に接続する第１のスイッチＳＷ１と、第２の基準電圧Ｖｒ２に接続する第２のスイッチＳＷ２と、第３の基準電圧Ｖｒ３に接続された第３のスイッチＳＷ３と、を備えている。また、入力データであるデジタル値に対応して容量値が可変される第１の容量Ｃ１と、第３の基準電圧Ｖｒ３に接続された第４のスイッチＳＷ４と、第１の容量Ｃ１及び第４のスイッチＳＷ４に接続された第５のスイッチＳＷ５と、を備えている。そして、第５のスイッチＳＷ５に接続されたオペアンプＯＰ１と、第５のスイッチＳＷ５とオペアンプＯＰ１に接続された第２の容量Ｃ２と、を備えている。さらに、第１のスイッチＳＷ１及び第２のスイッチＳＷ２と、第３のスイッチＳＷ３及び第１の容量Ｃ１と、を接続するように挿入された第６のスイッチＳＷ６を備えている。 As shown in FIG. 1, the main part of the D / A converter 10 according to the embodiment of the present invention includes a first switch SW1 connected to the first reference voltage Vr1 and a second switch connected to the second reference voltage Vr2. 2 switch SW2 and a third switch SW3 connected to the third reference voltage Vr3. In addition, the first capacitor C1 whose capacitance value is variable corresponding to the digital value that is the input data, the fourth switch SW4 connected to the third reference voltage Vr3, the first capacitor C1 and the fourth capacitor And a fifth switch SW5 connected to the switch SW4. An operational amplifier OP1 connected to the fifth switch SW5 and a second capacitor C2 connected to the fifth switch SW5 and the operational amplifier OP1 are provided. Further, a sixth switch SW6 is provided so as to connect the first switch SW1 and the second switch SW2, the third switch SW3 and the first capacitor C1.
　第１のスイッチＳＷ１と第２のスイッチＳＷ２とは、一方が閉じ他方が開放されるように制御線ＳＣＬで制御される。第１のスイッチＳＷ１と第２のスイッチＳＷ２とは、いずれか一方のみが閉じる相補関係になっている。一方、第１のスイッチＳＷ１及び第２のスイッチＳＷ２以外のスイッチ（ＳＷ３～ＳＷ６）は、クロックφ１及びクロックφ２によって開閉制御されている。 The first switch SW1 and the second switch SW2 are controlled by the control line SCL so that one is closed and the other is opened. The first switch SW1 and the second switch SW2 have a complementary relationship in which only one of them is closed. On the other hand, the switches (SW3 to SW6) other than the first switch SW1 and the second switch SW2 are controlled to be opened and closed by the clock φ1 and the clock φ2.
　第３の基準電圧Ｖｒ３は、本実施形態ではグランド電位である。本実施形態では、第１の基準電圧Ｖｒ１は、第２の基準電圧Ｖｒ２と大きさが同じで極性が異なる電圧である。また、オペアンプＯＰ１の非反転入力端子は第３の基準電圧Ｖｒ３に接続され、本実施形態ではグランド電位である。 In the present embodiment, the third reference voltage Vr3 is a ground potential. In the present embodiment, the first reference voltage Vr1 is a voltage having the same magnitude and a different polarity as the second reference voltage Vr2. The non-inverting input terminal of the operational amplifier OP1 is connected to the third reference voltage Vr3, which is the ground potential in this embodiment.
　なお、図示していないが、電源回路及び各スイッチ（ＳＷ１～ＳＷ６）を開閉制御するための制御回路によって、後述する回路動作が得られるように制御されている。また、アナログ電圧出力の初期値を設定するためのリセット回路や、ゲインを持たせた積分回路及び不完全積分回路等を備えるように、さらに他のスイッチや容量を追加するが、本実施形態の説明では省略している。なお、このような電源回路等を含むＤ／Ａ変換器１０の回路は、半導体集積回路として単体又は他の回路を含むシステムの状態で提供され、電子機器等に使用される。 Although not shown, the power supply circuit and the control circuit for controlling the opening and closing of the switches (SW1 to SW6) are controlled so as to obtain a circuit operation described later. Further, other switches and capacitors are added so as to include a reset circuit for setting an initial value of the analog voltage output, an integration circuit with gain, an incomplete integration circuit, and the like. It is omitted in the description. Note that the circuit of the D / A converter 10 including such a power supply circuit or the like is provided as a semiconductor integrated circuit as a single unit or a system including other circuits, and is used in an electronic device or the like.
　本発明の実施形態のＤ／Ａ変換器１０は、制御回路によって、入力データが正なのか負なのかを判断し、前述のように正の符号１のときは第１の基準電圧Ｖｒ１に接続する第１のスイッチＳＷ１を閉じる。極性が負の符号０のときは、第２の基準電圧Ｖｒ２に接続する第２のスイッチＳＷ２を閉じる。また、正の符号１のときは第２のスイッチＳＷ２を開き、負の符号０のときは第１のスイッチＳＷ１を開放する。第１のスイッチＳＷ１と第２のスイッチＳＷ２とは、いずれか一方が閉じると共に、いずれか他方が開放される。 The D / A converter 10 according to the embodiment of the present invention determines whether the input data is positive or negative by the control circuit, and is connected to the first reference voltage Vr1 when the positive sign is 1 as described above. The first switch SW1 to be closed is closed. When the polarity is a negative sign 0, the second switch SW2 connected to the second reference voltage Vr2 is closed. When the positive sign is 1, the second switch SW2 is opened, and when the negative sign is 0, the first switch SW1 is opened. One of the first switch SW1 and the second switch SW2 is closed and the other is opened.
　次に、制御回路によって、入力データの絶対値を求め、絶対値に比例した容量値となるように第１の容量Ｃ１の大きさを決定する制御信号Ｄｉｎが生成される。例えば、（１０１０）の絶対値は２であり、単位容量をＣ０とすれば、Ｃ１＝Ｃ０×２に調整される。 Next, the control signal Din is generated by the control circuit to determine the absolute value of the input data and determine the size of the first capacitor C1 so that the capacitance value is proportional to the absolute value. For example, the absolute value of (1010) is 2, and if the unit capacity is C0, C1 = C0 × 2 is adjusted.
　本発明の実施形態のＤ／Ａ変換器１０は、以下のスイッチング動作を行うように制御されて、アナログ電圧が出力される。例えば、（１０１０）が入力されると、前述のように、第１のスイッチＳＷ１を閉じ、第２のスイッチＳＷ２を開放する。そして、クロックφ１がハイレベルである期間に、第３のスイッチＳＷ３を開き、第４のスイッチＳＷ４を閉じ、第５のスイッチＳＷ５を開放すると共に、第６のスイッチＳＷ６を閉じる。これによって、制御信号Ｄｉｎで調整された第１の容量Ｃ１が第１の基準電圧Ｖｒ１になるように充電される。 The D / A converter 10 according to the embodiment of the present invention is controlled to perform the following switching operation and outputs an analog voltage. For example, when (1010) is input, as described above, the first switch SW1 is closed and the second switch SW2 is opened. Then, during the period when the clock φ1 is at a high level, the third switch SW3 is opened, the fourth switch SW4 is closed, the fifth switch SW5 is opened, and the sixth switch SW6 is closed. As a result, the first capacitor C1 adjusted by the control signal Din is charged so as to become the first reference voltage Vr1.
　続いて、クロックφ２がハイレベルである期間に、第４のスイッチＳＷ４と第６のスイッチＳＷ６とを開放すると共に、第３のスイッチＳＷ３と第５のスイッチＳＷ５とを閉じる。これによって、第１の容量Ｃ１を充電していた電荷を第２の容量Ｃ２に転送する。第２の容量Ｃ２に電荷が蓄積される積分動作が得られると共に、オペアンプＯＰ１の出力電圧は第１の容量Ｃ１と第２の容量Ｃ２との容量比に応じて決定される。 Subsequently, while the clock φ2 is at a high level, the fourth switch SW4 and the sixth switch SW6 are opened, and the third switch SW3 and the fifth switch SW5 are closed. As a result, the charge charged in the first capacitor C1 is transferred to the second capacitor C2. An integration operation for accumulating charges in the second capacitor C2 is obtained, and the output voltage of the operational amplifier OP1 is determined according to the capacitance ratio between the first capacitor C1 and the second capacitor C2.
　第１の容量Ｃ１は、入力データであるデジタル値に対応して容量値が可変される。より具体的には、本実施形態のＤ／Ａ変換器１０の主要部は、図２に示すように、第７のスイッチＳＷ７、第８のスイッチＳＷ８及び第３の容量Ｃ３を備えたスイッチ付き容量ＣＵがｎ個並列接続されてなる可変容量を含む回路である。ｎ個のスイッチ付き容量ＣＵは、０個～ｎ個が選択されて並列接続の合成容量値を階段状に設定可能になっている。 The capacitance value of the first capacitor C1 is variable corresponding to the digital value that is input data. More specifically, as shown in FIG. 2, the main part of the D / A converter 10 of the present embodiment includes a switch including a seventh switch SW7, an eighth switch SW8, and a third capacitor C3. This is a circuit including a variable capacitor in which n capacitors CU are connected in parallel. The n switched capacitors CU are selected from 0 to n, and the combined capacitance value of the parallel connection can be set in a staircase pattern.
　本実施形態のＤ／Ａ変換器１０は、制御回路によって、入力データの絶対値を求め、絶対値に比例した容量値となるように制御信号Ｄｉｎでスイッチ付き容量ＣＵの有効数が可変される。すなわち、入力データの絶対値に比例した有効数のスイッチ付き容量ＣＵに対して、制御信号Ｄｉｎに基づき、第７のスイッチＳＷ７を閉じると共に、第８のスイッチＳＷ８を開放するスイッチ制御が行われる。制御信号Ｄｉｎに基づき、第７のスイッチＳＷ７を閉じると共に、第８のスイッチＳＷ８を開いていれば、スイッチ付き容量ＣＵとして有効化され、この状態で第４のスイッチＳＷ４が第３の基準電圧Ｖｒ３に接続されたときに第３の容量Ｃ３が充電される。第７のスイッチＳＷ７を開放すると共に、第８のスイッチＳＷ８を閉じていれば、第３の容量Ｃ３は第８のスイッチＳＷ８と第４のスイッチＳＷ４との両側が第３の基準電圧Ｖｒ３に接続されるので、スイッチ付き容量ＣＵとして無効化される。 In the D / A converter 10 of the present embodiment, the control circuit calculates the absolute value of the input data, and the effective number of the switched capacitor CU is varied by the control signal Din so that the capacitance value is proportional to the absolute value. . That is, switch control for closing the seventh switch SW7 and opening the eighth switch SW8 is performed on the effective number of switched capacitors CU proportional to the absolute value of the input data based on the control signal Din. If the seventh switch SW7 is closed and the eighth switch SW8 is opened based on the control signal Din, the switch-enabled capacitor CU is validated. In this state, the fourth switch SW4 is set to the third reference voltage Vr3. When connected to the third capacitor C3, the third capacitor C3 is charged. If the seventh switch SW7 is opened and the eighth switch SW8 is closed, the third capacitor C3 has both sides of the eighth switch SW8 and the fourth switch SW4 connected to the third reference voltage Vr3. Therefore, the capacitor CU with a switch is invalidated.
　次に、本実施形態のＤ／Ａ変換器１０が備えている特徴部分について、従来の問題点とその解決手法を実施例により説明する。 Next, with respect to the features provided in the D / A converter 10 of the present embodiment, conventional problems and solutions thereof will be described by way of examples.
　図３に示すように、スイッチ付き容量ＣＵの等価回路は、抵抗と容量とからなる３端子回路である。第７のスイッチＳＷ７を開放すると共に、第８のスイッチＳＷ８を閉じているときは、第７のスイッチＳＷ７は高い抵抗値のオフ抵抗Ｒｏｆｆ、第８のスイッチＳＷ８は低い抵抗値のオン抵抗Ｒｏｎである。なお、図３の抵抗は、それぞれ１個のスイッチに対応させていたが、第６のスイッチＳＷ６等のスイッチが接続された等価回路は直列接続の抵抗で表わすことができる。したがって、図３の抵抗値を合成抵抗の抵抗値に置き換えれば、以下の説明は同じである。図３（ａ）に示すように、第１の基準電圧Ｖｒ１が第７のスイッチＳＷ７に印加されたときには、オフ抵抗Ｒｏｆｆを介して、第３の容量Ｃ３は、以下の式のように分圧された電圧Ｖｏｆｆ１に充電される。 As shown in FIG. 3, the equivalent circuit of the switched capacitor CU is a three-terminal circuit composed of a resistor and a capacitor. When the seventh switch SW7 is opened and the eighth switch SW8 is closed, the seventh switch SW7 is a high resistance off resistance Roff, and the eighth switch SW8 is a low resistance on resistance Ron. is there. 3 corresponds to one switch, but an equivalent circuit to which a switch such as the sixth switch SW6 is connected can be represented by a series-connected resistor. Therefore, if the resistance value of FIG. 3 is replaced with the resistance value of the combined resistance, the following description is the same. As shown in FIG. 3A, when the first reference voltage Vr1 is applied to the seventh switch SW7, the third capacitor C3 is divided by the following equation via the off-resistance Roff. The charged voltage Voff1 is charged.
　Ｖｏｆｆ１＝（Ｖｒ１－Ｖｒ３）×Ｒｏｎ／（Ｒｏｆｆ＋Ｒｏｎ） Voff1 = (Vr1-Vr3) × Ron / (Roff + Ron)
　同様に、図３（ｂ）に示すように、第２の基準電圧Ｖｒ２が第７のスイッチＳＷ７に印加されたときには、オフ抵抗Ｒｏｆｆを介して、第３の容量Ｃ３は、以下の式のように分圧された電圧Ｖｏｆｆ２に充電される。 Similarly, as shown in FIG. 3B, when the second reference voltage Vr2 is applied to the seventh switch SW7, the third capacitor C3 is expressed by the following equation via the off-resistance Roff. Is charged to a voltage Voff2 divided into two.
　Ｖｏｆｆ２＝（Ｖｒ２－Ｖｒ３）×Ｒｏｎ／（Ｒｏｆｆ＋Ｒｏｎ） Voff2 = (Vr2-Vr3) × Ron / (Roff + Ron)
　第３の基準電圧Ｖｒ３は、本実施形態ではグランド電位である。本実施形態では、第１の基準電圧Ｖｒ１と第２の基準電圧Ｖｒ２とは大きさが同じで極性が異なるので、電圧Ｖｏｆｆ１と電圧Ｖｏｆｆ２とは大きさが同じで極性が異なる数値である。 In the present embodiment, the third reference voltage Vr3 is a ground potential. In the present embodiment, since the first reference voltage Vr1 and the second reference voltage Vr2 have the same magnitude and different polarities, the voltage Voff1 and the voltage Voff2 are numerical values having the same magnitude and different polarities.
　これらの電圧が、第３の容量Ｃ３を充電する充電電圧Ｖｉｎとなる。スイッチ付き容量ＣＵが無効化されているとき、オフ抵抗Ｒｏｆｆを介した充電電圧Ｖｉｎによる蓄積電荷については従来考慮されていなかった。また、大きなアナログ電圧を出力するとき、その電圧に対する誤差要因としては無視されるものであった。 These voltages become the charging voltage Vin for charging the third capacitor C3. When the switch-attached capacitor CU is disabled, the accumulated charge due to the charging voltage Vin via the off-resistance Roff has not been considered conventionally. Further, when a large analog voltage is output, an error factor for the voltage is ignored.
　しかしながら、より小さなアナログ電圧を出力するときには、誤差要因として無視できない。すなわち、出力する電圧が小さいときは、相対的に大きな割合を占めるようになると共に、図２のスイッチ付き容量ＣＵの大半が無効化されているので、それらが加算された大きな誤差になる。これは、入力データがゼロのときに顕著となり、入力データが長時間ゼロであるようなデジタル信号のアナログ変換における高精度化の課題であった。 However, when outputting a smaller analog voltage, it cannot be ignored as an error factor. That is, when the output voltage is small, it occupies a relatively large proportion, and since most of the switched capacitor CU in FIG. 2 is invalidated, a large error is added. This becomes conspicuous when the input data is zero, and has been a problem of high accuracy in analog conversion of a digital signal in which the input data is zero for a long time.
　本実施形態では、入力された極性付きデジタル信号がゼロのとき、第１のスイッチＳＷ１が閉じられ、第２のスイッチＳＷ２が開放される場合と、第１のスイッチＳＷ１が開放され、第２のスイッチＳＷ２が閉じられる場合と、を切り替える制御が行われる。このとき、第１のスイッチＳＷ１が閉じられ、第２のスイッチＳＷ２が開放される回数と、第１のスイッチＳＷ１が開放され、第２のスイッチＳＷ２が閉じられる回数と、の差が最小となるように第１のスイッチＳＷ１と第２のスイッチＳＷ２とが制御される。具体的には、以下に説明する。 In the present embodiment, when the input digital signal with polarity is zero, the first switch SW1 is closed and the second switch SW2 is opened, and the first switch SW1 is opened and the second switch SW1 is opened. Control is performed to switch between when the switch SW2 is closed. At this time, the difference between the number of times the first switch SW1 is closed and the second switch SW2 is opened and the number of times the first switch SW1 is opened and the second switch SW2 is closed is minimized. Thus, the first switch SW1 and the second switch SW2 are controlled. Specifically, this will be described below.
　図４は、本発明の実施形態のＤ／Ａ変換器１０の第１実施例における駆動方法を示す説明図である。図５は、第２実施例における駆動方法を示す説明図である。図６は、比較例における駆動方法を示す説明図である。図４～図６のＤｉｎはスイッチ付き容量ＣＵを選択する信号（１又は０）、ＳＣＬは極性の符号（１又は０）であり、Ｖｉｎは第３の容量Ｃ３の充電電圧であり、横軸は時間軸である。なお、説明を分かりやすくするために、クロックφ１がハイレベルである期間における状態のみを模式的に示したものであり、クロックφ２がハイレベルである期間での挙動を省略している。 FIG. 4 is an explanatory diagram showing a driving method in the first example of the D / A converter 10 according to the embodiment of the present invention. FIG. 5 is an explanatory diagram showing a driving method in the second embodiment. FIG. 6 is an explanatory diagram showing a driving method in a comparative example. 4 to 6, Din is a signal (1 or 0) for selecting the switched capacitor CU, SCL is a polarity sign (1 or 0), Vin is a charging voltage of the third capacitor C3, and the horizontal axis Is the time axis. For ease of explanation, only the state in which the clock φ1 is at a high level is schematically shown, and the behavior in the period in which the clock φ2 is at a high level is omitted.
　はじめに、比較例として、従来の駆動方法を説明する。図６に示すように、スイッチ付き容量ＣＵとして有効化され、第１の基準電圧Ｖｒ１が第７のスイッチＳＷ７に印加されたときには、第３の容量Ｃ３は第１の基準電圧Ｖｒ１に充電される。スイッチ付き容量ＣＵとして無効化されているときには、第７のスイッチＳＷ７を開放すると共に、第８のスイッチＳＷ８を閉じているので、第１の基準電圧Ｖｒ１が第７のスイッチＳＷ７に印加されたときには、第３の容量Ｃ３は電圧Ｖｏｆｆ１に充電される。一方、スイッチ付き容量ＣＵとして有効化され、第２の基準電圧Ｖｒ２が第７のスイッチＳＷ７に印加されたときには、第３の容量Ｃ３は第２の基準電圧Ｖｒ２に充電される。スイッチ付き容量ＣＵとして無効化され、第２の基準電圧Ｖｒ２が第７のスイッチＳＷ７に印加されたときには、第３の容量Ｃ３は電圧Ｖｏｆｆ２に充電される。図６に示すように、従来の駆動方法では、入力された極性付きデジタル信号がゼロのとき、第１のスイッチＳＷ１と第２のスイッチＳＷ２とが直前に選択された状態が継続する。このため、電圧Ｖｏｆｆ１の状態で蓄積された電荷が連続して転送され、又は電圧Ｖｏｆｆ２の状態で蓄積された電荷が連続して転送され、出力がされているので、大きな誤差を生じていた。 First, a conventional driving method will be described as a comparative example. As shown in FIG. 6, when the capacitor CU with a switch is enabled and the first reference voltage Vr1 is applied to the seventh switch SW7, the third capacitor C3 is charged to the first reference voltage Vr1. . When the switch-attached capacitor CU is invalidated, the seventh switch SW7 is opened and the eighth switch SW8 is closed. Therefore, when the first reference voltage Vr1 is applied to the seventh switch SW7. The third capacitor C3 is charged to the voltage Voff1. On the other hand, when the second reference voltage Vr2 is applied to the seventh switch SW7 when it is validated as the switched capacitor CU, the third capacitor C3 is charged to the second reference voltage Vr2. When the capacitor CU with a switch is invalidated and the second reference voltage Vr2 is applied to the seventh switch SW7, the third capacitor C3 is charged to the voltage Voff2. As shown in FIG. 6, in the conventional driving method, when the input digital signal with polarity is zero, the state in which the first switch SW1 and the second switch SW2 are selected immediately before is continued. For this reason, the charge accumulated in the state of the voltage Voff1 is continuously transferred, or the charge accumulated in the state of the voltage Voff2 is continuously transferred and output, so that a large error occurs.
　これに対し、本実施形態の第１実施例では、図４に示すように、入力データがゼロになった場合、その前にデータがゼロの状態の極性を記憶しておき、その反転の極性となるように第１のスイッチＳＷ１と第２のスイッチＳＷ２とを切り替える制御が行われる。すなわち、入力された極性付きデジタル信号がゼロのときに、第１のスイッチＳＷ１が閉じられる回数と、第２のスイッチＳＷ２が閉じられる回数と、の差が最小となるように、第１のスイッチＳＷ１と第２のスイッチＳＷ２とが交互に閉じられる。この構成によれば、デジタル信号がゼロのとき、第１の基準電圧Ｖｒ１によって電圧Ｖｏｆｆ１の状態で正の出力がされる場合と、第２の基準電圧Ｖｒ２によって電圧Ｖｏｆｆ２の状態で負の出力がされる場合とが交互に繰り返されるので、いずれか一方の状態で蓄積される誤差が相殺され、安定してゼロに近い出力となる。 On the other hand, in the first example of the present embodiment, as shown in FIG. 4, when the input data becomes zero, the polarity of the state in which the data is zero is stored before that, and the polarity of the inverted polarity Control to switch between the first switch SW1 and the second switch SW2 is performed so that That is, when the input digital signal with polarity is zero, the first switch so that the difference between the number of times the first switch SW1 is closed and the number of times the second switch SW2 is closed is minimized. SW1 and the second switch SW2 are alternately closed. According to this configuration, when the digital signal is zero, a positive output is generated in the state of the voltage Voff1 by the first reference voltage Vr1, and a negative output is generated in the state of the voltage Voff2 by the second reference voltage Vr2. Since this is repeated alternately, the error accumulated in one of the states is canceled out, and the output is stably close to zero.
　本実施形態の第１変形例である第２実施例では、図５に示すように、入力された極性付きデジタル信号がゼロのときに、第１のスイッチＳＷ１と第２のスイッチＳＷ２とがランダムとみなすことができる符号により開閉を制御される。この構成によれば、デジタル信号が０のとき、第１の基準電圧Ｖｒ１によって電圧Ｖｏｆｆ１の状態で正の出力がされる場合と、第２の基準電圧Ｖｒ２によって電圧Ｖｏｆｆ２の状態で負の出力がされる場合とがランダムに繰り返されるので、平均化され、ゼロに近い出力となる。 In the second example, which is a first modification of the present embodiment, as shown in FIG. 5, when the input digital signal with polarity is zero, the first switch SW1 and the second switch SW2 are random. Opening and closing is controlled by a sign that can be considered as According to this configuration, when the digital signal is 0, a positive output is generated in the state of the voltage Voff1 by the first reference voltage Vr1, and a negative output is generated in the state of the voltage Voff2 by the second reference voltage Vr2. Are repeated at random, and averaged to produce an output close to zero.
　以下、本実施形態としたことによる効果について説明する。 Hereinafter, the effects of the present embodiment will be described.
　本実施形態のＤ／Ａ変換器１０は、入力された極性付きデジタル信号がゼロのとき、第１のスイッチＳＷ１が閉じられ、第２のスイッチＳＷ２が開放される場合と、第１のスイッチＳＷ１が開放され、第２のスイッチＳＷ２が閉じられる場合と、を切り替える制御が行われる。この構成によれば、デジタル信号がゼロのとき、第１の基準電圧Ｖｒ１によって、正の出力がされる場合と、第２の基準電圧Ｖｒ２によって負の出力がされる場合と、を切り替えるので、いずれか一方の状態で蓄積される誤差が相殺され、ゼロに近い出力となる。 In the D / A converter 10 of the present embodiment, when the input digital signal with polarity is zero, the first switch SW1 is closed and the second switch SW2 is opened, and the first switch SW1. Is opened and the second switch SW2 is closed. According to this configuration, when the digital signal is zero, switching is performed between a case where a positive output is generated by the first reference voltage Vr1 and a case where a negative output is generated by the second reference voltage Vr2. The error accumulated in either state is canceled out, and the output is close to zero.
　また本実施形態のＤ／Ａ変換器１０において、入力された極性付きデジタル信号がゼロのときに、第１のスイッチＳＷ１が閉じられ、第２のスイッチＳＷ２が開放される回数と、第１のスイッチＳＷ１が開放され、第２のスイッチＳＷ２が閉じられる回数と、の差が最小となるように第１のスイッチＳＷ１と第２のスイッチＳＷ２とが制御されることが好ましい。この構成によれば、デジタル信号がゼロのとき、第１の基準電圧Ｖｒ１によって、正の出力がされる場合と、第２の基準電圧Ｖｒ２によって負の出力がされる場合との回数の差が小さくなるように制御されるので、更にゼロに近い出力となる。 In the D / A converter 10 of the present embodiment, when the input digital signal with polarity is zero, the number of times the first switch SW1 is closed and the second switch SW2 is opened, Preferably, the first switch SW1 and the second switch SW2 are controlled so that the difference between the number of times the switch SW1 is opened and the second switch SW2 is closed is minimized. According to this configuration, when the digital signal is zero, the difference in the number of times between the case where a positive output is produced by the first reference voltage Vr1 and the case where a negative output is produced by the second reference voltage Vr2. Since the output is controlled to be smaller, the output is further close to zero.
　本実施形態のＤ／Ａ変換器１０において、入力された極性付きデジタル信号がゼロのときに、第１のスイッチＳＷ１と第２のスイッチＳＷ２とが交互に閉じられることが好ましい。この構成によれば、デジタル信号がゼロのとき、第１の基準電圧Ｖｒ１によって、正の出力がされる場合と、第２の基準電圧Ｖｒ２によって負の出力がされる場合とが交互に繰り返されるので、安定してゼロに近い出力となる。 In the D / A converter 10 of this embodiment, it is preferable that the first switch SW1 and the second switch SW2 are alternately closed when the input digital signal with polarity is zero. According to this configuration, when the digital signal is zero, the case where a positive output is generated by the first reference voltage Vr1 and the case where a negative output is generated by the second reference voltage Vr2 are alternately repeated. Therefore, the output is stable and close to zero.
本実施形態のＤ／Ａ変換器１０において、入力された極性付きデジタル信号がゼロのときに、第１のスイッチＳＷ１と第２のスイッチＳＷ２とがランダムとみなすことができる符号により開閉を制御されるようにしてもよい。この構成によれば、デジタル信号がゼロのとき、第１の基準電圧Ｖｒ１によって、正の出力がされる場合と、第２の基準電圧Ｖｒ２によって負の出力がされる場合とがランダムに繰り返されるので、ゼロに近い出力となる。 In the D / A converter 10 of this embodiment, when the input digital signal with polarity is zero, the opening / closing is controlled by a code that allows the first switch SW1 and the second switch SW2 to be regarded as random. You may make it do. According to this configuration, when the digital signal is zero, a case where a positive output is generated by the first reference voltage Vr1 and a case where a negative output is generated by the second reference voltage Vr2 are randomly repeated. Therefore, the output is close to zero.
　本実施形態のＤ／Ａ変換器１０において、第６のスイッチＳＷ６を備え、第１のスイッチＳＷ１と第２のスイッチＳＷ２とは、一方が閉じ他方が開放されるように制御線ＳＣＬで制御される。この構成によれば、第６のスイッチＳＷ６が開いていれば、第１のスイッチＳＷ１及び第２のスイッチＳＷ２のいずれか一方が閉じていても開放されるので、制御線ＳＣＬが１つで済む。第６のスイッチＳＷ６で必要なときに電流を流すように制御できるので、低消費電力で、高精度にすることができる。 The D / A converter 10 of this embodiment includes a sixth switch SW6, and the first switch SW1 and the second switch SW2 are controlled by the control line SCL so that one is closed and the other is opened. The According to this configuration, if the sixth switch SW6 is open, it can be opened even if either the first switch SW1 or the second switch SW2 is closed, so only one control line SCL is required. . Since the sixth switch SW6 can control the current to flow when necessary, low power consumption and high accuracy can be achieved.
　本実施形態のＤ／Ａ変換器１０において、第１の容量Ｃ１は、第７のスイッチＳＷ７、第８のスイッチＳＷ８及び第３の容量Ｃ３を備えたスイッチ付き容量ＣＵが複数並列接続されてなる可変容量である。この構成によれば、第１のスイッチＳＷ１及び第２のスイッチＳＷ２を入力とする可変容量であるので、複雑な制御を必要とせず、低消費電力で、高精度にすることができる。 In the D / A converter 10 of the present embodiment, the first capacitor C1 is formed by connecting a plurality of switched capacitors CU including a seventh switch SW7, an eighth switch SW8, and a third capacitor C3 in parallel. Variable capacity. According to this configuration, since it is a variable capacitor having the first switch SW1 and the second switch SW2 as inputs, complicated control is not required, and low power consumption and high accuracy can be achieved.
　なお、より高分解能のＤ／Ａ変換器を上記の可変容量で構成する場合は、並列接続するスイッチ付き容量ＣＵの個数を増やせばよい。このとき、スイッチ付き容量ＣＵの製造上のばらつきによって第３の容量の容量値が個々にばらつくため、有効化されるスイッチ付き容量ＣＵとしてクロックφ１ごとに異なるものを選択すれば、積分されたアナログ電圧の出力誤差への影響を低減することができる。このように制御すれば、さらに高精度にすることができる。 When a higher-resolution D / A converter is configured with the above-described variable capacitor, the number of switch-attached capacitors CU connected in parallel may be increased. At this time, since the capacitance value of the third capacitor varies individually due to manufacturing variations of the switched capacitor CU, if a different switched capacitor CU is selected for each clock φ1, integrated analog The influence of the voltage on the output error can be reduced. By controlling in this way, higher accuracy can be achieved.
　以上のように、本発明の実施形態及び第１変形例のＤ／Ａ変換器１０の主要部を具体的に説明したが、本発明は上記の実施形態に限定されるものではなく、要旨を逸脱しない範囲で種々変更して実施することが可能である。例えば次のように変形して実施することができ、これらも本発明の技術的範囲に属する。 As mentioned above, although the principal part of embodiment of this invention and D / A converter 10 of the 1st modification was explained concretely, the present invention is not limited to the above-mentioned embodiment, and a summary is given. Various modifications can be made without departing from the scope. For example, the present invention can be modified as follows, and these also belong to the technical scope of the present invention.
　図７は、可変容量の具体的事例を含む第２変形例のＤ／Ａ変換器２０を示す主要部の回路図である。図７に示すように、第２変形例のＤ／Ａ変換器２０の主要部は、図２に示すような第６のスイッチＳＷ６は挿入されていない。上記以外の部分は図２に示す可変容量の具体的事例を含むＤ／Ａ変換器１０の主要部と同じである。Ｄ／Ａ変換器２０においても、制御回路によって、入力データの絶対値を求め、絶対値に比例した容量値となるようにスイッチ付き容量ＣＵの有効数が可変される。 FIG. 7 is a circuit diagram of a main part showing a D / A converter 20 of a second modification including a specific example of a variable capacitor. As shown in FIG. 7, the sixth switch SW6 as shown in FIG. 2 is not inserted in the main part of the D / A converter 20 of the second modified example. The other parts are the same as the main part of the D / A converter 10 including the specific example of the variable capacitor shown in FIG. In the D / A converter 20 as well, the control circuit obtains the absolute value of the input data, and the effective number of the switched capacitor CU is varied so that the capacitance value is proportional to the absolute value.
　第２変形例のＤ／Ａ変換器２０は、制御回路によって、入力データが正なのか負なのかを判断し、極性が正の符号１のときは、クロックφ１がハイレベルになるタイミングで、第１の基準電圧Ｖｒ１に接続する第１のスイッチＳＷ１を閉じる。極性が負の符号０のときは、クロックφ１がハイレベルになるタイミングで、第２の基準電圧Ｖｒ２に接続する第２のスイッチＳＷ２を閉じる。また、正の符号１のときは第２のスイッチＳＷ２を開き、負の符号０のときは第１のスイッチＳＷ１を開放する。このとき、第１のスイッチＳＷ１と第２のスイッチＳＷ２とは、いずれか一方のみが閉じる相補関係になっている。 The D / A converter 20 of the second modified example determines whether the input data is positive or negative by the control circuit, and when the polarity is positive sign 1, at the timing when the clock φ1 becomes high level, The first switch SW1 connected to the first reference voltage Vr1 is closed. When the polarity is a negative sign 0, the second switch SW2 connected to the second reference voltage Vr2 is closed at the timing when the clock φ1 becomes high level. When the positive sign is 1, the second switch SW2 is opened, and when the negative sign is 0, the first switch SW1 is opened. At this time, the first switch SW1 and the second switch SW2 are in a complementary relationship in which only one of them is closed.
　第２変形例のＤ／Ａ変換器２０の主要部は、クロックφ１がハイレベルになるタイミングで第１のスイッチＳＷ１又は第２のスイッチＳＷ２を閉じるように制御することと、第６のスイッチＳＷ６を挿入していないこと以外は、図２に示す可変容量の具体的事例を含むＤ／Ａ変換器１０の主要部と同じである。 The main part of the D / A converter 20 of the second modified example controls to close the first switch SW1 or the second switch SW2 at the timing when the clock φ1 becomes high level, and the sixth switch SW6. 2 is the same as the main part of the D / A converter 10 including the specific example of the variable capacitor shown in FIG.
　第２変形例のＤ／Ａ変換器２０は、入力された極性付きデジタル信号がゼロのときに、第１のスイッチＳＷ１が閉じられる回数と、第２のスイッチＳＷ２が閉じられる回数と、の差が最小となるように、クロックφ１がハイレベルになるタイミングで第１のスイッチＳＷ１と第２のスイッチＳＷ２とが制御される。 The D / A converter 20 according to the second modified example has a difference between the number of times the first switch SW1 is closed and the number of times the second switch SW2 is closed when the input digital signal with polarity is zero. The first switch SW1 and the second switch SW2 are controlled at the timing when the clock φ1 becomes high level.
　この構成によれば、第１の基準電圧Ｖｒ１によって、正の出力がされる場合と、第２の基準電圧Ｖｒ２によって負の出力がされる場合との回数の差が小さくなるように制御されるので、いずれか一方の状態で蓄積される誤差が相殺される。 According to this configuration, the first reference voltage Vr1 is controlled so as to reduce the difference in the number of times between the case where a positive output is made and the case where a negative output is made by the second reference voltage Vr2. Therefore, the error accumulated in one of the states is canceled out.
　図８は、本発明の実施形態の第３変形例のＤ／Ａ変換器３０を示す主要部の回路図である。図９は、可変容量の具体的事例を含む第３変形例のＤ／Ａ変換器３０を示す主要部の回路図である。 FIG. 8 is a circuit diagram of a main part showing a D / A converter 30 according to a third modification of the embodiment of the present invention. FIG. 9 is a circuit diagram of a main part showing a D / A converter 30 of a third modification including a specific example of a variable capacitor.
　図８及び図９に示すように、第３変形例のＤ／Ａ変換器３０の主要部は、第１の基準電圧Ｖｒ１に接続する第１のスイッチＳＷ１１を制御する第１の制御線ＳＬ１と、第２の基準電圧Ｖｒ２に接続する第２のスイッチＳＷ１２を制御する第２の制御線ＳＬ２と、を備えている。これらの第１の制御線ＳＬ１と第２の制御線ＳＬ２とが、いずれも開放されているか、いずれか一方が閉じるように制御されている。 As shown in FIGS. 8 and 9, the main part of the D / A converter 30 of the third modified example is the first control line SL1 for controlling the first switch SW11 connected to the first reference voltage Vr1. , And a second control line SL2 for controlling the second switch SW12 connected to the second reference voltage Vr2. The first control line SL1 and the second control line SL2 are controlled such that either one is opened or one is closed.
　具体的には、図示しない制御回路によって、第１の制御線ＳＬ１には、入力データが正のとき、クロックφ１がハイレベルである期間に第１のスイッチＳＷ１１を閉じる制御信号が伝達される。また、第２の制御線ＳＬ２には、入力データが負のとき、クロックφ１がハイレベルである期間に第２のスイッチＳＷ１２を閉じる制御信号が伝達される。それら以外の状態では、第１のスイッチＳＷ１１及び第２のスイッチＳＷ１２は開いているように制御される。第１のスイッチＳＷ１１及び第２のスイッチＳＷ１２と、第３のスイッチＳＷ３及び第１の容量Ｃ１と、は直接接続され、図１及び図２に示すような第６のスイッチＳＷ６は挿入されていない。 More specifically, when the input data is positive, a control signal for closing the first switch SW11 is transmitted to the first control line SL1 by a control circuit (not shown) when the input data is positive. Further, when the input data is negative, a control signal for closing the second switch SW12 is transmitted to the second control line SL2 while the clock φ1 is at a high level. In other states, the first switch SW11 and the second switch SW12 are controlled to be open. The first switch SW11 and the second switch SW12 are directly connected to the third switch SW3 and the first capacitor C1, and the sixth switch SW6 as shown in FIGS. 1 and 2 is not inserted. .
　図９は、上記以外の部分は図２に示す可変容量の具体的事例を含むＤ／Ａ変換器１０の主要部と同じである。Ｄ／Ａ変換器３０においても、制御回路によって、入力データの絶対値を求め、絶対値に比例した容量値となるようにスイッチ付き容量ＣＵの有効数が可変される。 9 is the same as the main part of the D / A converter 10 including the specific example of the variable capacitor shown in FIG. Also in the D / A converter 30, the absolute value of the input data is obtained by the control circuit, and the effective number of the capacitance CU with the switch is varied so that the capacitance value is proportional to the absolute value.
　入力された極性付きデジタル信号がゼロのとき、第１の制御線ＳＬ１と第２の制御線ＳＬ２とのいずれか一方には、クロックφ１がハイレベルの期間にスイッチを閉じる制御信号が伝達されている。これにより、無効化されているスイッチ付き容量ＣＵのＳＷ７を介した充電電圧Ｖｉｎによる電荷が第３の容量Ｃ３に蓄積されてしまうので、アナログ電圧を出力するときの誤差になる。本発明の実施形態の第３変形例では、入力された極性付きデジタル信号がゼロのときに、適宜、第１の制御線ＳＬ１と第２の制御線ＳＬ２との制御信号を切り替えるように制御される。そして、入力された極性付きデジタル信号がゼロのときに、第１のスイッチＳＷ１１が閉じられる回数と、第２のスイッチＳＷ２が閉じられる回数と、の差が最小となるように、第１のスイッチＳＷ１１と第２のスイッチＳＷ１２とが制御される。この構成によれば、ゼロを出力する誤差が相殺されると共に、第１のスイッチＳＷ１１及び第２のスイッチＳＷ１２を必要なときに電流を流すように制御できるので、低消費電力で、高精度にすることができる。 When the input digital signal with polarity is zero, either the first control line SL1 or the second control line SL2 is transmitted with a control signal for closing the switch while the clock φ1 is at a high level. Yes. As a result, the charge due to the charging voltage Vin via the SW7 of the switched-capacitance capacitor CU that has been invalidated is accumulated in the third capacitor C3, resulting in an error when outputting an analog voltage. In the third modification of the embodiment of the present invention, when the input digital signal with polarity is zero, the control signal is appropriately switched between the first control line SL1 and the second control line SL2. The Then, when the input digital signal with polarity is zero, the first switch is set so that the difference between the number of times the first switch SW11 is closed and the number of times the second switch SW2 is closed is minimized. SW11 and the second switch SW12 are controlled. According to this configuration, the error of outputting zero is canceled out, and the first switch SW11 and the second switch SW12 can be controlled to flow current when necessary, so that low power consumption and high accuracy can be achieved. can do.
　１０、２０、３０　Ｄ／Ａ変換器
　Ｃ１　　第１の容量
　Ｃ２　　第２の容量
　Ｃ３　　第３の容量
　ＣＵ　　スイッチ付き容量
　ＳＣＬ　制御線
　ＳＬ１　第１の制御線
　ＳＬ２　第２の制御線
　ＯＰ１　オペアンプ
　Ｒｏｆｆ　オフ抵抗
　Ｒｏｎ　オン抵抗
　ＳＷ１、ＳＷ１１　第１のスイッチ
　ＳＷ２、ＳＷ１２　第２のスイッチ
　ＳＷ３　第３のスイッチ
　ＳＷ４　第４のスイッチ
　ＳＷ５　第５のスイッチ
　ＳＷ６　第６のスイッチ
　ＳＷ７　第７のスイッチ
　ＳＷ８　第８のスイッチ
　Ｖｒ１　第１の基準電圧
　Ｖｒ２　第２の基準電圧
　Ｖｒ３　第３の基準電圧 10, 20, 30 D / A converter C1 first capacitor C2 second capacitor C3 third capacitor CU switched capacitor SCL control line SL1 first control line SL2 second control line OP1 operational amplifier Roff OFF resistance Ron On-resistance SW1, SW11 First switch SW2, SW12 Second switch SW3 Third switch SW4 Fourth switch SW5 Fifth switch SW6 Sixth switch SW7 Seventh switch SW8 Eighth switch Vr1 First switch Reference voltage Vr2 Second reference voltage Vr3 Third reference voltage

Claims (7)

  1. 　第１の基準電圧に接続する第１のスイッチと、第２の基準電圧に接続する第２のスイッチと、前記第１のスイッチ及び前記第２のスイッチに接続され第３の基準電圧に接続する第３のスイッチと、前記第１のスイッチ、前記第２のスイッチ及び前記第３のスイッチに接続された第１の容量と、前記第１の容量に接続され第３の基準電圧に接続された第４のスイッチと、前記第１の容量及び前記第４のスイッチに接続された第５のスイッチと、前記第５のスイッチに接続されたオペアンプと、前記第５のスイッチと前記オペアンプに接続された第２の容量とを備え、
    　入力された極性付きデジタル信号がゼロのとき、前記第１のスイッチが閉じられ、前記第２のスイッチが開放される場合と、前記第１のスイッチが開放され、前記第２のスイッチが閉じられる場合と、を切り替える制御が行われることを特徴とするＤ／Ａ変換器。     A first switch connected to the first reference voltage; a second switch connected to the second reference voltage; and a third reference voltage connected to the first switch and the second switch. A third switch, a first capacitor connected to the first switch, the second switch, and the third switch; and a third reference voltage connected to the first capacitor. A fourth switch, a fifth switch connected to the first capacitor and the fourth switch, an operational amplifier connected to the fifth switch, and connected to the fifth switch and the operational amplifier. With a second capacity,
    When the input digital signal with polarity is zero, the first switch is closed and the second switch is opened, and the first switch is opened and the second switch is closed. A D / A converter characterized in that control for switching between cases is performed.
  2. 　入力された極性付きデジタル信号がゼロのときに、前記第１のスイッチが閉じられ、前記第２のスイッチが開放される回数と、前記第１のスイッチが開放され、前記第２のスイッチが閉じられる回数と、の差が最小となるように前記第１のスイッチと前記第２のスイッチとが制御されることを特徴とする請求項１に記載のＤ／Ａ変換器。 When the input digital signal with polarity is zero, the number of times that the first switch is closed and the second switch is opened, and the first switch is opened and the second switch is closed. 2. The D / A converter according to claim 1, wherein the first switch and the second switch are controlled so that a difference between the first switch and the second switch is minimized.
  3. 　入力された極性付きデジタル信号がゼロのときに、前記第１のスイッチと前記第２のスイッチとが交互に閉じられることを特徴とする請求項２に記載のＤ／Ａ変換器。 The D / A converter according to claim 2, wherein when the input digital signal with polarity is zero, the first switch and the second switch are alternately closed.
  4. 　入力された極性付きデジタル信号がゼロのときに、前記第１のスイッチと前記第２のスイッチとがランダムとみなすことができる符号により開閉を制御されることを特徴とする請求項１又は請求項２に記載のＤ／Ａ変換器。 2. The opening and closing of the first switch and the second switch are controlled by a code that can be regarded as random when the input digital signal with polarity is zero. 2. A D / A converter according to 2.
  5. 　前記第１のスイッチ及び前記第２のスイッチと、前記第３のスイッチ及び前記第１の容量と、を接続するように挿入された第６のスイッチを備え、
    　前記第１のスイッチと前記第２のスイッチとは、一方が閉じ他方が開放されるように制御線で制御されることを特徴とする請求項１乃至請求項４のいずれかに記載のＤ／Ａ変換器。     A sixth switch inserted to connect the first switch and the second switch, the third switch and the first capacitor;
    5. The D / C according to claim 1, wherein the first switch and the second switch are controlled by a control line so that one of them is closed and the other is opened. A converter.
  6. 　前記第１のスイッチを制御する第１の制御線と、前記第２のスイッチを制御する第２の制御線と、を備え、前記第１の制御線と前記第２の制御線とがいずれも開放されているか、いずれか一方が閉じるように制御されていることを特徴とする請求項１乃至請求項４のいずれかに記載のＤ／Ａ変換器。 A first control line for controlling the first switch; and a second control line for controlling the second switch, wherein both the first control line and the second control line are provided. The D / A converter according to any one of claims 1 to 4, wherein the D / A converter is controlled to be open or to be closed.
  7. 　前記第１の容量は、第７のスイッチ、第８のスイッチ及び第３の容量を備えたスイッチ付き容量が複数並列接続されてなる可変容量であることを特徴とする請求項１乃至請求項６のいずれかに記載のＤ／Ａ変換器。 7. The first capacitor according to claim 1, wherein the first capacitor is a variable capacitor formed by connecting a plurality of capacitors with a switch including a seventh switch, an eighth switch, and a third capacitor in parallel. The D / A converter in any one of.
PCT/JP2014/068812 2013-07-25 2014-07-15 D/a converter WO2015012159A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2013-154491 2013-07-25
JP2013154491A JP2016171357A (en) 2013-07-25 2013-07-25 D/a converter

Publications (1)

Publication Number Publication Date
WO2015012159A1 true WO2015012159A1 (en) 2015-01-29

Family

ID=52393203

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2014/068812 WO2015012159A1 (en) 2013-07-25 2014-07-15 D/a converter

Country Status (2)

Country Link
JP (1) JP2016171357A (en)
WO (1) WO2015012159A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021209829A1 (en) * 2020-04-13 2021-10-21 International Business Machines Corporation Differential mixed signal multiplier with three capacitors

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06303143A (en) * 1993-04-15 1994-10-28 Matsushita Electric Ind Co Ltd Integration type d/a converter
JP2000286708A (en) * 1999-03-31 2000-10-13 Nec Corp Noise reduction device in muting state
JP2002064384A (en) * 2000-08-22 2002-02-28 Sony Corp Δς modulator, digital signal processor and method for processing digital signal
JP2006092483A (en) * 2004-09-27 2006-04-06 Asahi Kasei Microsystems Kk Switched capacitor circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06303143A (en) * 1993-04-15 1994-10-28 Matsushita Electric Ind Co Ltd Integration type d/a converter
JP2000286708A (en) * 1999-03-31 2000-10-13 Nec Corp Noise reduction device in muting state
JP2002064384A (en) * 2000-08-22 2002-02-28 Sony Corp Δς modulator, digital signal processor and method for processing digital signal
JP2006092483A (en) * 2004-09-27 2006-04-06 Asahi Kasei Microsystems Kk Switched capacitor circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021209829A1 (en) * 2020-04-13 2021-10-21 International Business Machines Corporation Differential mixed signal multiplier with three capacitors
GB2610332A (en) * 2020-04-13 2023-03-01 Ibm Differential mixed signal multiplier with three capacitors

Also Published As

Publication number Publication date
JP2016171357A (en) 2016-09-23

Similar Documents

Publication Publication Date Title
CN1322062B (en) Sigma delta type analog-to-digital converter
CN110663187B (en) Analog-to-digital converter, measuring device and analog-to-digital conversion method
CN102843137B (en) Single-ended and difference two input analog-to-digital converter simultaneously sampled
JP5836020B2 (en) A / D converter
US9671253B2 (en) Electronic measurement circuit
CN108964664B (en) Self-oscillating multi-slope converter and method for converting capacitance into digital signal
US10735016B2 (en) D/A conversion circuit, quantization circuit, and A/D conversion circuit
US9759581B2 (en) Electronic measurement circuit
JP4428349B2 (en) Digital / analog conversion circuit
CN103023499B (en) Analog to digital converter and method of work thereof
JP5198427B2 (en) Sigma delta modulator
TWI536745B (en) Converter with an additional dc offset and method thereof
WO2015012159A1 (en) D/a converter
JP5695629B2 (en) Successive comparison type A / D converter and multi-bit delta-sigma modulator using the same
US10461765B2 (en) Successive approximation type AD converter and sensor device
JP4104835B2 (en) D / A converter circuit
CN109802680B (en) Capacitor array and analog-to-digital converter based on fractional reference
US20200153446A1 (en) Delta-sigma modulator, delta-sigma modulation type a/d converter and incremental delta-sigma modulation type a/d converter
JP2004194201A (en) Integrated circuit and a/d conversion circuit
CN105703775B (en) A kind of conversion method of integrating analog to digital converter and integral modulus
JP2020020769A (en) Capacitance detection circuit
JP5826153B2 (en) Semiconductor device
WO2021205962A1 (en) Integrated circuit
EP4135193A1 (en) Signal processing circuit
JP2010081221A (en) A-d converter

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14829490

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 14829490

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP