WO2015009249A1

WO2015009249A1 - Enhancement-mode iii-n transistor with n-polarity and method of fabricating the same

Info

Publication number: WO2015009249A1
Application number: PCT/SK2014/000011
Authority: WO
Inventors: Ján KUZMIK
Original assignee: Elektrotechnicky Ustav Sav; Centrum Vedecko-Technickych Informacii Sr (Cvti Sr)
Priority date: 2013-07-17
Filing date: 2014-04-30
Publication date: 2015-01-22
Also published as: WO2015009249A9

Abstract

Enhancement -mode III-N transistor with N-polarity consisting of the following layers, from the bottom: a bottom barrier layer ( 1 ); a channel layer ( 2 ); an upper barrier layer ( 3 ), the chemical composition of which is different from the composition of the bottom barrier layer; and a dielectric insulating layer ( 4 ), while the upper barrier layer/channel layer interface exhibits a negative polarization charge with an absolute value larger than the positive polarization charge at the channel layer/bottom barrier layer interface, and the transistor threshold voltage is freely adjustable.

Description

Enhancement-Mode III-N Transistor with N-polarity and Method of Fabricating the Same Field of the invention

Technical solution relates to electronics, particularly to the field of fabricating high electron mobility transistors (HEMTs).

Description of the Related Art

Present technological challenges of semiconductor industry relate mostly to a continuous trend of transistor miniaturization in order to increase switching speed and level of device integration. However, shrinking of a gate length of a Si-based transistor already faces its own physical limits and consequently it is necessary to look for alternative solutions. InN is a semiconductor material where the drift electron velocity is about 4 times higher than the electron velocity in Si.

III-N semiconductors are materials showing high level of spontaneous polarization P_D. Apart from that, considering that crystallographic structure of Ill-Nitrides lacks inversion symmetry, for a strained epitaxial layer along c axis a piezoelectric polarization P_piao is generated. The value of a piezoelectric field can be calculated as P_piao - (e₃i -

sj, where en, ¾ are piezoelectric constants, Cn, C33 are elastic constants, and ε; = ε_∞ + ε„, is an in-plane strain. If α» is a lattice constant of a relaxed epitaxial layer (i.e. of a layer without strain) and a is the lattice constant by applying the strain (i.e. lattice constant of the layer on which the strained layer is grown), then strain ει can be calculated as ει=2{α - a₀)lao. Total polarization defines a polarization-induced charge density p,_olai according to equation -ρ,_0Ιαι - ^' (Ppiezo + Po)- In other words, a hetero-junction of two materials exhibits the charge density of the polarization-induced charge as a consequence of difference in spontaneous polarizations APo of materials and in a case of strained materials with different lattice constants, also as a consequence of a gradient of the piezoelectric polarization APpiezo- A change in the polarization therefore generates the charge density which can act as donors or as acceptors. If at the given junction / is positive, then free electrons with a density n,_olai - PtoiJq, where q is the electron charge, are accumulated at the interface and compensate the polarization charge. Analogously, negative p,₀,_ai can cause accumulation of holes, providing an edge of a valence level crosses a Fermi level.

Table 1 shows values of polarizations and of some other physical parameters for A1N, GaN and InN, respectively, and also of some dielectric materials which are used for the transistor gate insulation (see J. Appl. Phys. 85, p.7727, 1999, J. Appl. Phys. 87, p.334, 2000, Semicond. Sci. Technol. 17, p. 540, 2002, J. Appl. Phys. 100, p. 01411 1, 2006, Appl. Phys. Express 5, p.015502, 2002). ε,. is a dielectric constant, AE_G is a width of an energetic gap, Φ_ΒΟΧ is a barrier height on a contact metal/dielectric, E_C is discontinuity of a conduction band, μ is the electron mobility in a low electric field, v, is an effective electron saturation velocity. Orientation of the polarization depends on a crystal polarity, e.g. if the crystal surface is terminated by bonds from a cation (Ga, Al, In) or from an anion (N). Negative value of all polarization parameters in Table 1 corresponds to the cation polarity (growth along (0001)), positive value corresponds to the anion polarity (growth along (000-1)).

Spontaneous polarization P₀of ternary compounds is calculated by using Vegard's law:

Po(A_XB,._XC) = Po(BC) + X(PQ(AQ- PO(BQ).

Ve ard's equation may be analogously used for any other parameter of Table 1.

Table 1

Polarization of III-N semiconductors is applied in the channel of high electron mobility transistors (HEMTs) without using dopants. Conductance of the channel is provided by a 2- dimensional electron gas in a quantum well at the junction of two semiconductors having different polarization or with a different value of AE_G. If layers show cation (Ga, Al, In) polarity, then creation of the 2-dimensional electron gas of transistors requires placing of the channel layer, having typically smaller AE_G (e.g. GaN), below the material of the barrier layer, having typically larger AE_G (e.g. AlGaN). For a case of the anion (N) polarity of the HEMT, sequence of layers is mirror-like, i.e. initially the barrier layer with the larger AE_G is grown and then a channel layer with smaller AE_G is grown. Free electrons are accumulated at the hetero-j unction of the created quantum well because of the positive polarization charge at the junction. From the review of Table 1 it is obvious that by creating InN-channel based transistors, extremely high switching speed can be expected as a consequence of high v_sal.

Threshold voltage (V_T) of transistors is a value of the voltage bias applied on the gate when the conductance of the channel is flipped (opened/closed channel) as a consequence of an electrostatic effect of the gate. If Vr> 0 V, than we deal with an enhancement-mode transistor, which is closed without applying the gate bias. In the opposite case we deal with a depletion-mode transistor. Construction and integration of both types of transistors is important for e.g. preparation of logic circuits. It is desirable that the enhancement-mode transistor VT value is sufficiently high in order to prevent undesired switching of the transistor.

From all known solutions, in US7,948,011 (B2) it is described that by applying a top barrier layer AlGaN in a system such as (from a top) AlGaN/GaN/AlGaN/GaN where GaN is the channel layer, AlGaN is a bottom barrier layer and GaN is a buffer layer on a substrate, see Fig. A, it is possible to construct an enhancement-mode transistor having N-polarity. Such a transistor was described with the gate based on the Schottky contact, or with using dielectrics to insulate the gate (concept of a metal- insulator-semiconductor). For a case of the Schottky contact, in order to enhance the Schottky barrier and to suppress leakage currents it is possible to replace the top AlGaN barrier layer with a semiconductor having larger AE_A or with a different chemical composition, such as A1N. Next it was described that adjustment of VT of depletion-mode transistors based on III-N semiconductors with N-polarity and thus integration of transistors with various VT is technologically possible by using AlGaN stop layer for deep etching of the GaN cap layer, while the stop layer is grown on the channel layer in different positions. As it follows in the document, VT of the enhancement-mode transistor can be changed with the thickness of the top AlGaN layer.

Figure A

Structure of the AlGaN/GaN enhancement-mode transistor with N-polarity is described in

US7,948,011.

From the abstract of WO2011008531 (A2) follows a method of fabricating enhancement- mode HEMT having the particular AIN/GaN configuration. According to the invention the enhancement-mode HEMT can be fabricated by using oxygen plasma. By using a masking layer to protect an area of the depletion-mode HEMT, both transistors can be fabricated on the same chip.

From the abstract of EP2385544 (A2) follows an invention incorporating the fabrication of enhancement-mode HEMT based on GaN, AlGaN and InAlN. Self-aligned gates with a p-type semiconductor, a selective epitaxial growth (SEG) as well as an epitaxial layer overgrowth (ELO) technique, respectively are used by the HEMT fabrication.

Document Kuzmik, J., Applied Physics Express 5 (2012) 044101 describes a proposal of the depletion-mode InN/GaN/InAIN transistor having N-polarity with a high concentration of electrons in the channel layer. Without mentioning a layer grown on the substrate, InAlN constitutes here simultaneously a role of the buffer layer as well as a role of the bottom barrier layer. Content of In in InAlN was chosen between 0.7 and 0.9 so that after relaxing the layer, following growth of the strained InN would be possible. In order to enhance the mobility of electrons in the channel layer, study describes a possibility of using extremely thin spacer layer (0.3 to 1 nm thick) between InN channel layer and InAlN layer.

Document Material and device issues of InAlN/GaN heterostructures, Author(s): Kuzmik, J., Inst, of Electr. Eng., Bratislava, Slovakia, Ninth International Conference on Advanced Semiconductor Devices & Microsystems (ASDAM), 2012, describes the state of the art in InAlN/GaN HEMTs and a novel concept of InN/InAIN HEMTs.

Document Author(s): Singisetti, U., et al, IEEE Electron Dev. Lett. 32 (2011) 137, describes a proposal of the enhancement-mode transistor having N-polarity with an insulated gate and with a self-aligned approach.

Contemporary solutions show following deficiencies and limitations:

As described in US7,948,011 (B2), various locations of the stop layer require additional complex processing steps, such as mastering SEG. Similarly, changing the thickness of the top AlGaN layer is difficult and may require SEG or a need for an exact control of the etching process in AlGaN, which practically excludes the possibility of a reproducible fabrication of the integrated circuit with a high homogeneity of parameters across the wafer. Described fabrication process also does not facilitate adjustment of V_rto an arbitrary value.

In the document WO2011008531 (A2), the described method does not facilitate fabrication of the enhancement-mode transistor without decreasing the maximal current, which is seemingly a consequence of the semiconductor surface plasma damage. In the same way, a maximal V_r value is only about 1 V, which is not sufficient. Also, an enhancement-mode transistor having N-polarity is not described in the document.

Disadvantages of the method described in EP2385544 (A2) is its complex approach, such as using SEG, the necessity of doping by acceptors and the impossibility to control V_T in the broad voltage scale. A limiting factor is also the saturated electron velocity in the GaN channel. Also, an enhancement-mode transistor with N-polarity is not described in the document.

Disadvantages of the method described in Applied Physics Express 5 (2012) 044101 is the tra sistor negative VT value and missing descriptions of the enhancement-mode transistor and a method of its integration.

Disadvantages of the method described in Author(s): Kuzmik, J., Inst, of Electr. Eng., Bratislava, Slovakia, Ninth International Conference on Advanced Semiconductor Devices & Microsystems (ASDAM), 2012, is the impossibility of V_T adjustment to an arbitrary value during the transistor fabrication, value of V_T only about 1 V, and the low saturation velocity of electrons in GaN. Enhancement-mode transistor with N-polarity is not described in the document.

Disadvantages of the method described in Author(s): Singisetti, U., et al, IEEE Electron Dev. Lett. 32 (2011) 137, is the impossibility of free control of V_T during the transistor fabrication, physical restriction of the maximal value of V_T as well as the low saturation velocity of electrons in the GaN channel layer. The process of integration of enhancement- and depletion-mode transistors is not described in the document.

Summary of the Invention

Disadvantages of contemporary solutions are removed by the invention of enhancement- mode metal-insulator-III-N semiconductor transistor with N-polarity and with a free adjustment of the threshold voltage without the necessity to manipulate the semiconductor structure during the fabrication process.

Enhancement-mode III-N transistor with N polarity contains from the bottom following layers: the bottom barrier layer, the channel layer, the upper barrier layer having chemical composition different from the composition of the bottom barrier layer, and the dielectric insulator of the gate while the upper barrier layer/channel layer interface shows a negative polarization charge with an absolute value greater than the positive polarization charge at the channel layer/bottom barrier layer interface. Described transistor contains the channel layer based on InN which enhances the speed performance.

Concept of the different chemical compositions of the bottom and of the upper barriers in the III-N enhancement-mode transistor with the insulated gate and N-polarity does not lead to the enhancement of the Schottky barrier in the gate electrode. Therefore this concept is seemingly useless, technologically counterproductive, and it was not described until now. Despite that (as will be explained below) this new concept under defined conditions brings new positive aspects, in particular the possibility of a simple and free adjustment of V_T, and in conjunction with the channel layer based on InN the possibility of integration with the depletion-mode transistor with high homogeneity and reproducibility of V_T of both types of transistors. Moreover, integration of transistors is possible with identical starting locations of all semiconductor layers while the channel layer itself is used by fabricating the depletion-mode transistor as the stop layer for plasma etching.

Brief description of the drawings

Fig. 1 Structure of the novel enhancement-mode metal-insulator-III-N semiconductor transistor with N-polarity and having a free adjustment of V_T.

Fig. 2 Simulated output characteristics of the novel enhancement-mode metal-insulator-III-N semiconductor transistor with N-polarity and 5 nm thick Hf0₂ dielectric insulating layer.

Fig. 3 Simulated dependences of V_T on the thickness of the Hf0₂ dielectric gate insulator of the novel enhancement-mode metal-insulator-III-N semiconductor transistor with N-polarity and of the depletion-mode transistor prepared on the same substrate.

Figs. 4-11 Technological sequence of fabricating transistors and integrated circuits.

Fig. 12 Simulated transfer characteristics of the novel enhancement-mode metal-insulator-III-N semiconductor transistor with N-polarity and of the depletion-mode transistor prepared on the same substrate.

Detailed Description of the Invention

Fig. 1 shows the enhancement-mode III-N transistor with N-polarity which from the bottom contains the bottom relaxed InAlN barrier layer 1, strained InN channel layer 2, the upper GaN barrier layer 3 and the Hf0₂-based dielectric gate insulator 4.

The following description is based on the analytical model of the HEMT transistor described in the IEEE Transactions on Electron Devices, vol. ED-30, pp. 207-212, 1983, which is here modified for a calculation of V_R of the transistor with anion (N) polarity, with the dielectric insulation of the gate and with the upper barrier layer grown on the channel layer. Polarization-induced charge is incorporated in the VT calculation:

VT = ΒΟΧ -∑ E - d_EoTox ij£cH- (dwrox+dwrr) τcn /S H- (dEoiOX+d_EOTT+dcn) PCWB/ECH (1) where S_CHI ^'S permittivity of the channel layer, άκοτοχ, d_EOn are equivalent thicknesses of the dielectric insulating layer and of the barrier layer in relation to S_CJH, d_CH is the thickness of the channel layer, the charge at the insulator/semiconductor interface which can be eliminated by annealing (see Applied Phys. Lett. 102, 072105, 2013), p_TCH and p_CH,_B are total polarization charges at the upper barrier layer/channel layer interface and at the channel layer/bottom layer interface, and layers are undoped. Simultaneously it is valid that

where p_R/B is the total polarization charge which would be created on a hypothetical interface upper barrier layer/bottom barrier layer. Consequently:

VT = ΒΟΧ -∑AEc - d_EomxN_ne ec - {ά_Εοτοχ⁺ά_Εοττ) pm / CH - dctipcHi scH (3)

In order to increase the electron mobility in the channel layer, it is possible to use the GaN interlayer between the bottom barrier layer and the channel layer. The thickness of this layer is chosen to be less than 1 nm in order to prevent relaxation of its lattice. Polarization dipole of such a thin interlayer can be neglected by calculating V_T, if the interlayer is used.

Saturation current I_sa, between the source and the drain is given as:

Im = (fiVf (1+2 R_SV'_G + V'G / V_s ² - (1 + β^Υ'ο)) /(1-β ² V_S ²) (4) where R_s is a parasitic source resistance and

β= εμΨ/dL (7)

Fig. 2 shows a simulation of output characteristics of the enhancement-mode transistor, schematic structure of which is shown in Fig. I . Calculation assumes relaxed Ino.9Alo_.1N bottom barrier layer, 5 nm thick strained InN channel layer, 1 nm thick GaN upper barrier layer, 5 nm thick HfC>2 dielectric insulator and 100 nm long gate which is located between the source and the drain having 1 μπι pitch. Contact resistance of the source and of the drain is assumed to be 0.1 Ωηιιη, the upper barrier layer in access regions of the transistor is removed in order to minimalize source-gate and gate- drain parasitic resistances. At the interface of the dielectric gate insulator with the semiconductor it is assumed that N_m, = 1 x 10¹³ cm^"2 is the maximal value corresponding to the non-optimized interface (see Applied Phys. Lett. 102, 072105, 2013). As it is shown, the transistor channel is opened only for gate bias larger than 3.1 V, which facilitates sufficient protection against the undesired switching. Maximal currents are above 4 A/mm. Next, Fig. 3 shows a simulation of the V_T dependence of the described enhancement-mode transistor on the thickness of the dielectric insulation layer. This graph demonstrates high variability of V_T adjustment of the proposed enhancement-mode transistor depending on the thickness of the dielectric insulator of the gate, with the possibility of adjusting V_R ~ 6 V already for 10 nm thick dielectric insulation of the gate without any manipulation of the semiconductor structure. However in the general case, as equations (1) and (3) show, described behavior can be obtained only if p < 0, i.e. if the absolute value of the negative polarization charge at the upper barrier layer/channel layer interface is larger than the positive polarization charge at the channel layer/ bottom barrier layer interface. This is a limiting condition for choosing chemical composition and/or for molar fractions of elements in both of barriers. In one example, by using GaN as the upper barrier layer and In_xAli_-xN as the bottom barrier layer, to meet mentioned specific inequality of polarization charges it is necessary to fulfill x > 0.4. By applying the equation for a calculation of the polarization charge it can be shown that VT adjustment of the described GaN InN/InAIN enhancement-mode transistor with insulated gate is possible to obtain also for a partially relaxed lattice of the upper GaN barrier layer. In this case however, the bottom limit for x will be larger than 0.4. Value of x of the relaxed bottom barrier layer is limited also by a need to secure growth of the strained channel layer, which in the case of InN is fulfilled for x ~ 0.7 ÷ 0.9. Arbitral combination of InGaN is also possible to use in the place of the channel layer while in this case x in the bottom barrier layer can be decreased closer to 0.4. As the bottom barrier layer it is also possible to use an arbitral combination of InAlGaN providing p_m < 0. As the dielectric insulating layer it is also possible to use other alternative materials and its combinations, such as A1₂0₃, Zr0₂, Ti0₂ or similar providing the gate leakage current is eliminated. Polarity of the grown layers may be set by the polarity of the substrate or by the growth of the bottom barrier layer on the N-polar GaN buffer layer.

The advantage of the described concept of the enhancement-mode metal-insulator-III-N semiconductor transistor with N-polarity is also given by a particular chemical composition of the upper barrier layer and of the channel layer. Used composition facilitates a selective plasma etching of the upper barrier layer over InN-containing channel layer. This provides a reproducible and homogeneous fabrication of the depletion-mode transistor together with the enhancement-mode transistor across the wafer while the enhancement-mode transistor is covered with a mask, such as with a photoresist, during the etching. Removal of the upper barrier layer is possible to be performed by using a fluoride-containing plasma which will form InF-based etch-stop layer on the surface of the channel layer. Value of V_T of the fabricated depletion-mode transistor is unambiguously given in this way and can be calculated by using equation (1) while after removal of the upper barrier layer it follows that ά_Εοπ = 0 nm and pr/cu = 0 Cm^'2 regardless of the former d_Eon value. Fig. 3 shows variability of V_T of the depletion-mode InN/InAIN transistor which is fabricated by removing the GaN upper barrier layer and by subsequent formation of the Hf0₂ dielectric insulating layer of variable thickness, while the channel layer thickness remains constant for both types of transistors. Moreover, before fabricating the gate metallization systems of both of transistors, it is additionally possible to deposit a second dielectric layer. In this way, in a sense of equations (1) and (3), a free and independent V_T adjustment of both of transistors is possible. In order to decrease parasitic resistances, selective etching of the upper barrier layer over the channel layer can be used also in the source-to-gate and gate-to-drain access regions as it was already mentioned by describing transistor simulations. Transistor contacts themselves can be used as the mask for etching.

An example of fabricating the enhancement-mode metal-insulator-III-N semiconductor transistor with N-polarity and free adjustment of the threshold voltage in the integration with the depletion-mode transistor on the identical wafer is as follows:

Epitaxial growth of III-N layers is done by using techniques like molecular-beam epitaxy (MBE) or by a metal-oxide chemical vapor deposition (MOCVD), or by a technique of sputtering on a properly chosen substrate. As a substrate 11, see Fig. 4, it can be used e.g. bulk GaN, SiC, Si, sapphire, diamond, or any other material which provides epitaxial growth of the GaN buffer layer 12 or InAlN layer 1 with the anion orientation. Anion (N) orientation of layers can be provided by e.g. growth on SiC with C orientation of the surface, on GaN with N orientation, by growth on an off-axis sapphire or by a proper preparation of the substrate surface. In the case of MBE the growth of GaN is N plasma assisted. In the case of MOCVD it is necessary to provide intensive nitridation of the substrate surface. Trimethylindium, trimethylaluminium, trimethylgalium and ammonia are used as precursors. Growth of about 100 nm to 3 μπι thick GaN buffer layer 12 is followed by the growth of the In_xAli_-xN bottom barrier layer 1. Alternatively it is also possible to grow In_xAl_1-xN layer 1 directly on the substrate H, omitting the GaN buffer layer 12. In this case the InAIN layer 1 fulfills simultaneously the role of the buffer layer as well as of the bottom barrier layer. Thickness of the In_xAli_-xN layer 1 is chosen between 100 nm to 3μηι so that when the growth is finished the layer is relaxed. The growth is performed with fixed x ~ 0.7 ÷ 0.9 or with a graded x. Content of In is chosen in a way to provide the growth of the strained InN-based channel layer 2 and of the upper GaN barrier layer 3_ in later steps. Residual donors in the bottom barrier layer 1 are compensated by e.g. Mg or Fe doping, or by an increased content of C in the layer. After growing the bottom barrier layer 1 follows the growth of about 5 nm thick InN channel layer 2 and finally the growth of about 1 nm thick GaN upper barrier layer 3. In the place of the bottom InAIN barrier layer 1 it is also possible to use InAlGaN, as the channel layer 2 it is also possible to use InGaN. Isolation of transistors on the future integrated circuit is done by either proton implantation, or by definition of mesa areas using plasma etching in reactive ions, see Fig. 4. Masking of areas can be done by using the resist mask 13 prepared by photolithography.

In the following step the area of transistors working in the depletion-mode is defined by e.g. photolithography and the upper GaN barrier layer 3 is selectively etched away, see Fig. 5. Selectivity of etching can be provided by plasma etching in fluoride-containing gasses, e.g. in the mixture of SiCl₄/SF₆ or in CCI₂F₂. The upper barrier layer 3 does not contain elements like In or Al and can be easily etched away. On the other hand on the surface of the channel layer 2 which contain In, the InF-based etch stop is created and etching will be terminated. Plasma etching in this and also in the below described processing steps is always performed with the absolute value of the self-induced bias less than 100 V so that the damage of the semiconductor surface is minimal. After the etching, on the whole area of the structure of integrated transistors follows the growth of about 5 to 10 nm thick dielectric insulating layer 4 with high permittivity, such as Zr0₂ or Hf0₂, see Fig. 6. The growth can be performed by using a technique of atomic layer deposition (ALD) at about 100 to 200 °C by using precursors or by using any other proper technique. Figs. 7, 8 show preparation of the source and the drain ohmic contacts 14 which is done on both types of transistors simultaneously. First, by using plasma etching in reactive ions through the particular resist mask 13. it is necessary to remove selectively the dielectric insulating layer 4, see Fig. 7. SFe -based etching which stops on the GaN surface 3 can be used for that. Next follows selective etching of the GaN upper barrier layer 3 of the enhancement-mode transistor by using e.g. SiCl₄/SF₆ or CC1₂F₂ plasma, this step however can be also skipped. After evaporating a system of ohmic metallization 14 (e.g. Ti/Al/Ni/Au) and its patterning by a technique of lift-off, a rapid thermal annealing at temperature below 400 °C may follow. Photolithography and the technique of lift-off may be used also in patterning gates 15, which is done on the whole area of the structure of integrated transistors, see Fig. 9.

Ni/Au may be used as gates 15 and the system is evaporated directly on the dielectric insulating layer 4. Fig. 10 shows removal of the dielectric layer 4 and subsequently also of the GaN barrier layer 3 from the areas between contacts 14 and 15, which is performed only on the enhancement-mode transistor, i.e. depletion-mode transistor during this technological step is covered by using e.g. the resist mask 13. Dielectric insulating layer 4 is removed by using e.g. SF_&- based etching which stops at the surface of GaN 3 and then the upper GaN barrier layer 3 is removed by using e.g. SiCVSFe or CCI2F2 plasma. Ohmic contacts 14 and the gate 15. of the enhancement-mode transistor may serve as a mask in the process of etching and consequently the usage of the resist mask is not necessary, see Fig. 10.

Passivation of the whole structure is the last technological step, see Fig. 11. Different materials and their combinations, such as SiN, AI₂0₃, Zr0₂, Hf0₂ and similar ones can be used as the passivation layer 16. As shown in the Fig. 11, the upper GaN barrier layer 3 is present only in areas below the gate of the enhancement-mode transistor (eventually below the source and the drain contacts, see Fig. 7), which is important for the minimization of the parasitic source-to-gate and gate-to-drain resistances of both types of transistors. By keeping a unified thickness of the insulating layer 4, e.g. 5 nm thickness on the whole area of the structure, using this method it is possible to prepare simultaneously extremely high transconductance (more than 2 S/mm) transistors operating in both modes with a high span of V_T, which is shown on simulations in Fig. 12.

Alternatively it is also possible to prepare transistors with different thicknesses of the dielectric insulating layer, providing the evaporation process of gates 15 shown in the Fig. 9 is performed separately for each type of the transistor using a separate mask for each. The thickness of the dielectric insulating layer 4 can be changed before evaporating the gate 15 of the particular transistor by using the same mask also for the evaporation of the additional insulating layer from e.g. an electron gun or by using the ALD technique at 100 °C. In this way a full variability of V_T values according to calculations shown in Fig. 3 is secured. Various materials and their combinations can be used for the preparation of the first and of the second dielectric insulating layers providing elimination of the leakage current through the gate is obtained. Industrial Applicability

The invention will be used in the semiconductor industry. Simple integration of the depletion-mode and of the enhancement-mode transistors with the InN channel layer and with the free adjustment of threshold voltage values will facilitate fabrication of a new generation of extremely fast digital or analogue integrated circuits.

Legend Figures 1-12:

1 bottom barrier layer

2 channel layer

3 upper barrier layer

4 dielectric insulating layer

11 substrate

12 buffer layer

13 resist mask

14 ohmic contacts

15 gate

16 passivation layer

Claims

PATENT CLAIMS

1. Enhancement-mode III-N transistor with N-polarity, characterized by consisting of the following layers, from the bottom: a bottom barrier layer (1); a channel layer (2); an upper barrier layer (3), the chemical composition of which is different from the composition of the bottom barrier; and dielectric insulating layer (4), while the upper barrier layer/channel layer interface exhibits a negative polarization charge with an absolute value larger than the positive polarization charge at the channel layer/bottom barrier layer interface, and the transistor threshold is freely adjustable.

2. Enhancement-mode III-N transistor with N-polarity of claim 1, characterized by the channel layer including InN and the upper barrier layer being made of undoped GaN.

3. Enhancement-mode III-N transistor with N-polarity of claim 1 and 2, characterized by the bottom barrier layer being made of In_xAl_yN, while x > 0.4.

4. Enhancement-mode III-N transistor with N-polarity of claim 1 and 2, characterized by the bottom barrier layer being made of a combination of InAlGaN.

5. Enhancement-mode III-N transistor with N-polarity of claim 1 and 2, characterized by the bottom barrier layer being grown on GaN.

6. Enhancement-mode III-N transistor with N-polarity of claim 1 and 2, characterized by the value of the positive threshold voltage of at least 3 V being adjusted by scaling of the thickness of the dielectric insulating layer of the gate.

7. Enhancement-mode III-N transistor with N-polarity of claim 1 and 2, characterized by the bottom barrier layer and the channel layer being separated by a thin GaN interlayer with a thickness of less than 1 nm.

8. Enhancement-mode III-N transistor with N-polarity of claim 1 and 2, characterized by the channel layer being made of a combination of InGaN.

9. Enhancement-mode III-N transistor with N-polarity of claim 1 and the method of fabricating the same, characterized by the fabrication being comprised of: forming of the bottom barrier layer (1); fonning of the channel layer (2); forming of the upper barrier layer (3), chemical composition of which is different from the composition of the bottom barrier layer; and forming of the dielectric insulating layer (4), with the formed channel layer containing InN and serving as a stop layer of the plasma etching.

10. Enhancement-mode III-N transistor with N-polarity of claim 1 and the method of fabricating the same of claim 9, characterized by the upper barrier layer being removed by selective plasma etching between formed contacts, and the source, drain and gate contacts serving as a mask for the etching, with fluoride-containing plasma being used for the upper barrier layer removal.

11. Enhancement-mode III-N transistor with N-polarity of claim 1 and the method of fabricating the same of claim 9, characterized by the enhancement-mode transistor being formed on an identical substrate together with the depletion-mode transistor.

12. Enhancement-mode III-N transistor with N-polarity of claim 1 and the method of fabricating the same of claim 9 and 11, characterized by the grown semiconductor structure being identical for both types of transistors, and before forming the first dielectric insulating layer on the depletion-mode transistor the upper barrier layer on this transistor being selectively removed by using the fluoride-containing plasma.

13. Enhancement-mode III-N transistor with N-polarity of claim 1 and the method of fabricating the same of claims 9 and 11, characterized by forming a second dielectric insulating layer on the first dielectric insulating layer of the depletion-mode transistor before forming the gate of this transistor.

14. Enhancement-mode III-N transistor with N-polarity of claim 1 and the method of fabricating the same of claims 9 and 11, characterized by forming a second dielectric insulating layer on the first dielectric insulating layer of the enhancement-mode transistor before forming the gate of this transistor.

15. Enhancement-mode III-N transistor with N-polarity of claim 1 and the method of fabricating the same of claims 9 and 11, characterized by the possibility of the threshold voltage of the enhancement-mode and also of the depletion-mode transistors being independently and freely adjusted by choosing thicknesses of the first and of the second dielectric insulating layers.