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WO2015043036A1 - 一种阵列基板及液晶显示面板 - Google Patents

一种阵列基板及液晶显示面板 Download PDF

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Publication number
WO2015043036A1
WO2015043036A1 PCT/CN2013/085780 CN2013085780W WO2015043036A1 WO 2015043036 A1 WO2015043036 A1 WO 2015043036A1 CN 2013085780 W CN2013085780 W CN 2013085780W WO 2015043036 A1 WO2015043036 A1 WO 2015043036A1
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WIPO (PCT)
Prior art keywords
pixel
region
switch
ratio
area occupied
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PCT/CN2013/085780
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English (en)
French (fr)
Inventor
陈政鸿
廖作敏
Original Assignee
深圳市华星光电技术有限公司
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Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to RU2016114305A priority Critical patent/RU2633404C1/ru
Priority to GB1601015.9A priority patent/GB2531211B/en
Priority to KR1020167010196A priority patent/KR101813417B1/ko
Priority to JP2016539386A priority patent/JP6293898B2/ja
Priority to US14/233,381 priority patent/US9053663B1/en
Publication of WO2015043036A1 publication Critical patent/WO2015043036A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2003—Display of colours
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134336—Matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0469—Details of the physics of pixel operation
    • G09G2300/0478—Details of the physics of pixel operation related to liquid crystal pixels
    • G09G2300/0495—Use of transitions between isotropic and anisotropic phases in liquid crystals, by voltage controlled deformation of the liquid crystal molecules, as opposed to merely changing the orientation of the molecules as in, e.g. twisted-nematic [TN], vertical-aligned [VA], cholesteric, in-plane, or bi-refringent liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0242—Compensation of deficiencies in the appearance of colours

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular, to an array substrate and a liquid crystal display panel.
  • the liquid crystal display Compared with the traditional CRT display, the liquid crystal display has many advantages such as light and thin, low power consumption, vivid picture and no flicker, and has gradually become the mainstream development direction of the display market.
  • the liquid crystal display mainly utilizes the photoelectric effect of the liquid crystal to control the deflection of the liquid crystal molecules by applying a voltage to the liquid crystal, so that the light emitted by the backlight passes through the liquid crystal layer or does not pass through the liquid crystal layer to achieve selective brightness and darkness effects, thereby generating different The color and pattern are achieved for the purpose of displaying the image.
  • liquid crystal displays have color shift problems. Since the liquid crystal display uses liquid crystal to realize display, the effective refractive index of liquid crystal molecules is different under different viewing angles, thereby causing a change in transmitted light intensity, which is manifested by a decrease in light transmission capability at oblique viewing angles, oblique viewing direction and positive The color of the viewing angle is inconsistent, that is, a normal image is observed under a positive viewing angle but not displayed at a large viewing angle, and a color shift exists.
  • the technical problem to be solved by the present invention is to provide an array substrate and a liquid crystal display panel, which can effectively reduce color difference at a large viewing angle and improve display quality.
  • the technical solution adopted by the present invention is to provide an array substrate including a plurality of first scan lines, a plurality of second scan lines, a plurality of third scan lines, a plurality of data lines, and a plurality of a pixel unit, each pixel unit corresponding to a first scan line, a second scan line, a third scan line, and a data line, each pixel unit including a first pixel area, a second pixel area, and a third pixel area, Each of the pixel units is one of an R pixel unit, a G pixel unit, or a B pixel unit; voltages applied to the first pixel region, the second pixel region, and the third pixel region are Va, Vb, and Vc, respectively, first The pixel region includes a first pixel electrode and a first switch, the second pixel region includes a second pixel electrode and a second switch, and the third pixel region includes a third pixel electrode and a third switch, and the first pixel electrode passes through the
  • the third switch inputs a Vc voltage to the third pixel electrode; Va, Vb, and Vc have the following relationship: Va>Vb>Vc, wherein the first pixel region, the second pixel region, and the third pixel region occupy the pixel unit region
  • the area ratio ranges from 5% to 25%, from 20% to 45%, and from 35% to 75%.
  • the ratio of the area occupied by the first pixel area in the pixel unit area ranges from 7% to 15%
  • the ratio of the area occupied by the second pixel area in the pixel unit area ranges from 23% to 30%
  • the third The ratio of the area occupied by the pixel area in the pixel unit area ranges from 60% to 70%.
  • the ratio of the area occupied by the first pixel area in the pixel unit area ranges from 17% to 22%
  • the ratio of the area occupied by the second pixel area in the pixel unit area ranges from 33% to 40%
  • the third The ratio of the area occupied by the pixel area in the pixel unit area ranges from 40% to 50%.
  • the ratio of the area occupied by the first pixel area in the pixel unit area ranges from 10% to 20%
  • the ratio of the area occupied by the second pixel area in the pixel unit area ranges from 25% to 40%
  • the third The ratio of the area occupied by the pixel area in the pixel unit area ranges from 45% to 65%.
  • the plurality of first scan lines, the plurality of second scan lines, and the plurality of third scan lines are arranged in a row, and the data lines are arranged in a row, and the first pixel electrode, the second pixel electrode, and the third pixel electrode are arranged in the column direction.
  • the first switch is a first thin film transistor
  • the first pixel electrode is connected to the first scan line and the data line of the corresponding pixel unit through the first thin film transistor
  • the second switch is the second thin film transistor
  • the second pixel electrode passes the first
  • the second thin film transistor is connected to the second scan line and the data line corresponding to the pixel unit
  • the third switch is the third thin film transistor
  • the third pixel electrode is connected to the third scan line and the data line corresponding to the pixel unit through the third thin film transistor.
  • an array substrate including a plurality of pixel units, each of which includes a first pixel region, a second pixel region, and a third pixel region;
  • the voltages applied to the one pixel region, the second pixel region, and the third pixel region are Va, Vb, and Vc, respectively, and Va, Vb, and Vc have the following relationship: Va>Vb>Vc, wherein the first pixel region and the second pixel
  • the ratio of the area occupied by the area and the third pixel area in the pixel unit area ranges from 5% to 25%, from 20% to 45%, and from 35% to 75%, respectively.
  • the ratio of the area occupied by the first pixel area in the pixel unit area ranges from 7% to 15%
  • the ratio of the area occupied by the second pixel area in the pixel unit area ranges from 23% to 30%
  • the third The ratio of the area occupied by the pixel area in the pixel unit area ranges from 60% to 70%.
  • the ratio of the area occupied by the first pixel area in the pixel unit area ranges from 17% to 22%
  • the ratio of the area occupied by the second pixel area in the pixel unit area ranges from 33% to 40%
  • the third The ratio of the area occupied by the pixel area in the pixel unit area ranges from 40% to 50%.
  • the ratio of the area occupied by the first pixel area in the pixel unit area ranges from 10% to 20%
  • the ratio of the area occupied by the second pixel area in the pixel unit area ranges from 25% to 40%
  • the third The ratio of the area occupied by the pixel area in the pixel unit area ranges from 45% to 65%.
  • Each of the pixel units is one of an R pixel unit, a G pixel unit, or a B pixel unit.
  • the array substrate further includes a plurality of first scan lines, a plurality of second scan lines, a plurality of third scan lines, and a plurality of data lines, each pixel unit corresponding to one first scan line, one second scan line, and one strip a third scan line including a first pixel electrode and a first switch, a second pixel region including a second pixel electrode and a second switch, the third pixel region including a third pixel electrode and a third switch
  • the first pixel electrode is connected to the first scan line and the data line corresponding to the pixel unit through the first switch
  • the second pixel electrode is connected to the second scan line and the data line corresponding to the pixel unit through the second switch
  • the electrode is connected to the third scan line and the data line corresponding to the pixel unit through the third switch.
  • the data line When the scan signal is input on the first scan line to control the first switch to be turned on, the data line inputs the Va through the first switch to the first pixel electrode. Voltage, when the scan signal is input on the second scan line to control the second switch to be turned on, the data line inputs the Vb voltage to the second pixel electrode through the second switch, and is input at the third scan line. When the scan signal is controlled to control the third switch to be turned on, the data line inputs the Vc voltage to the third pixel electrode through the third switch.
  • the plurality of first scan lines, the plurality of second scan lines, and the plurality of third scan lines are arranged in a row, and the data lines are arranged in a row, and the first pixel electrode, the second pixel electrode, and the third pixel electrode are arranged in the column direction.
  • the first switch is a first thin film transistor
  • the first pixel electrode is connected to the first scan line and the data line of the corresponding pixel unit through the first thin film transistor
  • the second switch is the second thin film transistor
  • the second pixel electrode passes the first
  • the second thin film transistor is connected to the second scan line and the data line corresponding to the pixel unit
  • the third switch is the third thin film transistor
  • the third pixel electrode is connected to the third scan line and the data line corresponding to the pixel unit through the third thin film transistor.
  • a liquid crystal display panel including an array substrate, a color filter substrate, and a liquid crystal layer between the array substrate and the color filter substrate; a pixel unit, each of the pixel units includes a first pixel region, a second pixel region, and a third pixel region; voltages applied to the first pixel region, the second pixel region, and the third pixel region are Va, Vb, and Vc, respectively Va, Vb, and Vc have the following relationship: Va>Vb>Vc, wherein the ratio of the area occupied by the first pixel region, the second pixel region, and the third pixel region in the pixel unit region ranges from 5% to 25, respectively. %, 20%-45% and 35%-75%.
  • the ratio of the area occupied by the first pixel area in the pixel unit area ranges from 7% to 15%
  • the ratio of the area occupied by the second pixel area in the pixel unit area ranges from 23% to 30%
  • the third The ratio of the area occupied by the pixel area in the pixel unit area ranges from 60% to 70%.
  • the ratio of the area occupied by the first pixel area in the pixel unit area ranges from 17% to 22%
  • the ratio of the area occupied by the second pixel area in the pixel unit area ranges from 33% to 40%
  • the third The ratio of the area occupied by the pixel area in the pixel unit area ranges from 40% to 50%.
  • the ratio of the area occupied by the first pixel area in the pixel unit area ranges from 10% to 20%
  • the ratio of the area occupied by the second pixel area in the pixel unit area ranges from 25% to 40%
  • the third The ratio of the area occupied by the pixel area in the pixel unit area ranges from 45% to 65%.
  • each pixel unit includes a first pixel region, a second pixel region, and a third pixel region, and the voltage applied to the first pixel region is different from the prior art.
  • Va, a voltage Vb applied to the second pixel region, and a voltage Vc applied to the third pixel region have the following relationship: Va>Vb>Vc, wherein the first pixel region, the second pixel region, and the third pixel region are in the pixel unit
  • the proportion of the area occupied by the area ranges from 5% to 25%, 20% to 45%, and 35% to 75%, respectively, thereby enabling the difference observed at a large viewing angle and a positive viewing angle to be reduced, achieving a large viewing angle.
  • Low color shift effect is the proportion of the area occupied by the area.
  • FIG. 1 is a schematic structural view of an embodiment of an array substrate of the present invention
  • FIG. 2 is a schematic structural view of an embodiment of a liquid crystal display panel of the present invention.
  • the array substrate includes a plurality of first scan lines 101 , a plurality of second scan lines 102 , a plurality of third scan lines 103 , a plurality of data lines 104 , and a plurality of pixels.
  • the unit 105 has a first scan line 101, a second scan line 102, a third scan line 103, and a data line 104.
  • Each of the pixel units 105 corresponds to one of an R pixel unit, a G pixel unit, or a B pixel unit.
  • Each of the pixel units 105 includes a first pixel area A, a second pixel area B, and a third pixel area C.
  • the first pixel area A includes a first switch Q1 and a first pixel electrode M1
  • the second pixel area B includes a second switch Q2 and a second pixel electrode M2
  • the third pixel area C includes a third switch Q3 and a third pixel.
  • the first switch Q1, the second switch Q2, and the third switch Q3 each include a control end, an input end, and an output end.
  • the control end of the first switch Q1 is electrically connected to the first scan line 101 corresponding to the pixel unit 105, and the input end of the first switch Q1 is electrically connected to the data line 104 corresponding to the pixel unit 105, and the output of the first switch Q1 is The terminal is electrically connected to the first pixel electrode M1 corresponding to the pixel unit 105.
  • the control end of the second switch Q2 is electrically connected to the second scan line 102 corresponding to the pixel unit 105, the input end of the second switch Q2 is electrically connected to the data line 104 corresponding to the pixel unit 105, and the output of the second switch Q2 is The terminal is electrically connected to the second pixel electrode M2 corresponding to the pixel unit 105.
  • the control end of the third switch Q3 is electrically connected to the third scan line 103 corresponding to the pixel unit 105, the input end of the third switch Q3 is electrically connected to the data line 104 corresponding to the pixel unit 105, and the output of the third switch Q3 is The terminal is electrically connected to the third pixel electrode M3 corresponding to the pixel unit 105.
  • the first switch Q1, the second switch Q2, and the third switch Q3 are thin film transistors, which are a first thin film transistor, a second thin film transistor, and a third thin film transistor, respectively, wherein the control end of the switch corresponds to a thin film.
  • the gate of the transistor, the input end of the switch corresponds to the source of the thin film transistor, and the output end of the switch corresponds to the drain of the thin film transistor.
  • the three switches may also be triodes, Darlington tubes, etc., which are not limited herein.
  • the first scan line 101, the second scan line 102, and the third scan line 103 are arranged in a row, and the data lines 104 are arranged in a row, and the first pixel area A, the second pixel area B, and the third pixel area C are sequentially arranged in the column direction. That is, the three pixel electrodes M1, M2, and M3 are sequentially arranged in the column direction.
  • the first scan line, the second scan line, and the third scan line may also be arranged in a row, and the data lines may also be arranged in a row, which is not limited herein.
  • the three pixel regions may also be arbitrarily arranged in the column direction, for example, the first pixel region is located between the second pixel region and the third pixel region, or the third pixel region is located between the first pixel region and the second pixel region. There are no specific restrictions on this.
  • Scanning signals are sequentially input to the scan first scan line 101, the second scan line 102, and the third scan line 103.
  • the scan signal is input to the first scan line 101 to control the first switch Q1 to be turned on, the data line 104 passes through the first switch.
  • Q1 inputs a Va voltage to the first pixel electrode M1 such that the voltage of the first pixel region A is Va; and when the second scan line 102 inputs a scan signal to control the second switch Q2 to be turned on, the data line 104 passes through the second switch Q2.
  • the Vb voltage is input to the second pixel electrode M2 such that the voltage of the second pixel region B is Vb; when the scan signal is input to the third scan line 103 to control the third switch Q3 to be turned on, the data line 104 passes through the third switch Q3.
  • the third pixel electrode M3 inputs the Vc voltage such that the voltage of the third pixel region C is Vc.
  • the voltages input by the first pixel electrode M1, the second pixel electrode M2, and the third pixel electrode M3 are different, and the voltages Va, Vb, and Vc have the following relationship: Va>Vb>Vc, that is, three pixel areas A.
  • the relationship between the voltages between B and C is: Va > Vb > Vc.
  • the ratio of the area occupied by the first pixel area A in the area of the pixel unit 105 ranges from 5% to 25%
  • the ratio of the area occupied by the two pixel area B in the area of the pixel unit 105 ranges from 20% to 45%
  • the ratio of the area occupied by the third pixel area C in the area of the pixel unit 105 ranges from 35% to 75%.
  • the sum of the areas occupied by the pixel areas A, B, and C is the area of the pixel unit 105.
  • the ratio of the area occupied by the first pixel area A in the pixel unit 105 may range from 7% to 15%, and the ratio of the area occupied by the second pixel area B in the pixel unit 105 may range from 23% - 30%, the ratio of the area occupied by the third pixel area C in the pixel unit 105 may range from 60% to 70%, and the total area occupied by the three pixel areas A, B, and C is the area of the pixel unit 105.
  • the ratio of the area occupied by the first pixel area A in the area of the pixel unit 105 is 9%, and the ratio of the area occupied by the second pixel area B in the area of the pixel unit 105 is 26%.
  • the ratio of the area occupied by the three-pixel area C in the area of the pixel unit 105 is 65%.
  • the ratio of the area occupied by the first pixel region, the second pixel region, and the third pixel region in the pixel unit region may be 12%, 28%, 60%, or may be 15%, 23%, 62%, etc., which are not limited herein, and may satisfy the above conditions.
  • one pixel unit 105 is divided into three pixel areas A, B, and C, and different voltages are applied to the three pixel areas A, B, and C, respectively, and the voltage applied by the first pixel area A is Va.
  • the voltage applied by the second pixel region B is Vb
  • the voltage applied by the third pixel region C is Vc, so that Va>Vb>Vc.
  • the ratio of the area occupied by the pixel area A, the second pixel area B, and the third pixel area C in the pixel unit 105 ranges from 5% to 25%, 20% to 45%, and 35% to 75%, respectively. Better reduce the color difference at large viewing angles and large viewing angles to achieve better low color shifting effect and improve display quality.
  • the ratio of the area occupied by the three pixel regions in the pixel unit of the present invention is 5%-25%, 20%-45%, and 35%-75%, respectively.
  • the ratio of the area occupied by the first pixel area in the pixel unit area may also be 17%-22%, and the ratio of the area occupied by the second pixel area in the pixel unit may also be 33%-40%.
  • the ratio of the area occupied by the third pixel region in the pixel unit region may also be 40%-50%.
  • the ratio of the area occupied by the first pixel region, the second pixel region, and the third pixel region in the pixel unit region may be other ranges, for example, 9%-16%, respectively. 28% - 38%, 48% - 55%, for example, may also be 10% - 20%, 25% - 40%, 45% - 65%, respectively.
  • the array substrate can also apply corresponding voltages to the three pixel regions by using three data lines respectively.
  • each pixel unit corresponds to the first data line, the second data line, the third data line, and one scan line, and the first pixel
  • the first pixel electrode in the region is connected to the first data line and the scan line through the first switch
  • the second pixel electrode in the second pixel region is connected to the second data line and the scan line through the second switch, in the third pixel region
  • the third pixel region electrode is connected to the third data line and the scan line through the third switch.
  • the first data line When the scan signal is input to the scan line, the first data line inputs a Va voltage to the first pixel electrode, the second data line inputs a Vb voltage to the second pixel electrode, and the third data line inputs a Vc voltage to the third pixel electrode, and the voltage Va, Vb and Vc have the following relationship: Va>Vb>Vc.
  • Va>Vb>Vc In this way, it is also possible to apply different voltages to the three pixel regions.
  • the ratio of the area occupied by the three pixel regions in the pixel unit ranges from 5% to 25%, 20% to 45%, and 35% to 75%, respectively, thereby effectively reducing the color difference at a large viewing angle. Improve display quality.
  • the liquid crystal display panel includes an array substrate 201 , a color filter substrate 202 , and a liquid crystal layer 203 between the array substrate 201 and the color filter substrate 202 .
  • the array substrate 201 is the array substrate in any of the above embodiments.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Geometry (AREA)
  • Liquid Crystal (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种阵列基板及液晶显示面板。阵列基板中，每个像素单元（105）包括第一像素区（A）、第二像素区（B）以及第三像素区（C），对第一像素区（A）施加的电压Va、对第二像素区（B）施加的电压Vb以及对第三像素区（C）施加的电压Vc具有如下关系：Va＞Vb＞Vc，第一像素区（A）、第二像素区（B）以及第三像素区（C）在像素单元（105）区域中所占的面积的比例范围分别为5%-25%、20%-45%和35%-75%。能够减小大视角下的颜色差异，提高显示质量。

Description

一种阵列基板及液晶显示面板
【技术领域】
本发明涉及液晶显示技术领域，特别是涉及一种阵列基板及液晶显示面板。
【背景技术】
相较于传统的CRT显示器，液晶显示器具有轻巧超薄、低功耗、画面逼真无闪烁等诸多优点，已逐渐成为显示市场的主流发展方向。液晶显示器主要是利用液晶的光电效应，通过对液晶施加电压以控制液晶分子的偏转，使背光源发出的光线穿过液晶层或不穿过液晶层来实现有选择性的明暗效果，进而产生不同的颜色和图案，达到显示图像的目的。
然而，液晶显示器却存在色偏问题。由于液晶显示器是利用液晶实现显示，在不同的视角下，液晶分子的有效折射率也不相同，由此会引起透射光强的变化，具体表现为斜视角下透光能力降低，斜视角方向和正视角方向所表现的颜色不一致，即在正视角下观察到正常的图像但在大视角下却显示不正常，存在色偏。
【发明内容】
本发明主要解决的技术问题是提供一种阵列基板及液晶显示面板，能够有效减小大视角下的颜色差异，提高显示质量。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种阵列基板，包括多条第一扫描线、多条第二扫描线、多条第三扫描线、多条数据线以及多个像素单元，每个像素单元对应一条第一扫描线、一条第二扫描线、一条第三扫描线以及一条数据线，每个像素单元包括第一像素区、第二像素区以及第三像素区，每个像素单元为R像素单元、G像素单元或B像素单元中的一种；对第一像素区、第二像素区以及第三像素区所施加的电压分别为Va、Vb以及Vc，第一像素区包括第一像素电极和第一开关，第二像素区包括第二像素电极和第二开关，第三像素区包括第三像素电极和第三开关，第一像素电极通过第一开关与对应本像素单元的第一扫描线和数据线连接，第二像素电极通过第二开关与对应本像素单元的第二扫描线和数据线连接，第三像素电极通过第三开关与对应本像素单元的第三扫描线和数据线连接，在第一扫描线输入扫描信号以控制第一开关导通时，数据线通过第一开关对第一像素电极输入Va电压，在第二扫描线输入扫描信号以控制第二开关导通时，数据线通过第二开关对第二像素电极输入Vb电压，在第三扫描线输入扫描信号以控制第三开关导通时，数据线通过第三开关对第三像素电极输入Vc电压；Va、Vb以及Vc具有如下关系：Va>Vb>Vc，其中，第一像素区、第二像素区以及第三像素区在像素单元区域中所占的面积的比例范围分别为5%-25%、20%-45%以及35%-75%。
其中，第一像素区在像素单元区域中所占的面积的比例范围为7%-15%，第二像素区在像素单元区域中所占的面积的比例范围为23%-30%，第三像素区在像素单元区域中所占的面积的比例范围为60%-70%。
其中，第一像素区在像素单元区域中所占的面积的比例范围为17%-22%，第二像素区在像素单元区域中所占的面积的比例范围为33%-40%，第三像素区在像素单元区域中所占的面积的比例范围为40%-50%。
其中，第一像素区在像素单元区域中所占的面积的比例范围为10%-20%，第二像素区在像素单元区域中所占的面积的比例范围为25%-40%，第三像素区在像素单元区域中所占的面积的比例范围为45%-65%。
其中，多条第一扫描线、多条第二扫描线以及多条第三扫描线分行排列，数据线分列排列，第一像素电极、第二像素电极以及第三像素电极沿列方向排列。
其中，第一开关为第一薄膜晶体管，第一像素电极通过第一薄膜晶体管与对应本像素单元的第一扫描线和数据线连接，第二开关为第二薄膜晶体管，第二像素电极通过第二薄膜晶体管与对应本像素单元的第二扫描线和数据线连接，第三开关为第三薄膜晶体管，第三像素电极通过第三薄膜晶体管与对应本像素单元的第三扫描线和数据线连接。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种阵列基板，包括多个像素单元，每个像素单元包括第一像素区、第二像素区以及第三像素区；对第一像素区、第二像素区以及第三像素区所施加的电压分别为Va、Vb以及Vc，Va、Vb以及Vc具有如下关系：Va>Vb>Vc，其中，第一像素区、第二像素区以及第三像素区在像素单元区域中所占的面积的比例范围分别为5%-25%、20%-45%以及35%-75%。
其中，第一像素区在像素单元区域中所占的面积的比例范围为7%-15%，第二像素区在像素单元区域中所占的面积的比例范围为23%-30%，第三像素区在像素单元区域中所占的面积的比例范围为60%-70%。
其中，第一像素区在像素单元区域中所占的面积的比例范围为17%-22%，第二像素区在像素单元区域中所占的面积的比例范围为33%-40%，第三像素区在像素单元区域中所占的面积的比例范围为40%-50%。
其中，第一像素区在像素单元区域中所占的面积的比例范围为10%-20%，第二像素区在像素单元区域中所占的面积的比例范围为25%-40%，第三像素区在像素单元区域中所占的面积的比例范围为45%-65%。
其中，每个像素单元为R像素单元、G像素单元或B像素单元中的一种。
其中，阵列基板还包括多条第一扫描线、多条第二扫描线、多条第三扫描线以及多条数据线，每个像素单元对应一条第一扫描线、一条第二扫描线、一条第三扫描线以及一条数据线，第一像素区包括第一像素电极和第一开关，第二像素区包括第二像素电极和第二开关，第三像素区包括第三像素电极和第三开关，第一像素电极通过第一开关与对应本像素单元的第一扫描线和数据线连接，第二像素电极通过第二开关与对应本像素单元的第二扫描线和数据线连接，第三像素电极通过第三开关与对应本像素单元的第三扫描线和数据线连接，在第一扫描线输入扫描信号以控制第一开关导通时，数据线通过第一开关对第一像素电极输入Va电压，在第二扫描线输入扫描信号以控制第二开关导通时，数据线通过第二开关对第二像素电极输入Vb电压，在第三扫描线输入扫描信号以控制第三开关导通时，数据线通过第三开关对第三像素电极输入Vc电压。
其中，多条第一扫描线、多条第二扫描线以及多条第三扫描线分行排列，数据线分列排列，第一像素电极、第二像素电极以及第三像素电极沿列方向排列。
其中，第一开关为第一薄膜晶体管，第一像素电极通过第一薄膜晶体管与对应本像素单元的第一扫描线和数据线连接，第二开关为第二薄膜晶体管，第二像素电极通过第二薄膜晶体管与对应本像素单元的第二扫描线和数据线连接，第三开关为第三薄膜晶体管，第三像素电极通过第三薄膜晶体管与对应本像素单元的第三扫描线和数据线连接。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种液晶显示面板，包括阵列基板、彩色滤光基板以及位于阵列基板和彩色滤光基板之间的液晶层；阵列基板包括多个像素单元，每个像素单元包括第一像素区、第二像素区以及第三像素区；对第一像素区、第二像素区以及第三像素区所施加的电压分别为Va、Vb以及Vc，Va、Vb以及Vc具有如下关系：Va>Vb>Vc，其中，第一像素区、第二像素区以及第三像素区在像素单元区域中所占的面积的比例范围分别为5%-25%、20%-45%以及35%-75%。
其中，第一像素区在像素单元区域中所占的面积的比例范围为7%-15%，第二像素区在像素单元区域中所占的面积的比例范围为23%-30%，第三像素区在像素单元区域中所占的面积的比例范围为60%-70%。
其中，第一像素区在像素单元区域中所占的面积的比例范围为17%-22%，第二像素区在像素单元区域中所占的面积的比例范围为33%-40%，第三像素区在像素单元区域中所占的面积的比例范围为40%-50%。
其中，第一像素区在像素单元区域中所占的面积的比例范围为10%-20%，第二像素区在像素单元区域中所占的面积的比例范围为25%-40%，第三像素区在像素单元区域中所占的面积的比例范围为45%-65%。
本发明的有益效果是：区别于现有技术的情况，本发明的阵列基板中，每个像素单元包括第一像素区、第二像素区以及第三像素区，对第一像素区施加的电压Va、对第二像素区施加的电压Vb以及对第三像素区施加的电压Vc具有如下关系：Va>Vb>Vc，其中，第一像素区、第二像素区以及第三像素区在像素单元区域中所占的面积的比例范围分别为5%-25%、20%-45%和35%-75%，由此能够使得在大视角和正视角下所观察到的差异减小，达到大视角下的低色偏效果。
【附图说明】
图1是本发明阵列基板一实施方式的结构示意图；
图2是本发明液晶显示面板一实施方式的结构示意图。
【具体实施方式】
下面将结合附图和实施方式对本发明进行详细说明。
参阅图1，本发明阵列基板的一实施方式中，阵列基板包括多条第一扫描线101、多条第二扫描线102、多条第三扫描线103、多条数据线104以及多个像素单元105，每个像素单元105对应一条第一扫描线101、一条第二扫描线102、一条第三扫描线103以及数据线104。每个像素单元105对应为R像素单元、G像素单元或B像素单元中的一种。
每个像素单元105包括第一像素区A、第二像素区B以及第三像素区C。其中，第一像素区A包括第一开关Q1和第一像素电极M1，第二像素区B包括第二开关Q2和第二像素电极M2，第三像素区C包括第三开关Q3和第三像素电极M3。第一开关Q1、第二开关Q2以及第三开关Q3均包括控制端、输入端以及输出端。第一开关Q1的控制端与对应本像素单元105的第一扫描线101电性连接，第一开关Q1的输入端与对应本像素单元105的数据线104电性连接，第一开关Q1的输出端与对应本像素单元105的第一像素电极M1电性连接。第二开关Q2的控制端与对应本像素单元105的第二扫描线102电性连接，第二开关Q2的输入端与对应本像素单元105的数据线104电性连接，第二开关Q2的输出端与对应本像素单元105的第二像素电极M2电性连接。第三开关Q3的控制端与对应本像素单元105的第三扫描线103电性连接，第三开关Q3的输入端与对应本像素单元105的数据线104电性连接，第三开关Q3的输出端与对应本像素单元105的第三像素电极M3电性连接。本实施方式中，第一开关Q1、第二开关Q2以及第三开关Q3均为薄膜晶体管，分别是第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管，其中，开关的控制端对应为薄膜晶体管的栅极，开关的输入端对应为薄膜晶体管的源极，开关的输出端对应为薄膜晶体管的漏极。在其他实施方式中，三个开关也可以是三极管、达林顿管等，在此不做限定。
第一扫描线101、第二扫描线102以及第三扫描线103分行排列，数据线104分列排列，第一像素区A、第二像素区B以及第三像素区C沿列方向依次排列，也即三个像素电极M1、M2以及M3沿列方向依次排列。在其他实施方式中，第一扫描线、第二扫描线以及第三扫描线也可以分列排列，数据线也可以分行排列，此处不做限定。当然，三个像素区也可以沿列方向任意排列，例如第一像素区位于第二像素区和第三像素区之间，或者第三像素区位于第一像素区和第二像素区之间，对此不做具体限制。
对扫描第一扫描线101、第二扫描线102以及第三扫描线103依次输入扫描信号，在第一扫描线101输入扫描信号以控制第一开关Q1导通时，数据线104通过第一开关Q1对第一像素电极M1输入Va电压，从而使得第一像素区A的电压为Va；在第二扫描线102输入扫描信号以控制第二开关Q2导通时，数据线104通过第二开关Q2对第二像素电极M2输入Vb电压，从而使得第二像素区B的电压为Vb；在第三扫描线103输入扫描信号以控制第三开关Q3导通时，数据线104通过第三开关Q3对第三像素电极M3输入Vc电压，从而使得第三像素区C的电压为Vc。其中，第一像素电极M1、第二像素电极M2以及第三像素电极M3所输入的电压各不相同，电压Va、Vb以及Vc具有如下关系：Va>Vb>Vc，也即三个像素区A、B和C之间的电压的关系为：Va>Vb>Vc。根据第一像素区A、第二像素区B以及第三像素区C之间的电压关系，控制第一像素区A、第二像素区B以及第三像素区C在像素单元105区域中所占的面积比例，以获得更好的低色偏效果。其中，在通过大量实验模拟和仿真之后，经过总结归纳得出：在一个像素单元105中，第一像素区A在像素单元105区域中所占的面积的比例范围为5%-25%，第二像素区B在像素单元105区域中所占的面积的比例范围为20%-45%，第三像素区C在像素单元105区域中所占的面积的比例范围为35%-75%，三个像素区A、B、C所占的面积总和即为像素单元105的面积。
进一步地，第一像素区A在像素单元105中所占的面积的比例范围可以为7%-15%，第二像素区B在像素单元105中所占的面积的比例范围可以为23%-30%，第三像素区C在像素单元105中所占的面积的比例范围可以为60%-70%，且三个像素区A、B、C所占的面积总和即为像素单元105的面积。例如，本实施方式中，第一像素区A在像素单元105区域中所占的面积的比例为9%，第二像素区B在像素单元105区域中所占的面积的比例为26%，第三像素区C在像素单元105区域中所占的面积的比例为65%。当然，在其他实施方式中，第一像素区、第二像素区以及第三像素区在像素单元区域中分别所占的面积的比例还可以是12%、28%、60%，或者也可以是15%、23%、62%等，此处不进行限定，满足上述条件的均可。
本实施方式中，将一个像素单元105分为三个像素区A、B和C，对三个像素区A、B和C分别施加不同的电压，第一像素区A所施加的电压为Va，第二像素区B所施加的电压为Vb，第三像素区C所施加的电压为Vc，使Va>Vb>Vc，在此基础上，通过大量的实验模拟后归纳总结得出：使第一像素区A、第二像素区B和第三像素区C在像素单元105中所占的面积的比例范围分别为5%-25%、20%-45%和35%-75%，由此能够更好地减小大视角大视角下的颜色差异，以获得更好的低色偏效果，提高显示品质。
在备选实施方式中，在满足本发明三个像素区在像素单元中所占的面积的比例范围分别为5%-25%、20%-45%和35%-75%的条件下，进一步地，第一像素区在像素单元区域中所占的面积的比例范围还可以为17%-22%，第二像素区在像素单元中所占的面积的比例范围还可以为33%-40%，第三像素区在像素单元区域中所占的面积的比例范围还可以为40%-50%。当然，在其他实施方式中，第一像素区、第二像素区以及第三像素区在像素单元区域中所占的面积的比例范围还可以是其他范围，例如可以分别是9%-16%、28%-38%、48%-55%，例如还可以分别是10%-20%、25%-40%、45%-65%。
此外，阵列基板也可以使用三条数据线分别对三个像素区施加相应的电压，例如，每个像素单元对应第一数据线、第二数据线、第三数据线以及一条扫描线，第一像素区中的第一像素电极通过第一开关与第一数据线和扫描线连接，第二像素区中的第二像素电极通过第二开关与第二数据线和扫描线连接，第三像素区中的第三像素区电极通过第三开关与第三数据线和扫描线连接。在扫描线输入扫描信号时，第一数据线对第一像素电极输入Va电压，第二数据线对第二像素电极输入Vb电压，第三数据线对第三像素电极输入Vc电压，电压Va、Vb以及Vc具有如下关系：Va>Vb>Vc。通过此种方式，同样能够对三个像素区分别施加不同的电压。其中，三个像素区在像素单元中所占的面积的比例范围分别为5%-25%、20%-45%和35%-75%，由此能够有效减小大视角下的颜色差异，提高显示品质。
参阅图2，本发明液晶显示面板的一实施方式中，液晶显示面板包括阵列基板201、彩色滤光基板202以及位于阵列基板201、彩色滤光基板202之间的液晶层203。其中，阵列基板201为上述任一实施方式中的阵列基板。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (18)

  1. 一种阵列基板，其中，包括多条第一扫描线、多条第二扫描线、多条第三扫描线、多条数据线以及多个像素单元，每个所述像素单元对应一条第一扫描线、一条第二扫描线、一条第三扫描线以及一条数据线，每个所述像素单元包括第一像素区、第二像素区以及第三像素区，每个所述像素单元为R像素单元、G像素单元或B像素单元中的一种；
    对所述第一像素区、第二像素区以及第三像素区所施加的电压分别为Va、Vb以及Vc，所述第一像素区包括第一像素电极和第一开关，所述第二像素区包括第二像素电极和第二开关，所述第三像素区包括第三像素电极和第三开关，所述第一像素电极通过第一开关与对应本像素单元的所述第一扫描线和数据线连接，所述第二像素电极通过第二开关与对应本像素单元的所述第二扫描线和数据线连接，所述第三像素电极通过第三开关与对应本像素单元的所述第三扫描线和数据线连接，在所述第一扫描线输入扫描信号以控制第一开关导通时，所述数据线通过所述第一开关对所述第一像素电极输入Va电压，在所述第二扫描线输入扫描信号以控制第二开关导通时，所述数据线通过所述第二开关对所述第二像素电极输入Vb电压，在所述第三扫描线输入扫描信号以控制第三开关导通时，所述数据线通过所述第三开关对所述第三像素电极输入Vc电压；
    所述Va、Vb以及Vc具有如下关系：Va>Vb>Vc，其中，所述第一像素区、第二像素区以及第三像素区在所述像素单元区域中所占的面积的比例范围分别为5%-25%、20%-45%以及35%-75%。
  2. 根据权利要求1所述的阵列基板，其中，
    所述第一像素区在所述像素单元区域中所占的面积的比例范围为7%-15%，所述第二像素区在所述像素单元区域中所占的面积的比例范围为23%-30%，所述第三像素区在所述像素单元区域中所占的面积的比例范围为60%-70%。
  3. 根据权利要求1所述的阵列基板，其中，
    所述第一像素区在所述像素单元区域中所占的面积的比例范围为17%-22%，所述第二像素区在所述像素单元区域中所占的面积的比例范围为33%-40%，所述第三像素区在所述像素单元区域中所占的面积的比例范围为40%-50%。
  4. 根据权利要求1所述的阵列基板，其中，
    所述第一像素区在所述像素单元区域中所占的面积的比例范围为10%-20%，所述第二像素区在所述像素单元区域中所占的面积的比例范围为25%-40%，所述第三像素区在所述像素单元区域中所占的面积的比例范围为45%-65%。
  5. 根据权利要求1所述的阵列基板，其中，
    所述多条第一扫描线、多条第二扫描线以及多条第三扫描线分行排列，所述数据线分列排列，所述第一像素电极、第二像素电极以及第三像素电极沿列方向排列。
  6. 根据权利要求1所述的阵列基板，其中，
    所述第一开关为第一薄膜晶体管，所述第一像素电极通过所述第一薄膜晶体管与对应本像素单元的所述第一扫描线和数据线连接，所述第二开关为第二薄膜晶体管，所述第二像素电极通过所述第二薄膜晶体管与对应本像素单元的所述第二扫描线和数据线连接，所述第三开关为第三薄膜晶体管，所述第三像素电极通过所述第三薄膜晶体管与对应本像素单元的所述第三扫描线和数据线连接。
  7. 一种阵列基板，其中，包括多个像素单元，每个所述像素单元包括第一像素区、第二像素区以及第三像素区；
    对所述第一像素区、第二像素区以及第三像素区所施加的电压分别为Va、Vb以及Vc，所述Va、Vb以及Vc具有如下关系：Va>Vb>Vc，其中，所述第一像素区、第二像素区以及第三像素区在所述像素单元区域中所占的面积的比例范围分别为5%-25%、20%-45%以及35%-75%。
  8. 根据权利要求7所述的阵列基板，其中，
    所述第一像素区在所述像素单元区域中所占的面积的比例范围为7%-15%，所述第二像素区在所述像素单元区域中所占的面积的比例范围为23%-30%，所述第三像素区在所述像素单元区域中所占的面积的比例范围为60%-70%。
  9. 根据权利要求7所述的阵列基板，其中，
    所述第一像素区在所述像素单元区域中所占的面积的比例范围为17%-22%，所述第二像素区在所述像素单元区域中所占的面积的比例范围为33%-40%，所述第三像素区在所述像素单元区域中所占的面积的比例范围为40%-50%。
  10. 根据权利要求7所述的阵列基板，其中，
    所述第一像素区在所述像素单元区域中所占的面积的比例范围为10%-20%，所述第二像素区在所述像素单元区域中所占的面积的比例范围为25%-40%，所述第三像素区在所述像素单元区域中所占的面积的比例范围为45%-65%。
  11. 根据权利要求7所述的阵列基板，其中，
    每个所述像素单元为R像素单元、G像素单元或B像素单元中的一种。
  12. 根据权利要求7所述的阵列基板，其中，
    所述阵列基板还包括多条第一扫描线、多条第二扫描线、多条第三扫描线以及多条数据线，每个所述像素单元对应一条第一扫描线、一条第二扫描线、一条第三扫描线以及一条数据线，所述第一像素区包括第一像素电极和第一开关，所述第二像素区包括第二像素电极和第二开关，所述第三像素区包括第三像素电极和第三开关，所述第一像素电极通过第一开关与对应本像素单元的所述第一扫描线和数据线连接，所述第二像素电极通过第二开关与对应本像素单元的所述第二扫描线和数据线连接，所述第三像素电极通过第三开关与对应本像素单元的所述第三扫描线和数据线连接，在所述第一扫描线输入扫描信号以控制第一开关导通时，所述数据线通过所述第一开关对所述第一像素电极输入Va电压，在所述第二扫描线输入扫描信号以控制第二开关导通时，所述数据线通过所述第二开关对所述第二像素电极输入Vb电压，在所述第三扫描线输入扫描信号以控制第三开关导通时，所述数据线通过所述第三开关对所述第三像素电极输入Vc电压。
  13. 根据权利要求12所述的阵列基板，其中，
    所述多条第一扫描线、多条第二扫描线以及多条第三扫描线分行排列，所述数据线分列排列，所述第一像素电极、第二像素电极以及第三像素电极沿列方向排列。
  14. 根据权利要求12所述的阵列基板，其中，
    所述第一开关为第一薄膜晶体管，所述第一像素电极通过所述第一薄膜晶体管与对应本像素单元的所述第一扫描线和数据线连接，所述第二开关为第二薄膜晶体管，所述第二像素电极通过所述第二薄膜晶体管与对应本像素单元的所述第二扫描线和数据线连接，所述第三开关为第三薄膜晶体管，所述第三像素电极通过所述第三薄膜晶体管与对应本像素单元的所述第三扫描线和数据线连接。
  15. 一种液晶显示面板，其中，包括阵列基板、彩色滤光基板以及位于所述阵列基板和彩色滤光基板之间的液晶层；
    所述阵列基板包括多个像素单元，每个所述像素单元包括第一像素区、第二像素区以及第三像素区；
    对所述第一像素区、第二像素区以及第三像素区所施加的电压分别为Va、Vb以及Vc，所述Va、Vb以及Vc具有如下关系：Va>Vb>Vc，其中，所述第一像素区、第二像素区以及第三像素区在所述像素单元区域中所占的面积的比例范围分别为5%-25%、20%-45%以及35%-75%。
  16. 根据权利要求15所述的液晶显示面板，其中，
    所述第一像素区在所述像素单元区域中所占的面积的比例范围为7%-15%，所述第二像素区在所述像素单元区域中所占的面积的比例范围为23%-30%，所述第三像素区在所述像素单元区域中所占的面积的比例范围为60%-70%。
  17. 根据权利要求15所述的液晶显示面板，其中，
    所述第一像素区在所述像素单元区域中所占的面积的比例范围为17%-22%，所述第二像素区在所述像素单元区域中所占的面积的比例范围为33%-40%，所述第三像素区在所述像素单元区域中所占的面积的比例范围为40%-50%。
  18. 根据权利要求15所述的液晶显示面板，其中，
    所述第一像素区在所述像素单元区域中所占的面积的比例范围为10%-20%，所述第二像素区在所述像素单元区域中所占的面积的比例范围为25%-40%，所述第三像素区在所述像素单元区域中所占的面积的比例范围为45%-65%。
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