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WO2014208043A1 - Physical quantity sensor - Google Patents

Physical quantity sensor Download PDF

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Publication number
WO2014208043A1
WO2014208043A1 PCT/JP2014/003219 JP2014003219W WO2014208043A1 WO 2014208043 A1 WO2014208043 A1 WO 2014208043A1 JP 2014003219 W JP2014003219 W JP 2014003219W WO 2014208043 A1 WO2014208043 A1 WO 2014208043A1
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WO
WIPO (PCT)
Prior art keywords
substrate
physical quantity
resistivity
insulating film
semiconductor layer
Prior art date
Application number
PCT/JP2014/003219
Other languages
French (fr)
Japanese (ja)
Inventor
圭正 杉本
酒井　峰一
Original Assignee
株式会社デンソー
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社デンソー filed Critical 株式会社デンソー
Publication of WO2014208043A1 publication Critical patent/WO2014208043A1/en

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01P—MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
    • G01P15/00—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration
    • G01P15/02—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses
    • G01P15/08—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values
    • G01P15/125—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values by capacitive pick-up
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01P—MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
    • G01P15/00—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration
    • G01P15/02—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses
    • G01P15/08—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values
    • G01P15/0802—Details
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01P—MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
    • G01P15/00—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration
    • G01P15/02—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses
    • G01P15/08—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values
    • G01P2015/0805—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values being provided with a particular type of spring-mass-system for defining the displacement of a seismic mass due to an external acceleration
    • G01P2015/0822—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values being provided with a particular type of spring-mass-system for defining the displacement of a seismic mass due to an external acceleration for defining out-of-plane movement of the mass
    • G01P2015/0825—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values being provided with a particular type of spring-mass-system for defining the displacement of a seismic mass due to an external acceleration for defining out-of-plane movement of the mass for one single degree of freedom of movement of the mass
    • G01P2015/0831—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values being provided with a particular type of spring-mass-system for defining the displacement of a seismic mass due to an external acceleration for defining out-of-plane movement of the mass for one single degree of freedom of movement of the mass the mass being of the paddle type having the pivot axis between the longitudinal ends of the mass, e.g. see-saw configuration

Definitions

  • a hermetic chamber is formed between a first substrate and a second substrate, a sensing unit that outputs a sensor signal corresponding to a physical quantity is provided in the hermetic chamber, and the second substrate is maintained at a predetermined potential.
  • the present invention relates to a physical quantity sensor.
  • Patent Document 1 a first substrate on which a sensing unit that outputs a sensor signal corresponding to a physical quantity is formed, and a second substrate that is bonded to the first substrate so as to seal the sensing unit,
  • a physical quantity sensor comprising: Note that the first substrate has a silicon substrate on which a sensing portion is formed, and the second substrate has a structure in which a silicon substrate to be a bonded substrate is covered with an insulating film.
  • a parasitic capacitance is generated between the first substrate and the second substrate, but the potential of the second substrate is not stable because the potential of the second substrate (bonded substrate) is in a floating state. It may become stable. For this reason, the parasitic capacitance generated between the first substrate and the second substrate varies, and the change in the parasitic capacitance may become noise.
  • a contact portion made of aluminum or the like is formed on a bonded substrate that constitutes the second substrate, and the bonded substrate and an external circuit are connected via the contact portion. It is conceivable to maintain a constant potential. That is, it is conceivable to make the parasitic capacitance generated between the first substrate and the second substrate constant. In this case, if the contact resistance between the bonded substrate and the contact portion is high, it is difficult to apply a sufficient charge to the bonded substrate, so it is desirable to reduce the contact resistance.
  • the present disclosure aims to provide a physical quantity sensor that can reduce the contact resistance between the bonded substrate and the contact portion without increasing the number of manufacturing steps.
  • a physical quantity sensor includes a first substrate having one surface, a second substrate having one surface, the second substrate being bonded to the first substrate in a state of facing the one surface of the first substrate, 1.
  • a sensing unit is provided in an airtight chamber formed between the first and second substrates and outputs a sensor signal corresponding to a physical quantity.
  • the second substrate is formed of a P-type silicon substrate having a resistivity of 0.01 to 0.2 [ ⁇ ⁇ cm], and is connected to a contact portion formed using a metal material to have a predetermined potential. Having a bonded substrate).
  • the first substrate is an SOI (Silicon-on-Insulator) substrate in which a support substrate, an insulating film, and a semiconductor layer are sequentially stacked, and the surface of the semiconductor layer opposite to the insulating film is one surface of the first substrate. It can be said that.
  • SOI Silicon-on-Insulator
  • At least a part of the sensing unit is formed in the semiconductor layer, and a periodic voltage carrier wave is input to the part. It can be composed of a silicon substrate having a rate of 0.01 to 20 [ ⁇ ⁇ cm].
  • the support substrate is made of a P-type silicon substrate having a resistivity of 0.01 to 0.2 [ ⁇ ⁇ cm], and is connected to an external circuit through a contact portion made of a metal material. Thus, it can be maintained at a predetermined potential.
  • the semiconductor layer can be composed of a P-type silicon substrate having a resistivity of 0.01 to 0.03 [ ⁇ ⁇ cm]. Further, the semiconductor layer can be formed of an N-type silicon substrate having a resistivity of 0.01 to 0.2 [ ⁇ ⁇ cm].
  • the sheet resistance (depletion layer resistance) is 1.0 ⁇ ⁇ cm 2 or less, and it is possible to suppress a decrease in detection accuracy.
  • the drawing It is sectional drawing of the acceleration sensor in 1st Embodiment of this indication. It is a top view by the side of the 2nd board
  • FIG. 8E It is sectional drawing which shows the manufacturing process following FIG. 8E. It is sectional drawing which shows the manufacturing process with respect to a bonded substrate board. It is sectional drawing which shows the manufacturing process following FIG. 9A. It is sectional drawing which shows the manufacturing process of the acceleration sensor shown in FIG. It is sectional drawing which shows the manufacturing process following FIG. 10A. It is sectional drawing which shows the manufacturing process following FIG. 10B.
  • FIG. 10C is a cross-sectional view showing a manufacturing step following FIG. 10C.
  • the acceleration sensor is configured by laminating a first substrate 10 and a second substrate 40. 1 corresponds to the II cross section in FIGS. 2 and 3.
  • FIG. 1 corresponds to the II cross section in FIGS. 2 and 3.
  • the first substrate 10 is an SOI (Silicon on Insulator) substrate in which a semiconductor layer 13 is disposed on a support substrate 11 via an insulating film 12, and one surface 10 a is insulated from the semiconductor layer 13. It is comprised by the surface on the opposite side to the film
  • the support substrate 11 and the semiconductor layer 13 are composed of a silicon substrate, and the insulating film 12 is composed of SiO 2 , SiN, or the like.
  • the semiconductor layer 13 is subjected to micromachining to form a groove portion 14, and the movable portion 20 and the peripheral portion 30 are partitioned by the groove portion 14.
  • the support substrate 11 and the insulating film 12 are recessed in a portion facing the movable portion 20. 15 is formed.
  • the movable portion 20 includes a rectangular frame-shaped frame portion 22 in which a planar rectangular opening portion 21 is formed, and a torsion beam 23 provided so as to connect opposite sides of the opening portion 21.
  • the movable portion 20 is supported by the support substrate 11 by connecting the torsion beam 23 to the anchor portion 24 supported by the insulating film 12.
  • the x-axis direction is the left-right direction in FIG. 1
  • the y-axis direction is the direction perpendicular to the x-axis in the plane of the first substrate 10
  • the z-axis direction is the surface of the first substrate 10. The direction is normal to the direction.
  • the torsion beam 23 is a member that becomes a rotation axis that becomes the rotation center of the movable portion 20 when an acceleration in the z-axis direction is applied, and is provided so as to divide the opening 21 into two in this embodiment.
  • the frame portion 22 has an asymmetric shape with respect to the torsion beam 23 so that it can rotate around the torsion beam 23 when an acceleration in the z-axis direction is applied.
  • the length of the frame portion 22 in the x-axis direction to the end of the portion farthest from the torsion beam 23 in the first portion 22a is farthest from the torsion beam 23 in the second portion 22b.
  • the length to the end of the part is shorter than the length in the x-axis direction. That is, in the frame portion 22 of the present embodiment, the mass of the first part 22a is smaller than the mass of the second part 22b.
  • pad portions 25 and 31 and a frame-shaped sealing portion 32 are formed on one surface 10a of the first substrate 10 (the surface of the semiconductor layer 13). Specifically, the pad portion 25 is formed on the anchor portion 24 and connected to the anchor portion 24 (movable portion 20), and the pad portion 31 is formed on the peripheral portion 30 and connected to the peripheral portion 30 for sealing.
  • the part 32 is formed in the peripheral part 30 so as to surround the movable part 20 (groove part 14).
  • the pad part 31 is arrange
  • a frame-like spacer 33 surrounding the sealing portion 32 is formed on the outer edge portion of the peripheral portion 30 on the one surface 10 a of the first substrate 10.
  • the spacer 33 maintains the distance between the first substrate 10 and the second substrate 40, and is composed of an insulating film such as an oxide film.
  • an oxide film such as an oxide film.
  • phosphorus or the like serving as an ion trap may be added to the oxide film constituting the spacer 33 in order to capture sodium ions or the like applied from the external environment.
  • the second substrate 40 is bonded to the bonded substrate 41, the insulating film 42 formed on one side and the side of the bonded substrate 41 facing the first substrate 10, and the bonded substrate 41.
  • the substrate 41 has an insulating film 43 formed on the other surface opposite to the first substrate 10 side. Then, one surface 40 a of the second substrate 40 is formed on the surface of the insulating film 42 facing the first substrate 10.
  • the bonded substrate 41 is made of a silicon substrate, the insulating film 42 is made of SiO 2 , SiN or the like, and the insulating film 43 is made of TEOS or the like.
  • the first and second wiring portions 51 and 52 are formed on the one surface 40a of the second substrate 40.
  • the first wiring part 51 is formed in a portion facing the first part 22a, and includes a first fixed electrode 51a and a first fixed electrode that form a predetermined capacity with the first part 22a.
  • the second wiring portion 52 is formed in a portion facing the second portion 22b, and is pulled out from the second fixed electrode 52a and the second fixed electrode 52a that constitutes a predetermined capacity between the second portion 22b.
  • Second lead wiring 52b Second lead wiring 52b.
  • the first and second fixed electrodes 51a and 52a have the same planar shape, and form an equal capacity between the first and second portions 22a and 22b when no acceleration is applied.
  • the first and second lead wires 51b and 52b have circular shapes at the ends opposite to the first and second fixed electrodes 51a and 52a, respectively. And the part which opposes the 1st, 2nd fixed electrodes 51a and 52a among the frame parts 22 becomes a movable electrode.
  • pad portions 53 and 54 are formed at portions facing the pad portion 25 and pad portion 31, and the sealing portion 32 is disposed at a portion facing the sealing portion 32.
  • the sealing part 55 having the same shape as that is formed.
  • the pad parts 53 and 54 and the sealing part 55 are made of aluminum or the like.
  • each through electrode portion 70 is formed in the second substrate 40 so as to penetrate the second substrate 40 in the thickness direction (the stacking direction of the first and second substrates 10 and 40).
  • a through electrode 70 c is formed in a through hole 70 a that penetrates the insulating film 43, the bonded substrate 41, and the insulating film 42 via an insulating film 70 b, and the through electrode 70 c and the external circuit are formed on the insulating film 43.
  • the pad portion 70d that is electrically connected to the pad is formed.
  • the through electrode portions 70 are electrically connected to the first and second wiring portions 51 and 52 and the pad portions 53 and 54, respectively. That is, the through hole 70a in each through electrode part 70 is formed to reach the first and second wiring parts 51 and 52 and the pad parts 53 and 54, respectively.
  • the two wiring portions 51 and 52 and the pad portions 53 and 54 are disposed in the through hole 70a so as to be electrically connected.
  • the movable portion 20 is connected to the through electrode 70c via the pad portions 25 and 53, and the first and second fixed electrodes 51a and 52a are connected to the through electrode 70c.
  • the peripheral portion 30 is connected to the through electrode 70 c via the pad portions 31 and 54.
  • the through hole 70a of the through electrode portion 70 that is electrically connected to the first and second wiring portions 51 and 52 corresponds to the first and second lead wirings 51b and 52b in the first and second wiring portions 51 and 52, respectively.
  • the first and second fixed electrodes 51a and 52a are formed so as to reach the end opposite to the side.
  • the through hole 70a is cylindrical
  • the insulating film 70b is made of an insulating material such as TEOS
  • the through electrode 70c is made of aluminum or the like.
  • a contact hole 43 a that opens a predetermined portion of the bonded substrate 41 is formed in the insulating film 43.
  • a contact portion 80 for connecting the bonded substrate 41 and an external circuit and maintaining the bonded substrate 41 at a predetermined potential is embedded.
  • the contact portion 80 is made of aluminum, like the through electrode 70c and the pad portion 70d.
  • the above is the configuration of the second substrate 40 in the present embodiment. And the said 1st, 2nd board
  • the first and second substrates 10 and 40 are integrated by metal bonding of the pad portion 25 and the pad portion 53, the pad portion 31 and the pad portion 54, and the sealing portion 32 and the sealing portion 55. It has become.
  • the space between the first and second substrates 10 and 40 forms an airtight chamber 90, and the frame portion 22 and the first and second fixed electrodes 51 a and 52 a (sensing unit 60) are sealed in the airtight chamber 90. ing.
  • the hermetic chamber 90 is, for example, a vacuum.
  • the above is the basic configuration of the acceleration sensor in the present embodiment. Next, the configuration of the support substrate 11, the semiconductor layer 13, and the bonded substrate 41 that are characteristic points of the present embodiment will be specifically described.
  • the contact resistance between silicon and aluminum becomes almost zero when the resistivity of silicon is 0.2 ⁇ ⁇ cm or less.
  • the contact resistance gradually increases as the resistivity of silicon increases. That is, silicon and aluminum are in ohmic contact when the resistivity of silicon is 0.2 ⁇ ⁇ cm or less, and are in Schottky contact when the resistivity of silicon is greater than 0.2 ⁇ ⁇ cm.
  • FIG. 4 is a diagram showing the relationship between the contact resistance between P-type silicon and aluminum, but the relationship between the resistivity of silicon and the contact resistance even when a metal material such as gold other than aluminum is used. The same.
  • the bonded substrate 41 is a P-type, and is formed of a silicon substrate having a resistivity of 0.01 to 0.2 ⁇ ⁇ cm.
  • the bonded substrate 41 is formed of a silicon substrate having a resistivity at which the contact resistance with the contact portion 80 is substantially zero.
  • 0.01 ⁇ ⁇ cm which is the lower limit of the resistivity, is the lowest limit resistivity when the silicon substrate is actually formed, and the same applies to the support substrate 11 and the semiconductor layer 13 described below.
  • the bonded substrate 41 is made of an N-type silicon substrate, if the contact resistance is made to be almost zero due to the work function with aluminum, the minimum limit resistivity when forming Si is obtained. A value lower than a certain 0.01 ⁇ ⁇ cm is required. For this reason, when the bonded substrate 41 is composed of an N-type silicon substrate, it is necessary to form a high-concentration layer in a portion in contact with the contact portion 80, which increases the manufacturing process.
  • the acceleration sensor as described above is a fully differential type composed of an operational amplifier 101, first and second capacitors 102a and 102b, and first and second switches 103a and 103b. It may be used by being connected to the CV conversion circuit 110.
  • the first capacitor 102a and the first switch 103a are arranged in parallel between the inverting input terminal of the operational amplifier 101 and the + side output terminal.
  • the second capacitor 102b and the second switch 103b are disposed in parallel between the non-inverting input terminal of the operational amplifier 101 and the negative output terminal.
  • the operational amplifier 101 has an inverting input terminal electrically connected to the first fixed electrode 51a and a non-inverting input terminal electrically connected to the second fixed electrode 52a.
  • a pulse-shaped periodic carrier wave having an amplitude between a voltage Vcc and 0 V and having a predetermined frequency is input to the movable unit 20.
  • the frame portion 22 rotates according to the acceleration with the torsion beam 23 as the rotation axis. Since the capacitance between the first portion 22a and the first fixed electrode 51a and the capacitance between the second portion 22b and the second fixed electrode 52a change according to the acceleration, the CV conversion circuit 110 Output a sensor signal Vout (V1-V2) corresponding to the capacitance.
  • the potential of the support substrate 11 is in a floating state, the potential of the support substrate 11 is displaced depending on the carrier wave input to the anchor portion 24 (frame portion 22).
  • the support substrate 11 has a resistivity, if the resistivity is large, the potential of the portion of the support substrate 11 that faces the anchor portion 24 via the insulating film 12 and the outer edge portion of the frame portion 22 And a potential of the portion facing each other. That is, the electrostatic force (parasitic capacitance) generated between a portion of the support substrate 11 that faces the anchor portion 24 via the insulating film 12 and the anchor portion 24, and the outer edge of the frame portion 22 of the support substrate 11.
  • the electrostatic force (parasitic capacitance) generated between the part facing the part and the outer edge part is different. For this reason, at the time of detection, the difference in electrostatic force becomes an output error, and the detection accuracy decreases.
  • the support substrate 11 is composed of a silicon substrate having a resistivity of 0.01 to 20 ⁇ ⁇ cm.
  • FIG. 6 shows a simulation result using a silicon substrate having a thickness of 120 ⁇ m, a width of 400 ⁇ m, and a length of 2 mm. Further, since the phase difference is the same between the P-type silicon substrate and the N-type silicon substrate, the support substrate 11 may be configured by either the P-type silicon substrate or the N-type silicon substrate.
  • the semiconductor layer 13 (frame portion 22) detects charges generated due to capacitance changes when acceleration is applied, the surface resistance (depletion) is reduced so as to make the phase shift at the electrode interface negligible.
  • the layer resistance is preferably 1.0 ⁇ ⁇ cm 2 or less. Therefore, as shown in FIG. 7, the semiconductor layer 13 is a P-type silicon substrate having a thickness of 0.01 to 0.03 ⁇ ⁇ cm or an N-type silicon substrate having a thickness of 0.01 to 0.2 ⁇ ⁇ cm. It is composed of a silicon substrate.
  • FIGS. 8A to 8F a method for manufacturing the acceleration sensor will be described with reference to FIGS. 8A to 8F, FIGS. 9A to 9B, and FIGS. 10A to 10D.
  • a support substrate 11 is prepared, and an insulating film 12 is formed on the support substrate 11 by a CVD (Chemical Vapor Deposition) method, thermal oxidation, or the like.
  • the support substrate 11 is composed of an N-type silicon substrate or a P-type silicon substrate having a resistivity of 0.01 to 20 ⁇ ⁇ cm.
  • a mask such as a resist or an oxide film is formed on the insulating film 12 and wet etching or the like is performed to form a recess 15 in the support substrate 11.
  • the insulating film 12 and the semiconductor layer 13 are joined to form the first substrate 10.
  • the bonding between the insulating film 12 and the semiconductor layer 13 is not particularly limited, but can be performed as follows, for example.
  • the bonding surface of the insulating film 12 and the bonding surface of the semiconductor layer 13 are irradiated with N 2 plasma, O 2 plasma, or an Ar ion beam to activate the bonding surfaces of the insulating film 12 and the semiconductor layer 13. Then, alignment is performed with an infrared microscope or the like using an appropriately formed alignment mark, and the insulating film 12 and the semiconductor layer 13 are bonded by so-called direct bonding at room temperature to 550 ° C.
  • the semiconductor layer 13 is a P-type silicon substrate having a resistivity of 0.01 to 0.03 ⁇ ⁇ cm, or an N-type having a resistivity of 0.01 to 0.2 ⁇ ⁇ cm. It is composed of a silicon substrate.
  • the insulating film 12 and the semiconductor layer 13 may be bonded by a bonding technique such as anodic bonding, intermediate layer bonding, or fusion bonding. And after joining, you may perform the process which improves joining quality, such as high temperature annealing. Further, after bonding, the semiconductor layer 13 may be processed to a desired thickness by grinding and polishing.
  • an insulating film is formed on one surface 10a of the first substrate 10 by a CVD method or the like.
  • the spacer 33 is formed by patterning the insulating film by reactive ion etching or the like using a mask (not shown) such as a resist or an oxide film.
  • a metal film is formed on one surface 10a of the first substrate 10 by a CVD method or the like.
  • the pad parts 25 and 31 and the sealing part 32 are formed by patterning the said metal film by reactive ion etching etc. using masks (not shown), such as a resist and an oxide film.
  • a groove 14 is formed in the semiconductor layer 13 by reactive ion etching or the like using a mask (not shown) such as a resist or an oxide film.
  • a mask such as a resist or an oxide film.
  • a bonded substrate 41 is prepared as shown in FIG. 9A, and an insulating film 42 is formed on the entire surface of the bonded substrate 41 by thermal oxidation or the like.
  • the bonded substrate 41 is composed of a P-type silicon substrate having a resistivity of 0.01 to 0.03 ⁇ ⁇ cm as described above.
  • a metal film is formed on a portion of the insulating film 42 facing the first substrate 10. Then, by patterning the metal film by reactive ion etching or the like using a mask (not shown) such as a resist or an oxide film, the first and second wiring parts 51 and 52, pad parts 53 and 54, sealing A stop 55 is formed.
  • a mask such as a resist or an oxide film
  • the first substrate 10 and the second substrate 40 are bonded. Specifically, alignment is performed by an infrared microscope or the like using appropriately formed alignment marks, and the pad portions 25 and 31 of the first substrate 10, the sealing portion 32, and the pad portions 53 and 54 of the second substrate 40. Then, the sealing portion 55 is metal-bonded at 300 to 500 °.
  • the space between the first substrate 10 and the second substrate 40 is sealed by the sealing portion 32 and the sealing portion 55 to form an airtight chamber 90, and the frame portion 22 and the first and second fixed electrodes 51a. , 52a (sensing unit 60) is hermetically sealed in the hermetic chamber 90. Note that the distance between the first substrate 10 and the second substrate 40 is defined by the spacer 33.
  • the insulating film 42 and the bonded substrate 41 are ground from the side opposite to the first substrate 10 side, and the insulating film 42 on the side opposite to the first substrate 10 side is removed and bonded.
  • the substrate 41 is thinned. This step may be performed before the first substrate 10 and the second substrate 40 are bonded.
  • the two through holes 70 a are formed by removing the bonded substrate 41 and the insulating film 42 at locations corresponding to the pad portions 53 and 54. Further, in a cross section different from FIG. 10C, by removing the bonding substrate 41 and the insulating film 42 at locations corresponding to the first and second lead wirings 51b and 52b in the first and second wiring parts 51 and 52, Two through holes 70a are formed. Then, an insulating film 70b such as TEOS is formed on the wall surface of each through hole 70a. At this time, the insulating film 43 is composed of an insulating film formed on the side of the bonded substrate 41 opposite to the first substrate 10 side.
  • the insulating film 43 and the insulating film 70b are formed in the same process. Thereafter, the insulating film 70b formed at the bottom of each through hole 70a is removed, and the first and second lead lines 51b and 52b and the pad part in the first and second wiring parts 51 and 52 are formed in each through hole 70a. 53 and 54 are exposed.
  • each through electrode 70c is electrically connected to the first and second lead wires 51b and 52b and the pad portions 53 and 54 in the first and second wiring portions 51 and 52, respectively. Thereafter, the through electrode portion 70 is formed by patterning the metal film on the insulating film 43 to form the pad portion 70d.
  • the acceleration sensor is manufactured by forming the contact hole 43a in the insulating film 43 and embedding the metal film in the contact hole 43a to form the contact portion 80.
  • substrates 10 and 40 are prepared, and after dicing and cutting these, it divides
  • the bonded substrate 41 is composed of a P-type silicon substrate having a resistivity of 0.01 to 0.03 ⁇ ⁇ cm. For this reason, the contact resistance between the bonded substrate 41 and the contact portion 80 can be made substantially zero without forming a high concentration layer on the bonded substrate 41 (see FIG. 4). That is, contact resistance can be reduced without increasing the number of manufacturing steps.
  • the support substrate 11 is made of a silicon substrate having a resistivity of 0.01 to 20 ⁇ ⁇ cm. Therefore, even when a carrier wave is input to the movable portion 20 (semiconductor layer 13) when connected to a fully differential CV conversion circuit, the potential of the support substrate 11 is prevented from varying from part to part. It can suppress and it can suppress that detection accuracy falls.
  • the semiconductor layer 13 is composed of a P-type silicon substrate having a resistivity of 0.01 to 0.03 ⁇ ⁇ cm or an N-type silicon substrate having a resistivity of 0.01 to 0.2 ⁇ ⁇ cm. Has been. For this reason, surface resistance (depletion layer resistance) becomes 1.0 ⁇ ⁇ cm 2 or less, and it is possible to suppress a decrease in detection accuracy.
  • the acceleration sensor that detects acceleration in the z-axis direction has been described as an example.
  • the present disclosure may be applied to an acceleration sensor that detects acceleration in the x-axis direction or the y-axis direction.
  • the first substrate 10 is formed with a movable part 20 having a movable electrode that is displaced according to acceleration, and a fixed part having a fixed electrode facing the movable electrode.
  • a carrier wave is input to either the movable electrode or the fixed electrode according to the CV conversion circuit to be connected. Therefore, the support substrate 11 is composed of a silicon substrate having a resistivity of 0.01 to 20 ⁇ ⁇ cm.
  • the physical quantity sensor of the present disclosure can be applied to an angular velocity sensor or the like.
  • a contact portion similar to the contact portion 80 may be formed on the support substrate 11, and the support substrate 11 and an external circuit may be connected to keep the potential of the support substrate 11 constant.
  • the support substrate 11 is composed of a P-type silicon substrate having a resistivity of 0.01 to 0.2 ⁇ ⁇ cm. According to this, it is possible to suppress a variation in parasitic capacitance generated between the semiconductor layer 13 and the support substrate 11 while reducing the contact resistance between the support substrate 11 and the contact portion.

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Abstract

　This physical quantity sensor is provided with a first substrate (10), a second substrate (40) joined to the first substrate, and a sensing unit (60) situated within an airtight chamber (90) formed between the first substrate and the second substrate, for outputting a sensor signal in response to a physical quantity. The second substrate is constituted by a p-type silicon substrate having resistivity of 0.01-0.2 ［Ω・cm］, and has a bonded substrate (41) which is maintained at a prescribed potential through connection to a contact part (80) constituted of metal material.

Description

物理量センサPhysical quantity sensor 関連出願の相互参照Cross-reference of related applications
　本開示は、２０１３年６月２７日に出願された日本出願番号２０１３－１３４８４０号に基づくもので、ここにその記載内容を援用する。 This disclosure is based on Japanese Application No. 2013-134840 filed on June 27, 2013, the contents of which are incorporated herein.
　本開示は、第１基板と第２基板との間に気密室が形成され、気密室に物理量に応じたセンサ信号を出力するセンシング部が備えられると共に第２基板が所定の電位に維持される物理量センサに関するものである。 In the present disclosure, a hermetic chamber is formed between a first substrate and a second substrate, a sensing unit that outputs a sensor signal corresponding to a physical quantity is provided in the hermetic chamber, and the second substrate is maintained at a predetermined potential. The present invention relates to a physical quantity sensor.
　従来より、例えば、特許文献１には、物理量に応じたセンサ信号を出力するセンシング部が形成された第１基板と、センシング部を封止するように第１基板と接合される第２基板とを備える物理量センサが提案されている。なお、第１基板はセンシング部が形成されるシリコン基板を有し、第２基板は貼り合わせ基板となるシリコン基板が絶縁膜で覆われた構成とされている。 Conventionally, for example, in Patent Document 1, a first substrate on which a sensing unit that outputs a sensor signal corresponding to a physical quantity is formed, and a second substrate that is bonded to the first substrate so as to seal the sensing unit, There has been proposed a physical quantity sensor comprising: Note that the first substrate has a silicon substrate on which a sensing portion is formed, and the second substrate has a structure in which a silicon substrate to be a bonded substrate is covered with an insulating film.
　このような物理量センサでは、センシング部を封止するように第１、第２基板が接合されているため、センシング部に異物等が付着することを抑制できる。 In such a physical quantity sensor, since the first and second substrates are joined so as to seal the sensing unit, it is possible to prevent foreign substances and the like from adhering to the sensing unit.
特開２０１０－１７１３６８号公報JP 2010-171368 A
　しかしながら、上記物理量センサでは、第１基板と第２基板との間に寄生容量が生成されるが、第２基板（貼り合わせ基板）の電位がフローティング状態であるため、第２基板の電位が不安定となる可能性がある。このため、第１基板と第２基板との間に生成される寄生容量がばらつき、当該寄生容量の変化がノイズとなる可能性がある。 However, in the physical quantity sensor, a parasitic capacitance is generated between the first substrate and the second substrate, but the potential of the second substrate is not stable because the potential of the second substrate (bonded substrate) is in a floating state. It may become stable. For this reason, the parasitic capacitance generated between the first substrate and the second substrate varies, and the change in the parasitic capacitance may become noise.
　この問題を解決するため、第２基板を構成する貼り合わせ基板にアルミニウム等で構成されるコンタクト部を形成し、当該コンタクト部を介して貼り合わせ基板と外部回路とを接続して当該貼り合わせ基板の電位を一定に維持することが考えられる。つまり、第１基板と第２基板との間に生成される寄生容量を一定にすることが考えられる。この場合、貼り合わせ基板とコンタクト部とのコンタクト抵抗が高いと貼り合わせ基板に十分な電荷を印加し難くなるため、コンタクト抵抗を小さくすることが望まれる。 In order to solve this problem, a contact portion made of aluminum or the like is formed on a bonded substrate that constitutes the second substrate, and the bonded substrate and an external circuit are connected via the contact portion. It is conceivable to maintain a constant potential. That is, it is conceivable to make the parasitic capacitance generated between the first substrate and the second substrate constant. In this case, if the contact resistance between the bonded substrate and the contact portion is high, it is difficult to apply a sufficient charge to the bonded substrate, so it is desirable to reduce the contact resistance.
　したがって、単純には、貼り合わせ基板に高濃度層を形成し、コンタクト部を当該高濃度層と接続することでコンタクト抵抗を小さくすることが考えられる。 Therefore, simply, it is conceivable to reduce the contact resistance by forming a high concentration layer on the bonded substrate and connecting the contact portion to the high concentration layer.
　しかしながら、このように貼り合わせ基板に高濃度層を形成する構造では、高濃度層を形成するための工程が必要となり、製造工程が増加する。 However, in such a structure in which the high concentration layer is formed on the bonded substrate, a process for forming the high concentration layer is required, and the number of manufacturing steps increases.
　本開示は、製造工程を増加することなく、貼り合わせ基板とコンタクト部とのコンタクト抵抗を低減できる物理量センサを提供することを目的とする。 The present disclosure aims to provide a physical quantity sensor that can reduce the contact resistance between the bonded substrate and the contact portion without increasing the number of manufacturing steps.
　本開示のある態様にかかる物理量センサは、一面を有する第１基板と、一面を有し、当該一面が第１基板の一面と対向する状態で第１基板と接合される第２基板と、第１、第２基板の間に形成された気密室に配置され、物理量に応じたセンサ信号を出力するセンシング部を備える。 A physical quantity sensor according to an aspect of the present disclosure includes a first substrate having one surface, a second substrate having one surface, the second substrate being bonded to the first substrate in a state of facing the one surface of the first substrate, 1. A sensing unit is provided in an airtight chamber formed between the first and second substrates and outputs a sensor signal corresponding to a physical quantity.
　第２基板は、抵抗率が０．０１～０．２［Ω・ｃｍ］であるＰ型のシリコン基板で構成され、金属材料を用いて構成されたコンタクト部と接続されることで所定の電位に維持される貼り合わせ基板を有している）。 The second substrate is formed of a P-type silicon substrate having a resistivity of 0.01 to 0.2 [Ω · cm], and is connected to a contact portion formed using a metal material to have a predetermined potential. Having a bonded substrate).
　これによれば、製造工程を増加することなく、コンタクト抵抗の低減を図ることができる。 According to this, it is possible to reduce the contact resistance without increasing the manufacturing process.
　例えば、第１基板は、支持基板と、絶縁膜と、半導体層とが順に積層されたＳＯＩ（Silicon on Insulator）基板とされ、半導体層のうち絶縁膜と反対側の面が第１基板の一面とされているものとできる。 For example, the first substrate is an SOI (Silicon-on-Insulator) substrate in which a support substrate, an insulating film, and a semiconductor layer are sequentially stacked, and the surface of the semiconductor layer opposite to the insulating film is one surface of the first substrate. It can be said that.
　この場合、センシング部は、少なくとも一部が半導体層に形成されると共に当該一部に周期的な電圧の搬送波が入力されるようになっており、支持基板は、電位がフローティング状態とされ、抵抗率が０．０１～２０［Ω・ｃｍ］であるシリコン基板で構成されているものとできる。 In this case, at least a part of the sensing unit is formed in the semiconductor layer, and a periodic voltage carrier wave is input to the part. It can be composed of a silicon substrate having a rate of 0.01 to 20 [Ω · cm].
　これによれば、半導体層に搬送波が入力される場合であっても、支持基板の電位が部分毎にばらつくことを抑制でき、検出精度が低下することを抑制できる。 According to this, even when a carrier wave is input to the semiconductor layer, it is possible to suppress the potential of the support substrate from varying from part to part, and it is possible to suppress a decrease in detection accuracy.
　また、支持基板は、抵抗率が０．０１～０．２［Ω・ｃｍ］であるＰ型のシリコン基板で構成され、金属材料を用いて構成されたコンタクト部を介して外部回路と接続されることで所定の電位に維持されているものとできる。 The support substrate is made of a P-type silicon substrate having a resistivity of 0.01 to 0.2 [Ω · cm], and is connected to an external circuit through a contact portion made of a metal material. Thus, it can be maintained at a predetermined potential.
　これによれば、支持基板の電位が維持されるため、検出精度が低下することを抑制できる。 According to this, since the potential of the support substrate is maintained, it is possible to suppress a decrease in detection accuracy.
　半導体層は、抵抗率が０．０１～０．０３［Ω・ｃｍ］であるＰ型のシリコン基板で構成されているものとできる。また、半導体層は、抵抗率が０．０１～０．２［Ω・ｃｍ］であるＮ型のシリコン基板で構成されているものとできる。 The semiconductor layer can be composed of a P-type silicon substrate having a resistivity of 0.01 to 0.03 [Ω · cm]. Further, the semiconductor layer can be formed of an N-type silicon substrate having a resistivity of 0.01 to 0.2 [Ω · cm].
　これによれば、面抵抗（空乏層抵抗）が１．０Ω・ｃｍ２以下となり、検出精度が低下することを抑制できる。 According to this, the sheet resistance (depletion layer resistance) is 1.0 Ω · cm 2 or less, and it is possible to suppress a decrease in detection accuracy.
　本開示についての上記目的およびその他の目的、特徴や利点は、添付の図面を参照しながら下記の詳細な記述により、より明確になる。その図面は、
本開示の第１実施形態における加速度センサの断面図である。 図１に示す第１基板における第２基板側の平面図である。 図１に示す第２基板における第１基板側の平面図である。 Ｐ型のシリコン基板の抵抗率とコンタクト抵抗との関係を示す図である。 センシング部とＣ－Ｖ変換回路の回路構成を示す図である。 支持基板の抵抗率と、支持基板のうち、アンカー部と対向する部分の電位と第２部位におけるトーション梁から最も離れている部分と対向する部分の電位の位相差との関係を示す図である。 半導体層の抵抗率と空乏層抵抗との関係を示す図である。 第１基板に対する製造工程を示す断面図である。 図８Ａに続く製造工程を示す断面図である。 図８Ｂに続く製造工程を示す断面図である。 図８Ｃに続く製造工程を示す断面図である。 図８Ｄに続く製造工程を示す断面図である。 図８Ｅに続く製造工程を示す断面図である。 貼り合わせ基板に対する製造工程を示す断面図である。 図９Ａに続く製造工程を示す断面図である。 図１に示す加速度センサの製造工程を示す断面図である。 図１０Ａに続く製造工程を示す断面図である。 図１０Ｂに続く製造工程を示す断面図である。 図１０Ｃに続く製造工程を示す断面図である。 The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description with reference to the accompanying drawings. The drawing
It is sectional drawing of the acceleration sensor in 1st Embodiment of this indication. It is a top view by the side of the 2nd board | substrate in the 1st board | substrate shown in FIG. It is a top view by the side of the 1st substrate in the 2nd substrate shown in FIG. It is a figure which shows the relationship between the resistivity of a P-type silicon substrate, and contact resistance. It is a figure which shows the circuit structure of a sensing part and a CV conversion circuit. It is a figure which shows the relationship between the resistivity of a support substrate, and the phase difference of the electric potential of the part which opposes an anchor part among the support boards, and the electric potential of the part which opposes the part most distant from the torsion beam in 2nd site | part. . It is a figure which shows the relationship between the resistivity of a semiconductor layer, and depletion layer resistance. It is sectional drawing which shows the manufacturing process with respect to a 1st board | substrate. It is sectional drawing which shows the manufacturing process following FIG. 8A. It is sectional drawing which shows the manufacturing process following FIG. 8B. It is sectional drawing which shows the manufacturing process following FIG. 8C. It is sectional drawing which shows the manufacturing process following FIG. 8D. It is sectional drawing which shows the manufacturing process following FIG. 8E. It is sectional drawing which shows the manufacturing process with respect to a bonded substrate board. It is sectional drawing which shows the manufacturing process following FIG. 9A. It is sectional drawing which shows the manufacturing process of the acceleration sensor shown in FIG. It is sectional drawing which shows the manufacturing process following FIG. 10A. It is sectional drawing which shows the manufacturing process following FIG. 10B. FIG. 10C is a cross-sectional view showing a manufacturing step following FIG. 10C.
　以下、本開示の実施形態について図に基づいて説明する。なお、以下の各実施形態相互において、互いに同一もしくは均等である部分には、同一符号を付して説明を行う。 Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be described with the same reference numerals.
　（第１実施形態）
　本開示の第１実施形態について図面を参照しつつ説明する。なお、本実施形態では、加速度を検出する加速度センサに本開示の物理量センサを適用した例を説明する。 (First embodiment)
A first embodiment of the present disclosure will be described with reference to the drawings. In the present embodiment, an example in which the physical quantity sensor of the present disclosure is applied to an acceleration sensor that detects acceleration will be described.
　図１に示されるように、加速度センサは、第１基板１０と第２基板４０とが積層されて構成されている。なお、図１は、図２および図３中のI－I断面に相当している。 As shown in FIG. 1, the acceleration sensor is configured by laminating a first substrate 10 and a second substrate 40. 1 corresponds to the II cross section in FIGS. 2 and 3. FIG.
　第１基板１０は、本実施形態では、支持基板１１上に絶縁膜１２を介して半導体層１３が配置されたＳＯＩ（Silicon on Insulator）基板とされており、一面１０ａが半導体層１３のうち絶縁膜１２側と反対側の表面で構成されている。なお、支持基板１１および半導体層１３はシリコン基板で構成され、絶縁膜１２はＳｉＯ２やＳｉＮ等で構成される。 In the present embodiment, the first substrate 10 is an SOI (Silicon on Insulator) substrate in which a semiconductor layer 13 is disposed on a support substrate 11 via an insulating film 12, and one surface 10 a is insulated from the semiconductor layer 13. It is comprised by the surface on the opposite side to the film | membrane 12 side. The support substrate 11 and the semiconductor layer 13 are composed of a silicon substrate, and the insulating film 12 is composed of SiO 2 , SiN, or the like.
　そして、半導体層１３には、図１および図２に示されるように、マイクロマシン加工が施されて溝部１４が形成され、溝部１４によって可動部２０と周辺部３０とが区画形成されている。 1 and 2, the semiconductor layer 13 is subjected to micromachining to form a groove portion 14, and the movable portion 20 and the peripheral portion 30 are partitioned by the groove portion 14.
　また、支持基板１１および絶縁膜１２には、可動部２０（後述する枠部２２）が支持基板１１および絶縁膜１２と接触することを防止するために、可動部２０と対向する部分に窪み部１５が形成されている。 Further, in order to prevent the movable portion 20 (frame portion 22, which will be described later) from coming into contact with the support substrate 11 and the insulating film 12, the support substrate 11 and the insulating film 12 are recessed in a portion facing the movable portion 20. 15 is formed.
　可動部２０は、平面矩形状の開口部２１が形成された矩形枠状の枠部２２と、開口部２１の対向辺部を連結するように備えられたトーション梁２３とを有している。そして、可動部２０は、トーション梁２３が絶縁膜１２に支持されたアンカー部２４と連結されることにより、支持基板１１に支持されている。 The movable portion 20 includes a rectangular frame-shaped frame portion 22 in which a planar rectangular opening portion 21 is formed, and a torsion beam 23 provided so as to connect opposite sides of the opening portion 21. The movable portion 20 is supported by the support substrate 11 by connecting the torsion beam 23 to the anchor portion 24 supported by the insulating film 12.
　ここで、図１～図３中のｘ軸、ｙ軸、ｚ軸の各方向について説明する。図１～図３中では、ｘ軸方向を図１中紙面左右方向とし、ｙ軸方向を第１基板１０の面内においてｘ軸と直交する方向とし、ｚ軸方向を第１基板１０の面方向に対する法線方向としている。 Here, the respective directions of the x-axis, y-axis, and z-axis in FIGS. 1 to 3 will be described. 1 to 3, the x-axis direction is the left-right direction in FIG. 1, the y-axis direction is the direction perpendicular to the x-axis in the plane of the first substrate 10, and the z-axis direction is the surface of the first substrate 10. The direction is normal to the direction.
　トーション梁２３は、ｚ軸方向の加速度が印加されたとき、可動部２０の回転中心となる回転軸となる部材であり、本実施形態では開口部２１を２分割するように備えられている。 The torsion beam 23 is a member that becomes a rotation axis that becomes the rotation center of the movable portion 20 when an acceleration in the z-axis direction is applied, and is provided so as to divide the opening 21 into two in this embodiment.
　枠部２２は、ｚ軸方向の加速度が印加されたとき、トーション梁２３を回転軸として回転できるように、トーション梁２３を基準として非対称な形状とされている。本実施形態では、枠部２２は、第１部位２２ａにおけるトーション梁２３から最も離れている部分の端部までのｘ軸方向の長さが、第２部位２２ｂにおけるトーション梁２３から最も離れている部分の端部までのｘ軸方向の長さより短くされている。つまり、本実施形態の枠部２２は、第１部位２２ａの質量が第２部位２２ｂの質量より小さくされている。 The frame portion 22 has an asymmetric shape with respect to the torsion beam 23 so that it can rotate around the torsion beam 23 when an acceleration in the z-axis direction is applied. In the present embodiment, the length of the frame portion 22 in the x-axis direction to the end of the portion farthest from the torsion beam 23 in the first portion 22a is farthest from the torsion beam 23 in the second portion 22b. The length to the end of the part is shorter than the length in the x-axis direction. That is, in the frame portion 22 of the present embodiment, the mass of the first part 22a is smaller than the mass of the second part 22b.
　また、第１基板１０の一面１０ａ（半導体層１３の表面）には、パッド部２５、３１および枠状の封止部３２が形成されている。具体的には、パッド部２５はアンカー部２４に形成されて当該アンカー部２４（可動部２０）と接続され、パッド部３１は周辺部３０に形成されて当該周辺部３０と接続され、封止部３２は、可動部２０（溝部１４）を囲むように周辺部３０に形成されている。 Further, pad portions 25 and 31 and a frame-shaped sealing portion 32 are formed on one surface 10a of the first substrate 10 (the surface of the semiconductor layer 13). Specifically, the pad portion 25 is formed on the anchor portion 24 and connected to the anchor portion 24 (movable portion 20), and the pad portion 31 is formed on the peripheral portion 30 and connected to the peripheral portion 30 for sealing. The part 32 is formed in the peripheral part 30 so as to surround the movable part 20 (groove part 14).
　なお、パッド部３１は、周辺部３０のうち封止部３２で囲まれる領域内に配置されており、パッド部２５、３１および封止部３２は、本実施形態では、アルミニウム等で構成されている。 In addition, the pad part 31 is arrange | positioned in the area | region enclosed by the sealing part 32 among the peripheral parts 30, and the pad parts 25 and 31 and the sealing part 32 are comprised by aluminum etc. in this embodiment. Yes.
　さらに、第１基板１０の一面１０ａには、周辺部３０における外縁部に封止部３２を囲む枠状のスペーサ３３が形成されている。このスペーサ３３は、第１基板１０と第２基板４０との間隔を維持するものであり、酸化膜等の絶縁膜で構成されている。特に限定されるものではないが、外部環境から印加されるナトリウムイオン等を捕獲するため、スペーサ３３を構成する酸化膜中にイオントラップとなるリン等を添加してもよい。 Furthermore, a frame-like spacer 33 surrounding the sealing portion 32 is formed on the outer edge portion of the peripheral portion 30 on the one surface 10 a of the first substrate 10. The spacer 33 maintains the distance between the first substrate 10 and the second substrate 40, and is composed of an insulating film such as an oxide film. Although not particularly limited, phosphorus or the like serving as an ion trap may be added to the oxide film constituting the spacer 33 in order to capture sodium ions or the like applied from the external environment.
　第２基板４０は、図１および図３に示されるように、貼り合わせ基板４１と、貼り合わせ基板４１のうち第１基板１０と対向する一面および側面に形成された絶縁膜４２と、貼り合わせ基板４１のうち第１基板１０側と反対側の他面に形成された絶縁膜４３とを有している。そして、絶縁膜４２のうち第１基板１０と対向する面にて第２基板４０の一面４０ａが構成されている。 As shown in FIGS. 1 and 3, the second substrate 40 is bonded to the bonded substrate 41, the insulating film 42 formed on one side and the side of the bonded substrate 41 facing the first substrate 10, and the bonded substrate 41. The substrate 41 has an insulating film 43 formed on the other surface opposite to the first substrate 10 side. Then, one surface 40 a of the second substrate 40 is formed on the surface of the insulating film 42 facing the first substrate 10.
　なお、貼り合わせ基板４１はシリコン基板で構成され、絶縁膜４２はＳｉＯ２やＳｉＮ等で構成され、絶縁膜４３はＴＥＯＳ等で構成される。 The bonded substrate 41 is made of a silicon substrate, the insulating film 42 is made of SiO 2 , SiN or the like, and the insulating film 43 is made of TEOS or the like.
　そして、第２基板４０の一面４０ａには、第１、第２配線部５１、５２が形成されている。具体的には、第１配線部５１は、第１部位２２ａと対向する部分に形成されて当該第１部位２２ａとの間に所定の容量を構成する第１固定電極５１ａと、第１固定電極５１ａから引き出された第１引き出し配線５１ｂとを有している。また、第２配線部５２は、第２部位２２ｂと対向する部分に形成されて当該第２部位２２ｂとの間に所定の容量を構成する第２固定電極５２ａと、第２固定電極５２ａから引き出された第２引き出し配線５２ｂとを有している。これにより、可動部２０と第１、第２固定電極５１ａ、５２ａとによって加速度に応じたセンサ信号を出力するセンシング部６０が構成されている。 The first and second wiring portions 51 and 52 are formed on the one surface 40a of the second substrate 40. Specifically, the first wiring part 51 is formed in a portion facing the first part 22a, and includes a first fixed electrode 51a and a first fixed electrode that form a predetermined capacity with the first part 22a. And a first lead wiring 51b led out from 51a. Further, the second wiring portion 52 is formed in a portion facing the second portion 22b, and is pulled out from the second fixed electrode 52a and the second fixed electrode 52a that constitutes a predetermined capacity between the second portion 22b. Second lead wiring 52b. Thereby, the sensing part 60 which outputs the sensor signal according to acceleration by the movable part 20 and the 1st, 2nd fixed electrodes 51a and 52a is comprised.
　なお、第１、第２固定電極５１ａ、５２ａは、同じ平面形状とされ、加速度が印加されていない状態において、第１、第２部位２２ａ、２２ｂとの間に等しい容量を構成している。また、第１、第２引き出し配線５１ｂ、５２ｂは、それぞれ第１、第２固定電極５１ａ、５２ａと反対側の端部の形状が円状とされている。そして、枠部２２のうち第１、第２固定電極５１ａ、５２ａと対向する部分が可動電極となる。 The first and second fixed electrodes 51a and 52a have the same planar shape, and form an equal capacity between the first and second portions 22a and 22b when no acceleration is applied. The first and second lead wires 51b and 52b have circular shapes at the ends opposite to the first and second fixed electrodes 51a and 52a, respectively. And the part which opposes the 1st, 2nd fixed electrodes 51a and 52a among the frame parts 22 becomes a movable electrode.
　また、第２基板４０の一面４０ａには、パッド部２５、パッド部３１と対向する部分にパッド部５３、５４が形成されていると共に、封止部３２と対向する部分に当該封止部３２と同じ形状の封止部５５が形成されている。なお、パッド部５３、５４および封止部５５は、アルミニウム等で構成されている。 Further, on one surface 40 a of the second substrate 40, pad portions 53 and 54 are formed at portions facing the pad portion 25 and pad portion 31, and the sealing portion 32 is disposed at a portion facing the sealing portion 32. The sealing part 55 having the same shape as that is formed. The pad parts 53 and 54 and the sealing part 55 are made of aluminum or the like.
　さらに、第２基板４０には、第２基板４０を厚さ方向（第１、第２基板１０、４０の積層方向）に貫通する４つの貫通電極部７０が形成されている。各貫通電極部７０は、絶縁膜４３、貼り合わせ基板４１、絶縁膜４２を貫通する貫通孔７０ａに絶縁膜７０ｂを介して貫通電極７０ｃが形成され、絶縁膜４３上に貫通電極７０ｃおよび外部回路と電気的に接続されるパッド部７０ｄが形成された構成とされている。 Furthermore, four through electrode portions 70 are formed in the second substrate 40 so as to penetrate the second substrate 40 in the thickness direction (the stacking direction of the first and second substrates 10 and 40). In each through electrode portion 70, a through electrode 70 c is formed in a through hole 70 a that penetrates the insulating film 43, the bonded substrate 41, and the insulating film 42 via an insulating film 70 b, and the through electrode 70 c and the external circuit are formed on the insulating film 43. The pad portion 70d that is electrically connected to the pad is formed.
　そして、各貫通電極部７０は、それぞれ第１、第２配線部５１、５２、パッド部５３、５４と電気的に接続されている。つまり、各貫通電極部７０における貫通孔７０ａは、それぞれ第１、第２配線部５１、５２、パッド部５３、５４に達するように形成されており、各貫通電極７０ｃは、それぞれ第１、第２配線部５１、５２、パッド部５３、５４と電気的に接続されるように貫通孔７０ａに配置されている。 The through electrode portions 70 are electrically connected to the first and second wiring portions 51 and 52 and the pad portions 53 and 54, respectively. That is, the through hole 70a in each through electrode part 70 is formed to reach the first and second wiring parts 51 and 52 and the pad parts 53 and 54, respectively. The two wiring portions 51 and 52 and the pad portions 53 and 54 are disposed in the through hole 70a so as to be electrically connected.
　これにより、可動部２０がパッド部２５、５３を介して貫通電極７０ｃと接続され、第１、第２固定電極５１ａ、５２ａが貫通電極７０ｃと接続される。また、周辺部３０がパッド部３１、５４を介して貫通電極７０ｃと接続される。 Thereby, the movable portion 20 is connected to the through electrode 70c via the pad portions 25 and 53, and the first and second fixed electrodes 51a and 52a are connected to the through electrode 70c. In addition, the peripheral portion 30 is connected to the through electrode 70 c via the pad portions 31 and 54.
　なお、第１、第２配線部５１、５２と電気的に接続される貫通電極部７０の貫通孔７０ａは、第１、第２配線部５１、５２における第１、第２引き出し配線５１ｂ、５２ｂのうち第１、第２固定電極５１ａ、５２ａ側と反対側の端部に達するように形成されている。また、本実施形態では、貫通孔７０ａは円筒状とされ、絶縁膜７０ｂはＴＥＯＳ等の絶縁材料で構成され、貫通電極７０ｃはアルミニウム等で構成されている。 Note that the through hole 70a of the through electrode portion 70 that is electrically connected to the first and second wiring portions 51 and 52 corresponds to the first and second lead wirings 51b and 52b in the first and second wiring portions 51 and 52, respectively. Of these, the first and second fixed electrodes 51a and 52a are formed so as to reach the end opposite to the side. In the present embodiment, the through hole 70a is cylindrical, the insulating film 70b is made of an insulating material such as TEOS, and the through electrode 70c is made of aluminum or the like.
　さらに、絶縁膜４３には、貼り合わせ基板４１の所定箇所を開口させるコンタクトホール４３ａが形成されている。そして、コンタクトホール４３ａには、貼り合わせ基板４１と外部回路とを接続して当該貼り合わせ基板４１を所定の電位に維持するためのコンタクト部８０が埋め込まれている。このコンタクト部８０は、貫通電極７０ｃおよびパッド部７０ｄと同様に、アルミニウムで構成されている。 Furthermore, a contact hole 43 a that opens a predetermined portion of the bonded substrate 41 is formed in the insulating film 43. In the contact hole 43a, a contact portion 80 for connecting the bonded substrate 41 and an external circuit and maintaining the bonded substrate 41 at a predetermined potential is embedded. The contact portion 80 is made of aluminum, like the through electrode 70c and the pad portion 70d.
　以上が本実施形態における第２基板４０の構成である。そして、上記第１、第２基板１０、４０が接合されて一体化されることにより、加速度センサが構成されている。具体的には、第１、第２基板１０、４０は、パッド部２５とパッド部５３、パッド部３１とパッド部５４、封止部３２と封止部５５とが金属接合されることにより一体化されている。そして、第１、第２基板１０、４０の間の空間によって気密室９０が構成され、枠部２２および第１、第２固定電極５１ａ、５２ａ（センシング部６０）が気密室９０に封止されている。 The above is the configuration of the second substrate 40 in the present embodiment. And the said 1st, 2nd board | substrates 10 and 40 are joined and integrated, and the acceleration sensor is comprised. Specifically, the first and second substrates 10 and 40 are integrated by metal bonding of the pad portion 25 and the pad portion 53, the pad portion 31 and the pad portion 54, and the sealing portion 32 and the sealing portion 55. It has become. The space between the first and second substrates 10 and 40 forms an airtight chamber 90, and the frame portion 22 and the first and second fixed electrodes 51 a and 52 a (sensing unit 60) are sealed in the airtight chamber 90. ing.
　なお、第１基板１０と第２基板４０との間隔は、スペーサ３３によって規定されている。また、気密室９０は、例えば、真空とされている。 Note that the distance between the first substrate 10 and the second substrate 40 is defined by the spacer 33. The hermetic chamber 90 is, for example, a vacuum.
　以上が本実施形態における加速度センサの基本的な構成である。次に、本実施形態の特徴点である支持基板１１、半導体層１３、貼り合わせ基板４１の構成について具体的に説明する。 The above is the basic configuration of the acceleration sensor in the present embodiment. Next, the configuration of the support substrate 11, the semiconductor layer 13, and the bonded substrate 41 that are characteristic points of the present embodiment will be specifically described.
　図４に示されるように、シリコンとアルミニウムとのコンタクト抵抗は、シリコンの抵抗率が０．２Ω・ｃｍ以下である場合にコンタクト抵抗がほぼゼロとなる。そして、シリコンの抵抗率が０．２Ω・ｃｍより大きい場合は、シリコンの抵抗率が大きくなるにつれてコンタクト抵抗も次第に大きくなる。つまり、シリコンとアルミニウムは、シリコンの抵抗率が０．２Ω・ｃｍ以下のときにオーミック接触となり、シリコンの抵抗率が０．２Ω・ｃｍより大きいときにショットキー接触となる。 As shown in FIG. 4, the contact resistance between silicon and aluminum becomes almost zero when the resistivity of silicon is 0.2 Ω · cm or less. When the resistivity of silicon is greater than 0.2 Ω · cm, the contact resistance gradually increases as the resistivity of silicon increases. That is, silicon and aluminum are in ohmic contact when the resistivity of silicon is 0.2 Ω · cm or less, and are in Schottky contact when the resistivity of silicon is greater than 0.2 Ω · cm.
　なお、図４は、Ｐ型のシリコンとアルミニウムとのコンタクト抵抗との関係を示す図であるが、アルミニウム以外の金等の金属材料を用いた場合でもシリコンの抵抗率とコンタクト抵抗との関係は同じである。 FIG. 4 is a diagram showing the relationship between the contact resistance between P-type silicon and aluminum, but the relationship between the resistivity of silicon and the contact resistance even when a metal material such as gold other than aluminum is used. The same.
　このため、本実施形態では、貼り合わせ基板４１は、Ｐ型であり、抵抗率が０．０１～０．２Ω・ｃｍとされたシリコン基板で構成されている。つまり、貼り合わせ基板４１は、コンタクト部８０とのコンタクト抵抗がほぼゼロとなる抵抗率とされたシリコン基板で構成されている。 For this reason, in this embodiment, the bonded substrate 41 is a P-type, and is formed of a silicon substrate having a resistivity of 0.01 to 0.2 Ω · cm. In other words, the bonded substrate 41 is formed of a silicon substrate having a resistivity at which the contact resistance with the contact portion 80 is substantially zero.
　なお、抵抗率の下限である０．０１Ω・ｃｍは、実際にシリコン基板を形成する際の最低限界抵抗率であり、以下で説明する支持基板１１および半導体層１３においても同様である。また、貼り合わせ基板４１をＮ型のシリコン基板で構成しようとした場合、アルミニウムとの間の仕事関数の関係上、コンタクト抵抗をほぼゼロにしようとするとＳｉを形成する際の最低限界抵抗率である０．０１Ω・ｃｍより低い値が必要となる。このため、貼り合わせ基板４１をＮ型のシリコン基板で構成する場合には、コンタクト部８０と接触する部分に高濃度層を形成する必要があり、製造工程が増加する。 Note that 0.01 Ω · cm, which is the lower limit of the resistivity, is the lowest limit resistivity when the silicon substrate is actually formed, and the same applies to the support substrate 11 and the semiconductor layer 13 described below. In addition, when the bonded substrate 41 is made of an N-type silicon substrate, if the contact resistance is made to be almost zero due to the work function with aluminum, the minimum limit resistivity when forming Si is obtained. A value lower than a certain 0.01 Ω · cm is required. For this reason, when the bonded substrate 41 is composed of an N-type silicon substrate, it is necessary to form a high-concentration layer in a portion in contact with the contact portion 80, which increases the manufacturing process.
　また、上記のような加速度センサは、図５に示されるように、演算増幅器１０１、第１、第２コンデンサ１０２ａ、１０２ｂ、第１、第２スイッチ１０３ａ、１０３ｂによって構成される全差動型のＣ－Ｖ変換回路１１０と接続されて用いられることがある。 Further, as shown in FIG. 5, the acceleration sensor as described above is a fully differential type composed of an operational amplifier 101, first and second capacitors 102a and 102b, and first and second switches 103a and 103b. It may be used by being connected to the CV conversion circuit 110.
　具体的には、第１コンデンサ１０２ａおよび第１スイッチ１０３ａは、演算増幅器１０１の反転入力端子と＋側の出力端子との間に並列的に配置される。また、第２コンデンサ１０２ｂおよび第２スイッチ１０３ｂは、演算増幅器１０１の非反転入力端子と－側の出力端子との間に並列的に配置される。 Specifically, the first capacitor 102a and the first switch 103a are arranged in parallel between the inverting input terminal of the operational amplifier 101 and the + side output terminal. The second capacitor 102b and the second switch 103b are disposed in parallel between the non-inverting input terminal of the operational amplifier 101 and the negative output terminal.
　そして、演算増幅器１０１は、反転入力端子が第１固定電極５１ａと電気的に接続され、非反転入力端子が第２固定電極５２ａと電気的に接続される。また、可動部２０には、電圧Ｖｃｃと０Ｖとの間で振幅し、所定の周波数を有するパルス状の周期的な搬送波が入力される。 The operational amplifier 101 has an inverting input terminal electrically connected to the first fixed electrode 51a and a non-inverting input terminal electrically connected to the second fixed electrode 52a. In addition, a pulse-shaped periodic carrier wave having an amplitude between a voltage Vcc and 0 V and having a predetermined frequency is input to the movable unit 20.
　この状態で、ｚ軸方向の加速度が印加されると、枠部２２がトーション梁２３を回転軸として加速度に応じた回転をする。そして、第１部位２２ａと第１固定電極５１ａとの間の容量と、第２部位２２ｂと第２固定電極５２ａとの間の容量とが加速度に応じて変化するため、Ｃ－Ｖ変換回路１１０から容量に応じたセンサ信号Ｖｏｕｔ（Ｖ１－Ｖ２）が出力される。 In this state, when acceleration in the z-axis direction is applied, the frame portion 22 rotates according to the acceleration with the torsion beam 23 as the rotation axis. Since the capacitance between the first portion 22a and the first fixed electrode 51a and the capacitance between the second portion 22b and the second fixed electrode 52a change according to the acceleration, the CV conversion circuit 110 Output a sensor signal Vout (V1-V2) corresponding to the capacitance.
　この場合、支持基板１１の電位はフローティング状態とされているため、支持基板１１の電位はアンカー部２４（枠部２２）に入力される搬送波に依存して変位する。このとき、支持基板１１は抵抗率を有しているため、抵抗率が大きいと、支持基板１１のうち絶縁膜１２を介してアンカー部２４と対向する部分の電位と、枠部２２の外縁部と対向する部分の電位との間で位相差が形成される。つまり、支持基板１１のうち絶縁膜１２を介してアンカー部２４と対向する部分と当該アンカー部２４との間に生成される静電気力（寄生容量）と、支持基板１１のうち枠部２２の外縁部と対向する部分と当該外縁部との間に生成される静電気力（寄生容量）とが異なる。このため、検出時において、静電気力の違いが出力誤差となり、検出精度が低下する。 In this case, since the potential of the support substrate 11 is in a floating state, the potential of the support substrate 11 is displaced depending on the carrier wave input to the anchor portion 24 (frame portion 22). At this time, since the support substrate 11 has a resistivity, if the resistivity is large, the potential of the portion of the support substrate 11 that faces the anchor portion 24 via the insulating film 12 and the outer edge portion of the frame portion 22 And a potential of the portion facing each other. That is, the electrostatic force (parasitic capacitance) generated between a portion of the support substrate 11 that faces the anchor portion 24 via the insulating film 12 and the anchor portion 24, and the outer edge of the frame portion 22 of the support substrate 11. The electrostatic force (parasitic capacitance) generated between the part facing the part and the outer edge part is different. For this reason, at the time of detection, the difference in electrostatic force becomes an output error, and the detection accuracy decreases.
　したがって、支持基板１１は、図６に示されるように、抵抗率が０．０１～２０Ω・ｃｍであるシリコン基板で構成されている。 Therefore, as shown in FIG. 6, the support substrate 11 is composed of a silicon substrate having a resistivity of 0.01 to 20 Ω · cm.
　なお、図６は、支持基板１１の厚さが１２０μｍ、幅が４００μｍ、長さが２ｍｍのシリコン基板を用いたシミュレーション結果である。また、位相差は、Ｐ型のシリコン基板およびＮ型のシリコン基板で同じであるため、支持基板１１はＰ型のシリコン基板およびＮ型のシリコン基板のどちらで構成してもよい。 FIG. 6 shows a simulation result using a silicon substrate having a thickness of 120 μm, a width of 400 μm, and a length of 2 mm. Further, since the phase difference is the same between the P-type silicon substrate and the N-type silicon substrate, the support substrate 11 may be configured by either the P-type silicon substrate or the N-type silicon substrate.
　さらに、半導体層１３（枠部２２）は、加速度が印加されたときの容量変化に伴う発生電荷が検出されるが、電極界面での位相ずれを無視できる程度に小さくするため、面抵抗（空乏層抵抗）が１．０Ω・ｃｍ２以下であることが好ましい。このため、図７に示されるように、半導体層１３は、０．０１～０．０３Ω・ｃｍであるＰ型のシリコン基板か、または、０．０１～０．２Ω・ｃｍであるＮ型のシリコン基板で構成されている。 Furthermore, although the semiconductor layer 13 (frame portion 22) detects charges generated due to capacitance changes when acceleration is applied, the surface resistance (depletion) is reduced so as to make the phase shift at the electrode interface negligible. The layer resistance is preferably 1.0 Ω · cm 2 or less. Therefore, as shown in FIG. 7, the semiconductor layer 13 is a P-type silicon substrate having a thickness of 0.01 to 0.03 Ω · cm or an N-type silicon substrate having a thickness of 0.01 to 0.2 Ω · cm. It is composed of a silicon substrate.
　次に、上記加速度センサの製造方法について図８Ａ～図８Ｆ、図９Ａ～図９Ｂ、及び図１０Ａ～図１０Ｄを参照して説明する。 Next, a method for manufacturing the acceleration sensor will be described with reference to FIGS. 8A to 8F, FIGS. 9A to 9B, and FIGS. 10A to 10D.
　まず、図８Ａに示されるように、支持基板１１を用意し、支持基板１１上にＣＶＤ（Chemical Vapor Deposition）法や熱酸化等によって絶縁膜１２を形成する。なお、支持基板１１は、上記のように、抵抗率が０．０１～２０Ω・ｃｍのＮ型のシリコン基板またはＰ型のシリコン基板で構成されている。 First, as shown in FIG. 8A, a support substrate 11 is prepared, and an insulating film 12 is formed on the support substrate 11 by a CVD (Chemical Vapor Deposition) method, thermal oxidation, or the like. As described above, the support substrate 11 is composed of an N-type silicon substrate or a P-type silicon substrate having a resistivity of 0.01 to 20 Ω · cm.
　次に、図８Ｂに示されるように、絶縁膜１２上にレジストや酸化膜等のマスク（図示せず）を形成してウェットエッチング等を行い、支持基板１１に窪み部１５を形成する。 Next, as shown in FIG. 8B, a mask (not shown) such as a resist or an oxide film is formed on the insulating film 12 and wet etching or the like is performed to form a recess 15 in the support substrate 11.
　続いて、図８Ｃに示されるように、絶縁膜１２と半導体層１３とを接合して第１基板１０を形成する。絶縁膜１２と半導体層１３との接合は、特に限定されるものではないが、例えば、次のように行うことができる。 Subsequently, as shown in FIG. 8C, the insulating film 12 and the semiconductor layer 13 are joined to form the first substrate 10. The bonding between the insulating film 12 and the semiconductor layer 13 is not particularly limited, but can be performed as follows, for example.
　まず、絶縁膜１２の接合面および半導体層１３の接合面にＮ２プラズマ、Ｏ２プラズマ、またはＡｒイオンビームを照射し、絶縁膜１２および半導体層１３の各接合面を活性化させる。そして、適宜形成されたアライメントマークを用いて赤外顕微鏡等によるアライメントを行い、室温～５５０℃で絶縁膜１２および半導体層１３をいわゆる直接接合により接合する。 First, the bonding surface of the insulating film 12 and the bonding surface of the semiconductor layer 13 are irradiated with N 2 plasma, O 2 plasma, or an Ar ion beam to activate the bonding surfaces of the insulating film 12 and the semiconductor layer 13. Then, alignment is performed with an infrared microscope or the like using an appropriately formed alignment mark, and the insulating film 12 and the semiconductor layer 13 are bonded by so-called direct bonding at room temperature to 550 ° C.
　なお、半導体層１３は、上記のように、抵抗率が０．０１～０．０３Ω・ｃｍであるＰ型のシリコン基板、または、抵抗率が０．０１～０．２Ω・ｃｍであるＮ型のシリコン基板で構成されている。 As described above, the semiconductor layer 13 is a P-type silicon substrate having a resistivity of 0.01 to 0.03 Ω · cm, or an N-type having a resistivity of 0.01 to 0.2 Ω · cm. It is composed of a silicon substrate.
　また、ここでは直接接合を例に挙げて説明したが、絶縁膜１２と半導体層１３とは、陽極接合や中間層接合、フージョン接合等の接合技術によって接合されてもよい。そして、接合後に、高温アニール等の接合品質を向上させる処理を行ってもよい。さらに、接合後に、半導体層１３を研削研磨によって所望の厚さに加工してもよい。 In addition, although direct bonding has been described as an example here, the insulating film 12 and the semiconductor layer 13 may be bonded by a bonding technique such as anodic bonding, intermediate layer bonding, or fusion bonding. And after joining, you may perform the process which improves joining quality, such as high temperature annealing. Further, after bonding, the semiconductor layer 13 may be processed to a desired thickness by grinding and polishing.
　次に、図８Ｄに示されるように、第１基板１０の一面１０ａにＣＶＤ法等によって絶縁膜を形成する。そして、レジストや酸化膜等のマスク（図示せず）を用いて反応性イオンエッチング等で当該絶縁膜をパターニングし、上記スペーサ３３を形成する。 Next, as shown in FIG. 8D, an insulating film is formed on one surface 10a of the first substrate 10 by a CVD method or the like. Then, the spacer 33 is formed by patterning the insulating film by reactive ion etching or the like using a mask (not shown) such as a resist or an oxide film.
　その後、図８Ｅに示されるように、第１基板１０の一面１０ａにＣＶＤ法等によって金属膜を形成する。そして、レジストや酸化膜等のマスク（図示せず）を用いて反応性イオンエッチング等で当該金属膜をパターニングすることにより、パッド部２５、３１および封止部３２を形成する。 Thereafter, as shown in FIG. 8E, a metal film is formed on one surface 10a of the first substrate 10 by a CVD method or the like. And the pad parts 25 and 31 and the sealing part 32 are formed by patterning the said metal film by reactive ion etching etc. using masks (not shown), such as a resist and an oxide film.
　次に、図８Ｆに示されるように、レジストや酸化膜等のマスク（図示せず）を用いて反応性イオンエッチング等で半導体層１３に溝部１４を形成する。これにより、可動部２０が形成された第１基板１０が用意される。 Next, as shown in FIG. 8F, a groove 14 is formed in the semiconductor layer 13 by reactive ion etching or the like using a mask (not shown) such as a resist or an oxide film. Thereby, the 1st board | substrate 10 with which the movable part 20 was formed is prepared.
　また、上記図８Ａ～図８Ｆとは別工程において、図９Ａに示されるように、貼り合わせ基板４１を用意し、熱酸化等によって貼り合わせ基板４１の全面に絶縁膜４２を形成する。なお、貼り合わせ基板４１は、上記のように、抵抗率が０．０１～０．０３Ω・ｃｍであるＰ型のシリコン基板で構成されている。 8A to 8F, a bonded substrate 41 is prepared as shown in FIG. 9A, and an insulating film 42 is formed on the entire surface of the bonded substrate 41 by thermal oxidation or the like. The bonded substrate 41 is composed of a P-type silicon substrate having a resistivity of 0.01 to 0.03 Ω · cm as described above.
　次に、図９Ｂに示されるように、絶縁膜４２のうち第１基板１０と対向する部分に金属膜を形成する。そして、レジストや酸化膜等のマスク（図示せず）を用いて反応性イオンエッチング等で当該金属膜をパターニングすることにより、第１、第２配線部５１、５２、パッド部５３、５４、封止部５５を形成する。 Next, as shown in FIG. 9B, a metal film is formed on a portion of the insulating film 42 facing the first substrate 10. Then, by patterning the metal film by reactive ion etching or the like using a mask (not shown) such as a resist or an oxide film, the first and second wiring parts 51 and 52, pad parts 53 and 54, sealing A stop 55 is formed.
　続いて、図１０Ａに示されるように、第１基板１０と第２基板４０とを接合する。具体的には、適宜形成されたアライメントマークを用いて赤外顕微鏡等によるアライメントを行い、第１基板１０のパッド部２５、３１、封止部３２と、第２基板４０のパッド部５３、５４、封止部５５とを３００～５００°で金属接合する。 Subsequently, as shown in FIG. 10A, the first substrate 10 and the second substrate 40 are bonded. Specifically, alignment is performed by an infrared microscope or the like using appropriately formed alignment marks, and the pad portions 25 and 31 of the first substrate 10, the sealing portion 32, and the pad portions 53 and 54 of the second substrate 40. Then, the sealing portion 55 is metal-bonded at 300 to 500 °.
　これにより、第１基板１０と第２基板４０との間の空間が封止部３２と封止部５５とにより封止されて気密室９０となり、枠部２２および第１、第２固定電極５１ａ、５２ａ（センシング部６０）が気密室９０に気密封止される。なお、第１基板１０と第２基板４０との間隔は、スペーサ３３によって規定される。 As a result, the space between the first substrate 10 and the second substrate 40 is sealed by the sealing portion 32 and the sealing portion 55 to form an airtight chamber 90, and the frame portion 22 and the first and second fixed electrodes 51a. , 52a (sensing unit 60) is hermetically sealed in the hermetic chamber 90. Note that the distance between the first substrate 10 and the second substrate 40 is defined by the spacer 33.
　次に、図１０Ｂに示されるように、絶縁膜４２および貼り合わせ基板４１を第１基板１０側と反対側から研削し、第１基板１０側と反対側の絶縁膜４２を除去すると共に貼り合わせ基板４１を薄くする。なお、この工程は、第１基板１０と第２基板４０とを接合する前に行ってもよい。 Next, as shown in FIG. 10B, the insulating film 42 and the bonded substrate 41 are ground from the side opposite to the first substrate 10 side, and the insulating film 42 on the side opposite to the first substrate 10 side is removed and bonded. The substrate 41 is thinned. This step may be performed before the first substrate 10 and the second substrate 40 are bonded.
　続いて、図１０Ｃに示されるように、パッド部５３、５４に対応する場所の貼り合わせ基板４１および絶縁膜４２を除去することにより、２つの貫通孔７０ａを形成する。また、図１０Ｃとは別断面において、第１、第２配線部５１、５２における第１、第２引き出し配線５１ｂ、５２ｂに対応する場所の貼り合わせ基板４１および絶縁膜４２を除去することにより、２つの貫通孔７０ａを形成する。そして、各貫通孔７０ａの壁面にＴＥＯＳ等の絶縁膜７０ｂを成膜する。このとき、貼り合わせ基板４１のうち第１基板１０側と反対側に形成された絶縁膜にて絶縁膜４３が構成される。つまり、絶縁膜４３と絶縁膜７０ｂとは同じ工程で形成される。その後、各貫通孔７０ａの底部に形成された絶縁膜７０ｂを除去し、各貫通孔７０ａ内において、第１、第２配線部５１、５２における第１、第２引き出し配線５１ｂ、５２ｂ、パッド部５３、５４を露出させる。 Subsequently, as shown in FIG. 10C, the two through holes 70 a are formed by removing the bonded substrate 41 and the insulating film 42 at locations corresponding to the pad portions 53 and 54. Further, in a cross section different from FIG. 10C, by removing the bonding substrate 41 and the insulating film 42 at locations corresponding to the first and second lead wirings 51b and 52b in the first and second wiring parts 51 and 52, Two through holes 70a are formed. Then, an insulating film 70b such as TEOS is formed on the wall surface of each through hole 70a. At this time, the insulating film 43 is composed of an insulating film formed on the side of the bonded substrate 41 opposite to the first substrate 10 side. That is, the insulating film 43 and the insulating film 70b are formed in the same process. Thereafter, the insulating film 70b formed at the bottom of each through hole 70a is removed, and the first and second lead lines 51b and 52b and the pad part in the first and second wiring parts 51 and 52 are formed in each through hole 70a. 53 and 54 are exposed.
　次に、図１０Ｄに示されるように、各貫通孔７０ａにスパッタ法や蒸着法等によって金属膜を配置して各貫通電極７０ｃを形成する。そして、各貫通電極７０ｃと第１、第２配線部５１、５２における第１、第２引き出し配線５１ｂ、５２ｂ、パッド部５３、５４とをそれぞれ電気的に接続する。その後、絶縁膜４３上の金属膜をパターニングしてパッド部７０ｄを形成することで貫通電極部７０を構成する。 Next, as shown in FIG. 10D, a metal film is disposed in each through hole 70a by a sputtering method, a vapor deposition method, or the like to form each through electrode 70c. Then, each through electrode 70c is electrically connected to the first and second lead wires 51b and 52b and the pad portions 53 and 54 in the first and second wiring portions 51 and 52, respectively. Thereafter, the through electrode portion 70 is formed by patterning the metal film on the insulating film 43 to form the pad portion 70d.
　また、絶縁膜４３にコンタクトホール４３ａを形成すると共にコンタクトホール４３ａに金属膜を埋め込んでコンタクト部８０を形成することにより、上記加速度センサが製造される。 Further, the acceleration sensor is manufactured by forming the contact hole 43a in the insulating film 43 and embedding the metal film in the contact hole 43a to form the contact portion 80.
　なお、上記では、１つの加速度センサの製造方法について説明したが、ウェハ状の第１、第２基板１０、４０を用意し、これらを接合した後にダイシングカットしてチップ単位に分割するようにしてもよい。 In addition, although the manufacturing method of one acceleration sensor was demonstrated above, the wafer-like 1st, 2nd board | substrates 10 and 40 are prepared, and after dicing and cutting these, it divides | segments into a chip unit. Also good.
　以上説明したように、貼り合わせ基板４１は、抵抗率が０．０１～０．０３Ω・ｃｍであるＰ型のシリコン基板で構成されている。このため、貼り合わせ基板４１に高濃度層を形成することなく、貼り合わせ基板４１とコンタクト部８０とのコンタクト抵抗をほぼゼロにすることができる（図４参照）。つまり、製造工程を増加することなく、コンタクト抵抗の低減を図ることができる。 As described above, the bonded substrate 41 is composed of a P-type silicon substrate having a resistivity of 0.01 to 0.03 Ω · cm. For this reason, the contact resistance between the bonded substrate 41 and the contact portion 80 can be made substantially zero without forming a high concentration layer on the bonded substrate 41 (see FIG. 4). That is, contact resistance can be reduced without increasing the number of manufacturing steps.
　また、支持基板１１は、抵抗率が０．０１～２０Ω・ｃｍであるシリコン基板で構成されている。このため、全差動型のＣ－Ｖ変換回路と接続され、可動部２０（半導体層１３）に搬送波が入力される場合であっても、支持基板１１の電位が部分毎にばらつくことを抑制でき、検出精度が低下することを抑制できる。 The support substrate 11 is made of a silicon substrate having a resistivity of 0.01 to 20 Ω · cm. Therefore, even when a carrier wave is input to the movable portion 20 (semiconductor layer 13) when connected to a fully differential CV conversion circuit, the potential of the support substrate 11 is prevented from varying from part to part. It can suppress and it can suppress that detection accuracy falls.
　さらに、半導体層１３は、抵抗率が０．０１～０．０３Ω・ｃｍであるＰ型のシリコン基板、または、抵抗率が０．０１～０．２Ω・ｃｍであるＮ型のシリコン基板で構成されている。このため、面抵抗（空乏層抵抗）が１．０Ω・ｃｍ２以下となり、検出精度が低下することを抑制できる。 Further, the semiconductor layer 13 is composed of a P-type silicon substrate having a resistivity of 0.01 to 0.03 Ω · cm or an N-type silicon substrate having a resistivity of 0.01 to 0.2 Ω · cm. Has been. For this reason, surface resistance (depletion layer resistance) becomes 1.0 Ω · cm 2 or less, and it is possible to suppress a decrease in detection accuracy.
　（変形例）
　本開示は上記した実施形態に限定されるものではなく、特許請求の範囲に記載した範囲内において適宜変更が可能である。 (Modification)
The present disclosure is not limited to the above-described embodiment, and can be appropriately changed within the scope described in the claims.
　例えば、上記第１実施形態では、ｚ軸方向の加速度を検出する加速度センサを例に挙げて説明したが、ｘ軸方向またはｙ軸方向の加速度を検出する加速度センサに本開示を適用することもできる。この場合、第１基板１０には、加速度に応じて変位する可動電極を有する可動部２０と、可動電極と対向する固定電極を有する固定部が形成される。そして、接続されるＣ－Ｖ変換回路に応じて可動電極または固定電極のいずれか一方に搬送波が入力される。したがって、支持基板１１は、抵抗率が０．０１～２０Ω・ｃｍのシリコン基板で構成されている。また、本開示の物理量センサを角速度センサ等に適用することもできる。 For example, in the first embodiment, the acceleration sensor that detects acceleration in the z-axis direction has been described as an example. However, the present disclosure may be applied to an acceleration sensor that detects acceleration in the x-axis direction or the y-axis direction. it can. In this case, the first substrate 10 is formed with a movable part 20 having a movable electrode that is displaced according to acceleration, and a fixed part having a fixed electrode facing the movable electrode. A carrier wave is input to either the movable electrode or the fixed electrode according to the CV conversion circuit to be connected. Therefore, the support substrate 11 is composed of a silicon substrate having a resistivity of 0.01 to 20 Ω · cm. Further, the physical quantity sensor of the present disclosure can be applied to an angular velocity sensor or the like.
　さらに、上記第１実施形態において、支持基板１１にコンタクト部８０と同様のコンタクト部を形成し、支持基板１１と外部回路とを接続して支持基板１１の電位を一定に維持してもよい。この場合は、上記貼り合わせ基板４１と同様に、支持基板１１は、抵抗率が０．０１～０．２Ω・ｃｍであるＰ型のシリコン基板で構成される。これによれば、支持基板１１とコンタクト部とのコンタクト抵抗を低減しつつ、半導体層１３と支持基板１１との間に生成される寄生容量がばらつくことも抑制できる。 Furthermore, in the first embodiment, a contact portion similar to the contact portion 80 may be formed on the support substrate 11, and the support substrate 11 and an external circuit may be connected to keep the potential of the support substrate 11 constant. In this case, like the bonded substrate 41, the support substrate 11 is composed of a P-type silicon substrate having a resistivity of 0.01 to 0.2 Ω · cm. According to this, it is possible to suppress a variation in parasitic capacitance generated between the semiconductor layer 13 and the support substrate 11 while reducing the contact resistance between the support substrate 11 and the contact portion.

Claims (6)

  1. 　一面（１０ａ）を有する第１基板（１０）と、
    　一面（４０ａ）を有し、当該一面が前記第１基板の一面と対向する状態で前記第１基板と接合される第２基板（４０）と、
    　前記第１、第２基板の間に形成された気密室（９０）に配置され、物理量に応じたセンサ信号を出力するセンシング部（６０）と、を備えた物理量センサにおいて、
    　前記第２基板は、抵抗率が０．０１～０．２［Ω・ｃｍ］であるＰ型のシリコン基板で構成され、金属材料を用いて構成されたコンタクト部（８０）と接続されることで所定の電位に維持される貼り合わせ基板（４１）を有している物理量センサ。     A first substrate (10) having one surface (10a);
    A second substrate (40) having one surface (40a) and bonded to the first substrate in a state where the one surface faces one surface of the first substrate;
    A physical quantity sensor comprising a sensing unit (60) disposed in an airtight chamber (90) formed between the first and second substrates and outputting a sensor signal corresponding to the physical quantity;
    The second substrate is made of a P-type silicon substrate having a resistivity of 0.01 to 0.2 [Ω · cm], and is connected to a contact portion (80) made of a metal material. A physical quantity sensor having a bonded substrate (41) maintained at a predetermined potential.
  2. 　前記第１基板は、支持基板（１１）と、絶縁膜（１２）と、半導体層（１３）とが順に積層されたＳＯＩ基板とされ、前記半導体層のうち前記絶縁膜と反対側の面が前記第１基板の一面とされている請求項１に記載の物理量センサ。 The first substrate is an SOI substrate in which a support substrate (11), an insulating film (12), and a semiconductor layer (13) are sequentially stacked, and the surface of the semiconductor layer opposite to the insulating film is The physical quantity sensor according to claim 1, wherein the physical quantity sensor is a surface of the first substrate.
  3. 　前記センシング部は、少なくとも一部が前記半導体層に形成されると共に当該一部に周期的な電圧の搬送波が入力されるようになっており、
    　前記支持基板は、電位がフローティング状態とされ、抵抗率が０．０１～２０［Ω・ｃｍ］であるシリコン基板で構成されている請求項２に記載の物理量センサ。     The sensing unit is formed at least in part in the semiconductor layer, and a periodic voltage carrier wave is input to the part.
    The physical quantity sensor according to claim 2, wherein the support substrate is formed of a silicon substrate having a potential in a floating state and a resistivity of 0.01 to 20 [Ω · cm].
  4. 　前記支持基板は、抵抗率が０．０１～０．２［Ω・ｃｍ］であるＰ型のシリコン基板で構成され、金属材料を用いて構成されたコンタクト部と接続されることで所定の電位に維持されている請求項２に記載の物理量センサ。 The support substrate is formed of a P-type silicon substrate having a resistivity of 0.01 to 0.2 [Ω · cm], and is connected to a contact portion formed using a metal material, thereby having a predetermined potential. The physical quantity sensor according to claim 2, wherein the physical quantity sensor is maintained.
  5. 　前記半導体層は、抵抗率が０．０１～０．０３［Ω・ｃｍ］であるＰ型のシリコン基板で構成されている請求項２ないし４のいずれか１つに記載の物理量センサ。 The physical quantity sensor according to any one of claims 2 to 4, wherein the semiconductor layer is formed of a P-type silicon substrate having a resistivity of 0.01 to 0.03 [Ω · cm].
  6. 　前記半導体層は、抵抗率が０．０１～０．２［Ω・ｃｍ］であるＮ型のシリコン基板で構成されている請求項２ないし４のいずれか１つに記載の物理量センサ。
          5. The physical quantity sensor according to claim 2, wherein the semiconductor layer is formed of an N-type silicon substrate having a resistivity of 0.01 to 0.2 [Ω · cm].
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JP2009283900A (en) * 2008-04-22 2009-12-03 Denso Corp Method for manufacturing mechanical quantity sensor, and mechanical quantity sensor
JP2010171368A (en) * 2008-12-25 2010-08-05 Denso Corp Semiconductor device, and method for manufacturing the same
JP2011017693A (en) * 2009-06-09 2011-01-27 Denso Corp Semiconductor dynamic quantity sensor and method of manufacturing the same

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