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WO2014121469A1 - 一种薄膜晶体管及其像素单元的制造方法 - Google Patents

一种薄膜晶体管及其像素单元的制造方法 Download PDF

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Publication number
WO2014121469A1
WO2014121469A1 PCT/CN2013/071471 CN2013071471W WO2014121469A1 WO 2014121469 A1 WO2014121469 A1 WO 2014121469A1 CN 2013071471 W CN2013071471 W CN 2013071471W WO 2014121469 A1 WO2014121469 A1 WO 2014121469A1
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source
layer
gate
region
drain
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PCT/CN2013/071471
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English (en)
French (fr)
Inventor
余晓军
魏鹏
刘自鸿
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深圳市柔宇科技有限公司
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Priority to PCT/CN2013/071471 priority Critical patent/WO2014121469A1/zh
Priority to CN201380000480.5A priority patent/CN104272443B/zh
Priority to US14/373,308 priority patent/US9269796B2/en
Publication of WO2014121469A1 publication Critical patent/WO2014121469A1/zh
Priority to US14/757,934 priority patent/US9583519B2/en

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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
    • H01L21/441—Deposition of conductive or insulating materials for electrodes
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/469—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers
    • H01L21/4757—After-treatment
    • H01L21/47573—Etching the layer
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/4763—Deposition of non-insulating, e.g. conductive -, resistive -, layers on insulating layers; After-treatment of these layers
    • H01L21/47635—After-treatment of these layers
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • the present invention belongs to the field of electronic technologies, and in particular, to a method for manufacturing a thin film transistor and a pixel unit thereof.
  • TFT Thin film transistor
  • ITZO In-Ga-Zn-O
  • TFT Thin film transistor
  • IGZO In-Ga-Zn-O
  • TFT is a basic circuit component that can be widely used in various electronic systems, and has various advantages such as high electron mobility, low temperature manufacturing process, high stability, transparency, and the like.
  • the overlap of the gate and the source and drain increases, resulting in a large parasitic capacitance of the gate source, which makes the overall performance of the thin film transistor poor.
  • the contact vias of the source and the drain are required to be aligned with the gate, and the low-precision mask focusing mode may cause the source-drain contact via to be asymmetrical, or even open/short, and the reliability is low.
  • An object of the present invention is to provide a method for fabricating a thin film transistor, which aims to solve the problem of poor performance and low reliability of the conventional thin film transistor.
  • the embodiment of the present invention is implemented by the method for manufacturing a thin film transistor, comprising the following steps:
  • a conductive material is filled in the source contact via and the drain contact via.
  • Another object of the embodiments of the present invention is to provide a method for fabricating a thin film transistor pixel unit, including the following steps:
  • a gate metal layer and a gate insulating layer located in the source and drain regions to form a contact via portion and an etch barrier layer in the gate interface region, the exposure being located at the source a region and a drain region for forming a metal oxide layer contacting the via portion and a gate metal layer at the gate interface region, thereby forming the source contact via, the drain contact via, and the gate
  • the interface area wire contacts the lower half of the via hole, and forms a complete source contact via hole, a drain contact via hole and a gate interface area contact via hole with the upper half thereof;
  • the conductive contact material is filled in the source contact via, the drain contact via, and the gate interface region.
  • the partial etch barrier layer, the gate metal layer and the gate insulating layer on the substrate are etched through the same mask, and the metal oxide layer, the gate insulating layer, the gate metal layer and the gate region are retained.
  • the position of the via hole is such that the source contact via and the drain contact via formed by the material replacement are equal to the gate pitch, so that the source drain and the gate are self-aligned and the source and drain are in contact with the via and
  • the gate is self-aligned and symmetrical, and the thin film transistor thus fabricated is less prone to short circuit and open circuit, and the parasitic capacitance is small, and the circuit produced is fast.
  • the process is suitable for thin film transistor pixel cell fabrication.
  • FIG. 1 is a flow chart showing an implementation of a method for fabricating a thin film transistor according to a first embodiment of the present invention
  • FIG. 2 is a schematic structural view showing deposition of a metal oxide layer on a substrate according to a first embodiment of the present invention
  • FIG 3 is a schematic structural view of an etched portion of a metal oxide layer according to a first embodiment of the present invention (the substrate is large, after etching away the metal oxide layer outside the thin film transistor region);
  • FIG. 4 is a schematic structural view showing deposition of a gate insulating layer, a gate metal layer, and an etch barrier layer on a metal oxide layer according to a first embodiment of the present invention
  • FIG. 5 is a schematic structural view showing a portion of an etch barrier layer, a gate metal layer, and a gate insulating layer etched through the same mask according to the first embodiment of the present invention
  • FIG. 6 is a schematic structural view showing etching of an exposed etch barrier layer and a gate metal layer and a gate insulating layer aligned therewith via the same mask according to the first embodiment of the present invention
  • FIG. 7 is a schematic view showing the structure of a photoresist in which a photoresist is thinned in a first embodiment of the present invention until a source portion and a drain region are completely removed to form a contact via portion;
  • FIG. 8 is a schematic structural view showing etching of an etch barrier layer in a source region and a drain region for forming a contact via portion in the first embodiment of the present invention
  • FIG. 9 is a view showing a metal oxide layer, a gate insulating layer, a gate metal layer, and an etch barrier layer of a gate region and a source region and a drain region for forming a contact via portion in a first embodiment of the present invention; Schematic diagram of a metal oxide layer, a gate insulating layer and a gate metal layer;
  • Figure 10 is a schematic view showing the structure of the exposed metal oxide layer to form a part of the source and drain electrodes in the first embodiment of the present invention
  • FIG. 11 is a schematic structural view showing deposition of a passivation layer on one side of a substrate according to a first embodiment of the present invention
  • Figure 12 is a schematic view showing the structure of the source and drain regions for forming the upper half of the contact via in the first embodiment of the present invention
  • Figure 13 is a schematic view showing the structure of the source and drain regions for forming the lower half of the contact via in the first embodiment of the present invention
  • Figure 14 is a schematic view showing the structure of the exposed metal oxide layer in the first embodiment of the present invention to form a complete source and drain;
  • 15 is a schematic structural view showing deposition of a conductive material in a source contact via and a drain contact via according to a first embodiment of the present invention
  • 16 is a schematic structural view showing deposition of a transparent metal electrode on a passivation layer of a source region and a drain region according to a first embodiment of the present invention
  • FIG. 17 is a schematic structural view of a metal oxide thin film transistor according to a first embodiment of the present invention (after removing a passivation layer);
  • FIG. 18 is a flowchart showing an implementation of a method for manufacturing a thin film transistor pixel unit according to a second embodiment of the present invention.
  • FIG. 19 is a schematic structural view showing deposition of a metal oxide layer on a substrate according to a second embodiment of the present invention.
  • 20 is a schematic structural view of a second embodiment of the present invention after etching away a metal oxide layer other than a thin film transistor region;
  • 21 is a schematic structural view showing deposition of a gate insulating layer, a gate metal layer, and an etch barrier layer on a metal oxide layer according to a second embodiment of the present invention
  • FIG. 22 is a schematic structural view of a second embodiment of the present invention etching a partially etched barrier layer, a gate metal layer, and a gate insulating layer via the same mask;
  • FIG. 23 is a schematic structural view showing etching of an exposed etch barrier layer and a gate metal layer and a gate insulating layer aligned therewith via the same mask according to a second embodiment of the present invention
  • Figure 24 is a schematic view showing the structure of the photoresist in the second embodiment of the present invention until the photoresist is completely removed until the storage capacitor region is located and the source and drain regions are formed to form a contact via portion;
  • 25 is a schematic structural view showing etching of an etch barrier layer located in a storage capacitor region and in a source region and a drain region for forming a contact via portion according to a second embodiment of the present invention
  • 26 is a second embodiment of the present invention, in which a metal oxide layer, a gate insulating layer, a gate metal layer, and an etch barrier layer are disposed in a gate region, and are located in a source region and a drain region to form a contact via portion.
  • Metal oxide layer, gate insulating layer and gate metal layer, gate insulating layer in gate interface region, gate metal layer and etch barrier layer, and gate insulating layer and gate metal in storage capacitor region Schematic diagram of the structure of the layer;
  • Figure 27 is a schematic view showing the structure of the metal oxide layer of the exposed metal oxide layer to form a part of the source and drain electrodes according to the second embodiment of the present invention.
  • FIG. 28 is a schematic structural view showing deposition of a passivation layer on one side of a substrate according to a second embodiment of the present invention.
  • 29 is a schematic structural view of a source region, a drain region, and a gate interface region for forming an upper portion of a contact via in a second embodiment of the present invention.
  • FIG. 30 is a schematic structural view of a source region, a drain region, and a gate interface region for forming a lower half of a contact via in a second embodiment of the present invention
  • 31 is a schematic view showing the structure of metallizing an exposed metal oxide layer to form a complete source and drain according to a second embodiment of the present invention.
  • 32 is a schematic structural view showing deposition of a conductive material in a source contact via, a drain contact via, and a gate contact region via via in a second embodiment of the present invention
  • Figure 33 is a schematic view showing the structure of depositing a transparent metal electrode according to a second embodiment of the present invention.
  • Figure 34 is a block diagram showing the structure of a storage capacitor fabricated in accordance with a second embodiment of the present invention.
  • the partial etch barrier layer, the gate metal layer and the gate insulating layer on the substrate are etched through the same mask, and the metal oxide layer, the gate insulating layer, the gate metal layer and the gate region are retained.
  • the position of the via hole is such that the source contact via and the drain contact via formed by the material replacement are equal to the gate pitch, so that the source drain and the gate are self-aligned and the source and drain are in contact with the via and
  • the gate is self-aligned and symmetrical, and the thin film transistor thus fabricated is less prone to short circuit and open circuit, and the parasitic capacitance is small, and the circuit produced is fast.
  • FIG. 1 is a flowchart showing an implementation process of a method for manufacturing a thin film transistor according to an embodiment of the present invention, which is described in detail below.
  • step S101 a metal oxide layer, a gate insulating layer, a gate metal layer, and an etch barrier layer are formed on the substrate.
  • the embodiment of the present invention first deposits a metal oxide layer 2 on the substrate 1, wherein the substrate 1 material may be glass, plastic, or the like, and the substrate 1 may also deposit at least one buffer layer in advance.
  • the substrate 1 material may be glass, plastic, or the like
  • the substrate 1 may also deposit at least one buffer layer in advance.
  • a metal oxide layer other than the thin film transistor region is etched away by a photolithography process.
  • a gate insulating layer 3 a gate metal layer 4, and an etch barrier layer 5 are sequentially deposited on the metal oxide layer 2, as shown in FIG.
  • step S102 the partial etch barrier layer, the gate metal layer and the gate insulating layer on the substrate are etched through the same mask, and the metal oxide layer, the gate insulating layer and the gate in the gate region are left. a metal layer and an etch barrier layer, and a metal oxide layer, a gate insulating layer and a gate metal layer at the source and drain regions for forming a contact via portion, such that the source region and the drain region are located The remaining portion of the metal oxide layer is exposed.
  • an embodiment of the present invention etches a portion of the etch barrier layer, a portion of the gate metal layer, and a portion of the gate insulating layer on the substrate 1 via the same mask 6.
  • the lithography process is used for etching. .
  • the polar region and the drain region are used to form a metal oxide layer, a gate insulating layer, and a gate metal layer that contact the via portion.
  • the metal oxide layer located in the remaining portions of the source region and the drain region is exposed, wherein at least the source region and the drain region are exposed to form a portion between the contact via and the gate region.
  • Metal oxide layer is used for etching away part of the etch barrier layer, part of the gate metal layer and part of the gate insulating layer, leaving the metal oxide layer
  • the photoresist is uniformly coated on the etch barrier layer 5 such that the upper surface of the photoresist is a flat surface, and the mask 6 is placed on the photoresist.
  • the mask version is a gray scale mask.
  • the photoresist is exposed to the mask 6 to expose and develop the photoresist, so that the photoresist located in the gate region is located in the source region and the drain region to form a contact via portion.
  • the photoresist is thick, and at the same time, the photoresist located in the source region for forming the contact via portion is thicker than the photoresist in the drain region for forming the contact via portion, and the photoresist is removed at other positions.
  • the thickness of the photoresist 7 at each position is determined by the transmittance of the corresponding portion of the gray scale mask.
  • a portion of the etch barrier layer, a portion of the gate metal layer, and a portion of the gate insulating layer are then etched away, and the number of etched film layers is determined by the mask 6.
  • all exposed etch barrier layers ie, etch barrier layers not covered by the photoresist
  • the gate metal layer and the gate insulating layer aligned with the etch barrier layer are etched first, as shown in FIG. 6 .
  • thinning the thickness of the photoresist at each position until the photoresist in the source and drain regions for forming the contact via portion is completely removed, as shown in FIG. 7;
  • the etch stop layer in the source and drain regions is formed to form a contact via portion, as shown in FIG. 8; finally, all of the photoresist is removed, as shown in FIG.
  • the action light can be ultraviolet light.
  • a very insulating layer and a gate metal layer At the same time, a portion of the metal oxide layer is exposed, i.e., the source and drain regions are exposed to form a metal oxide layer between the portion contacting the via and the gate region. Of course, the source and drain regions may also be exposed to form a metal oxide layer around the via portion.
  • the position of the gate, the source drain and the source and drain contacts the via is determined once, and the source contact via and the drain contact via formed by the material replacement are equal to the gate pitch, thereby making the source and drain
  • the self-aligned and gate-drain contact vias are self-aligned and symmetrical with respect to the gate, and the thin film transistor thus fabricated is less prone to short-circuit and open circuit, has small parasitic capacitance, and the circuit is operated at a high speed.
  • step S103 the exposed metal oxide layer in the source and drain regions is metallized to become a partial source and drain, and then a passivation layer is deposited.
  • an embodiment of the present invention first metallizes an exposed metal oxide layer located in the source and drain regions by plasma processing.
  • a silicon nitride SiNx:H insulating protective layer is hydrogenated in the gate region, the source region, and the drain region, and the hydrogenation process directly places the exposed metal oxide layer metal in the source region and the drain region. It becomes part of the source and drain, which greatly saves the process steps.
  • the portion of the source and drain are conductive sources and drains.
  • Plasma Ar or H-rich
  • NH3 forms a self-aligned source-drain device.
  • the drain resistance of the thin film transistor produced by the embodiment of the invention is greatly reduced, the device performance is remarkably improved, and the overall manufacturing cost is reduced because the manufacturing method reduces the expensive process steps.
  • the self-aligned process minimizes the overlap of the gate and source and drain, and the channel size can be precisely controlled, which can significantly reduce the channel size and improve device performance.
  • a passivation layer 8 covering the gate region, the source region and the drain region is deposited, that is, a passivation layer 8 is deposited on one side of the substrate, and the passivation layer 8 simultaneously covers the gate region and the source
  • the polar and drain regions are shown in Figure 11.
  • the passivation layer 8 may be a SiNx film or a SiO2/SiNx multilayer film.
  • step S104 etching a passivation layer, a gate metal layer and a gate insulating layer located in the source and drain regions to form a contact via portion, the exposure being located in the source region and the drain region A metal oxide layer is formed to contact the via portion, thereby forming a source contact via and a drain contact via.
  • the embodiment of the present invention etches a passivation layer, a gate metal layer, and a gate insulating layer located in the source and drain regions to form a contact via portion by a photolithography process, so as to be located in the source region and The drain region is exposed to form a metal oxide layer contacting the via portion, thereby forming a source contact via 9 and a drain contact via 10.
  • a passivation layer is formed on the source region and the drain region to form a contact via portion, thereby forming an upper portion of the source contact via and the drain contact via, as shown in FIG. Shown.
  • the side of the upper half can be inclined to the metal oxide layer, has low process requirements, and is easy to lithography.
  • a gate metal layer and a gate insulating layer located in the source and drain regions for forming a contact via portion are further etched. As shown in FIG.
  • the side of the lower half is perpendicular to the metal oxide layer such that the distance between the source contact via 9 and the lower half of the drain contact via 10 is equal and symmetrical with respect to the gate 11, that is, the thin film transistor does not occur. Open circuit, short circuit, etc.
  • step S105 the exposed metal oxide layers in the source and drain regions are metallized to electrically connect with the formed portions of the source and drain, respectively, to form a complete source and drain.
  • an embodiment of the present invention first metallizes an exposed metal oxide layer located in the source and drain regions by plasma processing.
  • a silicon nitride SiNx:H insulating protective layer is hydrogenated in the gate region, the source region, and the drain region, and the hydrogenation process directly places the exposed metal oxide layer metal in the source region and the drain region.
  • the complete source 12 and drain 13 are conductive sources and drains, and the metal oxide layer between the source 12 and drain 13 forms the channel 18 of the thin film transistor.
  • step S106 the source contact via and the drain contact via are filled with a conductive material.
  • the source contact via 9 and the drain contact via 10 are filled with a conductive material 14 , and the conductive material 14 is protruded from the passivation layer 8 to facilitate fabrication. Subsequent electrodes. In addition, a transparent metal electrode 19 is deposited over the source and drain region passivation layers. Of course, electrodes passing through the passivation layer and the etch barrier layer can also be formed in the gate region.
  • FIG. 18 is a flowchart showing an implementation process of a method for manufacturing a thin film transistor pixel unit according to an embodiment of the present invention, which is described in detail below.
  • step S201 a metal oxide layer, a gate insulating layer, a gate metal layer and an etch barrier layer are formed on the substrate, wherein the metal oxide layer is located in the thin film transistor region.
  • a metal oxide layer 22 is first deposited on the substrate 21.
  • the substrate 21 may be made of glass, plastic, or the like.
  • the substrate 21 may also be deposited with at least one buffer layer in advance.
  • a metal oxide layer other than the thin film transistor region on the substrate 21 needs to be etched away.
  • a metallization layer other than the thin film transistor region can be etched away by a photolithography process.
  • a gate insulating layer 23, a gate metal layer 24, and an etch barrier layer 25 are sequentially deposited on the substrate 21 and the metal oxide layer 22, as shown in FIG.
  • step S202 the partial etch barrier layer, the gate metal layer and the gate insulating layer on the substrate are etched through the same mask; the metal oxide layer, the gate insulating layer and the gate are retained in the gate region.
  • a metal layer and an etch barrier layer, the source region and the drain region are formed to form a metal oxide layer, a gate insulating layer and a gate metal layer contacting the via portion, a gate insulating layer located in the gate interface region, a gate metal layer and an etch barrier layer and a gate insulating layer and a gate metal layer in the storage capacitor region; exposing the metal oxide layer located in the remaining portions of the source region and the drain region.
  • an embodiment of the present invention etches a portion of the etch barrier layer, a portion of the gate metal layer, and a portion of the gate insulating layer on the substrate 21 via the same mask 26, where etching is performed by photolithography. .
  • the polar region and the drain region are used to form a metal oxide layer, a gate insulating layer and a gate metal layer contacting the via portion, a gate insulating layer, a gate metal layer and an etch barrier layer in the gate interface region, and A gate insulating layer and a gate metal layer located in the storage capacitor region.
  • the metal oxide layer located in the remaining portions of the source region and the drain region is exposed, wherein at least the source region and the drain region are exposed to form a portion between the contact via and the gate region.
  • Metal oxide layer is used to form a portion between the contact via and the gate region.
  • a photoresist is uniformly coated on the etch barrier layer 25, and a mask 26 is placed on the photoresist. Then, the photoresist is exposed to the mask plate 26 to expose and develop the photoresist, so that the photoresist located in the gate region and the gate interface region is located in the source region and the drain region.
  • Forming a photoresist layer contacting the via portion and the storage capacitor region, and making the photoresist in the gate region and the photoresist in the gate interface region are equal in thickness, and are located in the source region and the drain region for forming contact
  • the photoresist of the via portion is thicker than the photoresist located in the storage capacitor region, and is located at the source region for forming a photoresist and a drain region contacting the via portion to form a photoresist for contacting the via portion.
  • the photoresist is thick and removed at other positions, and the thickness of the photoresist 7 at each position is determined by the transmittance of the corresponding portion of the gray scale mask.
  • etch barrier layer a portion of the etch barrier layer, a portion of the gate metal layer and a portion of the gate insulating layer on the substrate 21 are etched away, and the number of etched film layers is determined by the mask 6.
  • all exposed etch barrier layers ie, etch barrier layers not covered by the photoresist
  • the gate metal layer and the gate insulating layer aligned with the etch barrier layer are etched first, as shown in FIG.
  • the thickness of the photoresist is then simultaneously reduced until the photoresist in the source and drain regions is formed to contact the via portion and the photoresist in the storage capacitor region is completely removed, such as Figure 24; then etching away the source and drain regions to form the contact via portion and the etch stop layer in the storage capacitor region, as shown in Figure 25; finally remove all photoresist, as shown 26 is shown.
  • the action light can be ultraviolet light.
  • the metal oxide layer, the gate insulating layer, the gate metal layer and the etch barrier layer in the gate region are retained, and the metal oxide layer and the gate are formed in the source region and the drain region to form a contact via portion.
  • the metal oxide layer located in the remaining portions of the source region and the drain region is exposed, that is, the source region and the drain region are exposed to form metal oxide between the portion contacting the via and the gate region. Layer of matter.
  • the source and drain regions may also be exposed to form a metal oxide layer around the via portion.
  • the position of the gate, the source drain and the source and drain contacts the via is determined once, and the source contact via and the drain contact via formed by the material replacement are equal to the gate pitch, thereby making the source and drain.
  • the self-aligned and gate-drain contact vias are self-aligned and symmetrical with respect to the gate, and the thin film transistor thus fabricated is less prone to short-circuit and open circuit, has small parasitic capacitance, and the circuit is operated at a high speed.
  • the positions of the storage capacitor and the gate interface region are determined, and the etch barrier layer located in the storage capacitor region is removed, so that the gate metal layer located in the storage capacitor region is used as one of the storage capacitors in the subsequent process. 36.
  • the embodiment of the present invention does not require alignment between the plurality of masks, and the position of the gate, the source drain, and the source and drain contact vias is determined by the same mask 26, so that the source and drain are connected to the gate.
  • Fully self-aligned, the source and drain contact vias are completely self-aligned and symmetrical with the gate, greatly improving the performance of the thin film transistor.
  • step S203 the exposed metal oxide layer in the source and drain regions is metallized to become a partial source and drain, and then a passivation layer is deposited.
  • the exposed metal oxide layer located in the source region and the drain region is metallized by plasma treatment.
  • a silicon nitride SiNx:H insulating protective layer is hydrogenated in the gate region, the source region, and the drain region, and the hydrogenation process directly places the exposed metal oxide layer metal in the source region and the drain region. It becomes part of the source and drain.
  • the portion of the source and drain are conductive sources and drains.
  • a passivation layer 28 covering the gate region, the source region, the drain region, the gate interface region, and the storage capacitor region is deposited, that is, a passivation layer 28 is deposited on the substrate 21 side, and the passivation layer
  • the gate region, the source region, the drain region, the gate interface region, and the storage capacitor region are simultaneously covered, as shown in FIG.
  • the passivation layer 28 may be a SiNx film or a SiO2/SiNx multilayer film.
  • a passivation layer is formed in the source region and the drain region for forming a contact via portion and a gate interface region, thereby forming a source contact via, a drain contact via, and a gate.
  • the pole interface area wire contacts the upper half of the via.
  • an embodiment of the present invention etches a passivation layer located in the source region and the drain region to form a contact via portion and a gate interface region by a photolithography process, thereby forming a source contact
  • the hole 29, the drain contact via 30, and the gate interface region line contact the upper half of the via 31.
  • the side of the upper half can be inclined to the metal oxide layer, has low process requirements, and is easy to lithography.
  • a gate metal layer and a gate insulating layer located in the source and drain regions for forming a contact via portion and an etch barrier layer in the gate interface region are further etched to expose a metal oxide layer located in the source and drain regions for forming a contact via portion and a gate metal layer in the gate interface region, thereby forming the source contact via, drain contact
  • the via and gate interface regions are in contact with the lower half of the via and form a complete source contact via, drain contact via, and gate interface contact via with the upper half.
  • the embodiment of the present invention further etches a gate metal layer and a gate insulating layer located in the source and drain regions to form a contact via portion, and is engraved in the gate interface region.
  • the via 29, the drain contact via 30, and the gate interface region are in contact with the lower half of the via 31, and form a complete source contact via, drain contact via, and gate interface region with the upper portion thereof. Connect the wires to the vias.
  • the sides of the source contact via 29 and the lower half of the drain contact via 30 are perpendicular to the metal oxide layer such that the source contact via 29 and the drain contact the lower half of the via 30
  • the spacing between the portion and the gate 32 is equal and symmetrical, that is, the formed thin film transistor does not have an open circuit or a short circuit.
  • step S206 the exposed metal oxide layers in the source and drain regions are metallized to electrically connect with the formed portions of the source and drain, respectively, to form a complete source and drain.
  • an embodiment of the present invention first metallizes an exposed metal oxide layer located in the source and drain regions by plasma processing.
  • a silicon nitride SiNx:H insulating protective layer is hydrogenated in the gate region, the source region, and the drain region, and the hydrogenation process directly places the exposed metal oxide layer metal in the source region and the drain region.
  • the complete source 33 and drain 34 are conductive sources and drains, and the metal oxide layer between the source 33 and drain 34 forms the channel 38 of the thin film transistor.
  • step S207 a conductive material is filled in the source contact via, the drain contact via, and the gate interface region via contact via.
  • the source contact via 29, the drain contact via 30, and the gate interface region connection via 31 are filled with a conductive material 35 (such as metal), and The conductive material 35 is protruded from the passivation layer 28 to facilitate fabrication of subsequent electrodes.
  • transparent metal electrodes 39 electrically connected to respective conductive materials are deposited on the source and drain region passivation layers, respectively.
  • the passivation layer located in the storage capacitor region is used as a dielectric layer of the storage capacitor, which is thinner than the storage capacitor dielectric layer of the bottom gate structure, thereby providing a capacitance per unit area, reducing the size of the capacitor, and increasing the aperture ratio.
  • electrodes passing through the passivation layer and the etch barrier layer can also be formed in the gate region.
  • the top gate structure thin film transistor has a simple manufacturing process and a lower process cost than the bottom gate structure thin film transistor.

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Abstract

公开了一种薄膜晶体管及其像素单元的制造方法，制造所述薄膜晶体管时经由同一掩膜版（6）刻蚀基板（1）上部分刻蚀阻挡层（5）、栅极金属层（4）和栅极绝缘层（3），保留位于栅极区的金属氧化物层（2）、栅极绝缘层（3）、栅极金属层（4）和刻蚀阻挡层（5）以及位于源极区和漏极区用以形成接触过孔部分的金属氧化物层（2）、栅极绝缘层（3）和栅极金属层（4），如此一次确定栅极（11）、源漏极（12，13）和源漏极接触过孔（9，10）的位置，并使后续通过材料替换形成的源极接触过孔（9）和漏极接触过孔（10）与栅极（11）的间距相等，从而使源漏极（12，13）与栅极（11）自对准和源漏极接触过孔（9，10）与栅极（11）自对准且对称，由此制成的薄膜晶体管不易发生短路、断路，寄生电容小，所制电路运行速度快。另外，本工艺适于薄膜晶体管像素单元制造。

Description

一种薄膜晶体管及其像素单元的制造方法 技术领域
本发明属于电子技术领域，尤其涉及一种薄膜晶体管及其像素单元的制造方法。
 背景技术
薄膜晶体管（TFT），如In-Ga-Zn-O (IGZO) TFT是一种可广泛用于各种电子系统的基本电路组成器件，具有多种优势，比如高电子迁移率、低温制造工艺、较高稳定性、透明等等。然而现有薄膜晶体管制造过程中因栅极与源漏极的重叠增加，导致栅源寄生电容大，使得薄膜晶体管整体性能差。另外，源极和漏极的接触过孔与栅极对准要求高，低精度的掩膜版对焦方式会导致源漏极接触过孔不对称，甚至发生断路/短路，可靠性低。
 技术问题
本发明实施例的目的在于提供一种薄膜晶体管的制造方法，旨在解决现有薄膜晶体管性能差、可靠性低的问题。
 技术解决方案
本发明实施例是这样实现的，一种薄膜晶体管的制造方法，包括以下步骤：
于基板上形成金属氧化物层、栅极绝缘层、栅极金属层和刻蚀阻挡层；
经由同一掩膜版刻蚀所述基板上部分刻蚀阻挡层、栅极金属层和栅极绝缘层，保留位于栅极区的金属氧化物层、栅极绝缘层、栅极金属层和刻蚀阻挡层以及位于源极区和漏极区用以形成接触过孔部分的金属氧化物层、栅极绝缘层和栅极金属层，使位于所述源极区和漏极区其余部分的金属氧化物层暴露；
金属化位于所述源极区和漏极区且暴露的金属氧化物层，使之成为部分源极和漏极，而后沉积钝化层；
刻蚀位于所述源极区和漏极区用以形成接触过孔部分的钝化层、栅极金属层和栅极绝缘层，暴露位于所述源极区和漏极区用以形成接触过孔部分的金属氧化物层，由此形成源极接触过孔和漏极接触过孔；
金属化位于所述源极区和漏极区且暴露的金属氧化物层，使之分别与已形成的部分源极和漏极电连接，形成完整的源极和漏极；
于所述源极接触过孔和漏极接触过孔内填充导电材料。
本发明实施例的另一目的在于提供一种薄膜晶体管像素单元的制造方法，包括以下步骤：
于基板上形成金属氧化物层、栅极绝缘层、栅极金属层和刻蚀阻挡层，其中所述金属氧化物层位于薄膜晶体管区；
经由同一掩膜版刻蚀所述基板上部分刻蚀阻挡层、栅极金属层和栅极绝缘层；保留位于栅极区的金属氧化物层、栅极绝缘层、栅极金属层和刻蚀阻挡层，位于源极区和漏极区用以形成接触过孔部分的金属氧化物层、栅极绝缘层和栅极金属层，位于栅极接口区的栅极绝缘层、栅极金属层和刻蚀阻挡层以及位于存储电容区的栅极绝缘层和栅极金属层；使位于所述源极区和漏极区其余部分的金属氧化物层暴露；
金属化位于所述源极区和漏极区且暴露的金属氧化物层，使之成为部分源极和漏极，而后沉积钝化层；
刻蚀位于所述源极区和漏极区用以形成接触过孔部分以及栅极接口区的钝化层，由此形成源极接触过孔、漏极接触过孔和栅极接口区连线接触过孔的上半部分；
进一步刻蚀位于所述源极区和漏极区用以形成接触过孔部分的栅极金属层和栅极绝缘层以及位于所述栅极接口区的刻蚀阻挡层，暴露位于所述源极区和漏极区用以形成接触过孔部分的金属氧化物层以及位于所述栅极接口区的栅极金属层，由此形成所述源极接触过孔、漏极接触过孔和栅极接口区连线接触过孔的下半部分，并与其上半部分构成完整的源极接触过孔、漏极接触过孔和栅极接口区连线接触过孔；
金属化位于所述源极区和漏极区且暴露的金属氧化物层，使之分别与已形成的部分源极和漏极电连接，形成完整的源极和漏极；
于所述源极接触过孔、漏极接触过孔和栅极接口区连线接触过孔内填充导电材料。
 有益效果
本发明实施例经由同一掩膜版刻蚀基板上部分刻蚀阻挡层、栅极金属层和栅极绝缘层，保留位于栅极区的金属氧化物层、栅极绝缘层、栅极金属层和刻蚀阻挡层以及位于源极区和漏极区用以形成接触过孔部分的金属氧化物层、栅极绝缘层和栅极金属层，如此一次确定栅极、源漏极和源漏极接触过孔的位置，并使后续通过材料替换形成的源极接触过孔和漏极接触过孔与栅极的间距相等，从而使源漏极与栅极自对准和源漏极接触过孔与栅极自对准且对称，由此制成的薄膜晶体管不易发生短路、断路，寄生电容小，所制电路运行速度快。另外，本工艺适于薄膜晶体管像素单元制造。
附图说明
图1是本发明第一实施例提供的薄膜晶体管的制造方法实现流程图；
图2是本发明第一实施例于基板上沉积金属氧化物层的结构示意图；
图3是本发明第一实施例刻蚀部分金属氧化物层的结构示意图（基板较大，刻蚀掉薄膜晶体管区以外的金属氧化物层后）；
图4是本发明第一实施例于金属氧化物层上沉积栅极绝缘层、栅极金属层和刻蚀阻挡层的结构示意图；
图5是本发明第一实施例经由同一掩膜版刻蚀部分刻蚀阻挡层、栅极金属层和栅极绝缘层的结构示意图；
图6是本发明第一实施例经由同一掩膜版刻蚀暴露的刻蚀阻挡层以及与之对位的栅极金属层和栅极绝缘层的结构示意图；
图7是本发明第一实施例减薄光刻胶直至完全移除位于源极区和漏极区用以形成接触过孔部分的光刻胶的结构示意图；
图8是本发明第一实施例刻蚀位于源极区和漏极区用以形成接触过孔部分的刻蚀阻挡层的结构示意图；
图9是本发明第一实施例保留栅极区的金属氧化物层、栅极绝缘层、栅极金属层和刻蚀阻挡层以及位于源极区和漏极区用以形成接触过孔部分的金属氧化物层、栅极绝缘层和栅极金属层的结构示意图；
图10是本发明第一实施例使暴露的金属氧化物层金属化，以形成部分源极和漏极的结构示意图；
图11是本发明第一实施例于基板一侧沉积钝化层的结构示意图；
图12是本发明第一实施例中源极区和漏极区用以形成接触过孔上半部分的结构示意图；
图13是本发明第一实施例中源极区和漏极区用以形成接触过孔下半部分的结构示意图；
图14是本发明第一实施例使暴露的金属氧化物层金属化，以形成完整的源极和漏极的结构示意图；
图15是本发明第一实施例于源极接触过孔和漏极接触过孔内沉积导电材料的结构示意图；
图16是本发明第一实施例于源极区和漏极区的钝化层上沉积透明金属电极的结构示意图；
图17是本发明第一实施例所制金属氧化物薄膜晶体管的结构示意图（移除钝化层后）；
图18是本发明第二实施例提供的薄膜晶体管像素单元的制造方法实现流程图；
图19是本发明第二实施例于基板上沉积金属氧化物层的结构示意图；
图20是本发明第二实施例刻蚀掉薄膜晶体管区以外的金属氧化物层后的结构示意图；
图21是本发明第二实施例于金属氧化物层上沉积栅极绝缘层、栅极金属层和刻蚀阻挡层的结构示意图；
图22是本发明第二实施例经由同一掩膜版刻蚀部分刻蚀阻挡层、栅极金属层和栅极绝缘层的结构示意图；
图23是本发明第二实施例经由同一掩膜版刻蚀暴露的刻蚀阻挡层以及与之对位的栅极金属层和栅极绝缘层的结构示意图；
图24是本发明第二实施例减薄光刻胶直至完全移除位于存储电容区以及位于源极区和漏极区用以形成接触过孔部分的光刻胶的结构示意图；
图25是本发明第二实施例刻蚀位于存储电容区以及位于源极区和漏极区用以形成接触过孔部分的刻蚀阻挡层的结构示意图；
图26是本发明第二实施例保留位于栅极区的金属氧化物层、栅极绝缘层、栅极金属层和刻蚀阻挡层，位于源极区和漏极区用以形成接触过孔部分的金属氧化物层、栅极绝缘层和栅极金属层，位于栅极接口区的栅极绝缘层、栅极金属层和刻蚀阻挡层以及位于存储电容区的栅极绝缘层和栅极金属层的结构示意图；
图27是本发明第二实施例使暴露的金属氧化物层金属化，以形成部分源极和漏极的结构示意图；
图28是本发明第二实施例于基板一侧沉积钝化层的结构示意图；
图29是本发明第二实施例中源极区、漏极区和栅极接口区用以形成接触过孔上半部分的结构示意图；
图30是本发明第二实施例中源极区、漏极区和栅极接口区用以形成接触过孔下半部分的结构示意图；
图31是本发明第二实施例使暴露的金属氧化物层金属化，以形成完整的源极和漏极的结构示意图；
图32是本发明第二实施例于源极接触过孔、漏极接触过孔和栅极接口区连线接触过孔内沉积导电材料的结构示意图；
图33是本发明第二实施例沉积透明金属电极的结构示意图；
图34是本发明第二实施例所制存储电容的结构示意图。
 本发明的实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
本发明实施例经由同一掩膜版刻蚀基板上部分刻蚀阻挡层、栅极金属层和栅极绝缘层，保留位于栅极区的金属氧化物层、栅极绝缘层、栅极金属层和刻蚀阻挡层以及位于源极区和漏极区用以形成接触过孔部分的金属氧化物层、栅极绝缘层和栅极金属层，如此一次确定栅极、源漏极和源漏极接触过孔的位置，并使后续通过材料替换形成的源极接触过孔和漏极接触过孔与栅极的间距相等，从而使源漏极与栅极自对准和源漏极接触过孔与栅极自对准且对称，由此制成的薄膜晶体管不易发生短路、断路，寄生电容小，所制电路运行速度快。
下面以金属氧化物薄膜晶体管为例对本发明的实现进行详细描述。
实施例一
图1示出了本发明实施例提供的薄膜晶体管的制造方法实现流程，详述如下。
在步骤S101中，于基板上形成金属氧化物层、栅极绝缘层、栅极金属层和刻蚀阻挡层。
如图2所示，本发明实施例先在基板1上沉积金属氧化物层2，其中所述基板1材料可以为玻璃、塑料等，所述基板1还可预先沉积至少一个缓冲层。如图3所示，采用光刻工艺刻蚀掉薄膜晶体管区以外的金属氧化物层。接着，在所述金属氧化物层2上依序沉积栅极绝缘层3、栅极金属层4和刻蚀阻挡层5，如图4所示。
在步骤S102中，经由同一掩膜版刻蚀所述基板上部分刻蚀阻挡层、栅极金属层和栅极绝缘层，保留位于栅极区的金属氧化物层、栅极绝缘层、栅极金属层和刻蚀阻挡层以及位于源极区和漏极区用以形成接触过孔部分的金属氧化物层、栅极绝缘层和栅极金属层，使位于所述源极区和漏极区其余部分的金属氧化物层暴露。
如图5所示，本发明实施例经由同一掩膜版6刻蚀所述基板1上部分刻蚀阻挡层、部分栅极金属层和部分栅极绝缘层，此处采用光刻工艺进行刻蚀。刻蚀掉部分刻蚀阻挡层、部分栅极金属层和部分栅极绝缘层后，保留位于栅极区的金属氧化物层、栅极绝缘层、栅极金属层和刻蚀阻挡层以及位于源极区和漏极区用以形成接触过孔部分的金属氧化物层、栅极绝缘层和栅极金属层。同时，使位于所述源极区和漏极区其余部分的金属氧化物层暴露，此处至少暴露所述源极区和漏极区用以形成接触过孔的部分与栅极区之间的金属氧化物层。
具体地，先于所述刻蚀阻挡层5之上均匀涂布光刻胶，使所述光刻胶上表面为平直表面，并将掩膜版6置于所述光刻胶之上。其中，所述掩膜版为灰阶掩膜版。接着由作用光投射于所述掩膜版6，对所述光刻胶进行曝光、显影处理，使位于栅极区的光刻胶较位于源极区和漏极区用以形成接触过孔部分的光刻胶厚，同时使位于源极区用以形成接触过孔部分的光刻胶与位于漏极区用以形成接触过孔部分的光刻胶等厚，并去除其它位置的光刻胶，此时所述光刻胶7处于各位置的厚度由灰阶掩膜版相应部分的透光率决定。然后刻蚀掉部分刻蚀阻挡层、部分栅极金属层和部分栅极绝缘层，刻蚀掉的薄膜层数由所述掩膜版6决定。具体刻蚀时先刻蚀所有暴露的刻蚀阻挡层（即未被光刻胶覆盖的刻蚀阻挡层）以及与该刻蚀阻挡层对位的栅极金属层和栅极绝缘层，如图6所示；接着减薄所述光刻胶处于各位置的厚度，直至位于所述源极区和漏极区用以形成接触过孔部分的光刻胶完全去除，如图7所示；然后刻蚀掉位于所述源极区和漏极区用以形成接触过孔部分的刻蚀阻挡层，如图8所示；最后去除所有光刻胶，如图9所示。其中，所述作用光可为紫外光。
这样保留了位于栅极区的金属氧化物层、栅极绝缘层、栅极金属层和刻蚀阻挡层以及位于源极区和漏极区用以形成接触过孔部分的金属氧化物层、栅极绝缘层和栅极金属层。同时，使部分金属氧化物层暴露，即暴露所述源极区和漏极区用以形成接触过孔的部分与栅极区之间的金属氧化物层。当然，还可以暴露所述源极区和漏极区用以形成接触过孔部分周围的金属氧化物层。如此一次确定栅极、源漏极和源漏极接触过孔的位置，并使后续通过材料替换形成的源极接触过孔和漏极接触过孔与栅极的间距相等，从而使源漏极与栅极自对准和源漏极接触过孔与栅极自对准且对称，由此制成的薄膜晶体管不易发生短路、断路，寄生电容小，所制电路运行速度快。
在步骤S103中，金属化位于所述源极区和漏极区且暴露的金属氧化物层，使之成为部分源极和漏极，而后沉积钝化层。
如图10所示，本发明实施例先通过等离子处理，使位于所述源极区和漏极区且暴露的金属氧化物层金属化。例如，于所述栅极区、源极区和漏极区氢化氮化硅SiNx:H绝缘保护层，该氢化过程直接将位于所述源极区和漏极区且暴露的金属氧化物层金属化，成为部分源极和漏极，大大节省了工艺步骤。金属化后，该部分源极和漏极为导电的源极和漏极。相比于现有技术通过等离子（Ar或者H-rich NH3）形成自对准的源漏极器件，本发明实施例所制薄膜晶体管源漏极电阻率大大降低，器件性能显著提高，同时因为本制造方法减少了昂贵的工艺步骤，整体制造成本降低。另外，本自对准工艺可以最小化栅极与源漏极的重叠，沟道尺寸可以精确控制，从而可能显著减小沟道尺寸，提高器件性能。
接着，沉积覆盖所述栅极区、源极区和漏极区的钝化层8，即在所述基板一侧沉积钝化层8，该钝化层8同时覆盖所述栅极区、源极区和漏极区，如图11所示。其中，所述钝化层8可以为SiNx薄膜或SiO2/SiNx的多层薄膜。
在步骤S104中，刻蚀位于所述源极区和漏极区用以形成接触过孔部分的钝化层、栅极金属层和栅极绝缘层，暴露位于所述源极区和漏极区用以形成接触过孔部分的金属氧化物层，由此形成源极接触过孔和漏极接触过孔。
本发明实施例通过光刻工艺刻蚀位于所述源极区和漏极区用以形成接触过孔部分的钝化层、栅极金属层和栅极绝缘层，使位于所述源极区和漏极区用以形成接触过孔部分的金属氧化物层暴露，由此形成源极接触过孔9和漏极接触过孔10。
具体地，先光刻位于所述源极区和漏极区用以形成接触过孔部分的钝化层，由此形成源极接触过孔和漏极接触过孔的上半部分，如图12所示。该上半部分的侧面可倾斜于金属氧化物层，工艺要求低，易于光刻。接着，进一步刻蚀位于所述源极区和漏极区用以形成接触过孔部分的栅极金属层和栅极绝缘层。如图13所示，直至暴露位于所述源极区和漏极区用以形成接触过孔部分的金属氧化物层，由此形成源极接触过孔和漏极接触过孔的下半部分，该下半部分的侧面垂直于金属氧化物层，这样使得源极接触过孔9和漏极接触过孔10的下半部分与栅极11的间距相等且对称，即所制薄膜晶体管不会发生断路、短路等现象。
在步骤S105中，金属化位于所述源极区和漏极区且暴露的金属氧化物层，使之分别与已形成的部分源极和漏极电连接，形成完整的源极和漏极。
如图14所示，本发明实施例先通过等离子处理，使位于所述源极区和漏极区且暴露的金属氧化物层金属化。例如，于所述栅极区、源极区和漏极区氢化氮化硅SiNx:H绝缘保护层，该氢化过程直接将位于所述源极区和漏极区且暴露的金属氧化物层金属化，并分别与已形成的部分源极和漏极电连接，形成完整的源极和漏极。金属化后，该完整的源极12和漏极13为导电的源极和漏极，而位于该源极12与漏极13间的金属氧化物层形成薄膜晶体管的沟道18。
在步骤S106中，于所述源极接触过孔和漏极接触过孔内填充导电材料。
如图15~17所示，本发明实施例于所述源极接触过孔9和漏极接触过孔10内填充导电材料14，并使该导电材料14凸设于钝化层8，利于制作后续电极。另外，于所述源极区和漏极区钝化层之上沉积透明金属电极19。当然，还可于所述栅极区制作穿过钝化层和刻蚀阻挡层的电极。
实施例二
图18示出了本发明实施例提供的薄膜晶体管像素单元的制造方法实现流程，详述如下。
在步骤S201中，于基板上形成金属氧化物层、栅极绝缘层、栅极金属层和刻蚀阻挡层，其中所述金属氧化物层位于薄膜晶体管区。
如图19所示，本发明实施例先在基板21上沉积金属氧化物层22，其中所述基板21材料可以为玻璃、塑料等，所述基板21还可预先沉积至少一层缓冲层。如图20所示，为制作具有存储电容的薄膜晶体管像素单元，需刻蚀掉所述基板21上薄膜晶体管区以外的金属氧化物层。当然，此处可以采用光刻工艺刻蚀掉薄膜晶体管区以外的金属氧化物层。接着，在所述基板21和金属氧化物层22上依序沉积栅极绝缘层23、栅极金属层24和刻蚀阻挡层25，如图21所示。
在步骤S202中，经由同一掩膜版刻蚀所述基板上部分刻蚀阻挡层、栅极金属层和栅极绝缘层；保留位于栅极区的金属氧化物层、栅极绝缘层、栅极金属层和刻蚀阻挡层，位于源极区和漏极区用以形成接触过孔部分的金属氧化物层、栅极绝缘层和栅极金属层，位于栅极接口区的栅极绝缘层、栅极金属层和刻蚀阻挡层以及位于存储电容区的栅极绝缘层和栅极金属层；使位于所述源极区和漏极区其余部分的金属氧化物层暴露。
如图22所示，本发明实施例经由同一掩膜版26刻蚀所述基板21上部分刻蚀阻挡层、部分栅极金属层和部分栅极绝缘层，此处采用光刻工艺进行刻蚀。光刻掉部分刻蚀阻挡层、部分栅极金属层和部分栅极绝缘层后，保留位于栅极区的金属氧化物层、栅极绝缘层、栅极金属层和刻蚀阻挡层，位于源极区和漏极区用以形成接触过孔部分的金属氧化物层、栅极绝缘层和栅极金属层，位于栅极接口区的栅极绝缘层、栅极金属层和刻蚀阻挡层以及位于存储电容区的栅极绝缘层和栅极金属层。同时，使位于所述源极区和漏极区其余部分的金属氧化物层暴露，此处至少暴露所述源极区和漏极区用以形成接触过孔的部分与栅极区之间的金属氧化物层。
具体地，先于所述刻蚀阻挡层25之上均匀涂布光刻胶，并将掩膜版26置于所述光刻胶之上。接着由作用光投射于所述掩膜版26，对所述光刻胶进行曝光、显影处理，使位于栅极区和栅极接口区的光刻胶较位于源极区和漏极区用以形成接触过孔部分和存储电容区的光刻胶厚，并使位于栅极区的光刻胶与位于栅极接口区的光刻胶等厚，位于源极区和漏极区用以形成接触过孔部分的光刻胶与位于存储电容区的光刻胶等厚，位于源极区用以形成接触过孔部分的光刻胶与漏极区用以形成接触过孔部分的光刻胶等厚，并去除其它位置的光刻胶，此时所述光刻胶7处于各位置的厚度由灰阶掩膜版相应部分的透光率决定。然后刻蚀掉所述基板21上部分刻蚀阻挡层、部分栅极金属层和部分栅极绝缘层，刻蚀掉的薄膜层数由所述掩膜版6决定。具体刻蚀时先刻蚀所有暴露的刻蚀阻挡层（即未被光刻胶覆盖的刻蚀阻挡层）以及与该刻蚀阻挡层对位的栅极金属层和栅极绝缘层，如图23所示；接着将光刻胶处于各位置的厚度同时减薄，直至位于源极区和漏极区用以形成接触过孔部分的光刻胶以及位于存储电容区的光刻胶完全去除，如图24所示；然后刻蚀掉位于源极区和漏极区用以形成接触过孔部分以及位于存储电容区的刻蚀阻挡层，如图25所示；最后去除所有光刻胶，如图26所示。其中，所述作用光可为紫外光。
这样保留了位于栅极区的金属氧化物层、栅极绝缘层、栅极金属层和刻蚀阻挡层，位于源极区和漏极区用以形成接触过孔部分的金属氧化物层、栅极绝缘层和栅极金属层，位于栅极接口区的栅极绝缘层、栅极金属层和刻蚀阻挡层以及位于存储电容区的栅极绝缘层和栅极金属层。同时，使位于所述源极区和漏极区其余部分的金属氧化物层暴露，即暴露所述源极区和漏极区用以形成接触过孔的部分与栅极区之间的金属氧化物层。当然，还可以暴露所述源极区和漏极区用以形成接触过孔部分周围的金属氧化物层。如此一次确定栅极、源漏极和源漏极接触过孔的位置，并使后续通过材料替换形成的源极接触过孔和漏极接触过孔与栅极的间距相等，从而使源漏极与栅极自对准和源漏极接触过孔与栅极自对准且对称，由此制成的薄膜晶体管不易发生短路、断路，寄生电容小，所制电路运行速度快。同时，确定了存储电容和栅极接口区的位置，且去除位于所述存储电容区的刻蚀阻挡层，以便后道工序将位于所述存储电容区的栅极金属层作为存储电容其中一个电极36。
换言之，因本发明实施例无需多个掩膜版之间进行对准，且由同一掩膜版26确定栅极、源漏极和源漏极接触过孔的位置，使源漏极与栅极完全自对准，源漏极接触过孔与栅极亦完全自对准且对称，极大地提升所制薄膜晶体管的性能。
在步骤S203中，金属化位于所述源极区和漏极区且暴露的金属氧化物层，使之成为部分源极和漏极，而后沉积钝化层。
如图27所示，本发明实施例先通过等离子处理，使位于所述源极区和漏极区且暴露的金属氧化物层金属化。例如，于所述栅极区、源极区和漏极区氢化氮化硅SiNx:H绝缘保护层，该氢化过程直接将位于所述源极区和漏极区且暴露的金属氧化物层金属化，成为部分源极和漏极。金属化后，该部分源极和漏极为导电的源极和漏极。
接着，沉积覆盖所述栅极区、源极区、漏极区、栅极接口区以及存储电容区的钝化层28，即在所述基板21一侧沉积钝化层28，该钝化层同时覆盖所述栅极区、源极区、漏极区、栅极接口区以及存储电容区，如图28所示。其中，所述钝化层28可以为SiNx薄膜或SiO2/SiNx的多层薄膜。
在步骤S204中，刻蚀位于所述源极区和漏极区用以形成接触过孔部分以及栅极接口区的钝化层，由此形成源极接触过孔、漏极接触过孔和栅极接口区连线接触过孔的上半部分。
如图29所示，本发明实施例通过光刻工艺刻蚀位于所述源极区和漏极区用以形成接触过孔部分以及栅极接口区的钝化层，由此形成源极接触过孔29、漏极接触过孔30和栅极接口区连线接触过孔31的上半部分。该上半部分的侧面可倾斜于金属氧化物层，工艺要求低，易于光刻。
在步骤S205中，进一步刻蚀位于所述源极区和漏极区用以形成接触过孔部分的栅极金属层和栅极绝缘层以及位于所述栅极接口区的刻蚀阻挡层，暴露位于所述源极区和漏极区用以形成接触过孔部分的金属氧化物层以及位于所述栅极接口区的栅极金属层，由此形成所述源极接触过孔、漏极接触过孔和栅极接口区连线接触过孔的下半部分，并与其上半部分构成完整的源极接触过孔、漏极接触过孔和栅极接口区连线接触过孔。
如图30所示，本发明实施例进一步刻蚀位于所述源极区和漏极区用以形成接触过孔部分的栅极金属层和栅极绝缘层以及位于所述栅极接口区的刻蚀阻挡层，直至暴露位于所述源极区和漏极区用以形成接触过孔部分的金属氧化物层以及位于所述栅极接口区的栅极金属层，由此形成所述源极接触过孔29、漏极接触过孔30和栅极接口区连线接触过孔31的下半部分，并与其上半部分构成完整的源极接触过孔、漏极接触过孔和栅极接口区连线接触过孔。其中，所述源极接触过孔29和漏极接触过孔30的下半部分的侧面垂直于金属氧化物层，这样使得所述源极接触过孔29和漏极接触过孔30的下半部分与栅极32的间距相等且对称，即所制薄膜晶体管不会发生断路、短路等现象。
在步骤S206中，金属化位于所述源极区和漏极区且暴露的金属氧化物层，使之分别与已形成的部分源极和漏极电连接，形成完整的源极和漏极。
如图31所示，本发明实施例先通过等离子处理，使位于所述源极区和漏极区且暴露的金属氧化物层金属化。例如，于所述栅极区、源极区和漏极区氢化氮化硅SiNx:H绝缘保护层，该氢化过程直接将位于所述源极区和漏极区且暴露的金属氧化物层金属化，并分别与已形成的部分源极和漏极电连接，形成完整的源极33和漏极34。金属化后，该完整的源极33和漏极34为导电的源极和漏极，而位于该源极33与漏极34间的金属氧化物层形成薄膜晶体管的沟道38。
在步骤S207中，于所述源极接触过孔、漏极接触过孔和栅极接口区连线接触过孔内填充导电材料。
如图32~34所示，本发明实施例于所述源极接触过孔29、漏极接触过孔30和栅极接口区连线接触过孔31内填充导电材料35（如金属），并使该导电材料35凸设于钝化层28，利于制作后续电极。另外，于所述源极区和漏极区钝化层之上分别沉积与各自导电材料电连接的透明金属电极39。在所述源极接触过孔29、漏极接触过孔30和栅极接口区连线接触过孔31内填充导电材料35时，位于所述存储电容区钝化层之上沉积用作存储电容另一电极37的导电材料（如金属层），制作工艺简单。此处将位于所述存储电容区的钝化层作为存储电容的介电层，较底栅结构的存储电容介电层薄，从而提供单位面积电容，减小电容尺寸，提高开口率。当然，还可于所述栅极区制作穿过钝化层和刻蚀阻挡层的电极。应当说明的是，本顶栅结构薄膜晶体管比底栅结构薄膜晶体管制造工艺简单，工艺成本降低。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (12)

  1. 一种薄膜晶体管的制造方法，其特征在于，所述方法包括以下步骤：
    于基板上形成金属氧化物层、栅极绝缘层、栅极金属层和刻蚀阻挡层；
    经由同一掩膜版刻蚀所述基板上部分刻蚀阻挡层、栅极金属层和栅极绝缘层，保留位于栅极区的金属氧化物层、栅极绝缘层、栅极金属层和刻蚀阻挡层以及位于源极区和漏极区用以形成接触过孔部分的金属氧化物层、栅极绝缘层和栅极金属层，使位于所述源极区和漏极区其余部分的金属氧化物层暴露；
    金属化位于所述源极区和漏极区且暴露的金属氧化物层，使之成为部分源极和漏极，而后沉积钝化层；
    刻蚀位于所述源极区和漏极区用以形成接触过孔部分的钝化层、栅极金属层和栅极绝缘层，暴露位于所述源极区和漏极区用以形成接触过孔部分的金属氧化物层，由此形成源极接触过孔和漏极接触过孔；
    金属化位于所述源极区和漏极区且暴露的金属氧化物层，使之分别与已形成的部分源极和漏极电连接，形成完整的源极和漏极；
    于所述源极接触过孔和漏极接触过孔内填充导电材料。
  2. 如权利要求1所述的方法，其特征在于，所述经由同一掩膜版刻蚀所述基板上部分刻蚀阻挡层、栅极金属层和栅极绝缘层，保留位于栅极区的金属氧化物层、栅极绝缘层、栅极金属层和刻蚀阻挡层以及位于源极区和漏极区用以形成接触过孔部分的金属氧化物层、栅极绝缘层和栅极金属层，使位于所述源极区和漏极区其余部分的金属氧化物层暴露的步骤具体为：
    于所述刻蚀阻挡层之上均匀涂布光刻胶，将掩膜版置于所述光刻胶之上；
    由作用光投射于所述掩膜版，对所述光刻胶进行曝光、显影处理，使位于栅极区的光刻胶较位于源极区和漏极区用以形成接触过孔部分的光刻胶厚；
    刻蚀所述基板上部分刻蚀阻挡层、栅极金属层和栅极绝缘层，保留位于栅极区的金属氧化物层、栅极绝缘层、栅极金属层和刻蚀阻挡层以及位于源极区和漏极区用以形成接触过孔部分的金属氧化物层、栅极绝缘层和栅极金属层，使位于所述源极区和漏极区其余部分的金属氧化物层暴露；
    其中，所述掩膜版为灰阶掩膜版，所述光刻胶的厚度由灰阶掩膜版各部分的透光率决定。
  3. 如权利要求1或2所述的方法，其特征在于，所述金属化位于所述源极区和漏极区且暴露的金属氧化物层，使之成为部分源极和漏极，而后沉积钝化层的步骤具体为：
    等离子处理，使位于所述源极区和漏极区且暴露的金属氧化物层金属化，成为部分源极和漏极；
    沉积覆盖所述栅极区、源极区和漏极区的钝化层。
  4. 如权利要求3所述的方法，其特征在于，所述等离子处理，使位于所述源极区和漏极区且暴露的金属氧化物层金属化，成为部分源极和漏极的步骤具体为：
    于所述栅极区、源极区和漏极区氢化氮化硅SiNx:H绝缘保护层，该氢化过程直接将位于所述源极区和漏极区且暴露的金属氧化物层金属化，成为部分源极和漏极。
  5. 如权利要求1、2或4所述的方法，其特征在于，所述刻蚀位于所述源极区和漏极区用以形成接触过孔部分的钝化层、栅极金属层和栅极绝缘层，暴露位于所述源极区和漏极区用以形成接触过孔部分的金属氧化物层，由此形成源极接触过孔和漏极接触过孔的步骤具体为：
    刻蚀位于所述源极区和漏极区用以形成接触过孔部分的钝化层；
    进一步刻蚀位于所述源极区和漏极区用以形成接触过孔部分的栅极金属层和栅极绝缘层，直至暴露位于所述源极区和漏极区用以形成接触过孔部分的金属氧化物层，并由此形成源极接触过孔和漏极接触过孔。
  6. 如权利要求1、2或4所述的方法，其特征在于，所述金属化位于所述源极区和漏极区且暴露的金属氧化物层，使之分别与已形成的部分源极和漏极电连接，形成完整的源极和漏极的步骤具体为：
    等离子处理，使位于所述源极区和漏极区且暴露的金属氧化物层金属化，并分别与已形成的部分源极和漏极电连接，形成完整的源极和漏极。
  7. 一种薄膜晶体管像素单元的制造方法，其特征在于，所述方法包括以下步骤：
    于基板上形成金属氧化物层、栅极绝缘层、栅极金属层和刻蚀阻挡层，其中所述金属氧化物层位于薄膜晶体管区；
    经由同一掩膜版刻蚀所述基板上部分刻蚀阻挡层、栅极金属层和栅极绝缘层；保留位于栅极区的金属氧化物层、栅极绝缘层、栅极金属层和刻蚀阻挡层，位于源极区和漏极区用以形成接触过孔部分的金属氧化物层、栅极绝缘层和栅极金属层，位于栅极接口区的栅极绝缘层、栅极金属层和刻蚀阻挡层以及位于存储电容区的栅极绝缘层和栅极金属层；使位于所述源极区和漏极区其余部分的金属氧化物层暴露；
    金属化位于所述源极区和漏极区且暴露的金属氧化物层，使之成为部分源极和漏极，而后沉积钝化层；
    刻蚀位于所述源极区和漏极区用以形成接触过孔部分以及栅极接口区的钝化层，由此形成源极接触过孔、漏极接触过孔和栅极接口区连线接触过孔的上半部分；
    进一步刻蚀位于所述源极区和漏极区用以形成接触过孔部分的栅极金属层和栅极绝缘层以及位于所述栅极接口区的刻蚀阻挡层，暴露位于所述源极区和漏极区用以形成接触过孔部分的金属氧化物层以及位于所述栅极接口区的栅极金属层，由此形成所述源极接触过孔、漏极接触过孔和栅极接口区连线接触过孔的下半部分，并与其上半部分构成完整的源极接触过孔、漏极接触过孔和栅极接口区连线接触过孔；
    金属化位于所述源极区和漏极区且暴露的金属氧化物层，使之分别与已形成的部分源极和漏极电连接，形成完整的源极和漏极；
    于所述源极接触过孔、漏极接触过孔和栅极接口区连线接触过孔内填充导电材料。
  8. 如权利要求7所述的方法，其特征在于，所述经由同一掩膜版刻蚀所述基板上部分刻蚀阻挡层、栅极金属层和栅极绝缘层；保留位于栅极区的金属氧化物层、栅极绝缘层、栅极金属层和刻蚀阻挡层，位于源极区和漏极区用以形成接触过孔部分的金属氧化物层、栅极绝缘层和栅极金属层，位于栅极接口区的栅极绝缘层、栅极金属层和刻蚀阻挡层以及位于存储电容区的栅极绝缘层和栅极金属层；使位于所述源极区和漏极区其余部分的金属氧化物层暴露的步骤具体为：
    于所述刻蚀阻挡层之上均匀涂布光刻胶，将掩膜版置于所述光刻胶之上；
    由作用光投射于所述掩膜版，对所述光刻胶进行曝光、显影处理，使位于栅极区和栅极接口区的光刻胶较位于源极区和漏极区用以形成接触过孔部分和存储电容区的光刻胶厚；
    刻蚀所述基板上部分刻蚀阻挡层、栅极金属层和栅极绝缘层；保留位于栅极区的金属氧化物层、栅极绝缘层、栅极金属层和刻蚀阻挡层，位于源极区和漏极区用以形成接触过孔部分的金属氧化物层、栅极绝缘层和栅极金属层，位于栅极接口区的栅极绝缘层、栅极金属层和刻蚀阻挡层以及位于存储电容区的栅极绝缘层和栅极金属层；使位于所述源极区和漏极区其余部分的金属氧化物层暴露；
    其中，所述掩膜版为灰阶掩膜版，所述光刻胶的厚度由灰阶掩膜版各部分的透光率决定。
  9. 如权利要求7或8所述的方法，其特征在于，所述金属化位于所述源极区和漏极区且暴露的金属氧化物层，使之成为部分源极和漏极，而后沉积钝化层的步骤具体为：
    等离子处理，使位于所述源极区和漏极区且暴露的金属氧化物层金属化，成为部分源极和漏极；
    沉积覆盖所述栅极区、源极区、漏极区、栅极接口区以及存储电容区的钝化层。
  10. 如权利要求9所述的方法，其特征在于，所述等离子处理，使位于所述源极区和漏极区且暴露的金属氧化物层金属化，成为部分源极和漏极的步骤具体为：
    于所述栅极区、源极区和漏极区氢化氮化硅SiNx:H绝缘保护层，该氢化过程直接将位于所述源极区和漏极区且暴露的金属氧化物层金属化，成为部分源极和漏极。
  11. 如权利要求7、8或10所述的方法，其特征在于，所述金属化位于所述源极区和漏极区且暴露的金属氧化物层，使之分别与已形成的部分源极和漏极电连接，形成完整的源极和漏极的步骤具体为：
    等离子处理，使位于所述源极区和漏极区且暴露的金属氧化物层金属化，并分别与已形成的部分源极和漏极电连接，形成完整的源极和漏极。
  12. 如权利要求11所述的方法，其特征在于，所述等离子处理，使位于所述源极区和漏极区且暴露的金属氧化物层金属化，并分别与已形成的部分源极和漏极电连接，形成完整的源极和漏极的步骤具体为：
    于所述栅极区、源极区和漏极区氢化氮化硅SiNx:H绝缘保护层，该氢化过程直接将位于所述源极区和漏极区且暴露的金属氧化物层金属化，并分别与已形成的部分源极和漏极电连接，形成完整的源极和漏极。
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US9583519B2 (en) 2017-02-28

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