WO2014117512A1

WO2014117512A1 - Method for preparing thin film transistor, method for preparing thin film transistor driving back panel, and thin film transistor driving back panel

Info

Publication number: WO2014117512A1
Application number: PCT/CN2013/082891
Authority: WO
Inventors: 徐苗; 周雷; 罗东向; 徐华; 李民; 庞佳威; 王琅; 王磊; 彭俊彪
Original assignee: 广州新视界光电科技有限公司
Priority date: 2013-02-04
Filing date: 2013-09-04
Publication date: 2014-08-07
Also published as: CN103094205B; CN103094205A

Abstract

Provided is a process for preparing a thin film transistor, which comprises: a. precipitating and patterning a metal conducting layer as a gate metal layer (03B) on a substrate (01); b. precipitating a first insulation thin film as a gate insulation layer (04) on the gate metal layer (03B); c. precipitating and patterning a metal oxide thin film as an active layer (05) on the gate insulation layer (04); d. precipitating a second insulation thin film on the active layer (05), and using a self-aligned exposure method to pattern the second insulation thin film as an etching barrier layer (06); e. precipitating a third insulation thin film as a protection layer (07) on the etching barrier layer (06), patterning the third insulation thin film, and forming a source-drain area by etching; and f. preparing and patterning a metal thin film layer (08) as a connecting wire on the protection layer (07). The process for preparing a thin film transistor is simple; and the prepared thin film transistor has good stability and a small size, and can achieve highly precise and low-cost manufacturing of a thin film transistor driving back panel. Also provided are a method for preparing a thin film transistor driving back panel and the prepared driving back panel.

Description

Thin film transistor, thin film transistor driving back plate manufacturing method and thin film transistor driving back plate

The present invention relates to the field of semiconductor technology, and in particular, to a thin film transistor, a method for fabricating a thin film transistor driving backplane, and a thin film transistor driving backplane prepared by the method. The present invention is based on an application for a Chinese patent application based on the application number 201310042927.7 and the application date being January 4, 2013.

Background technique

At present, the development of the flat panel display field is changing with each passing day. It has now been initially divided into two main product applications: one is a small-size display for mobile devices; the other is a large-size display for TVs. In both of these applications, higher pixel density, higher refresh rates, and lower power consumption are the industry's trends.

Thin film transistors (TFTs, Thin Film Transistors) are mainly used to control and drive liquid crystal displays (LCDs), sub-pixels of organic light-emitting diodes (OLED), which are in the field of flat panel display. The most important electronic device.

In the field of flat panel display, high pixel density means that more pixel units need to be arranged in the same area. The size of the thin film transistor determines the size of the pixel unit. Therefore, the small size of the thin film transistor is a prerequisite for achieving high pixel density. At the same time, for LCD displays, smaller size thin film transistors mean higher aperture ratios. When the display reaches the same brightness, the drive backplane with a higher aperture ratio requires less backlight brightness, which in turn reduces power consumption. On the other hand, if the parasitic capacitance of the thin film transistor is too large, it will affect the refresh rate of the driving backplane due to the limitation of the RC charging time, which may result in the failure of functions such as 3D display.

Therefore, the fabrication process of the thin film transistor array is developed, and each thin film transistor is guaranteed to have small size and low parasitic capacitance, and the display screen achieves high resolution, low power consumption, and high refresh frequency. The essential.

At present, the main structure used for the metal oxide thin film transistor driving backplane is an etch barrier structure and a back channel etch structure. Among them, the device fabricated by the back channel etching structure has poor stability, but a small-sized thin film transistor can be fabricated. The conventional etch barrier structure has good structural stability, but it is difficult to achieve small size and large parasitic capacitance, which is difficult to apply in high-definition displays and large-sized displays with high refresh rates.

The preparation of the thin film transistor driving backplane includes the preparation and subsequent processes of the thin film transistor, and the subsequent process is a common process in the field, but the preparation process of the thin film transistor directly determines the performance of the prepared thin film transistor and the thin film transistor driven backplane. Therefore, it is required to prepare a thin film transistor having high stability, small size, and low parasitic capacitance.

Therefore, in view of the deficiencies of the prior art, it is necessary to provide a thin film transistor having a simple process, high preparation stability, small size, and low parasitic capacitance, and a thin film transistor driving back plate composed of the thin film transistor. A high stability thin film transistor driver backplane is also provided.

Summary of the invention

SUMMARY OF THE INVENTION One object of the present invention is to provide a method for fabricating a thin film transistor which has a simple manufacturing process, a high stability of the prepared thin film transistor, a small size, and a low parasitic capacitance.

The above object of the present invention is achieved by the following technical means. A method for preparing a thin film transistor, comprising the following steps in sequence:

a. depositing and patterning a metal conductive layer on the substrate as a gate metal layer;

b. depositing a first insulating film on the gate metal layer as a gate insulating layer;

c. depositing a metal oxide film on the gate insulating layer and patterning as an active layer;

d. depositing a second insulating film on the active layer, and then patterning the second insulating film as an etch stop layer using a self-aligned exposure method;

Depositing a third insulating film as a protective layer on the etch barrier layer, and patterning the third insulating film to form a source/drain region;

f. Preparing and patterning a metal film layer on the protective layer as a connecting wire.

Patterning the second insulating film using the self-aligned exposure method in the above step d includes:

Forming a positive photoresist conforming to the shape of the gate metal layer on the second insulating film; and

The second insulating film not covering the positive photoresist is etched.

The positive photoresist prepared on the second insulating film and conforming to the shape of the metal conductive layer comprises:

Covering the second insulating film with a positive photoresist;

Using a gate metal layer as a self-aligned lithography mask;

Exposing the ultraviolet light from one side of the transparent substrate to expose the positive photoresist;

After development, a positive photoresist having a shape consistent with the gate metal layer is obtained;

Using a positive photoresist as a mask, the second insulating film is patterned using an etching method as an etch barrier.

The etching barrier layer has a thickness of 50 mn to 2000 nm; and the etching barrier layer is silicon dioxide, silicon nitride, aluminum oxide, hafnium oxide, titanium oxide, hafnium oxide, hafnium oxide, zirconium oxide, polyacryl A single layer film composed of an amine, a photoresist, styrenecyclobutene or polymethyl methacrylate, or a film of two or more layers composed of any combination of the above materials.

Preferably, in the method for preparing the thin film transistor, between the process steps d and e, a step y is further provided, and the step y is specifically: treating the active layer other than the etch barrier layer to a high level by using a post-processing method The conductive film forms a coplanar structure.

The post-processing method in the above step y is specifically: bombarding the film constituting the active layer with a plasma containing hydrogen, argon, oxygen or fluorine ions.

Further, the metal used for depositing and patterning the metal conductive layer on the substrate in the above step a is aluminum, copper, molybdenum, titanium, silver, gold, tantalum, tungsten, chromium or aluminum alloy;

The metal conductive layer is a single-layer aluminum film, a copper film, a molybdenum film, a titanium film, a silver film, a gold film, a tantalum film, a tungsten film, a chromium film or an aluminum alloy film; or two of the above single-layer metal films. a film above the layer;

The thickness of the metal conductive layer is set to be 100 nm to 2000 nm _;

The metal conductive layer serves as an electrical signal conductor, and the thin film transistor gate and the pixel circuit store a carrier layer of the lower electrode of the capacitor.

Further, the thickness of the first insulating film in the above step b is 50 nm to 500 nm;

The active layer in the step c has a thickness of 20 nm to 200 nm;

The semiconductor material constituting the active layer is a metal oxide!!^) ^. )!!^) , where 0 xl, O^y^ l , O^z^ l , and x+y+z=l, M is gallium, tin, silicon, aluminum, magnesium, lanthanum, cerium, lanthanum, nickel Any one or more of zirconium or lanthanide rare earth elements Combination

The thickness of the protective layer in the step e is set to 200 _nm to 5000 _nm , and the protective layer is silicon oxide, silicon nitride, aluminum oxide, titanium oxide, hafnium oxide, hafnium oxide, zirconium oxide, polyimide, a single-layer film composed of a photoresist, a styrene-butadiene or a polymethyl methacrylate layer, or a film of two or more layers composed of any combination of the above materials;

The metal used in the metal film layer in the step f is aluminum, copper, molybdenum, silver, gold, ruthenium, chromium, or titanium elemental or aluminum alloy or indium tin oxide transparent conductive film ITO;

The metal thin film layer has a thickness of 100 nm to 2000 nm;

The metal thin film layer is a single metal thin film or a multilayer metal thin film composed of a single metal thin film; the single metal thin film is a single film or aluminum alloy of aluminum, copper, molybdenum, silver, gold, bismuth, chromium or titanium. a thin film or an indium tin oxide transparent conductive film;

The metal thin film layer serves as a source and drain electrode of the thin film transistor, an upper electrode of the capacitor, and a carrier layer of the signal wiring, and is in communication with the metal conductive layer through the contact hole.

The method for fabricating the thin film transistor of the present invention uses the self-alignment method to form an etch barrier layer, which can greatly reduce the size of the thin film transistor. By maintaining the structural characteristics of the bottom gate and the etch barrier, the stability of the thin film transistor under various conditions of backlight, bias voltage and temperature can be ensured, and the number of masks can be reduced. The invention has the advantages of simple preparation process, good stability of the prepared thin film transistor, small size and low parasitic capacitance.

Another object of the present invention is to provide a method of fabricating a thin film transistor-driven backplane in which a thin film transistor is prepared by the method described above. The preparation method has the characteristics of simple manufacturing process, high stability of the prepared thin film transistor driving back plate, small size, and low parasitic capacitance.

A third object of the present invention is to provide a thin film transistor driving back sheet in which a thin film transistor is prepared by the method as described above. The thin film transistor drives the backplane with high stability, small size, and low parasitic capacitance.

DRAWINGS

The invention is further illustrated by the accompanying drawings, but the contents of the drawings do not constitute any limitation of the invention.

1 is a schematic view of a deposited and patterned metal conductive layer in accordance with an embodiment of the present invention;

2 is a schematic view of a gate insulating layer according to an embodiment of the present invention;

3 is a schematic view showing a deposition active layer according to an embodiment of the present invention;

4 is a schematic view of a deposition etch barrier layer according to an embodiment of the present invention;

Figure 5 is a schematic view showing self-aligned exposure and development of an embodiment of the present invention;

6 is a schematic view of a patterned etch barrier layer according to an embodiment of the present invention;

7 is a schematic diagram of processing an active layer other than an etch barrier layer as a high-conductivity film according to an embodiment of the present invention;

8 is a schematic view of fabricating a source and drain electrode according to an embodiment of the present invention;

Figure 9 is a schematic illustration of the fabrication and patterning of a metal film layer in accordance with an embodiment of the present invention.

In Figures 1 to 9, it includes:

Substrate 01, buffer layer 02, lower plate of capacitor 03A, gate of thin film transistor 03B, contact hole conductor 03C,

Gate insulating layer 04, active layer 05, high-conductivity film 05A, etch stop layer 06, protective layer 07,

Metal film layer 08, photoresist 10, Capacitor region, thin film transistor region 13, contact hole region C.

detailed description

The invention is further described in conjunction with the following examples.

Example 1.

A method for preparing a thin film transistor includes the following steps in sequence.

a. A metal conductive layer is deposited and patterned on the substrate as a gate metal layer.

Prior to performing this step a, silicon dioxide or silicon nitride may be pre-deposited as a buffer layer on a transparent substrate; step a specifically deposits and patterns a metal conductive layer as a gate metal layer on the buffer layer.

The metal used in the step of depositing and patterning the metal conductive layer on the substrate is aluminum, copper, molybdenum, titanium, silver, gold, tantalum, tungsten, chromium or an aluminum alloy.

The metal conductive layer is a single-layer aluminum film, a copper film, a molybdenum film, a titanium film, a silver film, a gold film, a tantalum film, a tungsten film, a chromium film or an aluminum alloy film; or two or more layers composed of the above single-layer metal film Film.

The thickness of the metal conductive layer is set to be 100 nm to 2000 nm _; the metal conductive layer serves as an electrical signal wire, the thin film transistor gate and the pixel circuit store the carrier layer of the lower electrode of the capacitor. After completing step a, proceed to step b.

Step b deposits a first insulating film on the gate metal layer as a gate insulating layer.

The first insulating film has a thickness of 50 nm to 500 nm. The first insulating film is a silicon dioxide, silicon nitride, aluminum oxide, tantalum pentoxide or tantalum oxide single-layer insulating film or a multilayer insulating film composed of two or more of the above-mentioned single-layer insulating films.

Further, in step c, a metal oxide film is deposited on the gate insulating layer and patterned as an active layer.

The active layer has a thickness of 20 nm to 200 nm. The semiconductor material constituting the active layer is a metal oxide (111 ₂ 0 ₃ ) _!( (3⁄410) ₇ (2110) ₂ , where 0 xl, O^y^ l , O^ z ^ l , and x+y +z=l, M is any combination of one or more of gallium, tin, silicon, aluminum, magnesium, lanthanum, cerium, lanthanum, nickel, zirconium or lanthanide rare earth elements;

Further, in step d, a second insulating film is deposited on the active layer, and then the second insulating film is patterned as an etch barrier using a self-aligned exposure method.

Forming a positive photoresist on the second insulating film in conformity with the shape of the gate metal layer;

The second insulating film not covering the positive photoresist is etched using an etchant.

Covering the second insulating film with a positive photoresist;

Using a gate metal layer as a self-aligned lithography mask;

Using a positive photoresist as a mask, a second insulating film is patterned using an dry etching method as an etch barrier. It should be noted that wet etching can also be used here.

The etching barrier layer has a thickness of 50 _nm to 2000 _{nm; the} etching barrier layer is silicon dioxide, silicon nitride, aluminum oxide, hafnium oxide, polyimide, photoresist, styrene butylene or polymethyl A single layer film composed of methyl acrylate or a multilayer film composed of the above insulating material. Then, proceeding to step e, depositing a third insulating film as a protective layer after the etching the barrier layer, and patterning the third insulating film to form a source/drain electrode region.

The thickness of the protective layer is set to 200 _nm ~ 5000 _nm , and the protective layer is silicon oxide, silicon nitride, aluminum oxide, titanium oxide, hafnium oxide, tantalum oxide, zirconium oxide, polyimide, photoresist, styrene ring A layer of ene or polymethyl methacrylate.

Returning to step f, a metal layer is prepared and patterned on the protective layer as a connecting wire.

The metal used in the metal thin film layer in the step f is aluminum, copper, molybdenum, silver, gold, ruthenium, chromium, or titanium, or an aluminum alloy or an indium tin oxide transparent conductive film ITO.

The metal thin film layer has a thickness of 100 nm to 2000 nm.

The metal thin film layer is a single metal thin film or a multilayer metal thin film composed of a single metal thin film; the single metal thin film is an aluminum, copper, molybdenum, silver, gold, rhodium, chromium, or titanium elemental film or an aluminum alloy film or oxidized. Indium tin transparent conductive film.

Wherein, the metal film layer is prepared by the following preparation process:

When the metal thin film layer is an inorganic thin film, it is prepared by a chemical plasma deposition system method, a physical vapor deposition method, an anodization method, an atomic layer deposition method or a pulsed laser film formation method;

When the metal thin film layer is an organic thin film, it is prepared by a spin coating method or a doctor blade method.

In the field of thin film transistor technology, the size of a thin film transistor is closely related to a specific line width CD value. The specific line width CD value is the minimum line width that the manufacturing process can achieve. Generally, the smaller the CD value, the higher the production cost. In order to realize a high-resolution display device, it is necessary to minimize the CD value of the thin film transistor.

The preparation process of the thin film transistor of the present invention can form an etch barrier layer by a self-alignment method, and the CD value can be artificially controlled by the bottom gate, and the size of the thin film transistor can be greatly reduced.

By maintaining the structural characteristics of the bottom gate and the etch barrier, the stability of the thin film transistor under various conditions of backlight, bias, and temperature can be ensured. It has been found through experiments that the thin film transistor prepared by the method of the present invention has an average pixel opening ratio of 68% when the thin film transistor is driven by the method of the present invention under the same CD value and 300 ppi display specification. The pixel aperture ratio of the prior art drive backplane is increased by about 50%. Therefore, the preparation process of the present invention can increase the pixel aperture ratio of the thin film transistor driving backplane, thereby reducing power consumption.

In the preparation process of the present invention, there is no overlapping area between the electrode and the bottom gate, so the parasitic capacitance is small.

The preparation process of the present invention uses the gate pattern for self-alignment, which can reduce the number of masks and reduce the manufacturing cost.

In summary, the preparation process of the invention has the advantages of simple preparation process, good stability of the prepared thin film transistor, small size, accurate size, low parasitic capacitance, etc., and can realize high definition and low cost of the thin film transistor driving back plate. Production.

Example 2.

A method of preparing a thin film transistor, the other steps are the same as in the first embodiment, except that: between the process steps d and e, a step y is further provided.

The step y is specifically: treating the active layer other than the etch barrier layer into a high-conductivity film to form a coplanar structure by using a post-processing method. The post-processing method in the step y is specifically: bombarding the film constituting the active layer with a plasma containing hydrogen, argon, oxygen or fluorine ions. The fabrication process of the thin film transistor of the present invention is performed by a self-aligned method to form an etch barrier layer, and the size of the thin film transistor can be greatly reduced by artificially controlling the CD value of the bottom gate.

By maintaining the structural characteristics of the bottom gate and the etch barrier, the stability of the thin film transistor under various conditions of backlight, bias, and temperature can be ensured. It has been found through experiments that the thin film transistor prepared by the method of the invention has an average pixel opening ratio of 70% under the same CD value and 300 ppi display specification. The pixel aperture ratio of the prior art drive backplane is increased by about 50%. Therefore, the preparation process of the present invention can increase the pixel aperture ratio of the thin film transistor driving backplane, thereby reducing power consumption.

Example 3.

A method of preparing a thin film transistor includes the following steps.

As shown in Figure 1, PVD (Physical Vapor) was used on an alkali-free glass substrate 01 with a 200 nm thick SiO ₂ buffer layer 02.

The Deposition method sequentially deposits a three-layer metal film of Mo/Al/Mo as a gate electrode, a capacitor lower electrode, and a signal wire, and has a thickness of 25 nm/100 nm/25 nm, respectively. It is patterned using a photolithography process to form a gate metal layer, where 03A is the lower plate of the capacitor, 03B is the gate of the thin film transistor, and 03C is the contact hole conductor.

It should be noted that the thickness of the metal conductive layer ranges from 100 nm to 2000 nm, and the specific size thereof can be flexibly set according to actual needs, and is not limited to the size of the embodiment. The constituent material of the metal conductive layer is not limited to the case of the present embodiment.

As shown in FIG. 2, a first insulating film is deposited on the patterned gate metal layer by a PECVD method (Plasma Enhanced Chemical Vapor Deposition), and the first insulating film is composed of 300 nm SiH^B 30 nm Si0 ₂ stack. The layer is formed as a gate insulating layer 04. It should be noted that the thickness of the first insulating film layer ranges from 50 nm to 500 nm, and the specific size thereof can be flexibly set according to actual needs, and is not limited to the size of the embodiment. The constituent material of the first insulating film layer is not limited to the case of the present embodiment.

As shown in Fig. 3, a 50 nm metal oxide IZO thin film (In: Zn atomic ratio of 1:1) was deposited by the PVD method as the active layer 05. It should be noted that the thickness of the active layer ranges from 20 nm to 200 nm, and the specific size thereof can be flexibly set according to actual needs, and is not limited to the size of the embodiment. The constituent material of the active layer is not limited to the case of the present embodiment.

As shown in FIG. 4, 100 nm of Si0 ₂ was deposited as a second insulating film by PECVD, and then a second insulating film was patterned as an etch barrier layer 06 using a self-aligned exposure method.

It should be noted that the thickness of the etch barrier layer ranges from 50 nm to 2000 nm, and the specific size thereof can be flexibly set according to actual needs, and is not limited to the size of the embodiment. The constituent material of the etching stopper layer is not limited to the case of the present embodiment.

Specifically, as shown in FIG. 5, the Ray Red 304 photoresist 10 is used, and the self-aligned exposure development is performed using the pattern of the gate metal layer.

As shown in FIG. 6, the second insulating film was etched using a dry etching apparatus using a volume flow ratio of the reaction gas CF ₄ /0 ₂ of 100/20 sccm.

As shown in Fig. 7, the surface of the substrate was treated with Ar plasma for 5 minutes. The active layer region without the etch barrier protection becomes the high-conductivity film 05A due to the bombardment of Ar ions. The high conductivity film has a resistivity as low as 4.3 x 10 - ³ Ω cm. Si0 _{2 having} a thickness of 300 nm was deposited as a protective layer 07 by PECVD. The protective layer 07 is etched using a dry etching apparatus using a volume flow ratio of the reaction gas CF ₄ /0 ₂ of 100 / 20 s _CCm . After the protective layer is etched, the etch stop layer of the A and C regions is further etched using a dry etch method. After the etch stop layer is etched, in the A and B regions, the etch atmosphere does not damage the gate insulating layer due to the active layer on the gate insulating layer for protection. For the C region, the dry etching gas further etches the etch barrier layer and the gate insulating layer, and finally forms a contact hole as shown in FIG. Where A is the capacitor region, B is the thin film transistor region, and C is the contact hole region.

As shown in FIG. 9, a Mo/Al/Mo laminated metal is prepared by using PVD as a source/drain electrode, a capacitor upper electrode, and a signal wire, respectively, having a thickness of 25 nm/100 nm/25 nm, and using wet etching to form Mo/Al. /Mo is patterned to form a metal thin film layer 08. The fabrication of the thin film transistor is completed.

The process can be used in the field of Liquid Crystal Display (LCD) and Active Matrix/Organic Light Emitting Diode (AMOLED).

The thin film transistor of the present invention fabricates an etch barrier by a self-aligned method, and the size of the thin film transistor can be greatly reduced by artificially controlling the CD value of the bottom gate.

By maintaining the structural characteristics of the bottom gate and the etch barrier, the stability of the thin film transistor under various conditions of backlight, bias, and temperature can be ensured. It has been found through experiments that the thin film transistor prepared by the method of the invention has a pixel aperture ratio of 69% driven by the method of the invention under the same CD value and 300 ppi display specification, compared with the existing one. 9%。 In the technology, the driving backplane pixel aperture rate is increased by about 49.9%. Therefore, the preparation process of the present invention can increase the pixel aperture ratio of the thin film transistor driving backplane, thereby reducing power consumption.

In summary, the preparation process of the invention has the advantages of simple preparation process, good stability of the prepared thin film transistor, small size, and accurate size, and can realize high-definition and low-cost fabrication of the thin film transistor driving back plate.

It should be noted that the size and ratio of the ratios involved in the present embodiment do not limit the preparation process of the thin film transistor of the present invention. In the actual preparation process, the user can flexibly adjust according to specific needs.

Example 4.

A method of preparing a thin film transistor includes the following steps.

The Deposition method sequentially deposits a three-layer Mo/Al/Mo metal film as a gate electrode, a capacitor lower electrode, and a signal wire, and has a thickness of 500 nm/2000 nm/500 nm, respectively. It is patterned using a photolithography process to form a gate metal layer, where 03A is the lower plate of the capacitor, 03B is the gate of the thin film transistor, and 03C is the contact hole wire.

As shown in FIG. 2, a first insulating film is deposited on the patterned gate metal layer by a PECVD method, and the first insulating film is made of a 500 nm SiN^ gate insulating layer 04.

As shown in FIG. 3, an 80 nm metal oxide IZO thin film (In: Zn atomic ratio of 1:1) was deposited by the PVD method as the active layer 05. As shown in FIG. 4, 2000 nm of SiO ₂ was deposited as a second insulating film by PECVD, and then a second insulating film was patterned as an etch barrier layer 06 using a self-aligned exposure method.

Specifically, as shown in FIG. 5, the Ray Red 304 photoresist 10 is used to perform self-aligned exposure development using the pattern of the gate metal layer. As shown in FIG. 6, the second insulating film was etched using a dry etching apparatus using a volume flow ratio of the reaction gas CF ₄ /0 ₂ of 100/20 sccm.

As shown in Fig. 7, the surface of the substrate was treated with Ar plasma for 5 minutes. The active layer region without the etch barrier protection becomes the high-conductivity film 05A due to the bombardment of Ar ions. The high conductivity film has a resistivity as low as 4.3 χ 10 - ³ Ω. ιη.

Si0 _{2 having} a thickness of 5000 nm was deposited as a protective layer 07 by PECVD. The protective layer 07 was etched using a dry etching apparatus using a volume flow ratio of the reaction gas CF4/0 ₂ of 100 / 20 sccm. After the protective layer is etched, the etch stop layer of the A and C regions is further etched using a dry etch method. After the etch stop layer is etched, in the A and B regions, the etch atmosphere does not damage the gate insulating layer due to the active layer on the gate insulating layer for protection. For the C region, the dry etching gas further etches the gate insulating layer, and finally forms a contact hole as shown in FIG. Where A is the capacitor region, B is the thin film transistor region, and C is the contact hole region.

As shown in FIG. 9, a Mo/Al/Mo laminated metal is prepared by using PVD as a source/drain electrode, a capacitor upper electrode, and a signal wire, respectively, having a thickness of 500 nm/2000 nm/500 nm, and using wet etching, Mo/Al/ Mo is patterned to form a metal thin film layer 08. The fabrication of the thin film transistor is completed.

By maintaining the structural characteristics of the bottom gate and the etch barrier, the stability of the thin film transistor under various conditions of backlight, bias, and temperature can be ensured. It has been found through experiments that the thin film transistor prepared by the method of the invention has a pixel aperture ratio of 69% driven by the method of the invention under the same CD value and 300 ppi display specification, compared with the existing one. The drive backplane pixel aperture ratio in the technology is increased by about 50%. Therefore, the preparation process of the present invention can increase the pixel aperture ratio of the thin film transistor driving backplane, thereby reducing power consumption.

Example 5.

A method of preparing a thin film transistor includes the following steps.

As shown in Figure 1, PVD (Physical Vapor) was used on an alkali-free glass substrate 01 with a 200 nm thick SiO ₂ buffer layer 0 ₂ .

The Deposition method deposits a 400 nm copper film as a gate, a capacitor lower electrode, and a signal conductor. It is patterned into a gate metal layer 03 using a photolithography process, wherein 03A is the lower plate of the capacitor, 03B is the gate of the thin film transistor, and 03C is the contact hole wire.

As shown in FIG. 2, on the patterned gate metal layer, a 200 nm A1 ₂ 0 ₃ first insulating film is deposited as a gate insulating layer 04 by an Atomic layer deposition method (ALD).

As shown in FIG. 3, a 100 nm metal oxide IGZO (In, Ga, Zn atom molar ratio of 1:2:1) was deposited as the active layer 05 by a PVD method. It should be noted that the metal oxide of the active layer is not limited to the IGZO in the present embodiment, and the 30 mn metal oxide ISZO may be deposited by the PVD method (the atomic molar ratio of In, Si, and Zn is 1:0.1:1). ) as the active layer 05.

As shown in FIG. 4, 200 nm of A10 _x was deposited as a second insulating film by an ALD method, and then a second insulating film was patterned as an etch barrier layer 06 using a self-aligned exposure method.

As shown in Fig. 6, using a dry etching apparatus, a volume flow ratio of the reaction gas C1 ₂ /BC1 ₃ was 35 /5 sccm, and etching was performed using an inductively coupled plasma etching apparatus.

As shown in Fig. 7, the surface of the substrate was treated with CHF ₃ plasma for 2 minutes. The active layer region without the etch barrier protection becomes the high conductivity film 05A due to the bombardment of H ions. The high-conductivity film has a resistivity as low as 2.8 x 10 - ³ Ω. ιη.

Si0 _{2 having} a thickness of 500 nm was deposited as a protective layer 07 by PECVD. The protective layer 07 was etched using a dry etching apparatus using a volume flow ratio of the reaction gas CF ₄ /0 ₂ of 100 / 20 sccm. After the protective layer is etched, replace the etching gas with C1 ₂ /BC1 ₃ and continue etching the etch barrier layers in the A and C regions. After the etch stop layer is etched, in the A and B regions, the etch atmosphere does not damage the gate insulating layer due to the active layer on the gate insulating layer for protection. For the C region, the replaced C1 ₂ /BC1 ₃ will further etch the gate insulating layer and finally form a contact hole as shown in FIG. Where A is the capacitor region, B is the thin film transistor region, and C is the contact hole region.

As shown in FIG. 9, a Mo/Al/Mo laminated metal is prepared using PVD as a source/drain electrode, a capacitor upper electrode, and a signal wire, respectively, having a thickness of 30 nm/150 nm/28 nm, and using wet etching to form Mo/Al. /Mo is patterned to form a metal thin film layer 08. The fabrication of the thin film transistor is completed.

The thin film transistor of the present invention fabricates an etch barrier layer by a self-aligned method, and the CD value can be artificially controlled by the bottom gate to greatly reduce the size of the thin film transistor.

By maintaining the structural characteristics of the bottom gate and the etch barrier, the stability of the thin film transistor under various conditions of backlight, bias, and temperature can be ensured. It has been found through experiments that the thin film transistor prepared by the method of the present invention can achieve a pixel aperture ratio of 70% by the method of the present invention under the same CD value and 300 ppi display specification, compared with the existing one. In the technology, the driver backplane pixel aperture rate is increased by about 50%. Therefore, the preparation process of the present invention can increase the pixel aperture ratio of the thin film transistor driving backplane, thereby reducing power consumption.

According to the preparation process of the present invention, there is no overlapping area between the electrode and the bottom gate, so the parasitic capacitance is small.

In summary, the preparation process of the invention has the advantages of simple preparation process, good stability of the prepared thin film transistor and accurate size, and can realize high-definition and low-cost fabrication of the thin film transistor driving back plate.

It should be noted that the size and the proportion of the ratio involved in the embodiment do not limit the manufacturing process of the thin film transistor driving back plate of the present invention. In the actual preparation process, the user can flexibly adjust according to specific needs.

Example 6.

A method of preparing a thin film transistor includes the following steps.

Deposition) deposits a 50 nm tungsten film as a gate, a capacitor lower electrode, and a signal conductor. It is patterned using a photolithography process to form a gate metal layer 03, where 03A is the lower plate of the capacitor, 03B is the gate of the thin film transistor, and 03C is the contact hole wire. As shown in FIG. 2, on the patterned gate metal layer, a 50 nm A1 ₂ 0 ₃ first insulating film is deposited as a gate insulating layer 04 by an Atomic layer deposition method (ALD).

As shown in Fig. 3, a 20 nm metal oxide IGZO (In, Ga, Zn atom molar ratio of 1:2:1) was deposited by the PVD method as the active layer 05.

As shown in FIG. 4, 50 nm of A10 _x was deposited as a second insulating film by an ALD method, and then a second insulating film was patterned as an etch barrier layer 06 using a self-aligned exposure method.

As shown in Fig. 7, the surface of the substrate was treated with CHF ₃ plasma for 2 minutes. The active layer region without the etch barrier protection becomes the high conductivity film 05A due to the bombardment of H ions. The high conductivity film has a resistivity as low as 2.8 x 10 - ³ Ω cm.

Si0 _{2 having} a thickness of 200 nm was deposited as a protective layer 07 by PECVD. Using a dry etching apparatus, the protective layer 07 is first etched by using a volume flow ratio of the reaction gas CF ₄ /0 ₂ of 100 / 20 sccm. After the protective layer is etched, the etching atmosphere is changed to C1 ₂ /BC1 ₃ to continue etching the etch barrier layers of the A and C regions. After the etch stop layer is etched, in the A and B regions, the etch atmosphere does not damage the gate insulating layer due to the active layer on the gate insulating layer for protection. For the area C, the reaction gas _(12/13 ₍₁₃ to further etching the gate insulating layer, and finally a contact hole is formed, as shown in FIG. Wherein A is the capacitor area, B is a thin film transistor region, contact hole C region.

By maintaining the structural characteristics of the bottom gate and the etch barrier, the stability of the thin film transistor under various conditions of backlight, bias, and temperature can be ensured. It has been found through experiments that the thin film transistor prepared by the method of the present invention can achieve a pixel aperture ratio of 71% in the thin film transistor driving back panel prepared by the method of the present invention under the same CD value and 300 ppi display specification, compared with the existing one. In the technology, the driver backplane pixel aperture rate is increased by about 50%. Therefore, the preparation process of the present invention can increase the pixel aperture ratio of the thin film transistor driving backplane, thereby reducing power consumption.

Example 7.

A method for fabricating a thin film transistor-driven backplane, using the method of any one of the above embodiments 1 to 3 to prepare a thin film transistor, and the thin film transistor is completed and then enters a subsequent process.

The subsequent process is a conventional process in the art that deposits and patterns the transparent electrode and the protective layer in accordance with the corresponding requirements of the drive backplane. For example, for the LCD driving backplane, a flat layer and a transparent electrode are sequentially prepared; for OLEDs, a flat layer, an OLED anode, and a pixel defining layer are sequentially prepared, or only a pixel defining layer is prepared as the case may be.

In the preparation method of the present invention, the thin film transistor process part can be completed by four masks. For the LCD or 0LED, the total number of masks is 5-7 masks. Therefore, the process is simple, and the thin film transistor channel is determined by the gate width, so that it can meet the requirements for fabricating short channel devices. At the same time, the bottom gate etch barrier structure can ensure device stability.

Therefore, the preparation process is simple, the prepared thin film transistor driving back plate has high stability and accurate size, and the thin film transistor driving back plate can be realized with high definition and low cost.

Example 8.

A thin film transistor driven backplane was prepared by the method described in Example 4. Since the thin film transistor channel is determined by the gate width, it can meet the requirements for fabricating a short channel device. At the same time, the bottom gate etch barrier structure can ensure device stability. Therefore, the prepared thin film transistor driving back plate has the characteristics of high stability and accurate size, and can realize high-definition and low-cost fabrication of the thin film transistor driving back plate.

It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the scope of the present invention. Although the present invention is described in detail with reference to the preferred embodiments, those skilled in the art The technical solutions of the present invention are modified or equivalently substituted without departing from the spirit and scope of the technical solutions of the present invention.

Industrial applicability

The preparation method of the thin film transistor of the invention, the preparation method of the thin film transistor driving back plate and the prepared driving back plate have the advantages of simple preparation process, good stability of the prepared thin film transistor, small size and low parasitic capacitance, and can be realized. The thin film transistor drive back plate is highly refined and low-cost, and has good industrial applicability.

Claims

Claim

A method of fabricating a thin film transistor, comprising the steps of:

c depositing a metal oxide film on the gate insulating layer and patterning as an active layer;

d. depositing a second insulating film on the active layer, and then patterning the second insulating film as an etch barrier using a self-aligned exposure method;

Depositing a third insulating film as a protective layer on the etch barrier layer, and patterning the third insulating film to form a source/drain electrode region;

2. The method of fabricating a thin film transistor according to claim 1, wherein:

Patterning the second insulating film using the self-aligned exposure method in the step d includes:

The second insulating film not covering the positive photoresist is etched.

3. The method of fabricating a thin film transistor according to claim 2, wherein:

Forming a positive photoresist on the second insulating film in conformity with the shape of the metal conductive layer, specifically comprising: covering the second insulating film with a positive photoresist;

Using a gate metal layer as a self-aligned lithography mask;

4. The method of fabricating a thin film transistor according to claim 3, wherein:

The thickness of the etch stop layer 50 _n m~2000 _nm; the etch stop layer is silicon dioxide, silicon nitride, aluminum oxide, ytterbium oxide, titanium oxide, hafnium oxide, tantalum oxide, zirconium oxide, poly A single-layer film composed of an imide, a photoresist, styrene-butadiene or polymethyl methacrylate, or a film of two or more layers composed of any combination of the above materials.

5. The method of fabricating a thin film transistor according to claim 1, wherein:

Between the process steps d and e, a step y is further provided. The step y is specifically: treating the active layer other than the etch stop layer protection into a high-conductivity film to form a coplanar structure by using a post-processing method.

6. The method of fabricating a thin film transistor according to claim 5, wherein: The post-processing method in the step y is specifically: bombarding the film constituting the active layer with a plasma containing hydrogen, argon, oxygen or fluoride ions.

7. The method of fabricating a thin film transistor according to claim 6, wherein:

The metal used for depositing and patterning the metal conductive layer on the substrate in the step a is aluminum, copper, molybdenum, titanium, silver, gold, tantalum, tungsten, chromium or aluminum alloy;

The thickness of the metal conductive layer is set to be 100 nm to 2000 nm _;

8. The method of fabricating a thin film transistor according to claim 6, wherein:

The thickness of the first insulating film in the step b is 50 nm to 500 nm;

The active layer in the step c has a thickness of 20 nm to 200 nm;

The semiconductor material constituting the active layer is a metal oxide (ln ₂ 0 ₃ ) _x (MO) _y (ZnO) _z , where 0 x 1, 0 y 1, O^z^ l , and _X +y+z =l, M is one or a combination of two or more of gallium, tin, silicon, aluminum, magnesium, lanthanum, cerium, lanthanum, nickel, zirconium or lanthanide rare earth elements;

The thickness of the protective layer in step e to 200 _n m~5000 nm, the protective layer is a silicon oxide, silicon nitride, aluminum oxide, titanium oxide, hafnium oxide, tantalum oxide, zirconium oxide, polyimide a single-layer film composed of a photoresist, a styrene-butadiene or a polymethyl methacrylate layer, or a film of two or more layers composed of any combination of the above materials;

The metal thin film layer has a thickness of 100 nm to 2000 nm;

The metal thin film layer is a single metal thin film or a multilayer metal thin film composed of a single metal thin film; the single metal thin film is a single film or aluminum alloy of aluminum, copper, molybdenum, silver, gold, bismuth, chromium or titanium. a thin film or an indium tin oxide transparent conductive film; the metal thin film layer serves as a source and drain electrode of the thin film transistor, an upper electrode of the capacitor, and a carrier layer of the signal wire, and is in communication with the metal conductive layer through the contact hole.

A method of producing a thin film transistor-driven back sheet, characterized in that a thin film transistor is produced by the method according to any one of claims 1 to 8.

A thin film transistor-driven backplane, which is produced by the method of claim 9.