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WO2014182239A1 - Modules de cartes à puce ultra-minces ayant des bosses de connexion disposées dans des vias d'un substrat et procédés de fabrications de ceux-ci - Google Patents

Modules de cartes à puce ultra-minces ayant des bosses de connexion disposées dans des vias d'un substrat et procédés de fabrications de ceux-ci Download PDF

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Publication number
WO2014182239A1
WO2014182239A1 PCT/SG2013/000182 SG2013000182W WO2014182239A1 WO 2014182239 A1 WO2014182239 A1 WO 2014182239A1 SG 2013000182 W SG2013000182 W SG 2013000182W WO 2014182239 A1 WO2014182239 A1 WO 2014182239A1
Authority
WO
WIPO (PCT)
Prior art keywords
chip
conductive
substrate
conductive pattern
smart card
Prior art date
Application number
PCT/SG2013/000182
Other languages
English (en)
Inventor
Eng Seng NG
Sze Yong PANG
Original Assignee
Smartflex Technology Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Smartflex Technology Pte Ltd filed Critical Smartflex Technology Pte Ltd
Priority to PCT/SG2013/000182 priority Critical patent/WO2014182239A1/fr
Publication of WO2014182239A1 publication Critical patent/WO2014182239A1/fr

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    • H01L2224/832—Applying energy for connecting
    • H01L2224/83201—Compression bonding
    • H01L2224/83203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • Embodiments of the invention relate to ultra-thin smart card modules and methods of fabricating such ultra-thin smart card modules.
  • Smart cards which contain a chip module mounted or inserted into a card carrier body, are used in a variety of applications, e.g. telecommunications, payment cards, etc. Due to the universal demand for smart cards, there have been numerous chip module arrangements and methods of production which attempt to increase reliability and form factor of the chip module.
  • Figure 1 is a cross-sectional view of a chip module 100 which comprises a substrate 110, a conductor layer 120 of copper, gold and nickel applied to a first side of the substrate, a chip 130 arranged on a second opposed side of the substrate, gold wire bonds 150 connecting the chip 130 to the conductor layer 120, and a mold cap 140 encapsulating the wire-bonded chip 130.
  • the wire bonds 50 are connected from the rear side of a bonding hole on the substrate 110 to the conductive pads of the chip 130.
  • the conductor layer 120 is to provide a contact surface to a desired application, e.g. phone or reader terminal. As breakage of the wire bonds 150 is the most common cause of package failure, there is a lower limit to the length of the wire bonds 150 in order to prevent breakage.
  • FIG. 2 is a cross-sectional view of a chip module 200 which comprises a PET substrate 210, conductor layers 220 of gold, nickel and copper applied to both sides of the substrate 210, a chip 230 arranged on one side of the substrate 210, and conductive bumps 250 of the chip 230 seated on one of the two conductor layers 220.
  • the conductor layer 220 which is remote from the bumps 250 is to provide a contact surface to a desired application, e.g. phone or reader terminal.
  • Embodiments of the invention relate to ultra-thin smart card modules that can achieve a module thickness of less than 500 microns.
  • a smart card module comprises a substrate having a first conductive pattern on a first face, a second face that is opposite the first face, and a plurality of via holes; at least a chip having a first plurality of conductive bumps formed on a first major surface of the chip, the chip being arranged so that the first plurality of conductive bumps are disposed in the plurality of via holes and electrically connected to the first conductive pattern; an encapsulant disposed to encapsulate the chip; and an underfill material disposed at least in a space between the chip and the second face of the substrate.
  • a method of fabricating a smart card module comprises: providing at least a chip which is attached with a first plurality of conductive bumps; providing a substrate being perforated with via holes and having a first conductive pattern applied on a first face of the substrate; providing an underfill material on the substrate; arranging the chip on the substrate so that the first plurality of conductive bumps are disposed in the via holes; curing the underfill material; and encapsulating the chip.
  • FIGS 1 and 2 illustrate existing chip modules
  • Figure 3 shows a schematic cross-sectional illustration of a smart card module according to one embodiment of the invention
  • Figure 4 shows a schematic cross-sectional illustration of a smart card module according to another embodiment of the invention.
  • Figure 5A shows a schematic cross-sectional illustration of a smart card module according to another embodiment of the invention.
  • Figure 5B shows a schematic cross-sectional illustration of a dual interface smart card module according to another embodiment of the invention.
  • Figure 5C shows a schematic cross-sectional illustration of a multi-chip smart card module according to another embodiment of the invention.
  • Figure 6 shows a schematic cross-sectional illustration of a smart card module according to another embodiment of the invention
  • Figure 7 illustrates a method of fabricating a smart card module of Figure 3
  • Figure 8 illustrates a method of fabricating a smart card module of Figure 4.
  • the present invention provides ultra-thin smart card modules which are configured for contact, contactless, dual interface and/or multi-chips smart card applications.
  • the module package structures and methods for producing the same will be described in the following paragraphs.
  • Figure 3 shows a schematic cross-sectional illustration of a smart card module
  • the smart card module 300 comprises a substrate 310 having a first conductive pattern 320 on a first face, a second face that is opposite the first face, and a plurality of via holes.
  • the substrate 310 having a first conductive pattern 320 on a first face, a second face that is opposite the first face, and a plurality of via holes.
  • the substrate 3 0 may be provided as a flexible substrate so that bending loads on the smart card containing the module are absorbed in particular by non-encapsulated edge regions of the module.
  • the substrate 310 may include glass epoxy, polyimide, polyethylene naphthalate (PEN), polyethylene terephthalate (PET) or other suitable materials.
  • the first conductive pattern 320 is to provide a contact surface which is to be interfaced or electrically connected with a desired application, e.g. handphone.
  • the first conductive pattern 320 includes copper and nickel, and is free of gold.
  • the first conductive pattern 320 includes copper, nickel and gold.
  • the substrate 310 is perforated with via holes which extend from the first face to the second face of the substrate 3 0.
  • the smart card module 300 of Figure 3 further comprises a chip 330 having a first plurality of conductive bumps 350 formed on a first major surface of the chip 330.
  • the chip 330 is being arranged so that the first plurality of conductive bumps 350 are disposed in the plurality of via holes and electrically connected to the first conductive pattern 320.
  • the chip 330 may be provided as a flip chip having the first plurality of conductive bumps 350 formed on an active area of the chip 330.
  • the chip 330 is mounted on the second face of the substrate 310 such that the conductive bumps 350 are seated in the via holes and on the first conductive pattern 320.
  • the smart card module 300 of Figure 3 further comprises an encapsulant 340 disposed to fully encapsulate the chip 330 to protect the chip 330 from environment and mechanical stresses.
  • the encapsulant 340 may be provided as a mold compound, thermal or ultraviolet (UV) cured resin or other suitable materials.
  • An underfill material 360 is disposed at least in a space between the chip 330 and the second face of the substrate 310 to reduce stress due to mismatch of the coefficient of thermal expansion of the chip 330 and the substrate 310.
  • the underfill material 360 may fill the via holes and act as an adhesive to bond the first plurality of conductive bumps 350 to the substrate 310.
  • FIG. 4 shows a schematic cross-sectional illustration of a smart card module 400 according to another embodiment of the invention.
  • the via holes are provided with thin conductive coatings 470 on the walls of the via holes.
  • the conductive coatings 470 extend from a first end of the via holes to a second end which is distal to the first end.
  • Conductive coatings 470 disposed at the first end of the via holes are electrically connected to the first conductive pattern 420.
  • Conductive coatings 470 disposed at the second end of the via holes are electrically connected to the first plurality of conductive bumps 450 of the chip 430, which are seated thereon.
  • the first plurality of conductive bumps 450 of the chip 430 are electrically connected to the first conductive pattern 420 through the conductive coatings 470.
  • an underfill material 460 is disposed in a space between the chip 430 and the second face of the substrate 410.
  • the via holes may be substantially free of the underfill material 460.
  • Figure 5A shows a schematic cross-sectional illustration of a smart card module 500A according to another embodiment of the invention.
  • the substrate 510 includes a first conductive pattern 520, and further includes a second conductive pattern 522 which is provided on the second face of the substrate 510.
  • the chip 530 is provided with a first plurality of conductive bumps 550 which are electrically connected to the first conductive 520 pattern, and a second plurality of conductive bumps 552 which are electrically connected to the second conductive pattern 522.
  • the first plurality of conductive bumps 550 are disposed in the via holes.
  • the first plurality of conductive bumps 550 are seated on the first conductive pattern 520.
  • the second plurality of conductive bumps 552 are seated on the second conductive pattern 522.
  • An encapsulant 540 is disposed to fully encapsulate the chip 530 and the second conductive pattern 522.
  • An underfill material 560 is disposed in a space between the chip 530 and the second face of the substrate 510 and in a space between the chip 530 and the second conductive pattern 522. The via holes may also be filled with the underfill material 560.
  • Figure 5B shows a schematic cross-sectional illustration of a smart card module 500B according to another embodiment of the invention.
  • the encapsulant 540B is disposed to fully encapsulate the chip 530 and partially encapsulate the second conductive pattern 522.
  • the embodiment of Figure 5B may be used in a dual interface smartcard where the first conductive pattern 520 is to be electrically connected to a contact interface whereas the second conductive pattern 522 is an antenna pad to be electrically connected to a radio frequency circuit external of the second conductive pattern 522.
  • the second conductive pattern 522 may be disposed with a radio frequency circuit within for implementing an antenna device.
  • FIG. 5C shows a schematic cross-sectional illustration of a smart card module 500C according to another embodiment of the invention.
  • the smart card module of Figure 5C includes a plurality of chips 530A, 530B which are electrically connected to a first conductive pattern 520 and a plurality of second conductive patterns 522A, 522B.
  • An encapsulant 540 is disposed to fully encapsulate the chips 530A, 530B and the plurality of second conductive patterns 522A, 522B.
  • Figure 6 shows a schematic cross-sectional illustration of a smart card module 600 according to another embodiment of the invention.
  • the via holes are provided with thin conductive coatings 670 on the walls of the via holes.
  • the conductive coatings 670 extend from a first end of the via holes to a second end which is distal to the first end.
  • Conductive coatings 670 disposed at the first end of the via holes are electrically connected to the first conductive pattern 620.
  • Conductive coatings 670 disposed at the second end of the via holes are electrically connected to the first plurality of conductive bumps 650 of the chip 630, which are seated thereon.
  • the first plurality of conductive bumps 650 of the chip 630 are electrically connected to the first conductive pattern 620 through the conductive coatings 670.
  • the second plurality of conductive bumps 652 are seated on the second conductive pattern 622 to be electrically connected thereto.
  • the first and the second conductive patterns may or may not be electrically connected to each other depending on product requirements.
  • the first conductive pattern may be connected to a contact interface for smart card applications while the second conductive pattern may be connected to a contactless interface, e.g. radio frequency circuit (not shown) for smart card applications. Routing connections from the conductive patterns to the contact or contactless interface are known in the art and will not be described here.
  • Figure 7 illustrates a method 700 of fabricating a smart card module such as the module of Figure 3.
  • the method includes providing a semiconductor chip or die which is attached with a first plurality of conductive bumps (block 702).
  • the method also includes providing a substrate that is perforated with via holes and having a first conductive pattern applied on a first face of the substrate (block 704).
  • Via holes may be formed in the substrate by suitable methods, e.g. punching or laser drilling.
  • the via holes are suitably positioned to complement the arrangement of the first plurality of conductive bumps of the chip.
  • the first conductive pattern may be applied to the substrate by a photo-etching process on a copper layer which is laminated onto the substrate. After the photo-etching process, the substrate undergoes a plating process to plate nickel onto the etched copper layer to provide the first conductive pattern.
  • An underfill material or adhesive is dispensed onto the substrate (block 706).
  • the underfill material may be a conductive or non-conductive paste.
  • the chip is arranged on the substrate so that the first plurality of conductive bumps are disposed in via holes (block 708). More particularly, the first plurality of conductive bumps are seated on the first conductive pattern.
  • the assembly obtained at this stage is then subject to thermal compression (block 710).
  • the thermal compression process cures the underfill material to bond the first plurality of conductive bumps to the substrate and to collapse the first plurality conductive bumps within the via holes.
  • the chip is encapsulated (block 712). This can be done by providing an encapsulant over the chip and thereafter curing the encapsulant.
  • Figure 8 illustrates a method of fabricating a smart card module such as the module of Figure 4.
  • the method includes providing a semiconductor chip or die which is attached with conductive bumps (block 802).
  • the method also includes providing a substrate that is perforated with via holes, the substrate having a first conductive pattern applied on a first face of the substrate, and having conductive coatings provided on walls of the via holes (block 804).
  • Via holes may be formed in the substrate by suitable methods, e.g. punching or laser drilling.
  • the via holes are suitably positioned to complement the arrangement of conductive bumps of the chip.
  • the first conductive pattern may be applied to the substrate by a photo-etching process on a copper layer which is laminated onto the substrate. After the photo- etching process, the substrate undergoes a plating process to plate nickel onto the etched copper layer to provide the first conductive pattern.
  • the underfill material may be a conductive or non-conductive paste.
  • the chip is arranged on the substrate so that the first plurality of conductive bumps are disposed in the via holes (block 808). More particularly, the conductive bumps are seated on the conductive coatings of the via holes.
  • the assembly obtained at this stage is then subject to thermal compression (block 810).
  • the thermal compression process cures the underfill material to bond the conductive bumps to the substrate and to slightly collapse the conductive bumps onto the conductive coatings.
  • the chip is encapsulated (block 812). This can be done by providing an encapsulant over the chip and thereafter curing the encapsulant.
  • the semiconductor chip is provided with a first plurality of conductive bumps having a first height and a second plurality of conductive bumps having a second height which is different from the first height.
  • the substrate is further provided with a second conductive pattern on a second face of the substrate, which is opposite to the first face of the substrate.
  • the chip is arranged on the substrate so that the first plurality of conductive bumps are disposed in the via holes and the second plurality of conductive bumps are disposed or seated on the second conductive pattern.
  • the chip and the second conductive pattern are encapsulated.
  • Embodiments of the invention are advantageous in achieving an ultra-thin chip module thickness of 200 microns to less than 500 microns.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

La présente invention concerne des modules de cartes à puces ultra-minces (300, 400, 500A, 500B, 500C, 600) permettant d'obtenir une épaisseur de boîtier de moins de 500 micromètres. Un tel module de carte à puce (300, 400, 500A, 500B, 500C, 600) comprend un substrat (310, 410, 510, 610) ayant un premier motif conducteur (320, 420, 520, 620) sur une première face, une deuxième face qui est opposée à la première face, et une pluralité de vias ; au moins une puce (330, 430, 530, 530A, 530B, 630) ayant une première pluralité de bosses conductrices (350, 450, 550, 650) formée sur une première surface principale de la puce (330, 430, 530, 530A, 530B, 630), la puce (330, 430, 530, 530A, 530B, 630) étant agencée de telle sorte que la première pluralité de bosses conductrices (350, 450, 550, 650) soit disposée dans la pluralité de vias et connectée électriquement au premier motif conducteur (320, 420, 520, 620) ; un encapsulant (340, 440, 540, 540B, 640) disposé pour encapsuler la puce (330, 430, 530, 530A, 530B, 630) ; et un matériau de remplissage sous-jacent (360, 460, 560, 660) disposé au moins dans un espace situé entre la puce (330, 430, 530, 530A, 530B, 630) et la deuxième face du substrat (310, 410, 510, 610). La première pluralité de bosses conductrices (350, 450, 550, 650) peut être liée à la pluralité de vias à travers le matériau de remplissage sous-jacent (360, 560) ou, d'une autre manière, peut être assise sur une pluralité de revêtements conducteurs (470, 670) prévus dans la pluralité de vias et connectés électriquement au premier motif conducteur (420, 620). Le substrat (510, 610) peut comporter un deuxième motif conducteur (522, 522A, 522B, 622) sur la deuxième face, auquel cas la puce (530, 530A, 530B, 630) comporte en outre une deuxième pluralité de bosses conductrices (552, 652) formée sur la première surface principale et disposée sur le deuxième motif conducteur (522, 522A, 522B, 622) et connectée électriquement à celui-ci. Pendant le procédé de fabrication du module de carte à puce (300, 400, 500A, 500B, 500C, 600), le matériau de remplissage sous-jacent (360, 460, 560, 660) est prévu sur le substrat (310, 410, 510, 610) avant le placement de la puce (330, 430, 530, 530A, 530B, 630) et durci après l'agencement de la puce (330, 430, 530, 530A, 530B, 630) de telle sorte que la première pluralité de bosses conductrices (350, 450, 550, 650) soit disposée dans les vias.
PCT/SG2013/000182 2013-05-07 2013-05-07 Modules de cartes à puce ultra-minces ayant des bosses de connexion disposées dans des vias d'un substrat et procédés de fabrications de ceux-ci WO2014182239A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/SG2013/000182 WO2014182239A1 (fr) 2013-05-07 2013-05-07 Modules de cartes à puce ultra-minces ayant des bosses de connexion disposées dans des vias d'un substrat et procédés de fabrications de ceux-ci

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/SG2013/000182 WO2014182239A1 (fr) 2013-05-07 2013-05-07 Modules de cartes à puce ultra-minces ayant des bosses de connexion disposées dans des vias d'un substrat et procédés de fabrications de ceux-ci

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