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WO2013127201A1 - Array substrate, manufacturing method and display device thereof - Google Patents

Array substrate, manufacturing method and display device thereof Download PDF

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Publication number
WO2013127201A1
WO2013127201A1 PCT/CN2012/084957 CN2012084957W WO2013127201A1 WO 2013127201 A1 WO2013127201 A1 WO 2013127201A1 CN 2012084957 W CN2012084957 W CN 2012084957W WO 2013127201 A1 WO2013127201 A1 WO 2013127201A1
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WIPO (PCT)
Prior art keywords
insulating layer
layer
gate
array substrate
etching
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PCT/CN2012/084957
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French (fr)
Chinese (zh)
Inventor
牛菁
刘圣烈
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京东方科技集团股份有限公司
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Publication of WO2013127201A1 publication Critical patent/WO2013127201A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device. Background technique
  • the active layer of a thin film transistor has always used a silicon-based material which is excellent in performance such as stability and workability.
  • Silicon-based materials are mainly classified into amorphous silicon and polycrystalline silicon, among which the mobility of amorphous silicon materials is very low, and although the polysilicon materials have high mobility, the uniformity of devices fabricated by them is poor, the yield is low, and the unit price is high. . Therefore, in recent years, a transparent oxide semiconductor film has been used for a channel formation block to manufacture a semiconductor active layer of a device such as a thin film transistor (TFT), and has been widely used in electronic devices and optical devices.
  • a field effect transistor using an amorphous In-Ga-Zn-0 material (a-IGZO) composed of indium, gallium, rhodium and oxygen as a constituent element has a higher mobility and a larger switching ratio. The most attention.
  • the cross-sectional structure of the existing oxide TFT technology is shown in Fig. 1.
  • An oxide layer 102 is first deposited on the substrate 101, and the gate electrode 104 is on the oxide layer and separated from the oxide layer by the first insulating layer 103, and the first insulating layer 103 covers the entire substrate surface.
  • the source/drain electrodes 106 are each composed of a metal material having a small electrical resistance, and are directly disposed on a Gate Insulation (GI) 105 and connected to the oxide layer through via holes in the gate insulating layer.
  • the pixel electrode 108 is disposed on a protective layer (PVX, also referred to as a passivation layer) 107, and a via hole is formed in the protective layer to connect the pixel electrode to the drain metal (including the data line).
  • PVX also referred to as a passivation layer
  • a protective layer is disposed between the pixel electrode and the drain in the prior art, in order to ensure the connection between the two, a plurality of via holes are required to be disposed on the protective layer, which is difficult in the process. If the conductive film of the pixel electrode is first deposited, such as ITO (Indium Tin Oxides), and then the source/drain metal layer is directly deposited thereon so that the two are directly connected, the method may be omitted on the protective layer.
  • ITO Indium Tin Oxides
  • An embodiment of the present invention provides an array substrate, including: an active layer, a first insulating layer, a gate, a gate insulating layer, a pixel electrode, and a source/drain sequentially disposed on one surface of the substrate; wherein, the first The insulating layer is disposed only on the pattern of the active layer, and the pixel electrode is directly electrically connected to the drain.
  • An embodiment of the present invention further provides a method for fabricating an array substrate, the method comprising: sequentially forming an active layer, a first insulating layer, and a gate layer on a substrate; performing a first patterning process to obtain an active layer a pattern of the first insulating layer and the gate electrode; forming a gate insulating layer and a pixel electrode layer sequentially on the processed substrate, performing a second patterning process to obtain a pattern of the pixel electrode and the via hole; forming a source/ The drain layer is subjected to a third patterning process to obtain a source/drain pattern.
  • Embodiments of the present invention also provide a display device, wherein the display device includes the above array substrate.
  • FIG. 1 is a schematic cross-sectional structural view of an array substrate of a top gate structure in the prior art
  • FIG. 2 is a schematic cross-sectional view of an array substrate of a top gate structure according to an embodiment of the present invention
  • FIG. 3 is a cross-sectional structural diagram of each intermediate state in a process of fabricating an array substrate of a top gate structure according to an embodiment of the present invention
  • the patterning process in the embodiment of the present invention refers to a photolithography process, including a process of coating (coating photoresist), exposure, development, etching, and the like. Processes such as gluing are the conventional technical means in the field, Embodiments of the Invention When describing a specific patterning process, a process of coating a photoresist or the like is not specifically described. Those skilled in the art can understand that the related process is not described, and does not mean that the embodiments of the present invention do not exist. Or omitted the relevant steps.
  • the prior art uses a process of processing the pixel electrode and the gate insulating layer by one patterning process to directly contact the pixel electrode and the drain, thereby avoiding providing a plurality of via holes on the protective layer.
  • the active layer, the first insulating layer and the gate structure are processed by one patterning process using a half exposure process.
  • the technical solution of the embodiment of the present invention reduces the preparation process of the entire array substrate from the original 6 masks to 3 masks, which reduces the complexity of the process and reduces product defects caused by misalignment. .
  • FIG. 2 is a partial cross-sectional view showing a thin film transistor on an array substrate according to an embodiment of the present invention.
  • the TFT is a top gate structure.
  • an active layer pattern 202, a first insulating layer pattern 203, and a gate electrode 204 are formed in this order (from bottom to top in FIG. 2), and a gate insulating (GI) layer 205 and a pixel electrode 208 are formed thereon.
  • GI gate insulating
  • a pixel electrode 208 are formed thereon.
  • source/drain including source 206-1 and drain 206-2.
  • the substrate 201 may be a transparent substrate or an opaque substrate.
  • the substrate 201 is required to be a transparent substrate, and when used for manufacturing an OLED panel, an opaque substrate can be used.
  • the first insulating layer does not cover the entire substrate, but is formed only on the active layer pattern 202, and the pixel electrode 208 is directly electrically connected to the drain 206-2.
  • the active layer of the embodiment of the present invention may be, for example, an oxide semiconductor such as IGZO.
  • the above structure does not need to provide a protective layer PVX on the array substrate, and directly applies the PI liquid of the liquid crystal alignment layer when performing a cell process (a process of forming a liquid crystal cell between the array substrate and the color filter substrate), and the subsequent work can be performed.
  • the PI liquid is a chemical liquid used to form a liquid crystal alignment layer, and is printed on a conductive glass to form an alignment layer after baking, which can provide a pretilt angle to the liquid crystal molecules, so that the rotation direction of the liquid crystal molecules is more uniform.
  • a thin film for example, an oxide IGZO thin film, IGZO is exemplified herein
  • a thin film of the first insulating layer 203a, and a gate layer 204a are sequentially formed on the transparent substrate 201 (for example, deposited). metal.
  • the photoresist PR is applied (Fig. 3)
  • it is half-exposed, for example, a Half Tone mask or a Gray Tone mask technique.
  • wet etching of the gate layer, dry etching of the first insulating layer film, and dry etching of the active layer are performed, and the cross-sectional structure formed is as shown in FIG.
  • an etched active layer pattern is formed on the substrate 201.
  • the photoresist PR is ashed (i.e., a certain thickness of photoresist is etched away) to expose a portion of the gate layer 204b (Fig. 5).
  • the second gate layer is then wet etched to form a pattern comprising the gate.
  • the common electrode lines may be disposed in the same layer of the gate electrode, and the common electrode lines are formed while forming a pattern including the gate electrodes.
  • the above process is the first patterning process in the manufacturing method according to the embodiment of the present invention, and the pattern of the active layer 202, the first insulating layer 203, and the gate electrode 204 is obtained by the process, and the cross-sectional view is shown in FIG. 6.
  • the first insulating layer material may be silicon oxide; the material of the gate layer may be molybdenum (Mo), titanium (Ti), chromium (Cr), aluminum (A1), aluminum germanium (AlNd) or a combination thereof (ie, two or more types) Alloy of the above metal).
  • a transparent conductive film of the gate insulating layer 205 and the pixel electrode layer 208a is formed (for example, deposited) on the substrate after the above processing (which may be any material suitable for the pixel electrode such as ITO, germanium, etc.)
  • the photoresist PR (Fig. 7) is followed by a second patterning process.
  • the half-exposure technique is still used in this patterning process, and the cross-sectional view after the first ITO wet etching after exposure is shown in Fig. 8.
  • dry etching of the gate insulating layer is performed, and the dry first insulating layer is simultaneously etched away.
  • the structure of FIG. 10 is obtained.
  • the first insulating layer 203 is then dry etched such that the IGZO at the via location is exposed. Therefore, a via hole penetrating the gate insulating layer and the first insulating layer can be formed, so that the source/drain formed in the subsequent step can be brought into contact with the IGZO layer.
  • the first insulating layer and the gate insulating layer may each be made of a silicon oxide material, and the preparation method may be deposited by plasma enhanced chemical vapor deposition (PECVD) technology, for example, under a certain pressure and a higher temperature condition. Next, the gas Si3 ⁇ 4 and N 2 0 are co-deposited in a certain ratio.
  • PECVD plasma enhanced chemical vapor deposition
  • the thickness of the gate insulating layer to be etched small that is, the area covered by the ITO
  • the height difference of the gate insulating layer between the domain and the region not covered by the ITO is small, so as not to affect the performance of the product.
  • the flow rate of Si3 ⁇ 4 (silane) used is larger than that of the first insulating layer when Si3 ⁇ 4 is deposited.
  • the flow rate is such that the etching rate of the gate insulating film after film formation is lower than the etching rate of the first insulating layer.
  • the material of the source/drain layer may also be molybdenum (Mo), titanium (Ti), chromium (Cr), aluminum (A1), aluminum lanthanum (AlNd) or a combination thereof (i.e., an alloy of two or more of the above metals).
  • the oxide TFT array substrate has been prepared, and all the processes have undergone three patterning processes. Compared with the previous six times, the number of processes is greatly reduced, the difficulty is reduced, and the production process is simplified.
  • Embodiments of the present invention also provide a display device including the array substrate as described above.
  • the display device may be: a liquid crystal panel, an electronic paper, an OLED panel, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, and the like, or any product or component having a display function.
  • Embodiments of the present invention provide a novel oxide TFT array substrate top gate structure and a method of fabricating the same.
  • the oxide layer, the first insulating layer and the gate are processed by only one patterning process by using a half exposure process, and the via arrangement of the pixel electrode and the gate insulating layer is also performed by one patterning process.
  • the process is completed, and finally the entire array substrate is completed through 3 masks, which simplifies the production process.
  • the process can directly connect the drain electrode to the pixel electrode, avoiding the arrangement of multiple via holes in the protective layer, saving production cost and improving product yield.
  • An array substrate comprising:
  • a method of manufacturing an array substrate comprising:
  • a third patterning process is performed to obtain a source/drain pattern.
  • the photoresist is subsequently ashed and a second etch of the gate layer is performed to form a pattern comprising the gate.
  • (11) The method according to any one of (8) to (10) wherein, in the second patterning process, after the exposure and development of the applied photoresist, the first of the pixel electrode layers is performed Sub-etching and etching of the gate insulating layer to obtain via holes in the gate insulating layer;
  • the photoresist is ashed, and the second etching of the pixel electrode layer and the etching of the first insulating layer are performed to obtain a pattern of the pixel electrode and a via hole in the first insulating layer.
  • the reaction gas used includes silane, and the flow rate of the silane used in forming the gate insulating layer is larger than the flow rate of the silane used in forming the first insulating layer.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

Provided are an array substrate, manufacturing method and display device thereof, the array substrate comprising an active layer (202), a first insulation layer (203), a gate (204), a gate insulation layer (205), a pixel electrode (208) and source/drain electrodes (206-1, 206-2) sequentially disposed on one side of a substrate(201); the first insulation layer (203) is only disposed on the pattern of the active layer (202); and the pixel electrode (208) is directly and electrically connected to the drain electrode (206-2). The display device comprises the array substrate.

Description

阵列基板和其制造方法以及显示装置 技术领域  Array substrate, manufacturing method thereof and display device
本发明的实施例涉及一种阵列基板和其制造方法以及显示装置。 背景技术  Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device. Background technique
在液晶显示领域中， 薄膜晶体管的有源层一直使用稳定性、 加工性等性 能均表现优异的硅系材料。 硅系材料主要分为非晶硅和多晶硅， 其中非晶硅 材料迁移率很低， 而多晶硅材料虽然有较高的迁移率， 但用其制造的器件均 匀性较差、 良率低、 单价高。 所以近年来， 将透明氧化物半导体膜用于沟道 形成区块来制造薄膜晶体管（TFT, Thin Film Transistor )等器件的半导体有 源层， 并应用于电子器件及光器件的技术受到广泛关注。 利用以铟、 镓、辞、 氧为构成元素的非晶质 In-Ga-Zn-0系材料（ a-IGZO )的场效应型晶体管因其 具有较高迁移率， 较大开关比， 而得到了最多的关注。  In the field of liquid crystal display, the active layer of a thin film transistor has always used a silicon-based material which is excellent in performance such as stability and workability. Silicon-based materials are mainly classified into amorphous silicon and polycrystalline silicon, among which the mobility of amorphous silicon materials is very low, and although the polysilicon materials have high mobility, the uniformity of devices fabricated by them is poor, the yield is low, and the unit price is high. . Therefore, in recent years, a transparent oxide semiconductor film has been used for a channel formation block to manufacture a semiconductor active layer of a device such as a thin film transistor (TFT), and has been widely used in electronic devices and optical devices. A field effect transistor using an amorphous In-Ga-Zn-0 material (a-IGZO) composed of indium, gallium, rhodium and oxygen as a constituent element has a higher mobility and a larger switching ratio. The most attention.
现有氧化物 TFT技术的顶栅结构截面如图 1所示。基板 101上首先沉积 氧化物层 102,栅极 104位于氧化物层上且与氧化物层之间由第一绝缘层 103 隔开， 第一绝缘层 103覆盖整个基板表面。 源 /漏电极 106均由电阻较小的金 属材料组成， 直接设置在栅绝缘层 ( GI, Gate Insulation ) 105上并通过栅绝 缘层中的过孔与氧化物层连接。 像素电极 108设置在保护层（PVX, 又称钝 化层） 107上， 且保护层上开有过孔， 使像素电极与漏极金属（包括数据线） 相连。  The cross-sectional structure of the existing oxide TFT technology is shown in Fig. 1. An oxide layer 102 is first deposited on the substrate 101, and the gate electrode 104 is on the oxide layer and separated from the oxide layer by the first insulating layer 103, and the first insulating layer 103 covers the entire substrate surface. The source/drain electrodes 106 are each composed of a metal material having a small electrical resistance, and are directly disposed on a Gate Insulation (GI) 105 and connected to the oxide layer through via holes in the gate insulating layer. The pixel electrode 108 is disposed on a protective layer (PVX, also referred to as a passivation layer) 107, and a via hole is formed in the protective layer to connect the pixel electrode to the drain metal (including the data line).
由于现有技术中像素电极与漏极之间设置有保护层，为保证两者的连接， 需在保护层上设置多个过孔，工艺难度大。若釆用先沉积像素电极的导电膜， 如 ITO ( Indium Tin Oxides, 氧化铟锡）等， 然后在其上直接沉积源 /漏金属 层令两者直接连接， 该方式可以省略在保护层上设置多个过孔的工艺， 但对 此外， 现有的氧化物 TFT阵列基板的制造工艺需进行 6次掩模 ( mask ) 曝光， 分别为形成氧化物层（IGZO ) 、 栅极（Gate ) 、 栅极绝缘层（GI )和 第一绝缘层的过孔设置、 数据线和源 /漏极（S/D ) 、 钝化层（PVX ) 、 以及 透明像素电极（ITO ) 的过程。 多次的构图工艺处理加大了工艺的难度， 容 易出现由于对位精度不足引起的不良， 产品良率下降。 发明内容 Since a protective layer is disposed between the pixel electrode and the drain in the prior art, in order to ensure the connection between the two, a plurality of via holes are required to be disposed on the protective layer, which is difficult in the process. If the conductive film of the pixel electrode is first deposited, such as ITO (Indium Tin Oxides), and then the source/drain metal layer is directly deposited thereon so that the two are directly connected, the method may be omitted on the protective layer. a process of a plurality of vias, but in addition, the fabrication process of the existing oxide TFT array substrate requires 6 mask exposures to form an oxide layer (IGZO), a gate (gate), and a gate. The process of the via insulating layer (GI) and the via arrangement of the first insulating layer, the data line and the source/drain (S/D), the passivation layer (PVX), and the transparent pixel electrode (ITO). Multiple patterning processes increase the difficulty of the process. It is prone to defects due to insufficient alignment accuracy, and product yield is degraded. Summary of the invention
本发明的实施例提供一种阵列基板， 包括： 在基板的一面上依次设置的 有源层、 第一绝缘层、 栅极、 栅极绝缘层、 像素电极和源 /漏极； 其中， 第一 绝缘层仅仅设置在有源层的图案上， 像素电极与漏极直接电连接。  An embodiment of the present invention provides an array substrate, including: an active layer, a first insulating layer, a gate, a gate insulating layer, a pixel electrode, and a source/drain sequentially disposed on one surface of the substrate; wherein, the first The insulating layer is disposed only on the pattern of the active layer, and the pixel electrode is directly electrically connected to the drain.
本发明的实施例还提供一种阵列基板的制造方法， 该方法包括： 在基板 上依次形成有源层、 第一绝缘层和栅极层； 进行第一次构图工艺处理， 得到 包括有源层、 第一绝缘层以及栅极的图案； 在经上述处理后的基板上依次形 成栅极绝缘层和像素电极层， 进行第二次构图工艺处理， 得到像素电极和过 孔的图案； 形成源 /漏极层， 进行第三次构图工艺处理， 得到源 /漏极图案。  An embodiment of the present invention further provides a method for fabricating an array substrate, the method comprising: sequentially forming an active layer, a first insulating layer, and a gate layer on a substrate; performing a first patterning process to obtain an active layer a pattern of the first insulating layer and the gate electrode; forming a gate insulating layer and a pixel electrode layer sequentially on the processed substrate, performing a second patterning process to obtain a pattern of the pixel electrode and the via hole; forming a source/ The drain layer is subjected to a third patterning process to obtain a source/drain pattern.
本发明的实施例还提供一种显示装置， 其中， 该显示装置包括上述阵列 基板。 附图说明  Embodiments of the present invention also provide a display device, wherein the display device includes the above array substrate. DRAWINGS
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。  In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly described below. It is obvious that the drawings in the following description relate only to some embodiments of the present invention, and are not intended to limit the present invention. .
图 1为现有技术中顶栅结构的阵列基板的截面结构示意图；  1 is a schematic cross-sectional structural view of an array substrate of a top gate structure in the prior art;
图 2为本发明的实施例中顶栅结构的阵列基板的截面结构示意图； 图 3-图 11为本发明的实施例中顶栅结构的阵列基板的制造过程中的各 中间状态的截面结构示意图。 具体实施方式  2 is a schematic cross-sectional view of an array substrate of a top gate structure according to an embodiment of the present invention; and FIG. 3 is a cross-sectional structural diagram of each intermediate state in a process of fabricating an array substrate of a top gate structure according to an embodiment of the present invention; . detailed description
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。  The technical solutions of the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings of the embodiments of the present invention. It is apparent that the described embodiments are part of the embodiments of the invention, rather than all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the described embodiments of the present invention without departing from the scope of the invention are within the scope of the invention.
本发明的实施例中的构图工艺， 指光刻工艺， 包括涂胶（涂布光刻胶）、 曝光、 显影、 刻蚀等工艺过程。 因涂胶等工艺为本领域的常规技术手段， 本 发明的实施例在描述具体构图工艺处理过程时， 并不对涂布光刻胶等过程进 行具体描述， 本领域的技术人员可以理解， 未描述相关过程， 并不意味着本 发明各实施例不存在或省略了相关步骤。 The patterning process in the embodiment of the present invention refers to a photolithography process, including a process of coating (coating photoresist), exposure, development, etching, and the like. Processes such as gluing are the conventional technical means in the field, Embodiments of the Invention When describing a specific patterning process, a process of coating a photoresist or the like is not specifically described. Those skilled in the art can understand that the related process is not described, and does not mean that the embodiments of the present invention do not exist. Or omitted the relevant steps.
本技术釆用使像素电极与栅极绝缘层通过一次构图工艺处理制备的工 艺， 使像素电极与漏极直接接触， 避免在保护层上设置多个过孔。 同时釆用 半曝光工艺， 使有源层、 第一绝缘层以及栅极结构通过一次构图工艺处理制 备完成。 本发明的实施例的技术方案使得整个阵列基板的制备工艺由原来的 6次掩模 ( mask )减为 3次掩模， 降低了工艺的复杂度， 减少了由于对位不 准引起的产品不良。  The prior art uses a process of processing the pixel electrode and the gate insulating layer by one patterning process to directly contact the pixel electrode and the drain, thereby avoiding providing a plurality of via holes on the protective layer. At the same time, the active layer, the first insulating layer and the gate structure are processed by one patterning process using a half exposure process. The technical solution of the embodiment of the present invention reduces the preparation process of the entire array substrate from the original 6 masks to 3 masks, which reduces the complexity of the process and reduces product defects caused by misalignment. .
参照附图 2, 对本发明的实施例中阵列基板的结构进行说明。 图 2为本 发明的实施例中阵列基板上薄膜晶体管局部截面图， 由该截面图可知， 本发 明的实施例的阵列基板中， TFT为顶栅结构。在基板 201的一面上，依次（图 2中自下而上）形成有源层图案 202、 第一绝缘层图案 203、 栅极 204, 之上 是栅极绝缘（ GI )层 205、 像素电极 208和源 /漏极 (包括源极 206-1和漏极 206-2 )。 基板 201可以为透明基板或者不透明基板。 在阵列基板用于制造液 晶显示面板时， 需要基板 201为透明基板， 在用于制造 OLED面板时， 可以 使用不透明基板。 区别于现有技术， 本发明实施例中第一绝缘层并未覆盖全 部基板，而是仅仅形成在有源层图案 202上， 同时像素电极 208与漏极 206-2 直接电连接。 本发明实施例的有源层例如可以为氧化物半导体， 比如 IGZO。 上述结构不需要在阵列基板上设置保护层 PVX,在进行成盒 ( Cell )工艺（阵 列基板与彩膜基板间形成液晶盒的工艺 )时直接涂液晶取向层的 PI液，进行 后续工段即可。 PI液是用来制作液晶取向层的化学液体， 印刷在导电玻璃上 经过烘烤后成为取向层， 可以给液晶分子提供一个预倾角， 使得液晶分子的 旋转方向一致性更好。  The structure of the array substrate in the embodiment of the present invention will be described with reference to FIG. 2 is a partial cross-sectional view showing a thin film transistor on an array substrate according to an embodiment of the present invention. As is apparent from the cross-sectional view, in the array substrate of the embodiment of the present invention, the TFT is a top gate structure. On one side of the substrate 201, an active layer pattern 202, a first insulating layer pattern 203, and a gate electrode 204 are formed in this order (from bottom to top in FIG. 2), and a gate insulating (GI) layer 205 and a pixel electrode 208 are formed thereon. And source/drain (including source 206-1 and drain 206-2). The substrate 201 may be a transparent substrate or an opaque substrate. When the array substrate is used for manufacturing a liquid crystal display panel, the substrate 201 is required to be a transparent substrate, and when used for manufacturing an OLED panel, an opaque substrate can be used. Different from the prior art, in the embodiment of the present invention, the first insulating layer does not cover the entire substrate, but is formed only on the active layer pattern 202, and the pixel electrode 208 is directly electrically connected to the drain 206-2. The active layer of the embodiment of the present invention may be, for example, an oxide semiconductor such as IGZO. The above structure does not need to provide a protective layer PVX on the array substrate, and directly applies the PI liquid of the liquid crystal alignment layer when performing a cell process (a process of forming a liquid crystal cell between the array substrate and the color filter substrate), and the subsequent work can be performed. . The PI liquid is a chemical liquid used to form a liquid crystal alignment layer, and is printed on a conductive glass to form an alignment layer after baking, which can provide a pretilt angle to the liquid crystal molecules, so that the rotation direction of the liquid crystal molecules is more uniform.
以下进一步结合图 3-图 11介绍上述阵列基板结构的制造工艺。  The manufacturing process of the above array substrate structure will be further described below with reference to FIGS.
首先参见图 3, 透明基板 201上依次形成（例如沉积）有源层 202a的薄 膜（比如氧化物 IGZO薄膜，此处以 IGZO为例进行说明 )、第一绝缘层 203a 的薄膜和栅极层 204a的金属。 涂覆光刻胶 PR后（图 3 ) , 对其进行半曝光， 例如可釆用半色调（ Half Tone )掩模或者灰度 ( Gray Tone )掩膜技术。 显影 后进行栅极层的湿刻蚀、 第一绝缘层薄膜的干刻蚀、 有源层的干刻蚀， 其形 成的截面结构如图 4所示。 在图 4中， 基板 201上形成刻蚀后的有源层图案 202、 第一绝缘层图案 203和栅极层 204b, 以及半刻蚀的光刻胶 PR。 由于有 源层图案 202和第一绝缘层图案 203在同一刻蚀步骤中形成,有源层图案 202 的边缘与第一绝缘层图案 203的边缘对齐。随后灰化光刻胶 PR (即刻蚀掉一 定厚度的光刻胶） ， 暴露出部分栅极层 204b (图 5 ) 。 然后对第二次栅极层 进行湿刻蚀以形成包括栅极的图案。 进一步地， 可以将公共电极线设置在栅 极的同一层， 在形成包括栅极的图案的同时形成公共电极线。 上述过程为根 据本发明实施例的制造方法中的第一次构图工艺处理， 通过该过程得到了有 源层 202、第一绝缘层 203以及栅极 204的图案，截面图见图 6。 第一绝缘层 材料可使用氧化硅； 栅极层的材料可以为钼 （Mo ) 、 钛（Ti ) 、 铬（Cr ) 、 铝 （A1 ) 、 铝钕（AlNd )或其组合（即两种以上上述金属的合金） 。 Referring first to FIG. 3, a thin film (for example, an oxide IGZO thin film, IGZO is exemplified herein), a thin film of the first insulating layer 203a, and a gate layer 204a are sequentially formed on the transparent substrate 201 (for example, deposited). metal. After the photoresist PR is applied (Fig. 3), it is half-exposed, for example, a Half Tone mask or a Gray Tone mask technique. After development, wet etching of the gate layer, dry etching of the first insulating layer film, and dry etching of the active layer are performed, and the cross-sectional structure formed is as shown in FIG. In FIG. 4, an etched active layer pattern is formed on the substrate 201. 202, a first insulating layer pattern 203 and a gate layer 204b, and a half-etched photoresist PR. Since the active layer pattern 202 and the first insulating layer pattern 203 are formed in the same etching step, the edges of the active layer pattern 202 are aligned with the edges of the first insulating layer pattern 203. Subsequently, the photoresist PR is ashed (i.e., a certain thickness of photoresist is etched away) to expose a portion of the gate layer 204b (Fig. 5). The second gate layer is then wet etched to form a pattern comprising the gate. Further, the common electrode lines may be disposed in the same layer of the gate electrode, and the common electrode lines are formed while forming a pattern including the gate electrodes. The above process is the first patterning process in the manufacturing method according to the embodiment of the present invention, and the pattern of the active layer 202, the first insulating layer 203, and the gate electrode 204 is obtained by the process, and the cross-sectional view is shown in FIG. 6. The first insulating layer material may be silicon oxide; the material of the gate layer may be molybdenum (Mo), titanium (Ti), chromium (Cr), aluminum (A1), aluminum germanium (AlNd) or a combination thereof (ie, two or more types) Alloy of the above metal).
随后， 在经上述处理后的基板上依次形成 (例如沉积）栅极绝缘层 205、 像素电极层 208a的透明导电膜（其可以为 ITO、 ΙΖΟ等任何适于做像素电极 的材料， 此处以 ΙΤΟ为例进行说明）以及光刻胶 PR (图 7 ) , 然后进行第二 次构图工艺处理工艺。 本次构图工艺处理仍釆用半曝光技术， 曝光后进行第 一次 ITO湿蚀刻后的截面图为图 8。 然后进行栅极绝缘层的干刻蚀， 本次干 第一绝缘层同时刻蚀掉。 由于 ITO刻蚀液中的水会影响 IGZO的性能， 同时 ITO刻蚀液对 IGZO的刻蚀速率也很高 ,若 ITO刻蚀液接触到有源层的 IGZO 会严重影响 IGZO的性能和图案。为避免后续的 ITO刻蚀工艺引起产品不良， 必须保证 IGZO不暴露在刻蚀液中， 因而通过有源层之上的第一绝缘层对有 源层的 IGZO形成保护。 上述过程完成后的截面图为图 9。  Subsequently, a transparent conductive film of the gate insulating layer 205 and the pixel electrode layer 208a is formed (for example, deposited) on the substrate after the above processing (which may be any material suitable for the pixel electrode such as ITO, germanium, etc.) As an example, the photoresist PR (Fig. 7) is followed by a second patterning process. The half-exposure technique is still used in this patterning process, and the cross-sectional view after the first ITO wet etching after exposure is shown in Fig. 8. Then, dry etching of the gate insulating layer is performed, and the dry first insulating layer is simultaneously etched away. Since the water in the ITO etching solution affects the performance of the IGZO, and the etching rate of the ITO etching solution to the IGZO is also high, if the ITO etching solution contacts the IGZO of the active layer, the performance and pattern of the IGZO may be seriously affected. In order to avoid the defect of the product caused by the subsequent ITO etching process, it is necessary to ensure that the IGZO is not exposed to the etching liquid, and thus the IGZO of the active layer is protected by the first insulating layer on the active layer. The cross-sectional view after the above process is completed is shown in Fig. 9.
栅极绝缘层干刻蚀完成后， 进行光刻胶 PR的灰化和 ITO的第二次湿刻 蚀，得到图 10的结构。 随后再对第一绝缘层 203进行干刻蚀，使得过孔位置 处的 IGZO暴露出来。 因此， 可以形成贯穿栅绝缘层和第一绝缘层的过孔， 从而能够使得在后续步骤中形成的源 /漏极与 IGZO层接触。 第一绝缘层干刻 蚀的同时， 暴露在外的栅极绝缘层也同时会被刻蚀掉一部分， 因而最终未被 ITO覆盖的栅极绝缘层的厚度略低于 ITO覆盖区域下的栅极绝缘层的厚度， 结构如图 11所示。本发明实施例中，第一绝缘层和栅极绝缘层可以均釆用氧 化硅材料， 制备方法可以利用等离子体增强化学气相沉积（PECVD )技术进 行沉积， 比如在一定压力、 较高温度的条件下， 由气体 Si¾和 N20按一定 比例共同沉积而成。 为使被刻蚀掉的栅极绝缘层厚度较小， 即被 ITO覆盖区 域和未被 ITO覆盖区域的栅极绝缘层高度差较小，从而达到不影响产品性能 的目的， 在沉积栅极绝缘层时， 使用的 Si¾ (硅烷）的流量大于第一绝缘层 沉积时 Si¾流量，使得成膜后栅极绝缘层膜的刻蚀速率低于第一绝缘层的刻 蚀速率。 After the dry etching of the gate insulating layer is completed, ashing of the photoresist PR and second wet etching of the ITO are performed, and the structure of FIG. 10 is obtained. The first insulating layer 203 is then dry etched such that the IGZO at the via location is exposed. Therefore, a via hole penetrating the gate insulating layer and the first insulating layer can be formed, so that the source/drain formed in the subsequent step can be brought into contact with the IGZO layer. When the first insulating layer is dry etched, the exposed gate insulating layer is also etched away at the same time, so that the thickness of the gate insulating layer not covered by ITO is slightly lower than that of the gate insulating region under the ITO covered region. The thickness of the layer, the structure is shown in Figure 11. In the embodiment of the present invention, the first insulating layer and the gate insulating layer may each be made of a silicon oxide material, and the preparation method may be deposited by plasma enhanced chemical vapor deposition (PECVD) technology, for example, under a certain pressure and a higher temperature condition. Next, the gas Si3⁄4 and N 2 0 are co-deposited in a certain ratio. In order to make the thickness of the gate insulating layer to be etched small, that is, the area covered by the ITO The height difference of the gate insulating layer between the domain and the region not covered by the ITO is small, so as not to affect the performance of the product. When depositing the gate insulating layer, the flow rate of Si3⁄4 (silane) used is larger than that of the first insulating layer when Si3⁄4 is deposited. The flow rate is such that the etching rate of the gate insulating film after film formation is lower than the etching rate of the first insulating layer.
然后溅射源 /漏极层的金属， 通过第三次构图工艺后， 得到源 /漏极图案， 最后得到图 2 的结构。 源 /漏极层的材料也可以为钼 （Mo ) 、 钛（Ti ) 、 铬 ( Cr )、 铝（A1 )、 铝钕（AlNd )或其组合（即两种以上上述金属的合金）。  Then, the metal of the source/drain layer is sputtered, and after the third patterning process, the source/drain pattern is obtained, and finally the structure of Fig. 2 is obtained. The material of the source/drain layer may also be molybdenum (Mo), titanium (Ti), chromium (Cr), aluminum (A1), aluminum lanthanum (AlNd) or a combination thereof (i.e., an alloy of two or more of the above metals).
至此， 氧化物 TFT阵列基板制备完成， 全部工艺共经历了三次构图工艺 处理， 相较于原有技术中的六次， 大大缩减了工艺数量， 降低了难度， 简化 了生产过程。  So far, the oxide TFT array substrate has been prepared, and all the processes have undergone three patterning processes. Compared with the previous six times, the number of processes is greatly reduced, the difficulty is reduced, and the production process is simplified.
本发明的实施例还提供一种显示装置， 包括如上所述的阵列基板。 所述 显示装置可以为： 液晶面板、 电子纸、 OLED面板、 液晶电视、 液晶显示器、 数码相框、 手机、 平板电脑等任何具有显示功能的产品或部件。  Embodiments of the present invention also provide a display device including the array substrate as described above. The display device may be: a liquid crystal panel, an electronic paper, an OLED panel, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, and the like, or any product or component having a display function.
本发明的实施例提供了一种新的氧化物 TFT 阵列基板顶栅结构及其制 造方法。 本发明的实施例中通过釆用半曝光工艺， 使得氧化物层、 第一绝缘 层以及栅极仅通过一次构图工艺处理制得， 而像素电极和栅绝缘层的过孔设 置也通过一次构图工艺处理制得， 最终整个阵列基板通过 3次掩模完成， 简 化了生产工艺。 同时釆用该工艺可以使漏极与像素电极直接电连接， 避免了 保护层中多个过孔的设置， 节约了生产成本并提高了产品良率。  Embodiments of the present invention provide a novel oxide TFT array substrate top gate structure and a method of fabricating the same. In the embodiment of the present invention, the oxide layer, the first insulating layer and the gate are processed by only one patterning process by using a half exposure process, and the via arrangement of the pixel electrode and the gate insulating layer is also performed by one patterning process. The process is completed, and finally the entire array substrate is completed through 3 masks, which simplifies the production process. At the same time, the process can directly connect the drain electrode to the pixel electrode, avoiding the arrangement of multiple via holes in the protective layer, saving production cost and improving product yield.
( 1 )一种阵列基板， 包括： (1) An array substrate comprising:
在基板的一面上依次设置的有源层、 第一绝缘层、 栅极、 栅极绝缘层、 像素电极和源 /漏极；其中，所述第一绝缘层仅仅设置在所述有源层的图案上， 所述像素电极与漏极直接电连接。  An active layer, a first insulating layer, a gate, a gate insulating layer, a pixel electrode, and a source/drain disposed sequentially on one side of the substrate; wherein the first insulating layer is disposed only on the active layer In the pattern, the pixel electrode is directly electrically connected to the drain.
( 2 )如（1 )所述的阵列基板， 其中， 所述有源层为透明氧化物半导体 膜。  (2) The array substrate according to (1), wherein the active layer is a transparent oxide semiconductor film.
( 3 )如（ 1 )或（ 2 )所述的阵列基板， 其中， 所述透明氧化物为铟镓辞 氧化物。  The array substrate according to (1) or (2), wherein the transparent oxide is indium gallium oxide.
( 4 )如（1 )至（3 ) 中任一项所述的阵列基板， 其中， 所述源 /漏极通 过所述栅极绝缘层和所述第一绝缘层中的过孔与所述有源层电连接。  The array substrate according to any one of (1) to (3), wherein the source/drain passes through the gate insulating layer and a via hole in the first insulating layer and the The active layer is electrically connected.
( 5 )如（ 1 )至（ 4 )中任一项所述的阵列基板， 其中， 所述栅极绝缘层 的刻蚀速率低于所述第一绝缘层的刻蚀速率。 The array substrate according to any one of (1) to (4), wherein the gate insulating layer The etch rate is lower than the etch rate of the first insulating layer.
(6)如（1 )至（5) 中任一项所述的阵列基板， 其中， 所述源 /漏极通 过贯穿所述栅绝缘层和所述第一绝缘层的过孔分别与所述有源层接触。  The array substrate according to any one of (1) to (5), wherein the source/drain passes through a via hole penetrating the gate insulating layer and the first insulating layer, respectively Active layer contact.
( 7 )如（ 1 )至（ 6 )中任一项所述的阵列基板， 其中， 所述第一绝缘层 的边缘与所述有源层的边缘对齐。  The array substrate according to any one of (1) to (6), wherein an edge of the first insulating layer is aligned with an edge of the active layer.
(8)—种阵列基板的制造方法， 包括：  (8) A method of manufacturing an array substrate, comprising:
在基板上依次形成有源层、 第一绝缘层和栅极层；  Forming an active layer, a first insulating layer and a gate layer sequentially on the substrate;
进行第一次构图工艺处理， 得到包括有源层、 第一绝缘层以及栅极的图 案；  Performing a first patterning process to obtain a pattern including an active layer, a first insulating layer, and a gate;
在经上述处理后的基板上依次形成栅极绝缘层和像素电极层； 进行第二次构图工艺处理， 得到像素电极和过孔的图案；  Forming a gate insulating layer and a pixel electrode layer on the substrate after the above processing; performing a second patterning process to obtain a pattern of pixel electrodes and via holes;
形成源 /漏极层；  Forming a source/drain layer;
进行第三次构图工艺处理， 得到源 /漏极图案。  A third patterning process is performed to obtain a source/drain pattern.
(9)如（8)所述的方法， 其中， 第一次及第二次构图工艺处理时， 釆 用半色调掩模或灰度掩膜进行构图。  (9) The method according to (8), wherein, in the first and second patterning processes, 构 patterning is performed using a halftone mask or a grayscale mask.
(10)如（8)或 （9)所述的方法， 其中， 第一次构图工艺处理时， 在 对涂布的光刻胶进行曝光显影后， 进行栅极层的第一次刻蚀、 第一绝缘层的 刻蚀和有源层的刻蚀以形成有源层和第一绝缘层的图案；  (10) The method according to (8) or (9), wherein, in the first patterning process, after the exposure and development of the applied photoresist, the first etching of the gate layer is performed, Etching of the first insulating layer and etching of the active layer to form a pattern of the active layer and the first insulating layer;
随后灰化光刻胶， 进行栅极层的第二次刻蚀以形成包括栅极的图案。 (11)如（8)至（10)中任一项所述的方法， 其中， 第二次构图工艺处 理时， 在对涂布的光刻胶进行曝光显影后， 进行像素电极层的第一次刻蚀和 栅极绝缘层的刻蚀， 得到栅极绝缘层中的过孔；  The photoresist is subsequently ashed and a second etch of the gate layer is performed to form a pattern comprising the gate. (11) The method according to any one of (8) to (10) wherein, in the second patterning process, after the exposure and development of the applied photoresist, the first of the pixel electrode layers is performed Sub-etching and etching of the gate insulating layer to obtain via holes in the gate insulating layer;
随后灰化光刻胶， 进行像素电极层的第二次刻蚀和第一绝缘层的刻蚀， 得到像素电极的图案和第一绝缘层中的过孔。  Subsequently, the photoresist is ashed, and the second etching of the pixel electrode layer and the etching of the first insulating layer are performed to obtain a pattern of the pixel electrode and a via hole in the first insulating layer.
( 12 )如（ 8 )至（ 11 )中任一项所述的方法， 其中， 形成所述栅极绝缘 层和所述第一绝缘层的方法均为釆用等离子化学气相沉积法沉积氧化硅， 所 使用的反应气体中包括硅烷， 并且形成所述栅极绝缘层时所使用的硅烷的流 量大于形成所述第一绝缘层时所使用的硅烷流量。  The method of any one of (8) to (11), wherein the method of forming the gate insulating layer and the first insulating layer is to deposit silicon oxide by plasma chemical vapor deposition The reaction gas used includes silane, and the flow rate of the silane used in forming the gate insulating layer is larger than the flow rate of the silane used in forming the first insulating layer.
(13)一种显示装置， 其中， 所述显示装置包括如（1)至（4) 中任一 项所述的阵列基板。 以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 本发明的保护范围由所附的权利要求确定。 (13) A display device, wherein the display device includes the array substrate according to any one of (1) to (4). The above is only the exemplary embodiments of the present invention, and is not intended to limit the scope of the invention. The scope of the invention is determined by the appended claims.

Claims

权利要求书 Claim
1、 一种阵列基板， 包括： 1. An array substrate comprising:
在基板的一面上依次设置的有源层、 第一绝缘层、 栅极、 栅极绝缘层、 像素电极和源 /漏极；其中，所述第一绝缘层仅仅设置在所述有源层的图案上， 所述像素电极与漏极直接电连接。  An active layer, a first insulating layer, a gate, a gate insulating layer, a pixel electrode, and a source/drain disposed sequentially on one side of the substrate; wherein the first insulating layer is disposed only on the active layer In the pattern, the pixel electrode is directly electrically connected to the drain.
2、根据权利要求 1所述的阵列基板， 其中， 所述有源层为透明氧化物半 导体膜。  The array substrate according to claim 1, wherein the active layer is a transparent oxide semiconductor film.
3、根据权利要求 1或 2所述的阵列基板， 其中， 所述透明氧化物为铟镓 辞氧化物。  The array substrate according to claim 1 or 2, wherein the transparent oxide is indium gallium oxide.
4、 根据权利要求 1至 3中任一项所述的阵列基板， 其中， 所述源 /漏极 通过所述栅极绝缘层和所述第一绝缘层中的过孔与所述有源层电连接。  The array substrate according to any one of claims 1 to 3, wherein the source/drain passes through the gate insulating layer and via holes in the first insulating layer and the active layer Electrical connection.
5、根据权利要求 1至 4中任一项所述的阵列基板， 其中， 所述栅极绝缘 层的刻蚀速率低于所述第一绝缘层的刻蚀速率。  The array substrate according to any one of claims 1 to 4, wherein an etching rate of the gate insulating layer is lower than an etching rate of the first insulating layer.
6、 根据权利要求 1至 5中任一项所述的阵列基板， 其中， 所述源 /漏极 通过贯穿所述栅绝缘层和所述第一绝缘层的过孔分别与所述有源层接触。  The array substrate according to any one of claims 1 to 5, wherein the source/drain are respectively connected to the active layer through via holes penetrating the gate insulating layer and the first insulating layer contact.
7、根据权利要求 1至 6中任一项所述的阵列基板， 其中， 所述第一绝缘 层的边缘与所述有源层的边缘对齐。  The array substrate according to any one of claims 1 to 6, wherein an edge of the first insulating layer is aligned with an edge of the active layer.
8、 一种阵列基板的制造方法， 包括：  8. A method of fabricating an array substrate, comprising:
在基板上依次形成有源层、 第一绝缘层和栅极层；  Forming an active layer, a first insulating layer and a gate layer sequentially on the substrate;
进行第一次构图工艺处理， 得到包括有源层、 第一绝缘层以及栅极的图 案；  Performing a first patterning process to obtain a pattern including an active layer, a first insulating layer, and a gate;
在经上述处理后的基板上依次形成栅极绝缘层和像素电极层；  Forming a gate insulating layer and a pixel electrode layer sequentially on the substrate after the above processing;
进行第二次构图工艺处理， 得到像素电极和过孔的图案；  Performing a second patterning process to obtain a pattern of pixel electrodes and via holes;
形成源 /漏极层； 以及  Forming a source/drain layer;
进行第三次构图工艺处理， 得到源 /漏极图案。  A third patterning process is performed to obtain a source/drain pattern.
9、根据权利要求 8所述的方法，其中，第一次及第二次构图工艺处理时， 釆用半色调掩模或灰度掩膜进行构图。  9. The method of claim 8, wherein the first and second patterning processes are patterned using a halftone mask or a grayscale mask.
10、 根据权利要求 8或 9所述的方法， 其中， 第一次构图工艺处理时， 在对涂布的光刻胶进行曝光显影后， 进行栅极层的第一次刻蚀、 第一绝缘层 的刻蚀和有源层的刻蚀以形成有源层和第一绝缘层的图案； The method according to claim 8 or 9, wherein, in the first patterning process, after the exposure and development of the coated photoresist, the first etching of the gate layer and the first insulation are performed. Floor Etching and etching of the active layer to form a pattern of the active layer and the first insulating layer;
随后灰化光刻胶， 进行栅极层的第二次刻蚀以形成包括栅极的图案。 The photoresist is subsequently ashed and a second etch of the gate layer is performed to form a pattern comprising the gate.
11、根据权利要求 8至 10中任一项所述的方法， 其中， 第二次构图工艺 处理时， 在对涂布的光刻胶进行曝光显影后， 进行像素电极层的第一次刻蚀 和栅极绝缘层的刻蚀， 得到栅极绝缘层中的过孔； The method according to any one of claims 8 to 10, wherein, in the second patterning process, after the exposure and development of the applied photoresist, the first etching of the pixel electrode layer is performed. And etching the gate insulating layer to obtain via holes in the gate insulating layer;
随后灰化光刻胶， 进行像素电极层的第二次刻蚀和第一绝缘层的刻蚀， 得到像素电极的图案和第一绝缘层中的过孔。  Subsequently, the photoresist is ashed, and the second etching of the pixel electrode layer and the etching of the first insulating layer are performed to obtain a pattern of the pixel electrode and a via hole in the first insulating layer.
12、根据权利要求 8至 11中任一项所述的方法， 其中， 形成所述栅极绝 缘层和所述第一绝缘层的方法均为釆用等离子化学气相沉积法沉积氧化硅， 所使用的反应气体中包括硅烷， 并且形成所述栅极绝缘层时所使用的硅烷的 流量大于形成所述第一绝缘层时所使用的硅烷流量。  The method according to any one of claims 8 to 11, wherein the method of forming the gate insulating layer and the first insulating layer is to deposit silicon oxide by plasma chemical vapor deposition, which is used The reaction gas includes silane, and the flow rate of the silane used in forming the gate insulating layer is larger than the flow rate of the silane used in forming the first insulating layer.
13、 一种显示装置， 包括如权利要求 1至 7中任一项所述的阵列基板。  A display device comprising the array substrate according to any one of claims 1 to 7.
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