WO2013104226A1

WO2013104226A1 - Thin film transistor, manufacturing method therefor, array substrate and display device

Info

Publication number: WO2013104226A1
Application number: PCT/CN2012/086217
Authority: WO
Inventors: 袁广才
Original assignee: 京东方科技集团股份有限公司
Priority date: 2012-01-13
Filing date: 2012-12-07
Publication date: 2013-07-18
Also published as: CN103208525B; CN102769039A; CN103208525A

Abstract

Provided are a thin film transistor, a manufacturing method therefor, an array substrate and a display device. The thin film transistor comprises a gate electrode, a gate insulating layer, a semiconductor active layer, a source electrode and a drain electrode, wherein the semiconductor active layer is in a multilayer structure, and at least comprises a semiconductor layer with a high conducting capability and a semiconductor layer with a low conducting capability; and the semiconductor layer with a high conducting capability is close to the gate electrode, and the semiconductor layer with a low conducting capability is close to the source electrode and the drain electrode.

Description

Thin film transistor and manufacturing method thereof, array substrate and display device

Embodiments of the present invention relate to a thin film transistor and a method of fabricating the same, an array substrate, and a display device. Background technique

One of the first research goals of OTFT (Oxide Thin Film Transistor) technology is to reduce the energy consumption of active display devices, making display devices thinner and lighter, and faster. Beginning at the beginning of the 21st century, the trial phase began.

FIG. 1 is a schematic structural view of a thin film transistor in the prior art. In the prior art, the gate electrode 11, the gate insulating layer 12, the semiconductor active layer 13, the etch stop layer 14, the source electrode 15a, the drain electrode 15b, and the blunt are sequentially formed on the glass substrate 10 by a 6-time exposure mask (Mask) process. The layer 16 and the pixel electrode 18, and the drain electrode 15b are connected to the pixel electrode 18 through the via hole 17. The semiconductor active layer 13 is made of a metal oxide such as indium gallium oxide IGZO.

The performance of the active layer determines the characteristics of the thin film transistor, and the conventional oxide thin film transistor shown in FIG. 1 cannot achieve a high off-state current ion while having a low off-state current Ioff, thereby failing to secure an oxide. The performance of thin film transistors ultimately affects the performance of the product. Summary of the invention

Embodiments of the present invention provide a thin film transistor, a method of fabricating the same, an array substrate, and a display device, which realize a high on-state current Ion and a low off-state current Ioff to improve characteristics of the thin film transistor.

In order to achieve the above object, embodiments of the present invention use the following technical solutions:

A thin film transistor comprising: a gate, a gate insulating layer, a semiconductor active layer, a source electrode and a drain electrode, wherein the semiconductor active layer is a multilayer structure including at least a semiconductor layer having high conductivity and a low conductivity a semiconductor layer having a high conductivity; the semiconductor layer having a high conductivity is adjacent to the gate, and a semiconductor layer having a low conductivity is adjacent to the source electrode and the drain electrode.

A method of manufacturing a thin film transistor, comprising: a process of forming a gate electrode, a gate insulating layer, a semiconductor active layer, a source electrode, and a drain electrode on a substrate; wherein, the process of forming the semiconductor active layer The method includes: forming a semiconductor layer having a high conductivity near the gate side; and forming a semiconductor layer having a low conductivity near the source electrode and the drain electrode side.

An array substrate comprising the above thin film transistor.

A display device comprising the above array substrate.

The thin film transistor and the manufacturing method thereof, the array substrate and the display device provided by the embodiments of the present invention layer-by-layer preparation of a high-conductivity semiconductor layer and a low-conductivity semiconductor layer; further, the formed semiconductor active layer includes two layers And a structure of two or more layers, and the semiconductor active layer close to the gate is formed of a semiconductor layer having high conductivity, achieving a high on-state current Ion, and a top layer of the semiconductor active layer close to the source and drain electrodes is turned on The ability to form a semiconductor layer achieves a low off-state current Ioff. The high on-state current Ion improves the characteristics of the oxide thin film transistor and ultimately ensures the performance of the product. DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly described below. It is obvious that the drawings in the following description relate only to some embodiments of the present invention, and are not intended to limit the present invention. .

1 is a schematic structural view of a thin film transistor in the prior art;

2 is a schematic structural diagram of a thin film transistor according to an embodiment of the present invention;

3A is a first schematic view showing a manufacturing process of an array substrate according to an embodiment of the present invention; FIG. 3B is a second schematic diagram of manufacturing an array substrate according to an embodiment of the present invention;

3C is a third schematic diagram of manufacturing an array substrate according to an embodiment of the present invention;

3D is a fourth schematic diagram of manufacturing an array substrate according to an embodiment of the present invention;

3E is a fifth schematic diagram of manufacturing an array substrate according to an embodiment of the present invention;

3F is a sixth schematic diagram of manufacturing an array substrate according to an embodiment of the present invention;

3G is a seventh schematic diagram of manufacturing an array substrate according to an embodiment of the present invention;

3H is an eighth schematic diagram of manufacturing an array substrate according to an embodiment of the present invention;

FIG. 31 is a ninth schematic diagram of manufacturing an array substrate according to an embodiment of the present invention;

FIG. 3 is a fourth schematic diagram of manufacturing an array substrate according to an embodiment of the present invention; FIG.

FIG. 3K is an eleventh schematic diagram of manufacturing an array substrate according to an embodiment of the present invention; FIG.

FIG. 3L is a twelfth schematic diagram of manufacturing an array substrate according to an embodiment of the present invention; FIG. FIG. 3 is a thirteenth schematic diagram of manufacturing an array substrate according to an embodiment of the present invention; FIG.

4 is a schematic structural diagram of a thin film transistor according to another embodiment of the present invention;

FIG. 5A is a first schematic diagram of manufacturing an array substrate according to another embodiment of the present invention; FIG.

FIG. 5B is a second schematic diagram of manufacturing an array substrate according to another embodiment of the present invention; FIG.

FIG. 5C is a third schematic diagram of manufacturing an array substrate according to another embodiment of the present invention; FIG.

FIG. 5D is a fourth schematic diagram of manufacturing an array substrate according to another embodiment of the present invention; FIG.

FIG. 5E is a fifth schematic diagram of manufacturing an array substrate according to another embodiment of the present invention. detailed description

The technical solutions of the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings of the embodiments of the present invention. It is apparent that the described embodiments are part of the embodiments of the invention, rather than all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the described embodiments of the present invention without departing from the scope of the invention are within the scope of the invention.

An embodiment of the present invention provides a thin film transistor including: a gate, a gate insulating layer, a semiconductor active layer, a source electrode, and a drain electrode;

The semiconductor active layer is a multilayer structure including at least a high-conductivity semiconductor layer and a low-conductivity semiconductor layer; wherein the high-conductivity semiconductor layer is close to the gate, and low-conducting capability The semiconductor layer is adjacent to the source and drain electrodes.

When the thin film transistor is a bottom gate structure, the thin film transistor includes a gate, a gate insulating layer, a semiconductor active layer, an etch barrier layer, and source and drain electrodes, wherein the gate is under the semiconductor active layer, the source electrode and the drain electrode The electrode is located above the semiconductor active layer; the semiconductor active layer is a multilayer structure including an etch barrier layer between the semiconductor active layer and the source and drain electrodes.

When the thin film transistor is a top gate structure, the thin film transistor includes a gate, a gate insulating layer, a semiconductor active layer, and a source/drain barrier layer, wherein the gate is above the semiconductor active layer, and the source and drain electrodes are located at the semiconductor active layer Below.

The implementation of the two modified structures of the thin film transistor provided by the embodiment of the present invention will be described below with reference to FIG. 2 and FIG. 4, but is not limited thereto.

As shown in FIG. 2, a thin film transistor according to an embodiment of the present invention includes: a gate 202 sequentially formed on a substrate 201, a gate insulating layer 203, a semiconductor layer 204 having high conductivity, and low conduction. Capacitive semiconductor layer 205, etch stop layer 206, metallization semiconductor layer, and data line metal layer. The high-conductivity semiconductor layer 204 and the low-conductivity semiconductor layer 205 constitute a semiconductor active layer, the semiconductor active layer is made of a metal oxide material; the etch stop layer 206 is over the oxide semiconductor active layer, Metalized semiconductor layers 207a and 207b on both sides of the etch barrier layer 206 are further formed over the oxide semiconductor active layer, and the data line metal layer includes a data line, a source electrode 208a and a drain electrode 208b of the thin film transistor. .

The oxide semiconductor active layer is formed by two or more layers using a layered optimization scheme. As shown in FIG. 2, the underlayer of the oxide semiconductor active layer of the bottom gate structure is a high conductivity semiconductor layer 204 having a high conductivity, and the top layer of the oxide semiconductor active layer is a semiconductor layer 205 having a low conductivity. Formed, but the oxide semiconductor active layer is formed by using a low-oxygen, high-conductivity semiconductor to improve the device's conduction capability, ie, to increase the on-state current (Ion) of the device; An oxide semiconductor with high oxygen content and low conductivity is used to control the leakage current of the device, that is, to reduce the off current (Ioff) of the device, thereby improving device performance. It can be understood that when the thin film transistor is a top gate structure, the top layer of the semiconductor active layer is a semiconductor layer with high conductivity, and the bottom layer of the active layer of the oxide semiconductor is formed of a semiconductor layer with low conductivity, an oxide semiconductor. The purpose of the active layer formation is to use a low-oxygen, high-conductivity semiconductor on the top layer to improve the device's conduction capability, ie, to increase the on-state current (Ion) of the device; the underlying semiconductor uses high oxygen content, A low-conductivity oxide semiconductor that controls the device's leakage current, which reduces the off-state current (Ioff) of the device, thereby improving device performance. Those skilled in the art can select the bottom gate or top gate structure according to the actual situation of the product.

After the active layer oxide semiconductor described above is formed, an etch stop layer is formed thereon as shown at 206 in FIG. After the etch barrier layer 206 is formed, a plasma (plasma) treatment of a gas such as hydrogen, N ₂ 0, CF ₄ or Ar is performed on the oxide semiconductor active layer exposed on both sides of the etch barrier layer, in the oxide semiconductor A metallized semiconductor layer is formed on the surface of the active layer, as shown in Fig. 2, 207a and 207b. The metallization of the semiconductor layer reduces the contact resistance of the active layer of the oxide semiconductor with the source and drain electrodes, thereby improving the ohmic contact characteristics of the device. The combination of the oxide semiconductor active layer, the metallized semiconductor layer, and the source and drain electrodes can achieve better output of device performance.

As shown in FIG. 4, another thin film transistor according to an embodiment of the present invention includes: a gate electrode 602 sequentially formed on a substrate (for example, a transparent glass substrate) 601, a gate insulating layer 603, and a semiconductor layer having high conductivity. 604, a low-conductivity semiconductor layer 605, an etch stop layer 606; A patterned low-oxygen, high-conductivity semiconductor transition layer 607a and 607b is formed over the patterned etch stop layer 606; a source electrode 608a and a drain electrode 608b are formed over the semiconductor transition layers 607a and 607b. The semiconductor transition layers 607a and 607b have a thickness of 5 to 50 nm, and the semiconductor transition layer is made of the same material as the high conductivity semiconductor layer.

The semiconductor transition layer having high conductivity can reduce the contact resistance between the active layer of the oxide semiconductor and the source and drain electrodes, thereby improving the ohmic contact characteristics of the device. The oxide semiconductor active layer and the semiconductor transition layer are combined with the source electrode and the drain electrode to form a sandwich TFT device, which can simultaneously have a high on-state current Ion and a low off-state current loff, and can solve the source electrode. The ohmic contact problem with the drain electrode, thereby maximally improving the performance of the TFT device. One of the features of the embodiments of the present invention is that in the process of fabricating an oxide TFT, the layered optimization scheme of the above sandwich structure is used to improve the performance of the device.

The thin film transistor provided by the invention can improve the on-state current (Ion) of the TFT device due to the layer-optimized oxide semiconductor active layer, and can control the off-state current of the device and reduce the leakage current (loff) of the device. Maximize the characteristics of the TFT. The semiconductor transition layer can solve the ohmic contact problem between the source electrode and the drain electrode and the active layer, improve the output capability of the device, thereby maximally improving the device performance, improving the yield of the entire substrate, and reducing the production cost.

In view of the difference in the process sequence of forming the layer-optimized oxide semiconductor active layer and the metallized semiconductor layer/oxide semiconductor transition layer of the above thin film transistor, the embodiment of the present invention provides an example of a method of manufacturing two thin film transistors.

The fabrication of the thin film transistor is an important part in the fabrication process of the array substrate; in the present embodiment, the fabrication process of the thin film transistor provided in the above embodiment will be described in conjunction with a method of fabricating an array substrate.

Next, the manufacturing process of the thin film transistor shown in Fig. 2 will be described by the first method. Specifically, the manufacturing process of the thin film transistor can be described with reference to the manufacturing process of the array substrate shown in FIG. 3A to FIG. 3M, and the specific steps include:

S401, forming a gate metal layer on the substrate;

As shown in FIG. 3A, a gate metal layer 502 is formed on a substrate (for example, a glass substrate) 501. In the fabrication process of the TFT, the gate metal layer is prepared by magnetron sputtering, and the gate material can be selected according to different device structures and process requirements. Commonly used gate metal layers are Mo, Mo-Al-Mo alloy, Mo/Al-Nd/Mo laminated metal layer, Cu and titanium metal and Its alloys, etc., and keep its sheet resistance at a relatively low level.

S402. Graphically pattern a gate metal layer.

As shown in FIG. 3B, the gate metal layer 502 is typically patterned by a patterning process, such as by wet etching, to form a gate 502a and a gate line 502b as shown in FIG. 3B.

S403, forming a gate insulating layer on the gate;

As shown in FIG. 3C, after the gate patterning, a pre-film cleaning (Pre-clean) process is performed. A gate insulating layer 503 is formed on a substrate on which a gate electrode and a gate line are formed by a plasma enhanced chemical vapor deposition (PECVD) method. The material of the gate insulating layer may be, for example, a silicon dioxide (SiO ₂ ) film, a silicon nitride film (SiNx ), a silicon oxynitride film (SiOxNy), an aluminum oxide (A1 ₂ 0 ₃ ) film, a TiOx film, and the like. Layer composite film.

S404, performing surface treatment on the gate insulating layer;

The surface of the gate insulating layer is treated by a plasma process to reduce the roughness of the surface of the film, and the metastable substance of the interface is removed to form a more stable interface. In this way, the field effect mobility can be improved and the stability of the TFT can be improved.

S405, forming a semiconductor layer with high conductivity;

As shown in Fig. 3D, a semiconductor layer 504 of high conductivity is formed. The most critical aspect of oxide TFT fabrication is the fabrication of semiconductor active layers. The formation of a high-conductivity semiconductor layer is very important. The high-conductivity semiconductor layer formed under a low-oxygen atmosphere forms a state of rich metal ions inside the film, and at the same time forms oxygen vacancies, thereby increasing current carrying capacity. Child's ability to conduct. Therefore, the semiconductor layer has a low oxygen content and a high conduction capability for increasing the on-state current Ion of the TFT device. Oxide semiconductors that are widely used today include indium gallium oxide (IGZO), indium tin oxide (ITZO), or indium oxide (IZO), and the like, and complex ratios thereof. The main production methods are magnetron sputtering deposition and solution method.

S406, forming a semiconductor layer with low conductivity;

The material used to fabricate the low-conductivity semiconductor layer is itself indistinguishable from the high-conductivity semiconductor layer. The semiconductor layer with low conductivity and the high-conductivity semiconductor layer are very different in the fabrication details. . First, in order to prevent leakage current, the conductive layer of the low-conductivity semiconductor layer is weaker than the low-conductivity semiconductor layer, and a low-conductivity semiconductor layer is formed under a high oxygen atmosphere, and oxygen enrichment is formed inside the semiconductor layer. The state of the ion, which limits the conduction of the carrier, can control the leakage current of the device; that is, the semiconductor layer with low conductivity can be low-conducting with high oxygen content. The passivation oxide semiconductor is shown as 505 in Figure 4E. It is used to control the leakage current of the device and reduce the off current (Ioff) of the device to maximize the performance of the device.

S407, patterning an active layer of the oxide semiconductor;

The high-conductivity semiconductor layer 504 and the low-conductivity semiconductor layer 505 as shown in FIG. 3E constitute an oxide semiconductor active layer, and the oxide semiconductor active layer is patterned by a patterning process, which is generally used. There are two etching methods, one is wet etching and the other is dry etching. Wet etching is now widely used, which can control the etching precision very well. The oxide semiconductor active layer is patterned by etching to form a high-conductivity semiconductor layer 504 and a low-conductivity semiconductor layer 505 as shown in Fig. 3F.

S408, forming an etch barrier layer;

As shown in FIG. 3G, an Etch Stop Layer (ESL) 506 is directly formed on the patterned oxide semiconductor active layer, and the material thereof is different according to different process requirements of different manufacturers, usually Inorganic insulating materials such as SiOx, SiNx, SiOxNy, A1 ₂ 0 ₃ , TiOx, Y ₂ 0 ₃ are required, and the purpose thereof is to reduce damage to the oxide semiconductor film during patterning of the data lines, and at the same time be effective The stability of the TFT device is improved to avoid the influence of the external environment on the TFT device.

S409, patterning the etch barrier layer;

The etch stop layer is patterned by dry etching as shown at 506a in Figure 3H. The key point in the fabrication of this step is to prevent over-etching of the gate insulating layer during how to control the etching of the etch barrier. If the control is not good, the short circuit or breakdown phenomenon between the gate metal line and the source and drain electrodes may occur during the process of fabricating the panel, thereby causing the panel to fail. If the materials with larger etching selectivity are selected separately for material selection, the above problems will be well avoided. At the same time, the combination of dry and wet etching can also avoid the above problems.

Further, there are two solutions for forming the etch barrier layer. The first solution is to deposit an etch barrier layer after depositing the active layer of the oxide semiconductor, and exposing the source electrode and the drain electrode by a patterning process. The contact via of the semiconductor, the peripheral edge pattern of the etch barrier layer is consistent with the pattern of the oxide semiconductor layer, and the ohmic contact region of the active layer of the oxide semiconductor can be directly defined by etching the via of the barrier layer; After depositing the active layer of the oxide semiconductor, patterning is performed, and then deposition of an etch barrier layer is performed. The etch barrier layer covers the entire substrate after forming the active layer of the oxide semiconductor, and then the etch barrier layer is performed. Graphical, just expose the source and drain electrodes and Where the active layer contacts, the etch stop of the other regions remains on the substrate. However, embodiments in accordance with the present invention are not limited to the above method or structure. As shown in FIG. 3H, the etch stop layer 506a may also cover only a portion of the oxide semiconductor active layer.

5410, performing metallization plasma treatment;

After the etch stop layer is prepared, a source electrode and a drain electrode are formed. Such a fabrication scheme can be combined with an active layer of an oxide semiconductor to achieve a better output of device performance. Preferably, before the source electrode and the drain electrode are formed, the surface of the oxide semiconductor can be treated with a plasma of a gas such as hydrogen, N ₂ O, CF ₄ or Ar, thereby improving the ohmic contact characteristics of the device, as shown in FIG. 3 . Shown in . Through step 410, metallized semiconductor layers 507a and 507b may be formed on the surface of the oxide semiconductor not covered by the etch barrier layer 506a.

5411, forming a data line metal layer, and patterning the source electrode and the drain electrode;

As shown in FIG. 3J, after the S409 and S410 processes, a data line metal layer is formed. First, a metal layer is deposited, and a data line and a source electrode 508a and a drain electrode 508b are formed by a patterning process. The metal layer is prepared by magnetron sputtering. The electrode materials can be selected according to different device structures and process requirements. Commonly used electrode metals are Mo, Mo-Al-Mo alloy, Mo/Al-Nd/Mo laminated structure electrode, Cu and titanium metal and its alloy, ITO electrode, Ti/Al/Ti, Mo/ITO, etc. , keeping its sheet resistance at a relatively low level. After the metal electrode layer is formed, it is patterned. It is patterned by wet etching, as shown by source 508a and drain 508b in Figure 4J.

So far, the fabrication of the thin film transistor has been completed; however, the fabrication of the array substrate further includes: formation of a passivation layer and formation of a pixel electrode, and a detailed description of the formation process of the passivation layer and the pixel electrode will be described below.

5412, formation of a passivation layer and via etching;

As shown in FIG. 3K, after the source electrode and the drain electrode are patterned, a passivation layer is formed on the entire substrate, usually using inorganic substances such as SiOx, SiNx, SiOxNy, A1 ₂ 0 ₃ , TiOx, Y ₂ 0 _{3 ,} etc. Insulating materials; At the same time, in the field of AMOLED (Active Matrix Organic Light Emitting Diode Panel), organic insulating layers such as resin materials and acrylic materials can also be used for the subsequent preparation conditions. After the passivation layer is formed, a via etching is performed by a patterning process to effect connection of the drain electrode and the pixel electrode, as shown by the via hole 509a and the via hole 509b in FIG. 3K.

S413, forming and patterning a pixel electrode; As shown in FIG. 3L, after the via is formed, the pixel electrode layer 510 is formed, and the patterning process is performed by a wet etching method. The pixel electrode is now widely used as indium tin oxide, and finally formed as shown in FIG. 3M. The oxide thin film transistor and the array substrate are shown.

Thus, the TFT device has a high on-state current Ion and a low off-state current Ioff by the structural design of the layer-optimized semiconductor active layer without increasing the number of steps, thereby improving the performance of the TFT device. Further, after the etch barrier layer is patterned, the semiconductor active layer is subjected to plasma treatment to solve the ohmic contact problem between the source electrode and the drain electrode and the oxide semiconductor active layer, thereby improving the TFT characteristics and ensuring product performance.

The fabrication process of the thin film transistor according to the embodiment of the present invention will be described below by the description of the second method. Specifically, the fabrication process of the thin film transistor can be described with reference to the method of manufacturing the array substrate shown in Figs. 5A to 5E.

In the embodiment of the present invention, in addition to the formation of the oxide semiconductor transition layer and the patterning of the data line metal layer and the oxide semiconductor transition layer (here, steps S710-S711) and the process sequence of the implementation of the first method (ie, step S410- S411) The steps may be referred to the above embodiments for the remaining steps.

The steps of the manufacturing method according to this embodiment include:

5701. Form a gate metal layer on the substrate.

5702. Graphically pattern the gate metal layer.

5703. Form a gate insulating layer on the gate.

5704. Process the surface of the gate insulating layer.

S705, forming a semiconductor layer with high conductivity.

5706, forming a semiconductor layer having low conductivity, a semiconductor layer having high conductivity and a semiconductor layer having low conductivity constitute an oxide semiconductor active layer.

5707. Patterning an active layer of an oxide semiconductor.

5708. Form an etch barrier layer.

S709, patterning the etch barrier layer;

It is the same as the first method before the step S709, except that the process is different from the process of the step S410 S411, and the process steps are the same after the step S412. Therefore, the present invention describes the steps S710 to S711 in the second method.

S710, forming a semiconductor transition layer;

As shown in FIG. 5A, after the process of step S701 709 is completed, the substrate 801 is A gate electrode 802a and a gate line 802b, a gate insulating layer 803, a high-conductivity semiconductor layer 804, a low-conductivity semiconductor layer 805, and an etch barrier layer 806 are formed. Thereafter, a layer of low oxygen, high conductivity oxide semiconductor, ie, a semiconductor transition layer, is formed over the patterned etch stop layer prior to formation of the data line metal layer. The oxide semiconductor transition layer has a thickness of 5 to 50 nm as shown by 807 in Fig. 5B. Forming a transition layer between the data line metal layer and the oxide semiconductor active layer, achieving ohmic contact between the source electrode and the drain electrode and the oxide semiconductor active layer, thereby minimizing the contact resistance of the device, thereby improving the device Performance. The oxide semiconductor active layer, the semiconductor transition layer, and the combination of the source and drain electrodes form a sandwich structure device that maximizes device performance.

According to an embodiment of the present invention, in the process of fabricating a thin film transistor, the layered optimization scheme of the above sandwich structure can improve the performance of the device. The material of the semiconductor transition layer and the semiconductor active layer can be made of homogenous or homogenous high-conductivity materials. Currently widely used oxide semiconductor active layer materials are indium gallium oxide (IGZO), indium tin oxide (ITZO), indium oxide (IZO), etc., and complexes of different ratios associated therewith. As long as the process is controlled, its high-conductivity performance is achieved, and the ohmic contact between the source and drain electrodes and the active layer of the oxide semiconductor is reduced. The main production methods are magnetron sputtering deposition and solution method. Different etching methods can be selected due to different process requirements.

S711, forming a data line metal layer, and patterning the data line metal layer and the semiconductor transition layer;

As shown in FIG. 5C, after the S710 process is completed, a data line metal layer 808 is formed over the semiconductor transition layer. The metal electrode is prepared by magnetron sputtering, and the electrode material can be selected according to different device structures and process requirements. Commonly used electrode metals are Μο, Μο-Α1-Μο alloy, Mo/Al-Nd/Mo laminated structure electrode, Cu and titanium metal and its alloy, ITO electrode, Ti/Al/Ti, Mo/ITO Etc., keep its sheet resistance at a relatively low level. After the data line metal layer is formed, it is patterned. The pattern was patterned by wet etching to obtain the source electrode 808a and the drain electrode 808b shown in Fig. 7D. At this step, it must be noted that the simultaneous etching of the source and drain electrodes and the oxide semiconductor transition layer is achieved, which not only improves the performance of the device but also increases the overall process, and does not increase production. the cost of.

S712, formation of a passivation layer, and via etching. S713, formation and patterning of the pixel electrode layer;

Finally, an oxide thin film transistor and an array substrate as shown in Fig. 5E are formed. As shown in FIG. 5E, 809 is a passivation layer, and 810 is a pixel electrode layer. Thus, the oxide thin film transistor array substrate is completed.

In this way, the device scheme of the sandwich structure optimized by layering can improve the performance of the device without increasing the process, not only has a high on-state current Ion and a low off-state current Ioff, but also due to the semiconductor transition layer. The existence of the ohmic contact between the source and drain electrodes and the active layer is solved, thereby ensuring device characteristics and product performance. The embodiment of the present invention can improve the performance of the TFT device, thereby playing a very important role in improving the overall substrate yield and reducing the cost.

It can be understood that the structure and preparation method of the oxide thin film transistor are described by way of example of the bottom gate structure. However, embodiments in accordance with the present invention are not limited to the above described bottom gate structure, and may be top gate structures or other various oxide thin film transistor structures. According to an embodiment of the present invention, a high-conductivity oxide semiconductor layer is used near the gate side, thereby enabling high on-state current

Ion; In addition, the low-on-state oxide semiconductor layer is close to the source/drain electrode side, so that a low off-state current Ioff can be realized. Therefore, if the oxide semiconductor thin film transistor is a top gate structure, a highly conductive semiconductor layer needs to be disposed on the top layer, and a low conduction semiconductor layer needs to be disposed on the bottom layer. That is, the oxide semiconductor layer is disposed between the source/drain electrode and the gate electrode, and the low-conductivity semiconductor layer in the oxide semiconductor layer is disposed on the source/drain electrode side, and the high-conductivity semiconductor layer is disposed. On the side of the gate.

In addition, the "high conduction capability" and "low conduction capability" in the semiconductor layer having high on capability and the semiconductor layer having low on capability according to the embodiment of the present invention are two relative concepts, and are set such that both are opened. The purpose of the current and the off current. Further, in the embodiment according to the present invention, the specific conductivity of the semiconductor layer having high on capability and low on capability is not particularly limited and may be arbitrarily selected depending on the actual situation.

In each of the above embodiments, the semiconductor active layer has been described by taking a metal oxide semiconductor material as an example, but the semiconductor material according to an embodiment of the present invention is not limited thereto. In the case where the semiconductor active layer is made of a metal oxide semiconductor material, the semiconductor layer having high conductivity can be used with a metal oxide having a low oxygen content, and the semiconductor layer having a low conductivity can be used with a higher oxygen content. High metal oxides. Under the structure of the multilayered semiconductor active layer, the specific oxygen content can be set to an appropriate value according to actual needs. In addition, it should be noted that the high conduction capability and the low conduction performance in the embodiment of the present invention are The semiconductor material of the force is not limited to the above-mentioned metal oxide having a low oxygen content and a high oxygen content.

Further, in the embodiment of the above manufacturing method, only an example of the manufacturing method of the bottom gate structure thin film transistor is given. For the fabrication method of the top gate structure thin film transistor, the fabrication order of the gate electrode, the gate insulating layer, the semiconductor active layer, the source electrode and the drain electrode is different from that of the bottom gate structure. For example, the source and drain electrodes, the semiconductor active layer, the gate insulating layer, and the gate electrode may be sequentially formed. For other structures or more detailed steps, reference may be made to an example of a method of fabricating a bottom gate structure, which will not be described herein.

The present invention also provides an array substrate comprising the thin film transistor described in any of the above embodiments, and the structure shown in Figs. 2 and 4 can be specifically referred to.

In the meantime, the present invention provides a display device, which may specifically be a liquid crystal display, an organic light emitting diode (OLED) display, an active electronic paper display, and other display devices driven using the above thin film transistor and array substrate.

The above is only an exemplary embodiment of the present invention, and is not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims.

Claims

Claim

A thin film transistor comprising: a gate, a gate insulating layer, a semiconductor active layer, a source electrode, and a drain electrode, wherein

The semiconductor active layer is a multilayer structure including at least a semiconductor layer having high conductivity and a semiconductor layer having low conductivity;

The high-conductivity semiconductor layer is adjacent to the gate, and the low-conductivity semiconductor layer is adjacent to the source electrode and the drain electrode.

2. The thin film transistor according to claim 1, wherein

The low-conductivity semiconductor layer and the source and drain electrodes are further provided with a high-conductivity semiconductor transition layer.

3. The thin film transistor according to claim 2, wherein

The high conductivity semiconductor transition layer is the same material as the high conductivity semiconductor layer.

4. The thin film transistor according to claim 2 or 3, wherein

The semiconductor transition layer has a thickness of 5 to 50 nm.

The thin film transistor according to any one of claims 1 to 4, wherein

A metallization semiconductor layer is further disposed between the low-conductivity semiconductor layer and the source and drain electrodes.

The thin film transistor according to any one of claims 1 to 5, wherein

An etch barrier layer is further disposed between the high conductivity semiconductor layer and the source and drain electrodes.

The thin film transistor according to any one of claims 1 to 6, wherein a material of the semiconductor active layer is a metal oxide material.

The thin film transistor according to any one of claims 1 to 5, wherein

The gate is below the semiconductor active layer, and the source and drain electrodes are located above the active layer of the semiconductor;

An etch stop layer is further disposed between the semiconductor active layer and the source and drain electrodes.

The thin film transistor according to any one of claims 1 to 5, wherein

The gate is above the semiconductor active layer, and the source and drain electrodes are located in the half Below the active layer of the conductor.

10. A method of fabricating a thin film transistor, comprising: a process of forming a gate electrode, a gate insulating layer, a semiconductor active layer, a source electrode, and a drain electrode on a substrate;

The process of forming the semiconductor active layer includes:

Forming a semiconductor layer with high conductivity near the gate side;

A semiconductor layer having a low conductivity is formed on the side close to the source electrode and the drain electrode.

The method of manufacturing a thin film transistor according to claim 10, wherein the semiconductor active layer is formed after the gate electrode and the gate insulating layer and before the source electrode and the drain electrode, and The method also includes forming a pattern of the etch stop layer.

The method of manufacturing a thin film transistor according to claim 10, wherein the semiconductor active layer is formed after the source and drain electrodes and before the gate electrode and the gate insulating layer.

The method of manufacturing a thin film transistor according to claim 11, wherein after forming the etch stop layer between the semiconductor active layer and the source electrode and the drain electrode, and forming the source electrode and Before draining the electrode, it also includes:

The surface of the semiconductor active layer not covered with the etch barrier layer is metallized by a plasma treatment process to form a metallized semiconductor layer on the surface of the semiconductor active layer.

The method of manufacturing a thin film transistor according to claim 11 or 13, wherein, between the semiconductor active layer and the source and drain electrode layers, further comprising:

After forming the etch stop layer and before forming the source and drain electrodes, the method further includes: forming a high conductivity semiconductor transition layer on the substrate on which the etch barrier layer pattern is formed.

The method of manufacturing a thin film transistor according to claim 12, further comprising: between the semiconductor active layer and the source and drain electrodes, further comprising:

After forming the source and drain electrodes and before forming the semiconductor active layer, the method further includes: forming a semiconductor layer having high conductivity on the substrate on which the source and drain electrodes are formed.

The method of manufacturing a thin film transistor according to any one of claims 10 to 15, wherein the semiconductor transition layer is the same material as that of the high conductivity semiconductor layer.

The method of manufacturing a thin film transistor according to any one of claims 10 to 15, wherein The semiconductor transition layer has a thickness of 5 to 50 nm.

The method of manufacturing a thin film transistor according to claim 11, wherein the process of forming the semiconductor active layer and the etch stop layer comprises:

Forming a semiconductor active layer film and an etch barrier film on the substrate on which the gate insulating layer is formed;

The semiconductor active layer and the etch stop layer are formed by one patterning process.

The method of manufacturing a thin film transistor according to any one of claims 10 to 12, wherein the semiconductor active layer material is a metal oxide material.

An array substrate comprising the thin film transistor according to any one of claims 1 to 9.

A display device comprising the array substrate of claim 20.