WO2013155944A1

WO2013155944A1 - Boundary clock, transparent clock, and method for clock transmission

Info

Publication number: WO2013155944A1
Application number: PCT/CN2013/074098
Authority: WO
Inventors: 陈雨; 杨晓东
Original assignee: 中兴通讯股份有限公司
Priority date: 2012-04-19
Filing date: 2013-04-11
Publication date: 2013-10-24
Also published as: CN103378916A

Abstract

Disclosed in the present invention are a boundary clock, a transparent clock, and a method for clock transmission, comprising: an ordinary clock (OC)-slave clock physical entity of a boundary clock completes clock or time synchronization with a master clock, and performs clock or time synchronization with an intermediate physical entity of said boundary clock; said intermediate physical entity performs clock or time synchronization with an OC-master clock physical entity of said boundary clock, and said OC-master clock physical entity performs clock or time synchronization with a slave clock. The present invention, by means of virtual network elements, solves the problem of support for IEEE 1588v2 protocol in networks where implementing IEEE 1588v2 protocol is not possible.

Description

Clock transmission method, boundary clock and transparent transmission clock

Technical field

The present invention relates to a general-purpose clock synchronization technique, and more particularly to a clock transmission method, a boundary clock, and a transparent transmission clock.

Background technique

The air interface synchronization of wireless technologies such as CDMA2000, TD-SCDMA, LTE-TDD and LTE-A in wireless systems, and the application of Multimedia Broadcast Multicast Service (MBMS) have corresponding requirements for time synchronization. In these wireless systems, the base station controller (BSC/RNC) typically transmits time to the base station, which requires the intermediate backhaul network to support time synchronization across the network.

The IEEE 1588v2 protocol is a network clock synchronization protocol that can be implemented by the Institute of Electrical and Electronics Engineers (IEEE) to achieve accurate clock synchronization. Its accuracy can reach sub-microseconds. It is widely used in Ethernet, communication networks and systems, and distribution. Fields such as measurement and control. With the continuous development of the 1588 clock synchronization technology, its application in the field of communication is now more and more extensive.

The IEEE 1588v2 protocol implements clock or time synchronization by exchanging synchronization messages between the master clock (1588v2 Master) and the slave clock (1588v2 Slave). The master clock and the slave clock are also called ordinary clocks (OCs) in the protocol. ).

FIG. 1 is a schematic diagram of a master-slave clock synchronization message exchange based on the IEEE 1588v2 protocol, and the synchronization information exchange process includes:

Step A. The 1588v2 Master periodically sends a synchronization packet (Sync packet) to the 1588v2 Slave, and sends the timestamp T1 timestamp of the synchronization packet to the 1588v2 Slave through the synchronization packet or the follow-up packet (FollowUp packet).

Step B. After receiving the synchronization packet, the 1588v2 Slave records the timestamp of the T2 time of the synchronization packet, and parses the T1 timestamp from the synchronization packet or the follow-up packet.

If the 1588v2 Slave and the 1588v2 Master are to achieve clock (frequency) synchronization, the T1 and T2 timestamps obtained in steps A and B can meet the clock synchronization requirements. The current time (phase) is synchronized, and steps 〇 and 0 are also required.

Step C. The 1588v2 Slave sends a delay request message (DelayReq message) to the 1588v2 Master and records the timestamp of the T3 time.

Step D. After receiving the delay request message, the 1588v2 Master records the timestamp of the arrival time T4 and promptly responds to the delayed response message (DelayResp message) and sends the T4 timestamp to the 1588v2 Slave, 1588v2 in the message. Slave parses the T4 timestamp from the delayed response message and uses these four timestamps to estimate and calibrate the time offset.

The 1588 clock is a typical packet-type clock. The Delay Delay jitter (PDV) of the master-slave transmission network equipment introduces noise into the clock or time signal carried by the end-to-end transmitted packet. 1588 synchronization performance has a significant impact. The Boundary Clock (BC) and the Transparent Clock (TC) in the IEEE 1588v2 protocol can greatly reduce the impact of PDV on the 1588 clock synchronization performance. From the current application of 1588, it is generally The transmission device of the 1588 master-slave device is required to support 1588v2. The role of the transmission device can be selected as the boundary clock or transparent transmission clock according to the actual application scenario.

Figure 2 shows the BC model in the IEEE 1588v2 protocol. The processing unit includes:

1588v2 Slave port: The input port of the 1588 signal. The input signal is reflected in the form of 1588 ·^艮 before generating the timestamp;

1588 timestamp generator: 1588 ^ The timestamp generation process of input and output, 1588 message forms 1588 clock signal after passing the 1588 timestamp generator;

System clock and time unit: Local clock or time passes 1588 input signal is controlled as

1588 BC network element system clock and time;

1588v2 Master port: The output port of the 1588 signal. The 1588BC network element outputs the controlled system clock through the 1588v2 Master port. The 1588 clock is transmitted to the next level 1588 network element.

Figure 3 shows the TC model in the IEEE 1588v2 protocol. The processing unit includes:

Local clock and time unit: 1588 TC NE working clock and time, providing working clock and time for the time set and delay correction processing unit. 1588 TC NE working clock and time are not required to be controlled by external clock and time. Reference source Incoming time gathering unit: inputting the input time of the input 1588 signal, and the incoming time is carried in the 15884 text in the form of a time stamp;

1588 signal transmission unit: The 1588 signal is transparently transmitted through the transparent transmission unit inside the 1588 TC network element, and the specific physical form of the 1588 signal transmission unit is usually an Ethernet switch chip;

The time-stamping and delay-correcting processing unit: the output time of the output 1588 signal is collected, and is compared with the incoming time of the 1588 message, and the resident delay of the 1588 signal in the 1588 TC network element is calculated, and The dwell delay is added to the Correction Field of the 1588 message.

From the functions of BC and TC in the standard IEEE 1588v2 protocol, BC mainly reduces the impact of PDV on the end-to-end 1588 master-slave synchronization performance by step-by-step control of clock or time. The TC mainly reduces the noise introduced by the PDV by correcting the pass delay of the clock or time signal.

In the 1588 clock subnet, the backhaul network generally plays the role of BC and TC. This requires that each network element of the backhaul network supports the IEEE 1588v2 protocol, but the IEEE 1588v2 protocol is usually implemented in the Ethernet port of the network element. For non-Ethernet backhaul networks, standard IEEE 1588v2 BC and TC cannot be implemented. Summary of the invention

The technical problem to be solved by the present invention is to provide a clock transmission method, a boundary clock, and a transparent transmission clock, which solves the problem that the non-Ethernet backhaul network cannot support the IEEE 1588v2 protocol.

To solve the above technical problem, a clock transmission method of the present invention includes:

The normal clock of the boundary clock - the slave clock physical entity completes the clock or time synchronization with the master clock, and the intermediate physical entity performs clock or time synchronization on the normal clock-master clock physical entity of the boundary clock, the normal clock-master The clock physical entity clocks or time synchronizes the slave clock.

When clock synchronization is performed, the physical entities of the boundary clock are clocked by a clock signal; when time synchronization is performed, the physical entities of the boundary clock are clocked by a clock signal, and time is performed by a time signal. Synchronize. The clock is a STM-N line clock when the physical network element is a synchronous digital system (SDH) physical network element; when the physical network element is a synchronous Ethernet network, the clock signal is a synchronous Ethernet clock; Microwave air interface 1 second pulse (PPS); When the physical network element is a level network element, the time signal is 1PPS cable coded in the form of 1PPS cable or timestamp.

A clock transmission method includes:

After receiving the packet sent by the master clock, the physical entity of the transparent transmission clock collects the incoming time of the packet, multiplies the incoming time by (-1) and adds it to the synchronization packet correction domain, and transparently transmits the packet to the transparent packet. An intermediate physical entity that transmits a clock;

The intermediate physical entity transparently transmits the packet to the physical entity where the output port is located, and the physical entity where the output port is located collects the time of the packet, and multiplies the time of the output by (+1) to the synchronization packet correction domain. .

When clock synchronization is performed, the physical entities of the transparent transmission clock are clock-synchronized by a clock signal; when time synchronization is performed, the physical entities of the transparent transmission clock are clock-synchronized by a clock signal, and the time signal is passed. Time synchronization.

A boundary clock includes: a normal clock - a slave clock physical entity, an intermediate physical entity, and a normal clock - a master clock physical entity, where:

The normal clock-slave clock physical entity is set to: complete with the clock or time of the master clock, the intermediate physical entity is set to: clock or time synchronize the normal clock-master clock physical entity of the boundary clock;

The normal clock-master clock physical entity is set to: clock or time synchronize the slave clock. The common clock-slave clock physical entity includes: a standard interface and processing unit, a clock and time signal input/output processing unit, and a system clock and time synchronization maintenance unit, where:

The standard interface and the processing unit are configured to: implement a protocol interface, and interface with a network element supporting the corresponding protocol;

The clock and time signal input/output processing unit is configured to: implement an input signal to the system Clock and time reference source signal conversion; and, to achieve system clock and time to output clock and time signal conversion;

The system clock and time synchronization maintenance unit is configured to: implement reference clock selection of system clock and time, synchronization and distribution of clock and time.

The standard interface and processing unit includes: a 1588v2 protocol processing module, a 1588v2 timestamp generator module, and a 1588v2 signal input/output processing module, where:

The 1588v2 protocol processing module is configured to: read a local timestamp from the 1588v2 timestamp generator module, and parse the timestamp from the 1588v2 protocol packet, match the timestamp into a pair, and send the timestamp to the 1588v2 signal input and output. Processing module

The 1588v2 timestamp generator module is configured to: identify and check the output and input Ethernet messages, and generate a timestamp;

The 1588v2 signal input/output processing module is configured to: output a clock or a time reference source signal according to the paired timestamps sent by the 1588v2 protocol processing module.

The clock and time signal input/output processing unit comprises: a clock signal input/output processing module and a time signal input/output processing module, wherein:

The clock signal input/output processing module is configured to: convert the input signal to the system clock reference source signal; and, implement conversion of the system clock to the output clock signal;

The time signal input/output processing module is configured to: convert the input signal to the system time reference source signal; and implement conversion of the system time to the output time signal.

The system clock and time synchronization maintenance unit includes: a system clock and time distribution module, a system clock and time synchronization module, and a clock and time reference source selection module, wherein:

The clock and time reference source selection module is configured to: select from a clock or time reference source signal output by the 1588v2 signal input/output processing module and a clock or time reference source signal sent by the clock and time signal input/output processing unit a primary clock and a time reference source, and output to the system clock and time synchronization module;

The system clock and time synchronization module is configured to: synchronize the system clock with time according to the primary clock and the time reference source, and output the synchronized system clock and time signal;

The system clock and time distribution module is configured to: perform system clock and time distribution. The common clock-master clock physical entity includes: a 1588v2 protocol processing module, a 1588 timestamp generator module, a clock and time signal input/output processing unit, and a system clock and time synchronization maintenance unit;

The intermediate physical entity includes: a clock and time signal input/output processing unit and a system clock and time synchronization maintenance unit.

A transparent transmission clock includes: a boundary physical entity and an intermediate physical entity, where:

The border physical entity is configured to: after receiving the packet sent by the master clock, collect the packet incoming time, multiply the incoming time by (-1), and add the packet to the synchronization packet correction domain, and transparently transmit the packet to the middle. After receiving the packet sent by the intermediate physical entity, the time of collecting the packet is multiplied by (+1) and added to the synchronization packet correction field;

The intermediate physical entity is configured to: transparently transmit the "3⁄4" text to the physical entity where the output port is located. The boundary physical entity includes: a clock and time signal input/output processing unit, a system clock and a time synchronization maintenance unit, and a delay correction processing. Unit, where:

The clock and time signal input/output processing unit is configured to: convert the input signal to the system clock and the time reference source signal; and, implement conversion of the system clock and time to the output clock and time signals;

The system clock and time synchronization maintenance unit is configured to: implement reference clock selection of system clock and time, synchronization and distribution of clock and time;

The delay correction processing unit is configured to: implement transparent transmission of signals and correction of resident delay. The delay correction processing unit includes: an in-time collection module, a 1588 signal transparent transmission module, and an output timing and delay correction processing module, wherein:

The input time collection module is configured to: collect the time of the 1588 signal, and send the 1588 signal to the 1588 signal transparent transmission module;

The 1588 signal transparent transmission module is configured to: when receiving the 1588 signal sent by the ingress time collection module, transparently transmit the 1588 signal to the next physical entity; when receiving the transparent transmission of the upper physical entity 1588 When the signal is transmitted, the 1588 signal is transparently transmitted to the time set and the delay correction processing module; the output time set and the delay correction processing module are set to: collect the received time of the 1588 signal and perform signal delay Correction processing, outputting the corrected 1588 signal to the slave clock. The intermediate physical entity includes: a clock and time signal input and output processing unit, a system clock and time synchronization maintenance unit, and a delay correction processing unit, wherein the delay correction processing unit includes: 1588 signal transparent transmission module, wherein:

The 1588 signal transparent transmission module is configured to transparently transmit the received 1588 signal transparently transmitted by the upper physical entity to the next physical entity.

In summary, the present invention solves the problem of supporting the IEEE 1588v2 protocol in a network in which the IEEE 1588v2 protocol cannot be implemented through a virtual network element.

BRIEF abstract

1 is a schematic diagram of a master-slave clock synchronization packet exchange in the IEEE 1588v2 protocol in the prior art; FIG. 2 is a schematic diagram of a method for implementing an IEEE 1588v2 protocol BC in the prior art;

3 is a schematic diagram of a method for implementing an IEEE 1588v2 protocol TC in the prior art;

4 to FIG. 5 are schematic diagrams of the 1588v2 virtual BC according to the embodiment;

6 is a schematic diagram of a 1588v2 virtual TC according to the embodiment;

Figure 7 is a schematic diagram of a physical entity of the present embodiment.

Preferred embodiment of the invention

This embodiment provides a virtual network element supporting IEEE 1588v2, including a virtual TC supporting IEEE 1588v2 and a virtual BC supporting IEEE 1588v2, where:

(1) The virtual BC supporting IEEE 1588v2 is physically represented as a non-Ethernet backhaul network. The network consists of multiple physical entities, including:

(1) The virtual BC is connected to the 1588v2 Master through the IEEE 1588v2 clock or time interface. The physical entity connected to the 1588v2 Master is the normal clock-slave clock (OC-Slave) physical entity, and the BC is synchronized to the input 1588v2 clock or time signal. ;

(2) Virtual BC internal physical entities achieve frequency synchronization through clock signals;

The clock signal has different forms for different transmission networks. For an SDH (Synchronous Digital Hierarchy) network, the clock signal is an STM-N line clock; for a microwave network, the clock signal is a microwave air interface clock; For synchronous Ethernet networks, the clock signal is the SyncE (synchronous Ethernet) clock.

(3) The time synchronization of the internal physical entities of the virtual BC is realized by an internally defined time signal, and the time signal can be selected in different forms, such as a 1 second pulse (PPS) signal;

(4) The virtual BC is connected to the 1588v2 Slave through the IEEE 1588v2 clock or time interface. The physical entity connected to the BC and the 1588v2 Slave is the physical clock of the normal clock-main clock (OC-Master), and the clock or time is output from the BC to the 1588v2 Slave. signal.

(2) Supporting the virtual TC of IEEE 1588v2, physically represented as a non-Ethernet backhaul network, the network consists of multiple physical entities, including:

(1) The virtual TC interfaces with the 1588v2 Master through the IEEE 1588v2 clock or time interface. The physical entity to which the TC is connected to the 1588v2 Master is a boundary physical entity, and implements the function of time-in-time collection;

(2) Frequency synchronization between physical entities through clock signals;

The clock signal has different forms for different transmission networks. For SDH networks, the clock signal is the STM-N line clock. For the microwave network, the clock signal is the microwave air interface clock. For the synchronous Ethernet network, the clock signal is the SyncE clock.

(3) Time synchronization between physical entities through internally defined time signals;

The time signal can be selected in different forms, such as the 1PPS signal.

(4) The TC transparent transmission signal is transparently transmitted through the intermediate physical entity; the virtual TC is connected to the 1588v2 Slave through the IEEE 1588v2 clock or time interface. The physical entity to which the TC and the 1588v2 Slave are connected is the physical entity where the output port is located. The physical entity belongs to the boundary physical entity. It implements the time set and the TC internal resident delay correction function.

The physical entity constituting the virtual network element supporting the IEEE 1588v2, such as the BC and the TC, in the embodiment includes:

The standard interface and the processing unit, including the 1588v2 protocol processing module, the 1588 timestamp generator module, and the 1588v2 clock input/output processing module, mainly implement the IEEE 1588v2 protocol interface, and can interface with other network elements supporting the IEEE 1588v2 protocol; The clock and time signal input/output processing unit includes a clock signal input/output processing module and a time signal input/output processing module. Conversion of the input signal to the system clock and the time reference source signal for the input clock and time signals; conversion of the system clock and time to the output clock and time signals for the output clock and time signals;

The system clock and time synchronization maintenance unit includes a system clock and time distribution module, a system clock and time synchronization module, and a clock and time reference source selection module, which mainly implements reference source selection, synchronization, and distribution of the system clock and time. The system clock and time are the clock and time reference of the physical entity.

The delay correction processing unit includes an entry time collection module, a 1588 signal transparent transmission module, and an output time set and a delay correction processing module. The unit mainly implements the transparent transmission of the 1588 signal and the correction of the internal resident delay of the virtual network element.

The specific embodiments of the present embodiment will be further described in detail below with reference to the accompanying drawings.

FIG. 4 is a 1588v2 virtual BC according to the embodiment. The physical entity that the BC is connected to the 1588v2 Master is a common clock-slave physical entity, and implements the 1588v2 OC-Slave function (referred to as the OC-Slave physical entity of the BC for short), and implements BC synchronization on the input 1588v2 clock or time signal; The synchronization mode between physical entities inside the BC may be clock (frequency) synchronization or time (phase) synchronization, and is related to whether the virtual network element's 1588 synchronization application mode is clock synchronization or time synchronization. The physical entity that is connected to the 1588v2 Slave is the common clock-primary clock physical entity, which implements the 1588v2 OC-Master function (the physical entity is the OC-Master physical entity of the BC), and implements the clock or time signal output from the BC to the 1588v2 Slave.

(1) When using 1588-based clock (frequency) synchronization, as shown in Figure 4, the BC internally uses clock signals to implement clock synchronization between physical entities to implement 1588-based clock transmission.

The clock signal between physical entities in the BC depends on the physical network element where the physical entity resides. For a microwave physical network element, the clock signal is generally a microwave air interface clock; for an SDH physical network element, the clock signal is generally an STM-N line clock.

(2) When using 1588-based time (phase) synchronization, as shown in Figure 5, the BC internally uses the clock signal to achieve clock synchronization between physical entities. On the basis of clock synchronization, in BC. The time (phase) synchronization between the physical entities inside the virtual network element is implemented by the time signal to implement time transfer based on 1588. The time signal between each physical entity in the BC is generally a 1PPS signal. In actual application, the 1PPS signal can be embodied in different forms. For the microwave physical network element, the time signal is generally 1PPS for the microwave air interface. For the level network element, the time signal is generally 1PPS cable coded in the form of 1PPS cable or timestamp. This embodiment does not limit the specific form of the 1PPS signal.

The specific process of 1588 signal transmission is described as follows:

(1) The 1588v2 Master sends a synchronization packet and records the timestamp of the T1 timeout of the packet, and sends the timestamp T1 of the synchronization packet to the OC-Slave physical entity of the BC through the synchronization packet or the follow-up packet.

(2) The OC-Slave physical entity of the BC records the timestamp of the T2 time of the packet when receiving the synchronization packet of the 1588v2 Master. The 1588 packet is terminated internally by the OC-Slave physical entity that is connected to the 1588v2 Master. The OC's OC-Slave physical entity uses the T1 and T2 timestamps to complete the clock synchronization between the BC and the 1588v2 Master. If the BC is used for time transfer, the BC OC-Slave physical entity needs to send a delay request message and record its transmission time. T3 timestamp;

(3) After receiving the delay request message, the 1588v2 Master records the T4 timestamp at the arrival time and promptly responds to the delayed response message and sends the T4 timestamp to the OC-Slave physical entity in the message;

(4) The OC's OC-Slave physical entity parses the T4 timestamp from the delayed response message, and uses these four timestamps to complete the estimation and calibration of the time offset to achieve time synchronization between the BC and the 1588v2 Master;

(5) The OC-Master physical entity of the BC sends a synchronization packet to the 1588v2 Slave cycle, and

Slave, if BC is used for clock transmission, 1588v2 Slave uses T1 and T2 timestamps to complete 1588v2 Slave and BC clock synchronization; if BC is used for time transfer, 1588v2 Slave needs to send a delay request message and record its transmission time T3 timestamp. After receiving the delay request message, the OC-Master physical entity of the BC records the timestamp of the arrival time T4 and quickly responds to the delayed response message and sends the T4 timestamp to the 1588v2 Slave in the message, and the 1588v2 Slave is extended. The time reply message parses out the T4 timestamp, and uses these four timestamps to complete the estimation and calibration of the time offset to achieve 1588v2. Slave is synchronized with the time of BC.

Figure 6 is a 1588v2 virtual TC of the present embodiment.

The time (phase) signal between the physical entities inside the TC needs to realize the time synchronization between the physical entities to ensure the accuracy of the 1588 signal resident delay calculation. The TC internally uses the clock signal to implement clock synchronization between physical entities. On the basis of clock synchronization, the TC internally uses time signals to implement time synchronization between physical entities.

The clock signal between physical entities in the TC depends on the physical network element where the physical entity resides. For a microwave physical network element, the clock signal is generally a microwave air interface clock; for an SDH network element, the clock signal is generally an STM-N line clock. The time signal between each physical entity in the TC is generally a 1PPS signal. In practical applications, the 1PPS signal can be embodied in different forms. For the micro-wave physical network element, the time signal is generally 1PPS for the microwave air interface. For the level network element, the time signal is generally 1PPS cable coded in the form of 1PPS cable or time stamp. This embodiment does not limit the specific form of the 1PPS signal.

The specific process of 1588 signal transmission is described as follows:

(― ) 1588v2 Master sends a synchronous packet to the 1588v2 Slave (virtual TC transparent transmission signal) When the physical entity of the TC enters the virtual TC, it collects the incoming time of the synchronization packet (input timestamp) and multiplies it by (-1). ) accumulate in the Correction Field of the synchronization message (Correction Field);

(2) Synchronization >3⁄4 text is transparently transmitted inside the virtual TC. When the physical entity of the virtual TC output port is located, the time of the synchronization message is output (output timestamp) and multiplied by (+1) to the synchronization message. In the correction domain, the resident delay of the synchronization message inside the virtual TC is corrected.

(3) The delay measurement request message sent by the 1588v2 Slave to the 1588v2 Master (if any) enters the virtual TC, and collects the incoming time of the message and multiplies it by (-1) to the correction domain of the synchronization message;

(4) The delay measurement request is transparently transmitted inside the virtual TC. After the physical entity where the virtual TC output port is located, the delay measurement request is collected and the time is multiplied by (+1) to the delay measurement request. In the correction domain of the message, the delay of the delay measurement request message within the virtual TC is corrected. The composition of the unit, specifically including the processing unit is as follows:

Standard interface and processing unit, including I588v2 protocol processing module, 1588v2 timestamp generator module and 1588v2 signal input and output processing module, wherein each module has the following functions:

1588v2 protocol processing module: complete input and output 1588v2 protocol "^ text processing, achieve different

The IEEE 1588v2 protocol clock type handles the 1588v2 protocol and completes timestamp collection and matching. The collection process includes reading the local timestamp from the 1588v2 timestamp generator and parsing the timestamp from the 1588v2 protocol message. The collected timestamps are matched and sent to the 1588v2 signal input/output processing module.

1588v2 signal input and output processing module: The module input is a pair of 1588 timestamps, and the output is 1588 clock or time reference source signal;

The 1588 timestamp generator module: identifies and checks the output and input Ethernet messages, and generates 1588 timestamps for event messages conforming to the standard IEEE 1588v2 protocol;

The clock and time signal input/output processing unit includes a clock signal input/output processing module and a time signal input/output processing module. The functions of each module are as follows:

Clock signal input and output processing module: for input clock signal, realize conversion of input signal to system clock reference source signal; for output clock signal, realize conversion of system clock to output clock signal;

Time signal input and output processing module: for input time signal, realize conversion of input signal to system time reference source signal; for output time signal, realize conversion of system time to output time signal;

The system clock and time synchronization maintenance unit includes a system clock and time distribution module, a system clock and a time synchronization module, and a clock and time reference source selection module, wherein the functions of each module are as follows:

Clock and time reference source selection module: Input is multi-channel clock and time signal, including clock or time reference source signal, and other classes sent by clock and time signal input and output processing unit Type clock or time reference source signal. The module determines the clock and time reference source used by the system according to the system clock and the time reference source state and priority information, and selects the main clock and the time reference source output to the system clock and time synchronization module;

System clock and time synchronization module: The module input is the system clock and time reference source signal. According to the main clock and the time reference source, the system clock and time synchronization are mainly realized, and the synchronized system clock and time signal are output;

System clock and time distribution module: The module input is the synchronized system clock and time signal, which mainly completes the system clock and time distribution to each module inside the device.

The delay correction processing unit comprises an entry time collection module, a 1588 signal transparent transmission module, and an output time set and a delay correction processing module, wherein the functions of each module are as follows:

The input time collection module: transmits the 1588 signal to the virtual network element, and sends the 1588 signal that has been collected to the 1588 signal transparent transmission module;

1588 signal transmission module: Implement 1588 signal transmission. Specifically, when the physical entity is a boundary physical entity of the TC, if the input is a transparent transmission 1588 signal from the collected time of the incoming time collection module, the signal is directly transmitted to the next physical entity; If the input is a 1588 signal transparently transmitted by the physical entity of the upper level, the signal is transmitted and transmitted to give a time set and a delay correction processing module. When the physical entity is an intermediate physical entity inside the TC, the input is a 1588 signal transparently transmitted by the physical entity of the upper level, and the signal is directly transmitted to the next TC physical entity;

The time set and delay correction processing module: the module input is a transparent transmission 1588 signal from the 1588 signal transparent transmission module, and the time of transmitting the 1588 signal is transmitted and the signal delay correction processing is performed, and the corrected 1588 is to be corrected. The signal is output to 1588v2 Slave.

The physical entity may choose to include some of the processing units in the virtual BC/TC, as shown in Table 1 and Table 2:

Table 1

1588v2 protocol processing module

1588v2 signal input and output processing module

1588 timestamp generator module

Clock signal input and output processing module Time signal input and output processing module System clock and time distribution module

System clock and time synchronization module

Clock and time reference source selection module

Incoming time acquisition module

1588 signal transmission module

Time acquisition and delay correction processing module

Table 2

The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention. Various modifications and variations of the present invention are possible in the art. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and scope of the present invention are intended to be included within the scope of the present invention.

Industrial applicability

The present invention solves the problem of supporting the IEEE 1588v2 protocol in a network in which the IEEE 1588v2 protocol cannot be implemented through a virtual network element.

Claims

Claim

1. A clock transmission method, comprising:

2. The method according to claim 1, wherein, when clock synchronization is performed, physical functions of the boundary clock are clocked by a clock signal; when time synchronization is performed, physical entities of the boundary clock are After clock synchronization by the clock signal, time synchronization is performed by the time signal.

3. The method according to claim 2, wherein: the microwave air interface clock; when the physical network element is a synchronous digital hierarchy (SDH) physical network element, the clock signal is an STM-N line clock; and the physical network element is a synchronous Ethernet In the network network, the clock signal is a synchronous Ethernet clock; a microwave air interface 1 second pulse (PPS); when the physical network element is a level network element, the time signal is a 1PPS cable or a time stamped 1PPS signal code.

4. A clock transmission method, comprising:

The method of claim 4, wherein, when performing clock synchronization, the physical entities of the transparent transmission clock are clocked by a clock signal; when time synchronization is performed, the physical entity of the transparent transmission clock After clock synchronization is performed by the clock signal, time synchronization is performed by the time signal.

6. A boundary clock, comprising: a normal clock-slave clock physical entity, an intermediate physical entity, and a normal clock-primary clock physical entity, wherein: the normal clock-slave clock physical entity is set to: complete a clock with the master clock or Time synchronization, and, 曰物 ^ ^^-^M^?^, 曰

The intermediate physical entity is configured to: perform clock or time synchronization on a common clock-master clock physical entity of the boundary clock;

The normal clock-master clock physical entity is set to: clock or time synchronize the slave clock.

7. The boundary clock according to claim 6, wherein the normal clock-slave clock physical entity comprises: a standard interface and a processing unit, a clock and time signal input/output processing unit, and a system clock and time synchronization maintenance unit, wherein: The standard interface and the processing unit are configured to: implement a protocol interface, and interface with a network element supporting the corresponding protocol;

8. The boundary clock of claim 7, wherein the standard interface and processing unit comprises: a 1588v2 protocol processing module, a 1588v2 timestamp generator module, and a 1588v2 signal input/output processing module, wherein: the 1588v2 protocol processing module The method is configured to: read a local timestamp from the 1588v2 timestamp generator module, and parse the timestamp from the 1588v2 protocol message, match the timestamp into a pair, and send the timestamp to the 1588v2 signal input/output processing module; The 1588v2 timestamp generator module is configured to: identify and check an output and input Ethernet message, and generate a timestamp;

9. The boundary clock according to claim 8, wherein the clock and time signal input/output processing unit comprises: a clock signal input/output processing module and a time signal input/output processing module, wherein:

10. The boundary clock according to claim 9, wherein the system clock and time synchronization maintenance unit comprises: a system clock and time distribution module, a system clock and time synchronization module, and a clock and time reference source selection module, wherein:

The system clock and time distribution module is configured to: perform system clock and time distribution.

11. The boundary clock of claim 10, wherein:

The common clock-master clock physical entity includes: a 1588v2 protocol processing module, a 1588 time stamp generator module, a clock and time signal input/output processing unit, and a system clock and time synchronization maintenance unit;

The intermediate physical entity includes: a clock and time signal input and output processing unit and a system clock and time synchronization maintenance unit.

12. A transparent transmission clock, comprising: a boundary physical entity and an intermediate physical entity, where: the boundary physical entity is configured to: after receiving the packet sent by the primary clock, collecting the incoming message, multiplying the incoming time Adding (-1) to the synchronization packet correction domain, transparently transmitting the packet to the intermediate physical entity; after receiving the packet sent by the intermediate physical entity, collecting the time of the packet, multiplying the time by (+ 1) Accumulate to the synchronization message correction field;

The intermediate physical entity is configured to: transparently transmit the "3⁄4" text to the physical entity where the output port is located.

The transparent transmission clock according to claim 12, wherein the boundary physical entity comprises: a clock and a time signal input/output processing unit, a system clock and a time synchronization maintenance unit, and a delay correction processing unit, wherein:

The delay correction processing unit is configured to: implement transparent transmission of signals and correction of resident delay.

14. The transparent transmission clock according to claim 13, wherein the delay correction processing unit comprises: an in-time collection module, a 1588 signal transparent transmission module, and an output timing and delay correction processing module, wherein:

The 1588 signal transparent transmission module is configured to: when receiving the 1588 signal sent by the ingress time collection module, transparently transmit the 1588 signal to the next physical entity; when receiving the transparent transmission of the upper physical entity 1588 When the signal is transmitted, the 1588 signal is transparently transmitted to the time set and the delay correction processing module; the output time set and the delay correction processing module are set to: collect the received time of the 1588 signal and perform signal delay Correction processing, outputting the corrected 1588 signal to the slave clock.

15. The transparent transmission clock according to claim 13, wherein the intermediate physical entity comprises: a clock and time signal input/output processing unit, a system clock and a time synchronization maintenance unit, and a delay correction The processing unit, wherein the delay correction processing unit includes: a 1588 signal transparent transmission module, where: the 1588 signal transparent transmission module is configured to: transparently transmit the received 1588 signal transparently transmitted by the upper physical entity to the lower Primary physical entity.