WO2013016997A1

WO2013016997A1 - Method and apparatus for controlling power supplying sequence

Info

Publication number: WO2013016997A1
Application number: PCT/CN2012/077897
Authority: WO
Inventors: 叶位彬
Original assignee: 中兴通讯股份有限公司
Priority date: 2011-08-03
Filing date: 2012-06-29
Publication date: 2013-02-07
Also published as: CN102915097A

Abstract

Disclosed in the invention is a method for controlling power supplying sequence. The method comprises: timing the power supplying time of a plurality of power supplied modules by the predetermined timer; supplying the power supplied modules respectively by a control power when the power supplying time of the power supplied modules arrives. Also disclosed in the invention isan apparatus for controlling power supplying sequence, which can realize the precision control of power supplying time with a simple and low cost way and meets the more complex requirement for power supplying sequence.

Description

Method and device for controlling power-on sequence

The present invention relates to the field of communications, and in particular, to a method and apparatus for controlling a power-on sequence. Background technique

Each board in the communication device has a power-on sequence requirement. There are two main methods for power-on sequence control: First, as shown in Figure 1, different capacitor charging delays are used to control the enable of each board power supply. The signal is used to obtain different power-on times. Second, as shown in Figure 2, the output of the previous single-board power supply is used as the enable signal for the next single-board power supply. Although the first method is simple in circuit, it is not easy to obtain an accurate capacitor charging delay. The resistance value must be carefully adjusted, and it is difficult to achieve a large-scale power-on delay, which has great limitations in practical applications. The second method is more complicated, and the power-on delay of the two boards is very large. If there are multiple boards, the power-on sequence needs to be controlled. The last board power is higher than the first board. There will be a large delay in powering up the power supply. Both of these methods can only be applied to simple power-up sequence control situations, and it is increasingly difficult to cope with the increasingly complex power-up sequence requirements. Summary of the invention

SUMMARY OF THE INVENTION A primary object of the present invention is to provide a method and apparatus for controlling the power-on sequence to achieve accurate power-on time control in a simple, low-cost manner to meet increasingly complex power-up sequencing requirements.

The present invention provides a method of controlling a power-on sequence, the method comprising:

Counting the power-on time of multiple powered modules by a preset timer;

When the power-on time of the power-on module arrives, the control power supply respectively powers up the powered module.

In the above solution, the control power is respectively powered on each module, including: When a plurality of power sources respectively correspond to the power-on modules, when the power-on time of the timer arrives, the power source corresponding to the power-on module that has reached the power-on time is started, and power-on is performed.

In the above solution, the control power is respectively powered on each module, including:

When there is only one power supply, when the power-on time of the timer arrives, the switch corresponding to the power-on module that has reached the power-on time is started, and the power is turned on.

In the above solution, the timer is one or more.

In the above solution, when there are a plurality of timers, each of the powered modules is clocked by the plurality of timers.

The present invention also provides an apparatus for controlling a power-on sequence, the apparatus comprising:

a timing module, configured to time the power-on time of the plurality of powered modules by using a preset timer;

The power-on module is configured to: when the power-on time of the power-on module arrives, the control power source respectively powers on the power-on module.

In the above solution, the power-on module is configured to: when there are multiple power sources respectively corresponding to the powered-on module, when the power-on time of the timer arrives in the timing module, the power-on time is started. Power is supplied to the power supply corresponding to the power-on module.

In the above solution, the power-on module is configured to: when there is only one power source, when the power-on time of the timer arrives in the timing module, the switch corresponding to the power-on module that reaches the power-on time is started, and the switch is performed. Electricity.

In the above solution, the timer is one or more.

In the above solution, when there are a plurality of timers, the timing module respectively counts each power-on module by the timer.

The invention provides a method and a device for controlling a power-on sequence, which implements an accurate power-on time control and a complicated power-on sequence control in a simple and low-cost manner, and meets an increasingly complex single-board or chip power-on sequence requirement. It is also possible to multiplex the existing CPLD or FPGA in the communication device for logic. Control to improve the reliability of the board. Through the invention, the power-on time and the power-on sequence are adjusted, and only the corresponding code needs to be modified, and the hardware circuit is not needed to simplify the design process. DRAWINGS

1 is a schematic diagram of a power-on sequence control circuit of the prior art;

2 is a schematic diagram of another power-on sequence control circuit of the prior art;

3 is a schematic diagram of a component structure in an application scenario of a device for controlling a power-on sequence according to an embodiment of the present invention;

4 is a schematic structural diagram of another application scenario of a device for controlling a power-on sequence according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a composition structure of an apparatus for controlling a power-on sequence according to an embodiment of the present invention; FIG.

6 is a schematic flowchart of a method for controlling a power-on sequence according to an embodiment of the present invention;

FIG. 7 is a schematic structural diagram of a device for controlling a power-on sequence according to the present invention. detailed description

It is understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

Embodiments of the present invention provide a device for controlling a power-on sequence, and the device may include a control module, a low-power power supply for supplying power to the control module, and other peripheral circuits. The main function of the control module is timing, and the power of each power-on module is activated at each set time. The control module mainly includes a timer and a plurality of control output pins, which can be realized by Complex Programmable Logic Device (CPLD), Field Programmable Logic Controller (FPLD) or other controller plus crystal oscillator. The crystal generates a fixed period pulse to the CPLD or FPLD. The counter inside the CPLD or FPLD counts the pulse. The period of the pulse multiplied by the count value is the value of the timer. The low-power supply can be implemented with a low-cost Low DropOut linear regulator (LDO) that converts the device's main supply voltage into a voltage that can be used by the CPLD or FPLD. The function of the peripheral circuit is to activate or deactivate the power supply in conjunction with the control module.

According to the application scenario, this embodiment has two implementation modes:

1) As shown in FIG. 3, the application scenario has multiple power supplies 300 (three power supplies are taken as an example, respectively, power supply 1, power supply 2, and power supply 3), and different power supply 300s correspond to different powered modules, and are powered on. Order requirements. The small power source 100 supplies power to the control module 200. The control module 200 is clocked by an internal timer. When the set time point is reached, the enable pin of the corresponding power source 300 is controlled to be activated by the control pin, and the plurality of power sources 300 are set. The required requirements are to start and supply power to the powered module.

2) As shown in Figure 4, the application scenario has a power supply 300 that requires multiple outputs with different startup times. The first output can be output directly through the power supply 300, the second and subsequent outputs are controlled by a controllable switch 400, or by a plurality of controllable switches 400, respectively, corresponding to each powered module. The controllable switch 400 can be implemented by a power metal oxide semiconductor (MOS) tube, but is not limited to a power MOS transistor. The low-power power supply 100 supplies power to the control module 200. The control module 200 is timed by an internal timer. When the set time point is reached, the corresponding controllable switch 400 is controlled to be turned on by the control pin to achieve multi-output according to the set requirements. The purpose of the startup.

Referring to FIG. 5 and FIG. 6, the three power supplies are still taken as an example. The method for controlling the power-on sequence in the embodiment of the present invention includes the following steps:

Step S101: Count the power-on time of the plurality of powered modules by using a preset timer. The main power of the device is powered on, and the low-power power supply 100 supplies power to the control module 200, that is, supplies power to the CPLD or FPLD and the crystal oscillator 202, and the counter 201 inside the control module 200 starts counting the pulses;

Step S102: When the power-on time of the power-on module arrives, the control power source respectively powers on the powered-on module. The control module 200 determines whether the preset preset time is reached by checking the timer 201, and if so, starts the power supply 301 through the control pin. Control module 200 passes The timer 201 is checked to determine whether the set time two is reached. If it is reached, the power supply 302 is activated through the control pin. Repeat the above process until power supply 303 is activated.

It should be noted that the timers in the embodiments of the present invention are one or more. When there are multiple timers, each power-on module is clocked by multiple timers.

In the embodiment of the present invention, the existing CPLD or FPGA in the communication device can be multiplexed for logical control, and the accurate power-on time control and the complicated power-on sequence control can be realized in a simple and low-cost manner to meet increasingly complex boards. Or the power-on sequence of the chip is required to improve the reliability of the board. Through the invention, the power-on time and the power-on sequence are adjusted, and only the corresponding code needs to be modified, and the hardware circuit is not required to be modified, thereby simplifying the design process.

Referring to FIG. 7, the apparatus 500 for controlling the power-on sequence according to the embodiment of the present invention may include:

The timing module 10 is configured to time the power-on time of the plurality of powered modules by using a preset timer;

The power-on module 20 is configured to: when the power-on time of the powered-on module arrives, control power is powered on the powered-on module.

The system architecture of this embodiment includes a control module, a small power supply for powering the control module, and other peripheral circuits, and the device 500 for controlling the power-on sequence may be the control module 200 described above, or a device built-in or external to the control module. The main function of the device 500 for controlling the power-on sequence is timing, and the power of each power-on module is activated at each set time point. In practical applications, the timing module 10 can be implemented by a CPLD, FPLD or other controller plus a crystal oscillator. The crystal oscillator generates a fixed period pulse to the CPLD or FPLD. The counter inside the CPLD or FPLD counts the pulse, and the period of the pulse is multiplied by the count value. This is the value of the timer.

A low-power supply can be implemented with a low-cost LDO that converts the device's mains voltage into a voltage that can be used by CPLDs or FPLDs. The function of the peripheral circuit is to activate or deactivate the power supply with the device 500 that controls the power-on sequence.

For different application scenarios, the embodiment of the present invention has two implementation manners: 1) In the application scenario shown in Figure 3, there are multiple power supplies 300 (taking three power supplies as an example). Different power supplies 300 correspond to different powered modules, and there is a power-on sequence requirement. The low-power power supply 100 supplies power to the device 500 for controlling the power-on sequence (in this case, the control module 200), and the timing module 10 is clocked by an internal timer. When the set-up time is reached, the power-on module 20 controls the corresponding power supply 300 through the control pin. The enable pin is enabled to start, and the plurality of power sources 300 are activated according to the set requirements and are powered by the power-on module.

2) In the application scenario shown in Figure 4, there is a power supply 300 that needs to generate multiple outputs with different startup times. The first output can be output directly through the power supply 300, the second and subsequent outputs are controlled by a controllable switch 400, or by a plurality of controllable switches 400, corresponding to each powered module. The controllable switch 400 can be implemented by a power MOS transistor, but is not limited to a power MOSFET. The low-power power supply 100 supplies power to the device 500 (in this case, the control module 200) that controls the power-on sequence. The timing module 10 is clocked by an internal timer. When the set-up time is reached, the power-up module 20 controls the corresponding control pin. The opening of the controllable switch 400 achieves the purpose of starting the multi-output according to the set requirements.

The three power supplies 300 shown in FIG. 3 are the power supply one, the power supply two, and the power supply three. In this application scenario, the device 500 for controlling the power-on sequence is the control module 200, and the application scenario shown in FIG. 3 is used in the embodiment of the present invention. The process of controlling the power-on sequence is as follows:

The timing module 10 counts the power-on time of the plurality of powered modules by a preset timer. The main power of the device is powered on, and the low-power power supply 100 supplies power to the timing module 10, that is, supplies power to the CPLD or FPLD and the crystal oscillator, and the counter inside the timing module 10 starts counting the pulses;

When the power-on time of the power-on module arrives, the power-on module 20 controls the power supply to power on the power-on module. The power-on module 20 checks whether the preset time is reached by checking the timer of the timing module 10, and if it is reached, the power supply 1 is started through the control pin. The power-on module 20 determines whether the set time 2 is reached by checking the timer of the timing module 10, and if it is reached, the power supply 2 is started by the control pin. Repeat the above process until power supply three is activated. It should be noted that the timers in the embodiments of the present invention are one or more. When there are a plurality of timers, each of the powered modules is clocked by a plurality of timers.

The above description is only the preferred embodiment of the present invention, and is not intended to limit the scope of the invention, and the equivalent structure or equivalent flow transformation made by the specification and the drawings of the present invention may be directly or indirectly applied to other related The technical field is equally included in the scope of patent protection of the present invention.

Claims

Claim

A method for controlling a power-on sequence, the method comprising: timing a power-on time of a plurality of powered modules by using a preset timer;

2. The method according to claim 1, wherein the controlling power supply respectively powers up each module, including:

When a plurality of power sources respectively correspond to the power-on modules, when the power-on time of the timer arrives, the power source corresponding to the power-on module that has reached the power-on time is started, and the power is turned on.

The method of claim 1, wherein the controlling power supply respectively powers up each module, including:

The method according to any one of claims 1 to 3, wherein the timers are one or more.

The method according to claim 4, wherein when the plurality of timers are plural, each of the powered modules is clocked by the plurality of timers.

A device for controlling a power-on sequence, the device comprising: a timing module, configured to time a power-on time of a plurality of powered modules by using a preset timer;

The device of claim 6, wherein the power-on module is configured to: when there are multiple power sources respectively corresponding to the powered-on module, powering on the timer in the timing module When the time arrives, the power supply corresponding to the power-on module that arrives at the power-on time is started. Power on.

The device of claim 6, wherein the power-on module is configured to: when there is only one power source, when the power-on time of the timer arrives in the timing module, the power-on time is started. The switch corresponding to the power-on module is powered on.

The apparatus according to any one of claims 6 to 8, wherein the timers are one or more.

The device according to claim 9, wherein when the timer is plural, the timing module respectively counts each power-on module by the timer.