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WO2013007191A1 - 一种氮化镓发光二极管的制作方法 - Google Patents

一种氮化镓发光二极管的制作方法 Download PDF

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Publication number
WO2013007191A1
WO2013007191A1 PCT/CN2012/078468 CN2012078468W WO2013007191A1 WO 2013007191 A1 WO2013007191 A1 WO 2013007191A1 CN 2012078468 W CN2012078468 W CN 2012078468W WO 2013007191 A1 WO2013007191 A1 WO 2013007191A1
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layer
gallium nitride
emitting diode
fabricating
light emitting
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PCT/CN2012/078468
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English (en)
French (fr)
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潘群峰
吴志强
林科闯
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厦门市三安光电科技有限公司
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Publication of WO2013007191A1 publication Critical patent/WO2013007191A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/0242—Crystalline insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen

Definitions

  • the present invention relates to a method of fabricating a light emitting diode, and more particularly to a method of fabricating a positive-loading gallium nitride-based light emitting diode including a roughened nitrogen polar surface.
  • gallium nitride (GaN)-based light-emitting diode technology has developed rapidly.
  • the crystal quality of the light emitting material is improved to improve the internal quantum efficiency
  • the chip structure and the packaging process are improved to improve the light extraction efficiency.
  • surface (interface) roughening or texturing technology is one of the simpler and more effective methods, such as patterned substrate, epitaxial surface roughening, transparent conductive layer roughening, photonic crystal, etc. Or the roughening technique of the substrate has been widely adopted and a significant effect is obtained.
  • the crystal orientation selective coarsening of the nitrogen polar surface gallium nitride can obtain a hexagonal cone (pyramid) roughening morphology of a submicron period, and thus has an extremely high light extraction efficiency, but It is commonly used in thin film gallium nitride LED chip structures based on substrate stripping. Conventional gallium nitride LED chips are relatively difficult to obtain because the growth plane is gallium polarity.
  • Document 1 forms a dicing street by laser front dicing, the scribe line provides a lateral etch channel, a high temperature phosphoric acid and sulfuric acid etched the n-GaN layer on the epitaxial sidewall of the etched slab bordering the sapphire substrate, and the lower surface of the n-GaN layer It is nitrogen-polar, forming a hexagonal cone-shaped ribbon that hangs upside down around the edge of the chip's scribe line.
  • the technical solution adopted by the present invention to solve the technical problem thereof is: a manufacturing method of a gallium nitride light emitting diode, characterized in that the manufacturing steps are as follows: 1) A roughenable layer is grown on the sapphire substrate, the material of which is a gallium nitride based compound, and the side (lower surface) in contact with the sapphire substrate is nitrogen polarity; 2) the roughenable layer of the etched partial region To expose the sapphire substrate to form a plurality of lateral etched channels 3) using a wet method to etch the lower surface of the edge of the roughenable layer close to the lateral etched trench into an inverted hexagonal pyramid; 4) continuing to grow the luminescent epitaxial layer on the roughenable layer, and laterally filling the luminescent epitaxial layer Flat lateral etching channel; 5) polarizing the light-emitting epitaxial layer and separating into a plurality of light-emitting core particles, and each of the light-emit
  • the innovation of the present invention is that an epitaxial pyramidal roughened epitaxial layer is placed in the internal structure of the gallium nitride light emitting diode chip by two epitaxial growth.
  • An epitaxially grown roughenable layer is used as a roughening medium.
  • the wet etching can etch the edge portion of the roughenable layer near the laterally etched trench into an inverted hexagonal pyramidal shape by a lateral etching channel located inside the chip.
  • the light-emitting layer is grown by secondary epitaxy and the electrodes are fabricated, so that each of the light-emitting chips has one or several inverted hexagonal taper bands inside. In this way, the area of the roughened area can be further enlarged on the basis of the roughening of the original hexagonal cone, and the light extraction efficiency is improved to a greater extent.
  • the roughenable layer may be undoped gallium nitride or n-type gallium nitride, such that secondary epitaxial growth does not reduce the crystal quality of the light-emitting epitaxial layer; in order to obtain a coarse-scale morphology of sufficient scale
  • the roughened layer must ensure a sufficient thickness, and the ideal thickness must be 1 micron or more; in order not to increase the lateral growth difficulty of the light-emitting epitaxial layer, the lateral etching channel width must be less than or equal to 10 micrometers; wet etching can be roughened
  • the layer can be either high temperature (above 100 ° C) mixed solution of phosphoric acid and sulfuric acid, high temperature alkaline solution, such as potassium hydroxide, sodium hydroxide, ammonia water, etc., or assisted by ultraviolet light to accelerate the etching rate; lateral etching depth It must also be optimized to achieve a better roughened size and to prevent peeling of the epitaxial layer.
  • the width of the edge where
  • FIGS. 1 to 6 are schematic views showing a process of fabricating a gallium nitride light emitting diode according to a preferred embodiment of the present invention.
  • FIG. 7 through 8 are lithographic layouts for forming a lateral etched channel in accordance with a preferred embodiment of the present invention.
  • 10 sapphire substrate
  • 11 buffer layer
  • 12 roughenable layer
  • 13 n-GaN layer
  • 14 multiple quantum well (MQW)
  • 15 p-GaN layer
  • 20 ITO layer
  • 21 p electrode
  • 22 n electrode
  • 100 lateral etching channel
  • 200 SiO2 mask
  • 300 cutting track.
  • a manufacturing method of a gallium nitride light emitting diode the manufacturing steps thereof include:
  • epitaxial growth is performed on the sapphire substrate 10 by metal organic chemical vapor deposition (MOCVD): a buffer layer 11 and a roughenable layer 12.
  • MOCVD metal organic chemical vapor deposition
  • the material of the buffer layer 11 is undoped GaN
  • the material of the roughizable layer 12 is a gallium nitride based compound.
  • the roughenable layer 12 is an n-GaN layer having a thickness of about 2 ⁇ m.
  • SiO2 mask region 200 and lateral etch channel region 100 are defined over roughenable layer 12 using photolithography and etching.
  • the lithographic pattern can be designed using FIG. 7 or FIG. 8.
  • FIG. 7 shows that the center position of each illuminating core includes a single-stage lateral etched channel, the channel width is set to 5 micrometers, and the length can be set as a relative chip. The side length is retracted; as shown in Fig. 8, the center position of each of the illuminating core particles includes two segments of the etched lateral etched channel. Similarly, the channel width can be set to 5 micrometers, and the length can be set to the opposite side of the chip. Long contraction.
  • the roughizable layer 12 and the buffer layer 11 of the laterally etched channel region 100 can be etched using dry plasma until the sapphire substrate 10 is completely exposed.
  • the epitaxial layer of the lateral etching channel 100 is wet-etched by using sulfuric acid and phosphoric acid (ratio 3:2) at 250 ° C, and the etching time is controlled in 2 to 4 minutes, so that the circumferential etching groove can be obtained.
  • the lateral etch depth of the track 100 is in the shape of an inverted hexagonal cone of about 5 to 15 microns.
  • the epitaxial growth of the light-emitting layer is continued over the roughenable layer 12, which in turn includes an n-GaN layer 13, a multiple quantum well (MQW) 14 and a p-GaN layer 15, and the light-emitting epitaxial layer is laterally filled with a width.
  • the channel 100 is laterally etched to a 5 micron.
  • a light-emitting chip is formed, including etching an epitaxial layer of a partial region to expose the n-GaN layer 13, forming an ITO transparent conductive layer 20 on the p-GaN layer 15, and forming a p-electrode on the ITO layer 20. 21; an n-electrode 22 is formed on the n-GaN layer 13.
  • a SiO2 mask layer is deposited on the light-emitting chip, and then a front side scribe is performed by laser to separate the light-emitting core particles.
  • the laser is drawn around the light-emitting core particles to form a dicing street 300, and the dicing street 300 exposes the sapphire lining.
  • the epitaxial layer at the edge of the dicing street 300 is wet-etched by using sulfuric acid and phosphoric acid (ratio 3:2) at 250 ° C, and the etching time is controlled to be 2 to 4 minutes, thereby obtaining a lateral etching depth of about 5 to 15 ⁇ m around the dicing street 300.
  • the inverted hexagonal cone looks. After the wet etching, the mask layer is removed and the luminescent core particles are completely separated by the cleavage.
  • the wet etching solution can also use a high-temperature alkaline solution such as potassium hydroxide, sodium hydroxide, ammonia water, etc., if assisted by ultraviolet light to accelerate the etching rate.
  • a light-emitting chip having a roughened structure of a dicing street and an inverted hexagonal pyramid inside the chip as shown in FIG. 6 can be obtained, and the area of the roughened area is increased compared to the light-emitting chip which is only roughened by the scribe line.
  • the light extraction efficiency of the light emitting chip is further improved.

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Abstract

本发明公开了一种氮化镓发光二极管的制作方法，其包括步骤：在蓝宝石衬底上生长一可粗化层，其材料为氮化镓基化合物，并且其与蓝宝石衬底接触的一侧呈氮极性；蚀刻部分区域的可粗化层至露出蓝宝石衬底，以形成多个侧向蚀刻沟道；采用湿法方式蚀刻靠近侧向蚀刻沟道的可粗化层边缘的下表面从而获得粗化的表面；在可粗化层上继续生长发光外延层，并且发光外延层横向填平侧向蚀刻沟道；电极化发光外延层并分离成多个发光芯粒，并且每个发光芯粒内部至少包含一段侧向蚀刻沟道。

Description

一种氮化镓发光二极管的制作方法 技术领域
本发明涉及一种发光二极管的制作方法，更为具体地，涉及一种包含粗化氮极性面的正装氮化镓基发光二极管的制作方法。
背景技术
近年来，随着半导体照明逐渐普及，氮化镓（GaN）基发光二极管技术发展迅速。为了提高氮化镓发光二极管的发光效率，一方面要改善发光材料的晶体质量以提高内量子效率，另一方面则要通过芯片结构以及封装工艺的改进以提升取光效率。为了提升芯片的取光效率，表面（界面）粗化或者纹理化技术是较为简单有效的方式之一，诸如图形化衬底、外延表面粗化、透明导电层粗化、光子晶体等针对出光面或者衬底的粗化技术已经被广泛采用并获得明显效果。
在各种粗化技术中，针对氮极性面氮化镓的晶向选择性粗化可以获得亚微米级周期的六角锥（金字塔）粗化形貌，因而具有极高的取光效率，但其通常用在基于衬底剥离的薄膜氮化镓LED芯片结构上，常规的氮化镓LED芯片因生长面为镓极性，所以比较难以获得。
文献1（L-C Chang, C-H Kuo, C-W Kuo, Output power enhancements of nitride-based light-emitting diodes with inverted pyramid sidewalls structure, Solid-State Electronics 56 (2011) 8–12）报道了采用高温硫酸和磷酸腐蚀切割道侧壁边缘的n-GaN层形成倒六角锥（金字塔）状的粗化界面，通过优化条件可以获得27%的亮度提升。文献1通过激光正面划片形成切割道，切割道提供了横向蚀刻通道，高温磷酸和硫酸蚀刻切割道外延侧壁上与蓝宝石衬底交界的n-GaN层，且此n-GaN层的下表面呈氮极性，从而形成一环绕芯片切割道边缘的倒挂悬空的六角锥形貌带。
 发明内容
本发明的目的即在于改进现有技术的上述局限，以进一步提高正装氮化镓基发光二极管芯片的取光效率。
本发明解决其技术问题所采用的技术方案是：一种氮化镓发光二极管的制作方法，其特征在于：制作步骤如下：1） 在蓝宝石衬底上生长一可粗化层，其材料为氮化镓基化合物，并且其与蓝宝石衬底接触的一侧（下表面）呈氮极性；2）蚀刻部分区域的可粗化层至露出蓝宝石衬底，以形成多个侧向蚀刻沟道 ；3）采用湿法方式将靠近侧向蚀刻沟道的可粗化层边缘的下表面蚀刻成倒六角锥状； 4） 在可粗化层上继续生长发光外延层，并且发光外延层横向填平侧向蚀刻沟道； 5）电极化发光外延层并分离成多个发光芯粒，并且每个发光芯粒内部至少包含一段侧向蚀刻沟道。
本发明的创新之处在于通过两次外延生长，在氮化镓发光二极管芯片内部结构中置入倒六角锥粗化外延层带。一次外延生长可粗化层作为粗化介质，通过位于芯片内部的侧向蚀刻沟道，湿法蚀刻可以将靠近侧向蚀刻沟道的可粗化层边缘部分蚀刻成倒六角锥状形貌带，然后再通过二次外延生长发光层以及制作电极，使得每个发光芯片内部拥有一个或者数个倒六角锥形貌带。这样可在原有切割道倒六角锥粗化的基础上更进一步的扩大粗化区域面积，更大程度上提高取光效率。
在本发明中进一步地，可粗化层可为未掺杂氮化镓或者n型氮化镓，这样二次外延生长不会降低发光外延层的晶体质量；为了获得足够尺度的粗化形貌，可粗化层必须保证足够的厚度，较为理想的厚度须在1微米以上；为了不增加发光外延层横向生长难度，侧向蚀刻沟道宽度须小于或者等于10微米；湿法蚀刻可粗化层既可采用高温（100℃以上）的磷酸和硫酸混合溶液，也可以采用高温碱性溶液，如氢氧化钾、氢氧化钠、氨水等，或者借助紫外光辅助以加快蚀刻速率；横向蚀刻深度也必须优化以获得较佳之粗化尺寸并防止外延层剥落，可粗化层被蚀刻的边缘宽度建议不超过20微米。
 附图说明
附图用来提供对本发明的进一步理解，并且构成说明书的一部分，与本发明的实施例一起用于解释本发明，并不构成对本发明的限制。此外，附图数据是描述概要，不是按比例绘制。
图1～图6是本发明优选实施例的氮化镓发光二极管的制作过程的示意图。
图7～图8是本发明优选实施例的形成侧向蚀刻沟道的光刻版图。
图中部件符号说明：
10：蓝宝石衬底 ；11：缓冲层； 12：可粗化层；13：n-GaN层； 14：多量子阱（MQW）；15：p-GaN层； 20：ITO层；21：p电极 ；22：n电极 ；100：侧向蚀刻沟道； 200：SiO2掩膜；300：切割道。
 具体实施方式
下面结合附图和优选实施例对本发明做进一步说明。需要说明的是，只要不构成冲突，本发明中的各个实施例以及各实施例中的各个特征可以相互结合，所形成的技术方案均在本发明的保护范围之内。
一种氮化镓发光二极管的制作方法，其制作步骤包括：
如图1所示，在蓝宝石衬底10上采用金属有机化学气相沉积（MOCVD）依次外延生长：缓冲层11和可粗化层12。缓冲层11材料为未掺杂GaN，可粗化层12的材料为氮化镓基化合物，为获得较好的外延晶格质量，可为未掺杂氮化镓或者n型氮化镓。在本实施例中可粗化层12为厚度2微米左右的n-GaN层。
如图2所示，采用光刻和蚀刻在可粗化层12之上定义出SiO2掩膜区200和侧向蚀刻沟道区域100。光刻版图可以采用图7或者图8进行设计，图7所示为每一发光芯粒中心位置包含单一段侧向蚀刻沟道，沟道宽度设定为5微米，长度可以设定为相对芯片边长内缩；图8所示则为每一发光芯粒中心位置包含两段成十字交叉的侧向蚀刻沟道，同样地，沟道宽度可以设为5微米，长度可以设为相对芯片边长内缩。定义完掩膜区200和侧向蚀刻沟道区100后，即可采用干法等离子体蚀刻侧向蚀刻沟道区100的可粗化层12和缓冲层11直至完全露出蓝宝石衬底10。
如图3所示，采用250℃的硫酸和磷酸（比例3:2）湿法蚀刻侧向蚀刻沟道100两端的外延层，蚀刻时间控制在2~4分钟，这样可以得到环绕侧向蚀刻沟道100的横向蚀刻深度在5~15微米左右的倒六角锥形貌带。
如图4所示，在可粗化层12之上继续外延生长发光层，依次包括n-GaN层13、多量子阱（MQW）14和p-GaN层15，并且发光外延层横向填平宽度为5微米的侧向蚀刻沟道100。
如图5所示，制作发光芯片，包括蚀刻部分区域的发光外延层至露出n-GaN层13，在p-GaN层15之上制作ITO透明导电层20，在ITO层20之上制作p电极21；在n-GaN层13上制作n电极22。
如图6所示，在发光芯片之上沉积SiO2掩膜层，随后采用激光进行正面划片以分离发光芯粒，激光正划在发光芯粒四周形成切割道300，切割道300暴露出蓝宝石衬底10与外延层的界面。采用250℃的硫酸和磷酸（比例3:2）湿法蚀刻切割道300边缘的外延层，蚀刻时间控制在2~4分钟，从而得到将环绕切割道300的横向蚀刻深度在5~15微米左右的倒六角锥形貌带。湿法蚀刻后去除掩膜层并采用裂片完全分离发光芯粒。湿法蚀刻液也可以采用高温碱性溶液，如氢氧化钾、氢氧化钠、氨水等，若借助紫外光辅助以加快蚀刻速率。
完成上述步骤后，即可获得如图6所示的具有切割道和芯片内部倒六角锥粗化结构的发光芯片，相比于仅切割道粗化的发光芯片，由于增加了粗化区域面积，发光芯片的取光效率得到更进一步的提升。
很明显地，本发明的说明不应理解为仅仅限制在上述实施例，而是包括利用本发明构思的全部实施方式。

Claims (12)

  1. 一种氮化镓发光二极管的制作方法，包括如下步骤：
    在蓝宝石衬底上生长一可粗化层，其材料为氮化镓基化合物，并且其与蓝宝石衬底接触的一侧呈氮极性；
    蚀刻部分区域的可粗化层至露出蓝宝石衬底，以形成多个侧向蚀刻沟道；
    采用湿法方式蚀刻靠近侧向蚀刻沟道的可粗化层边缘的下表面从而获得粗化的表面；
    在可粗化层上继续生长发光外延层，并且发光外延层横向填平侧向蚀刻沟道；
    电极化发光外延层并分离成多个发光芯粒，并且每个发光芯粒内部至少包含一段侧向蚀刻沟道。
  2. 根据权利要求 1 所述的氮化镓发光二极管的制作方法， 其特征在于：所述的可粗化层为未掺杂氮化镓或者 n 型氮化镓。
  3. 根据权利要求 1 所述的氮化镓发光二极管的制作方法，其特征在于：所述的可粗化层厚度大于或者等于 1 微米。
  4. 根据权利要求 1 所述的氮化镓发光二极管的制作方法，其特征在于：所述侧向蚀刻沟道位于芯片内部，通过湿法蚀刻靠近侧向蚀刻沟道的可粗化层边缘部分，从而获得粗化的表面。
  5. 根据权利要求 1 所述的氮化镓发光二极管的制作方法，其特征在于：采用湿法方式将靠近侧向蚀刻沟道的可粗化层边缘的下表面蚀刻成倒六角锥状。
  6. 据权利要求1所述的氮化镓发光二极管的制作方法，其特征在于：所述的侧向蚀刻沟道宽度小于或者等于10微米。
  7. 根据权利要求1所述的氮化镓发光二极管的制作方法，其特征在于：所述可粗化层被蚀刻的边缘宽度小于或者等于20微米。
  8. 根据权利要求1所述的氮化镓发光二极管的制作方法，其特征在于：所述湿法蚀刻可粗化层采用磷酸和硫酸混合溶液。
  9. 根据权利要求6所述的氮化镓发光二极管的制作方法，其特征在于：所述磷酸和硫酸混合溶液的温度大于或者等于100℃。
  10. 根据权利要求1所述的氮化镓发光二极管的制作方法，其特征在于：所述湿法蚀刻可粗化层采用氢氧化钾、氢氧化钠、氨水等碱性溶液。
  11. 根据权利要求8所述的氮化镓发光二极管的制作方法，其特征在于：通过加温或者紫外光辅助照射加快湿法蚀刻的速率。
  12. 根据权利要求1所述的氮化镓发光二极管的制作方法，其特征在于：还包括采用湿法蚀刻方式将发光芯粒切割道边缘的可粗化层下表面蚀刻成倒六角锥状。
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CN102306693A (zh) * 2011-09-30 2012-01-04 厦门市三安光电科技有限公司 图形化氮化镓基发光外延片、发光芯片及其制作方法
CN105826442A (zh) * 2016-03-21 2016-08-03 佛山市国星半导体技术有限公司 氮化镓材料层表面粗化的方法
CN110034216A (zh) * 2018-01-12 2019-07-19 中国科学院苏州纳米技术与纳米仿生研究所 Iii-v族氮化物深紫外发光二极管结构及其制作方法
CN109308992A (zh) * 2018-09-21 2019-02-05 苏州汉骅半导体有限公司 回收碳化硅衬底的方法
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