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WO2013001743A1 - Semiconductor reception device - Google Patents

Semiconductor reception device Download PDF

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Publication number
WO2013001743A1
WO2013001743A1 PCT/JP2012/003966 JP2012003966W WO2013001743A1 WO 2013001743 A1 WO2013001743 A1 WO 2013001743A1 JP 2012003966 W JP2012003966 W JP 2012003966W WO 2013001743 A1 WO2013001743 A1 WO 2013001743A1
Authority
WO
WIPO (PCT)
Prior art keywords
transmission line
terminal
transistors
mixer
line
Prior art date
Application number
PCT/JP2012/003966
Other languages
French (fr)
Japanese (ja)
Inventor
信二 宇治田
健志 福田
酒井　啓之
Original Assignee
パナソニック株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by パナソニック株式会社 filed Critical パナソニック株式会社
Publication of WO2013001743A1 publication Critical patent/WO2013001743A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P5/00—Coupling devices of the waveguide type
    • H01P5/08—Coupling devices of the waveguide type for linking dissimilar lines or devices
    • H01P5/10—Coupling devices of the waveguide type for linking dissimilar lines or devices for coupling balanced lines or devices with unbalanced lines or devices
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
    • G01S7/03—Details of HF subsystems specially adapted therefor, e.g. common to transmitter and receiver
    • G01S7/032—Constructional details for solid-state radar subsystems
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14—Balanced arrangements
    • H03D7/1425—Balanced arrangements with transistors
    • H03D7/1441—Balanced arrangements with transistors using field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14—Balanced arrangements
    • H03D7/1425—Balanced arrangements with transistors
    • H03D7/1458—Double balanced arrangements, i.e. where both input signals are differential
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/16—Multiple-frequency-changing
    • H03D7/165—Multiple-frequency-changing at least two frequency changers being located in different paths, e.g. in two paths with carriers in quadrature
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D2200/00—Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
    • H03D2200/0001—Circuit elements of demodulators
    • H03D2200/0023—Balun circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D2200/00—Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
    • H03D2200/0041—Functional aspects of demodulators
    • H03D2200/0082—Quadrature arrangements

Definitions

  • the present invention relates to a semiconductor receiving device mounted on an MMIC (Monolithic Integrated Circuit) chip in a high-frequency semiconductor device such as various communication devices or radars.
  • MMIC Compolithic Integrated Circuit
  • CMOS Complementary Metal Oxide Semiconductor
  • an ultra-wide band called UWB Ultra Wide Band
  • quasi-millimeter waves and millimeter waves are also expected for large-capacity communication and ultrahigh-speed communication applications.
  • quasi-millimeter waves and millimeter waves are greatly expected to be used for sensing because they are less attenuated by obstacles such as rain and clouds than visible light and infrared light and have higher resolution than microwaves. Yes.
  • a modulator and a quadrature demodulator are indispensable for a semiconductor receiver for these applications.
  • a radar apparatus using a spread spectrum method will be described as an example.
  • a transmission radio wave is modulated using a pseudo noise code (PN) used for spreading.
  • PN pseudo noise code
  • the receiver despreads the reflected wave reflected from the object using the same code as the PN code used for modulating the transmission radio wave. For this reason, radio waves modulated with different codes and radio waves radiated from other types of radar devices that do not use code modulation are suppressed in the receiver.
  • the transmission radio wave is frequency spread by the PN code, the power per unit frequency can be reduced. Thereby, the influence which transmission radio waves have on other wireless systems can be reduced. Furthermore, the relationship between the distance resolution and the maximum detection distance can be freely set by adjusting the chip rate and code cycle of the PN code. In addition, since the radio wave can be transmitted continuously, the peak power does not increase. Further, by using the quadrature demodulator, a stable radar reception spectrum can be obtained without being influenced by the phase of the reception signal.
  • a spread spectrum radar apparatus always requires a semiconductor receiver including a spread modulator and a quadrature demodulator.
  • demodulation is first performed by a modulator and then frequency down-converted by an orthogonal demodulator in a path through which a received signal propagates. If the received signal is first frequency down-converted by the quadrature demodulator, an element or a circuit through which an ultra-wideband baseband signal propagates is required, which makes it difficult to design.
  • FIG. 13 is a diagram illustrating a configuration of the quadrature demodulator 112 described in Patent Document 1.
  • FIG. 13 is a diagram illustrating a configuration of the quadrature demodulator 112 described in Patent Document 1.
  • Transistors Tr107, Tr108, Tr109, Tr110, Tr111 and Tr112 are bipolar transistors, and these transistors form a Gilbert cell mixer. Further, the transistors Tr113, Tr114, Tr115, Tr116, Tr117, and Tr118 are bipolar transistors, and these transistors form a Gilbert cell mixer. These two Gilbert cell mixers constitute a quadrature demodulator 112.
  • the Gilbert cell mixer constituting the quadrature demodulator includes a constant current source.
  • a transistor having a current mirror configuration is used for the constant current source.
  • silicon ICs with good high frequency characteristics are low breakdown voltage devices that can only apply a small voltage. Furthermore, low power consumption is required for mobile applications and the like from an application viewpoint, and it is difficult to apply a large voltage to the device.
  • the transistor amplification stage and the modulation stage are vertically stacked. Furthermore, the conventional circuit is three-stage stacked when including a transistor constituting a constant current source. Therefore, considering the voltage drop of the load resistance, the voltage applied between the drain and source (assuming a CMOS device) for one stage of the transistor is very small. This makes it difficult to operate the transistor with a high mutual conductance (gm) and good high frequency characteristics.
  • an object of the present invention is to provide a semiconductor receiver that improves high-frequency characteristics.
  • a semiconductor receiver includes a first mixer that converts an input signal into first and second modulated signals having a phase difference of 180 ° from each other, and Second and third mixers for converting the first and second modulation signals into first to fourth output signals having phase differences of 0 °, 90 °, 180 ° and 270 °;
  • Each of the first, second, and third mixers includes a first to third terminals, a modulation stage having a Gilbert cell mixer configuration that includes first to fourth transistors, A constant current source including fifth and sixth transistors; an unbalanced transmission line having one line end connected to the first terminal; first and second balanced transmission lines; And an unbalanced balanced converter comprising two grounded capacitors, the first balanced transmission.
  • One line end of the line is connected to the first ground capacitor and the drain terminal of the fifth transistor, and the other line end is connected to the source terminal of the first and second transistors.
  • One line end of the second balanced transmission line is connected to the second grounded capacitor and the drain terminal of the sixth transistor, and the other line end is connected to the third and fourth transistors.
  • a drain terminal of the first and third transistors is connected to the second terminal, and a drain terminal of the second and fourth transistors is connected to the third terminal.
  • the input signal is input to the first terminal of the first mixer, and the first and second modulation signals are input to the second and third terminals of the first mixer.
  • the first terminal of the second mixer is connected to the second terminal of the first mixer via the first transmission line, and the second terminal of the second mixer is connected to the second terminal of the second mixer.
  • the first and third output signals are output to the second and third terminals, and the first terminal of the third mixer is connected to the first mixer via the second transmission line.
  • the second and fourth output signals are output to the second and third terminals of the third mixer.
  • the semiconductor receiver according to an aspect of the present invention can reduce the number of transistors stacked in the first to third mixers. Thereby, the high frequency characteristic of each mixer can be improved. Therefore, the semiconductor receiving device can improve high frequency characteristics. Further, by distributing the first and second modulated signals by the unbalanced and balanced converter, it is possible to realize the distribution of the differential signal to the second and third mixers.
  • the other line end of the unbalanced transmission line included in the second mixer and the other line end of the unbalanced transmission line included in the third mixer are connected, and the other of the two other The line end may be grounded via a power source at a point equidistant from the two other line ends.
  • each of the second and third mixers the gate terminals of the first and fourth transistors are connected to each other, and the gate terminals of the second and third transistors are connected to each other,
  • Each of the second and third mixers is further connected to a first resistance element connected to the drain terminals of the first and third transistors and to the drain terminals of the second and fourth transistors. And a second resistance element that is provided.
  • the unbalanced balanced converter further includes a capacitor connected between the other line end of the first balanced transmission line and the other line end of the second balanced transmission line. You may prepare.
  • This configuration can reduce the size of the unbalanced / balanced converter.
  • first balanced transmission line, the second balanced transmission line, and the unbalanced transmission line may be arranged on the same plane.
  • first balanced transmission line and the second balanced transmission line are arranged on the same plane, and the unbalanced transmission line is in a different layer from the first and second balanced transmission lines. It may be arranged.
  • the present invention can be realized not only as such a semiconductor receiver but also as a semiconductor integrated circuit (LSI) that realizes part or all of the functions of such a semiconductor receiver.
  • LSI semiconductor integrated circuit
  • the present invention can provide a semiconductor receiver capable of improving high-frequency characteristics.
  • FIG. 1 is a circuit diagram of a semiconductor receiver according to a comparative example of the present invention.
  • FIG. 2 is a block diagram of a semiconductor receiver according to a comparative example of the present invention.
  • FIG. 3 is a block diagram of the semiconductor receiver according to the embodiment of the present invention.
  • FIG. 4 is a circuit diagram of the semiconductor receiver according to the embodiment of the present invention.
  • FIG. 5 is a circuit diagram of the modulator according to the embodiment of the present invention.
  • FIG. 6 is a circuit diagram of the quadrature demodulator according to the embodiment of the present invention.
  • FIG. 7 is a diagram showing the configuration of the merchant balun according to the embodiment of the present invention.
  • FIG. 8 is a diagram showing a configuration of a modified example of the merchant balun according to the embodiment of the present invention.
  • FIG. 9A is a perspective view showing a structure of a merchant balun according to the embodiment of the present invention.
  • FIG. 9B is a perspective view showing the structure of the merchant balun according to the embodiment of the present invention.
  • FIG. 10A is a perspective view showing a structure of a modified example of the merchant balun according to the embodiment of the present invention.
  • FIG. 10B is a perspective view showing a structure of a modified example of the merchant balun according to the embodiment of the present invention.
  • FIG. 11A is a perspective view showing a structure of a modified example of the merchant balun according to the embodiment of the present invention.
  • FIG. 11B is a perspective view showing a structure of a modified example of the merchant balun according to the embodiment of the present invention.
  • FIG. 12 is a graph showing the local signal power dependence of the conversion gain of the semiconductor receiver according to the embodiment of the present invention.
  • FIG. 13 is a circuit diagram of a conventional quadrature demodulator.
  • FIG. 1 is a diagram showing a configuration of a semiconductor receiver according to a comparative example of the present invention.
  • This semiconductor receiver includes a quadrature demodulator 112 shown in FIG. Further, the semiconductor receiving device includes a modulator 105. Note that a description overlapping the description of FIG. 13 described above is omitted.
  • Transistors Tr101, Tr102, Tr103, Tr104, Tr105, and Tr106 are bipolar transistors (may be field effect transistors), and these transistors form a Gilbert cell mixer and constitute the modulator 105.
  • the modulator 105 has differential input terminals 101 and 102 and differential output terminals 103 and 104.
  • the quadrature demodulator 112 has differential input terminals 106 and 107 and output terminals 108, 109, 110 and 111.
  • the output terminal 108 is a 0 ° output terminal
  • the output terminal 109 is a 180 ° output terminal
  • the output terminal 110 is a 90 ° output terminal
  • the output terminal 111 is a 270 ° output terminal.
  • the signals output from these output terminals are subjected to signal processing by a digital IC.
  • the output terminal 103 of the modulator 105 and the input terminal 106 of the quadrature demodulator 112 are connected via an impedance matching circuit 113.
  • the output terminal 104 of the modulator 105 and the input terminal 107 of the quadrature demodulator 112 are connected via an impedance matching circuit 114.
  • the impedance matching circuits 113 and 114 are preferably composed only of transmission lines, but a stub (open or short) or a spiral inductor that can be handled as a lumped element may be used as necessary.
  • the Gilbert cell mixer constituting the modulator 105 and the quadrature demodulator 112 includes a constant current source.
  • a transistor having a current mirror configuration is used for the constant current source.
  • circuit configuration of FIG. 1 can be represented by a simple block as shown in FIG.
  • the transistor amplification stage and the modulation stage are vertically stacked.
  • the Gilbert cell mixer configuration is three-stage stacked when including the transistors constituting the constant current source. Therefore, in consideration of the voltage drop of the load resistance, the voltage applied between the collector and the emitter for one stage of the transistor (between the drain and the source in the case of a field effect transistor) becomes very small. This makes it difficult to operate the transistor with a high mutual conductance (gm) and good high frequency characteristics.
  • connection wiring from the modulator 105 of FIG. 1 to the two quadrature demodulator 112 becomes a problem.
  • the impedance matching circuits 113 and 114 can match the output impedance of the modulator 105 and the input impedance of the quadrature demodulator 112.
  • the differential of 180 ° phase difference between Tr107 and Tr108 due to the wiring distributed from the input terminal 106 of the quadrature demodulator 112 to Tr107 and Tr114 and the wiring distributed from the input terminal 107 to Tr108 and Tr113.
  • a differential signal having a phase difference of 180 ° can be input to Tr113 and Tr114.
  • the phase is likely to be shifted depending on the length of the transmission line such as the wiring. It is done.
  • the amplification stage of the Gilbert cell mixer included in the modulator and the quadrature demodulator is replaced with a merchant balun (unbalanced balanced converter) configured by a coupled line. Further, the output terminal of the modulator is connected to the input end of the unbalanced transmission line of the merchant balun.
  • the semiconductor receiving device can improve high-frequency characteristics and realize differential distribution to the quadrature demodulator.
  • FIG. 3 is a block diagram of the semiconductor receiver 50 according to the embodiment of the present invention.
  • FIG. 4 is a circuit diagram of the semiconductor receiver 50.
  • the semiconductor receiver 50 includes an input terminal 1, a modulator 6, a quadrature demodulator 15, output terminals 11, 12, 13 and 14, and matched transmission lines 16 and 17.
  • the semiconductor receiver 50 has a role of processing an input signal received by an antenna and input through a low noise amplifier (LNA: Low Noise Amp) or the like.
  • LNA Low Noise Amp
  • the antenna has a differential wiring configuration, there are problems such as an increase in size and a loss due to a complicated configuration. Therefore, it is preferable that the antenna has a single-ended configuration.
  • FIG. 5 is a circuit diagram of the modulator 6.
  • the modulator 6 includes an input terminal 1, a merchant balun 2 (hereinafter also referred to as balun 2), a modulation stage 3 having a Gilbert cell mixer configuration (hereinafter also referred to as modulation stage 3), output terminals 4 and 5, A current source 31.
  • the modulator 6 converts the input signal input to the input terminal 1 into first and second modulation signals having a phase difference of 180 ° from each other, and outputs the converted first and second modulation signals to the output terminal 4. And 5 are output.
  • the modulator 6 corresponds to the first mixer of the present invention, and the input terminal 1 and the output terminals 4 and 5 correspond to the first to third terminals of the present invention.
  • the input signal propagated through the antenna and the LNA is input to the input terminal 1.
  • the balun 2 is composed of a coupled line and has an unbalanced transmission line.
  • the balun 2 converts a single signal input to the input terminal 1 into a differential signal having a phase difference of 180 °.
  • the converted differential signal is input to the modulation stage 3.
  • the modulation stage 3 includes field effect transistors Tr1, Tr2, Tr3 and Tr4.
  • the modulation stage 3 modulates the differential signal converted by the balun 2 and propagates the modulated differential signals (first and second modulation signals) to the output terminals 4 and 5, respectively.
  • the field effect transistors Tr1 to Tr4 correspond to the first to fourth transistors of the present invention.
  • the drain terminals of the transistors Tr1 and Tr3 are connected to the output terminal 4.
  • the drain terminals of the transistors Tr2 and Tr4 are connected to the output terminal 5.
  • the current source 31 supplies a constant current to the field effect transistor constituting the modulation stage 3 through the balanced transmission line of the balun 2.
  • the current source 31 includes field effect transistors Tr5 and Tr6.
  • the transistors Tr5 and Tr6 constitute a current mirror circuit.
  • the field effect transistors Tr5 and Tr6 correspond to the fifth and sixth transistors of the present invention.
  • FIG. 6 is a circuit diagram of the quadrature demodulator 15.
  • the orthogonal demodulator 15 includes input terminals 7 and 8, output terminals 11 to 14, and down-conversion mixers 33a and 33b (hereinafter also referred to as mixers 33a and 33b).
  • the signal output from the modulator 6 is input to the input terminals 7 and 8.
  • the quadrature demodulator 15 converts the first and second modulated signals generated by the modulator 6 into first to fourth output signals having phase differences of 0 °, 90 °, 180 °, and 270 °.
  • the converted first to fourth output signals are output to the output terminals 11 to 14, respectively.
  • the mixer 33a includes an input terminal 7, output terminals 11 and 12, a merchant balun 9a (hereinafter also referred to as balun 9a), a modulation stage 10a (hereinafter also referred to as modulation stage 10a) having a Gilbert cell mixer configuration, a current source 32a.
  • the mixer 33b includes an input terminal 8, output terminals 13 and 14, a merchant balun 9b (hereinafter also referred to as a balun 9b), a modulation stage 10b having a Gilbert cell mixer configuration (hereinafter also referred to as a modulation stage 10b), a current source 32b.
  • the mixers 33a and 33b correspond to the second and third mixers of the present invention.
  • the input terminal 7 and the output terminals 11 and 12 correspond to the first to third terminals of the present invention.
  • the input terminal 8 and the output terminals 13 and 14 correspond to the first to third terminals of the present invention.
  • the balun 9a is composed of a coupled line and has an unbalanced transmission line. This balun 9a corresponds to the unbalanced balanced converter of the present invention.
  • the balun 9a converts the single signal input to the input terminal 7 (8) into a differential signal.
  • the converted differential signal is input to the modulation stage 10a (10b).
  • the modulation stage 10a includes field effect transistors Tr7, Tr8, Tr9 and Tr10, load resistors R1 and R2, and output terminals 11 and 12 (13 and 14).
  • the field effect transistors Tr7, Tr8, Tr9 and Tr10 correspond to the first to fourth transistors of the present invention.
  • the load resistors R1 and R2 correspond to the first and second resistance elements of the present invention.
  • the load resistor R1 is inserted between the drain terminals of the transistors Tr7 and Tr9 and the power supply.
  • the output terminal 11 (13) is connected to a node between the connection point between the drain terminal of the transistor Tr7 and the drain terminal of the transistor Tr9 and the load resistor R1.
  • the load resistor R2 is inserted between the drain terminals of the transistors Tr8 and Tr10 and the power supply.
  • the output terminal 12 (14) is connected to a node between the connection point between the drain terminal of the transistor Tr8 and the drain terminal of the transistor Tr10 and the load resistor R2.
  • the current source 32a (32b) supplies a constant current to the field effect transistors constituting the modulation stage 10a (10b) via the balanced transmission line of the balun 9a (9b).
  • the current source 32a includes field effect transistors Tr11 and Tr12.
  • the transistors Tr11 and Tr12 constitute a current mirror circuit.
  • the field effect transistors Tr11 and Tr12 correspond to the fifth and sixth transistors of the present invention.
  • the local differential signal input to the modulation stage 10a of the mixer 33a and the local differential signal input to the modulation stage 10b of the mixer 33b are set to have a 90 ° phase difference.
  • the quadrature demodulator 15 converts the differential signal from the local oscillator into four signals having a phase difference of 0 °, 90 °, 180 °, and 270 ° using a 90 ° phase shifter.
  • the differential signal of 180 ° is input to the local signal input terminal of the modulation stage 10a
  • the differential signal of 90 ° and 270 ° is input to the local signal input terminal of the modulation stage 10b.
  • the 90 ° phase shifter a polyphase filter using a resistor and a capacitor, or a branch line phase shifter constituted by a ⁇ / 4 transmission line is generally used.
  • a branch line phase shifter in an ultrahigh frequency region such as a quasi-millimeter wave and a millimeter wave band, it is preferable to use a branch line phase shifter because loss due to resistance or the like in the polyphase filter is large.
  • the phase of the signal output from the output terminal 11 is 0 °
  • the signal phase of the output terminal 12 is 180 °
  • the signal phase of the output terminal 13 is 90 °
  • the signal phase of the output terminal 14 is 270 °.
  • a constant radar spectrum can be obtained regardless of the phase of the received signal.
  • the line end 35a on the side different from the input terminal 7 of the unbalanced transmission line of the balun 9a and the line end 35b on the side different from the input terminal 8 of the unbalanced transmission line of the balun 9b are connected. Further, the line ends 35a and 35b are grounded via the power source 34 from a point equidistant from the line end 35a and the line end 35b.
  • the power source 34 is connected to the drain terminals of the field effect transistor group included in the modulation stage 3 of the modulator 6 via the unbalanced transmission lines of the baluns 9a and 9b and the matched transmission lines 16 and 17.
  • the phase and further the intensity of the differential signals input to the modulation stages 10a and 10b can be set equal.
  • the unbalanced transmission line 21 has one line end connected to the single input terminal 18.
  • One line end 42 of the balanced transmission line 22 is connected to the drain terminal of the first ground capacitor 24b and the fifth transistor (Tr5 or Tr11), and the other line end is connected to the differential output terminal 19. Has been.
  • the differential output terminal 19 is connected to the source terminals of the first and second transistors (Tr1 and Tr2 or Tr7 and Tr8).
  • One line end 43 of the balanced transmission line 23 is connected to the second ground capacitor 24c and the drain terminal of the sixth transistor (Tr6 or Tr11), and the other line end is connected to the differential output terminal 20. Has been.
  • the differential output terminal 20 is connected to the source terminals of the third and fourth transistors (Tr3 and Tr4 or Tr9 and Tr10).
  • the unbalanced transmission line 21A and the balanced transmission line 22 have the same length, and are arranged in parallel via a dielectric layer. The same applies to the unbalanced transmission line 21B and the balanced transmission line 23.
  • the unbalanced transmission lines 21A and 21B and the balanced transmission lines 22 and 23 are each 1 ⁇ 4 the wavelength ⁇ of the used frequency band.
  • the wavelength In the ultra-high frequency band such as quasi-millimeter wave and millimeter wave, the wavelength is short, so the size of the merchant balun can be reduced.
  • the size of the merchant balun becomes significantly large, and it becomes difficult to configure the merchant balun in the chip.
  • FIG. 8 is a view showing a modification of the merchant baluns 2, 9a and 9b.
  • the merchant balun shown in FIG. 8 further includes a capacitor 25 in addition to the configuration shown in FIG.
  • the capacitor 25 is connected between the differential output terminals 19 and 20.
  • the length of the balanced transmission lines 22 and 23 can be set to 1 ⁇ 4 or less of the wavelength ⁇ of the used frequency band. Thereby, the size of the merchant balun can be further reduced.
  • FIG. 9B is a diagram showing a modification of the structure of the merchant balun shown in FIG. 9A.
  • the unbalanced transmission line 21 and the balanced transmission lines 22 and 23 are formed of different wiring layers. That is, the balanced transmission lines 22 and 23 are arranged on the same plane, and the unbalanced transmission line 21 and the balanced transmission lines 22 and 23 are arranged in different layers.
  • either the unbalanced transmission line 21 or the balanced transmission lines 22 and 23 may be formed of an upper wiring layer. Further, a wiring layer different from the wiring layer formed between the unbalanced transmission line 21 and the balanced transmission lines 22 and 23 may exist. The number of different wiring layers may be one or more. However, the different wiring layers existing between the unbalanced transmission line 21 and the balanced transmission lines 22 and 23 are within a region that affects electromagnetic coupling between the unbalanced transmission line 21 and the balanced transmission lines 22 and 23. In addition, a passive element such as a transmission line is not formed.
  • a capacitor may be inserted between the output terminals 19 and 20 of the merchant balun shown in FIGS. 9A and 9B.
  • FIG. 10A is a diagram showing a modification of the structure of the merchant balun shown in FIG. 9A.
  • the unbalanced transmission lines 21A and 21B and the balanced transmission lines 22 and 23 are each composed of two transmission lines.
  • the two transmission lines constituting the unbalanced transmission line 21A and the two transmission lines constituting the balanced transmission line 22 are alternately arranged. Further, the two transmission lines constituting the unbalanced transmission line 21B and the two transmission lines constituting the balanced transmission line 23 are alternately arranged.
  • the two transmission lines constituting the unbalanced transmission line 21A are connected on the input terminal 18 side, and the two transmission lines constituting the unbalanced transmission line 21B are grounded via the capacitor 24a. Connected with. Two line ends different from the input terminals 18 of the two transmission lines constituting the unbalanced transmission line 21A and two line ends different from the line ends 41 of the two transmission lines constituting the unbalanced transmission line 21B In total, the four line ends are connected to each other.
  • the two transmission lines constituting the balanced transmission line 22 are connected on the line end 42 side that is grounded via the capacitor 24b.
  • the two transmission lines constituting the balanced transmission line 23 are connected on the line end 43 side that is grounded via the capacitor 24c.
  • the line ends different from the line ends 42 of the two transmission lines constituting the balanced transmission line 22 are connected to each other and to the output terminal 19.
  • the line ends different from the line ends 43 of the two transmission lines constituting the balanced transmission line 23 are connected to each other and to the output terminal 20.
  • the unbalanced transmission lines 21A and 21B and the balanced transmission lines 22 and 23 are formed on the same plane. Since it is difficult to form the wiring connected to the output terminals 19 and 20 and the wiring connecting the unbalanced transmission lines 21A and 21B on the same plane, a bridge wiring may be used as necessary. Absent.
  • FIG. 10B is a diagram showing a modification of the structure of the merchant balun shown in FIG. 10A. This structure is the same as the structure shown in FIG. 10A in that the unbalanced transmission lines 21A and 21B and the balanced transmission lines 22 and 23 are each composed of two transmission lines.
  • the unbalanced transmission lines 21A and 21B and the balanced transmission lines 22 and 23 are formed of different wiring layers. Note that whichever of the unbalanced transmission lines 21A and 21B and the balanced transmission lines 22 and 23 may be formed of an upper wiring layer. Further, a wiring layer different from the wiring layer formed between the unbalanced transmission lines 21A and 21B and the balanced transmission lines 22 and 23 may exist. Further, the number of different wiring layers may be one or more. However, the different wiring layers existing between the unbalanced transmission line 21 and the balanced transmission lines 22 and 23 are within a region that affects electromagnetic coupling between the unbalanced transmission line 21 and the balanced transmission lines 22 and 23. In addition, a passive element such as a transmission line is not formed.
  • a capacitor may be inserted between the output terminals 19 and 20 of the merchant balun shown in FIGS. 10A and 10B.
  • FIG. 11A is a diagram showing a modification of the structure of the merchant balun in FIG. 9A.
  • the unbalanced transmission line 26 is connected to the input terminal 18, and the line end on the side different from the input terminal 18 of the unbalanced transmission line 26 is grounded via the capacitor 24d.
  • the line end may be grounded via the power source 34 instead of the capacitor 24d.
  • the unbalanced transmission line 26 has the same length as the unbalanced transmission line 21 of the merchant balun shown in FIG. 9A.
  • a balanced transmission line 27 is connected to the differential output terminals 19 and 20.
  • the balanced transmission line 27 has a configuration in which the balanced transmission lines 22 and 23 of the merchant balun shown in FIG. 9A are formed in a circular shape.
  • the balanced transmission line 27 is configured by connecting line ends 42 and 43 on the side different from the output terminals 19 and 20 of the balanced transmission lines 22 and 23, respectively.
  • the balanced transmission line 27 is grounded through the capacitor 24e from the middle point of the balanced transmission line 27.
  • the middle point of the balanced transmission line 27 may be grounded via the power source 34 instead of the capacitor 24e. I do not care.
  • the length of the balanced transmission line 27 is the same as the total length of the balanced transmission lines 22 and 23 of the merchant balun shown in FIG. 9A.
  • the size of the merchant balun can be reduced. Further, the unbalanced transmission line 26 and the balanced transmission line 27 of the merchant balun shown in FIG. 11A are formed on the same plane.
  • FIG. 11B is a diagram showing a modification of the structure of the merchant balun in FIG. 11A.
  • the unbalanced transmission line 26 and the balanced transmission line 27 are formed of different wiring layers.
  • either the unbalanced transmission line 26 or the balanced transmission line 27 may be formed of an upper wiring layer.
  • a wiring layer different from the wiring layer formed between the unbalanced transmission line 26 and the balanced transmission line 27 may exist.
  • the number of different wiring layers may be one or more.
  • the different wiring layers existing between the unbalanced transmission line 26 and the balanced transmission line 27 are provided in the transmission line within a region that affects electromagnetic coupling between the unbalanced transmission line 26 and the balanced transmission line 27. Do not form passive elements such as.
  • a capacitor may be inserted between the output terminals 19 and 20 of the merchant balun in FIGS. 11A and 11B.
  • a signal is propagated from the primary wiring to the secondary wiring by magnetic coupling using the circular primary wiring and the secondary wiring, instead of using the circular shaped merchant balun. You may use a transformer.
  • FIG. 12 is a graph showing a simulation result of the dependence of the conversion gain on the local signal power in the semiconductor receiver 50.
  • FIG. 12 shows the conversion gain 28 of the semiconductor receiver 50 according to the present embodiment shown in FIG. 4 and the conversion gain 29 of the semiconductor receiver according to the comparative example shown in FIG.
  • FIG. 1 shows a bipolar transistor
  • the simulation result shown in FIG. 12 shows that the conversion gain 29 is obtained when a field effect transistor is used as in the semiconductor receiver 50 according to the present embodiment shown in FIG. It is.
  • the local signal refers to a signal input to the gate terminal of the field effect transistor that constitutes the modulation stage of the Gilbert cell mixer configuration of the quadrature demodulator included in the semiconductor receiver.
  • the conversion gains 28 and 29 of both semiconductor receivers each exhibit saturation characteristics, in the saturated state, the conversion gain 28 of the semiconductor receiver 50 according to the present embodiment is compared with the conversion gain 29 of the semiconductor receiver according to the comparative example. About 8 dB higher.
  • the reason why the gain is improved is that the modulator 6 and the quadrature demodulator 15 are matched and connected by the merchant baluns 9a and 9b. Further, in this embodiment, the transistor amplification stage forming the Gilbert cell mixer of the modulator 6 and the quadrature demodulator 15 is removed, and the transistor amplification stage is replaced with a merchant balun that is a passive element. Thereby, the drain-source voltage of each transistor included in the modulation stage 3 of the modulator 6 and the modulation stages 10a and 10b of the quadrature demodulator 15 can be increased. Therefore, the fact that the transistors can be operated under a bias condition in which the gm of these transistors is large is also cited as a factor for improving the gain.
  • the transistors constituting the semiconductor receiver 50 may be other transistors such as bipolar transistors instead of field effect transistors.
  • the semiconductor substrate constituting the IC including the semiconductor receiver 50 may be a Si-based semiconductor or a compound semiconductor such as GaAs.
  • a thick film rewiring structure in which a thick dielectric layer and a wiring layer are added on the Si process.
  • a thick dielectric layer By adding a thick dielectric layer, the influence of the conductive Si substrate can be suppressed.
  • the thick film rewiring structure is taken as an example.
  • the thick film is being increased in the Si process.
  • the merchant balun included in the semiconductor receiver 50 of this embodiment may be formed by an upper wiring layer that is distant from the Si substrate in the Si process.
  • the material of the thick film dielectric is preferably a material having a low relative dielectric constant and dielectric loss.
  • BCB benzocyclobutene
  • polyimide, tetrafluoroethylene, polyphenylene oxide, or the like may be used.
  • the semiconductor receiver concerning the present invention was explained based on the embodiment, the present invention is not limited to these embodiments. Unless it deviates from the meaning of this invention, the form which made
  • the semiconductor receiver according to the above embodiment is typically realized as an LSI that is an integrated circuit. These may be individually made into one chip, or may be made into one chip so as to include a part or all of them.
  • division of functional blocks in the block diagram is an example, and a plurality of functional blocks can be realized as one functional block, a single functional block can be divided into a plurality of functions, or some functions can be transferred to other functional blocks. May be.
  • the circuit configuration shown in the circuit diagram is an example, and the present invention is not limited to the circuit configuration. That is, like the above circuit configuration, a circuit that can realize a characteristic function of the present invention is also included in the present invention.
  • the present invention includes a device in which a device such as a switching device (transistor), a resistor, or a capacitor is connected in series or in parallel to a certain device within a range in which a function similar to the above circuit configuration can be realized. It is.
  • “connected” in the above-described embodiment is not limited to the case where two terminals (nodes) are directly connected, and the two terminals (nodes) can be realized within a range in which a similar function can be realized. ) Is connected via an element.
  • the present invention can be applied to a semiconductor receiver.
  • the present invention can be routinely used for various communication devices or high-frequency semiconductor devices such as radar.

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Abstract

This semiconductor reception device (50) is provided with: a modulator (6) for converting an input signal into first and second modulation signals having a phase difference of 180º with respect to each other; and mixers (33a and 33b) for converting the first and second modulation signals into first through fourth output signals having a phase difference of 0º, 90º, 180º, and 270º. Each of the modulator (6) and the mixers (33a and 33b) is provided with a modulating stage (3, 10a, and 10b) having a Gilbert cell mixer configuration, and with a Marchand balun (2, 9a, and 9b). The Marchand baluns (2, 9a, and 9b) are provided with an unbalanced transmission line (21) and first and second balanced transmission lines (22 and 23), one end of the unbalanced transmission line being connected to an input terminal (18).

Description

半導体受信装置Semiconductor receiver
　本発明は、各種通信機器又はレーダ等の高周波半導体装置内のＭＭＩＣ（Ｍｏｎｏｌｉｔｈｉｃ　Ｍｉｃｒｏｗａｖｅ　Ｉｎｔｅｇｒａｔｅｄ　Ｃｉｒｃｕｉｔ）チップに搭載される半導体受信装置に関するものである。 The present invention relates to a semiconductor receiving device mounted on an MMIC (Monolithic Integrated Circuit) chip in a high-frequency semiconductor device such as various communication devices or radars.
　近年、Ｓｉ系半導体デバイスの微細化が進み、６５ｎｍＣＭＯＳ（Ｃｏｍｐｌｅｍｅｎｔａｒｙ　Ｍｅｔａｌ　Ｏｘｉｄｅ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒ）の量産も実現されている。このようなＣＭＯＳ技術の微細化により、トランジスタの使用可能周波数も次第に高くなってきている。これにより、このようなＣＭＯＳ技術を、車載レーダ又はＨＤＭＩ（Ｈｉｇｈ－Ｄｅｆｉｎｉｔｉｏｎ　Ｍｕｌｔｉｍｅｄｉａ　Ｉｎｔｅｒｆａｃｅ）無線システムなどの準ミリ波及びミリ波帯を用いるアプリケーションに適用するための研究開発が進められている。 In recent years, miniaturization of Si-based semiconductor devices has progressed, and mass production of 65 nm CMOS (Complementary Metal Oxide Semiconductor) has also been realized. With such miniaturization of CMOS technology, the usable frequency of transistors is gradually increasing. As a result, research and development for applying such CMOS technology to applications using quasi-millimeter waves and millimeter-wave bands such as in-vehicle radars or HDMI (High-Definition Multimedia Interface) radio systems are being promoted.
　準ミリ波及びミリ波では、ＵＷＢ（Ｕｌｔｒａ　Ｗｉｄｅ　Ｂａｎｄ）と呼ばれる超広帯域が使用可能であるため、準ミリ波及びミリ波は、大容量通信及び超高速通信用途にも期待されている。また、準ミリ波及びミリ波は、可視光及び赤外線に比べて雨及び雲等の障害物による減衰が小さく、マイクロ波に比べて分解能が高いという特長を持つためセンシング用途にも大いに期待されている。 In quasi-millimeter waves and millimeter waves, an ultra-wide band called UWB (Ultra Wide Band) can be used, so quasi-millimeter waves and millimeter waves are also expected for large-capacity communication and ultrahigh-speed communication applications. In addition, quasi-millimeter waves and millimeter waves are greatly expected to be used for sensing because they are less attenuated by obstacles such as rain and clouds than visible light and infrared light and have higher resolution than microwaves. Yes.
　それらのアプリケーションに向けた半導体受信装置には、変調器及び直交復調器が必要不可欠である。例えば、スペクトル拡散方式を用いたレーダ装置を例に説明する。スペクトル拡散方式レーダ装置では、拡散に用いる擬似雑音符号（ＰＮ：Ｐｓｅｕｄｏ　Ｎｏｉｓｅ）を用いて送信電波が変調される。受信機は、送信電波を変調する際に用いられたＰＮ符号と同じ符号を用いて、物体から反射された反射波を逆拡散する。このため、異なる符号で変調された電波、及び符号変調を用いない他方式のレーダ装置から放射される電波は受信機内で抑圧される。 ∙ A modulator and a quadrature demodulator are indispensable for a semiconductor receiver for these applications. For example, a radar apparatus using a spread spectrum method will be described as an example. In the spread spectrum radar apparatus, a transmission radio wave is modulated using a pseudo noise code (PN) used for spreading. The receiver despreads the reflected wave reflected from the object using the same code as the PN code used for modulating the transmission radio wave. For this reason, radio waves modulated with different codes and radio waves radiated from other types of radar devices that do not use code modulation are suppressed in the receiver.
　また、送信電波はＰＮ符号により周波数拡散されるため、単位周波数あたりの電力を小さくできる。これにより、送信電波が他の無線システムに与える影響を低くできる。さらに、ＰＮ符号のチップレートと符号周期とを調整することで、距離分解能と最大探知距離との関係を自由に設定できる。また、電波を連続的に送信できるので、ピーク電力が大きくならない。さらに直交復調器を用いることで、受信信号の位相の影響を受けず、安定したレーダの受信スペクトルが得られる。 Moreover, since the transmission radio wave is frequency spread by the PN code, the power per unit frequency can be reduced. Thereby, the influence which transmission radio waves have on other wireless systems can be reduced. Furthermore, the relationship between the distance resolution and the maximum detection distance can be freely set by adjusting the chip rate and code cycle of the PN code. In addition, since the radio wave can be transmitted continuously, the peak power does not increase. Further, by using the quadrature demodulator, a stable radar reception spectrum can be obtained without being influenced by the phase of the reception signal.
　上記のような理由で、スペクトル拡散方式レーダ装置には、拡散変調器及び直交復調器を含む半導体受信装置が必ず必要となる。また、準ミリ波及びミリ波帯では、受信信号が伝搬する経路において、変調器でまず逆拡散変調が施されてから、直交復調器にて周波数ダウンコンバートされる方が好ましい。なお、受信信号が、先に直交復調器にて周波数ダウンコンバートされると、超広帯域なベースバンド信号が伝搬する素子又は回路が必要となるので、その設計が困難となる。 For the reasons described above, a spread spectrum radar apparatus always requires a semiconductor receiver including a spread modulator and a quadrature demodulator. In the quasi-millimeter wave and millimeter-wave bands, it is preferable that demodulation is first performed by a modulator and then frequency down-converted by an orthogonal demodulator in a path through which a received signal propagates. If the received signal is first frequency down-converted by the quadrature demodulator, an element or a circuit through which an ultra-wideband baseband signal propagates is required, which makes it difficult to design.
　また、上記直交復調器として、例えば、特許文献１に記載の直交復調器１１２を用いることができる。図１３は、特許文献１に記載の直交復調器１１２の構成を示す図である。 Further, as the quadrature demodulator, for example, the quadrature demodulator 112 described in Patent Document 1 can be used. FIG. 13 is a diagram illustrating a configuration of the quadrature demodulator 112 described in Patent Document 1. In FIG.
　トランジスタＴｒ１０７、Ｔｒ１０８、Ｔｒ１０９、Ｔｒ１１０、Ｔｒ１１１及びＴｒ１１２はバイポーラトランジスタであり、これらのトランジスタにより、ギルバートセルミキサが形成される。さらに、トランジスタＴｒ１１３、Ｔｒ１１４、Ｔｒ１１５、Ｔｒ１１６、Ｔｒ１１７及びＴｒ１１８はバイポーラトランジスタであり、これらのトランジスタにより、ギルバートセルミキサが形成される。そして、これら二つのギルバートセルミキサは、直交復調器１１２を構成する。 Transistors Tr107, Tr108, Tr109, Tr110, Tr111 and Tr112 are bipolar transistors, and these transistors form a Gilbert cell mixer. Further, the transistors Tr113, Tr114, Tr115, Tr116, Tr117, and Tr118 are bipolar transistors, and these transistors form a Gilbert cell mixer. These two Gilbert cell mixers constitute a quadrature demodulator 112.
　また、直交復調器を構成するギルバートセルミキサには、定電流源が含まれている。この定電流源には、一般的には、カレントミラー構成のトランジスタが使用される。 Also, the Gilbert cell mixer constituting the quadrature demodulator includes a constant current source. In general, a transistor having a current mirror configuration is used for the constant current source.
特開平０８－２３７０７７号公報Japanese Patent Laid-Open No. 08-237077
　しかしながら、高周波特性が良好なシリコンＩＣは、小さい電圧しか印加できない低耐圧デバイスである。さらに、アプリケーションの視点でもモバイル用途等では低消費電力化が求められており、デバイスに大きな電圧を与えることが困難となる。 However, silicon ICs with good high frequency characteristics are low breakdown voltage devices that can only apply a small voltage. Furthermore, low power consumption is required for mobile applications and the like from an application viewpoint, and it is difficult to apply a large voltage to the device.
　従来回路のようなギルバートセルミキサ構成では、トランジスタの増幅段及び変調段を２段縦積みにしている。さらに、従来回路は、定電流源を構成するトランジスタを含むと３段縦積みである。よって、負荷抵抗の電圧降下も考慮すると、トランジスタ１段分のドレイン－ソース間（ＣＭＯＳデバイスを想定）にかかる電圧は非常に小さくなる。これにより、相互コンダクタンス（ｇｍ）が大きい、高周波特性が良好な状態でトランジスタを動作させることが困難となる。 In the Gilbert cell mixer configuration like the conventional circuit, the transistor amplification stage and the modulation stage are vertically stacked. Furthermore, the conventional circuit is three-stage stacked when including a transistor constituting a constant current source. Therefore, considering the voltage drop of the load resistance, the voltage applied between the drain and source (assuming a CMOS device) for one stage of the transistor is very small. This makes it difficult to operate the transistor with a high mutual conductance (gm) and good high frequency characteristics.
　本発明は、上記の問題点を鑑みて、高周波特性を向上する半導体受信装置を提供することを目的とする。 In view of the above problems, an object of the present invention is to provide a semiconductor receiver that improves high-frequency characteristics.
　上記目的を達成するために、本発明の一形態に係る半導体受信装置は、入力信号を、互いに１８０°の位相差を有する第１及び第２の変調信号に変換する第１のミキサと、前記第１及び第２の変調信号を、０°、９０°、１８０°及び２７０°の位相差を有する第１～第４の出力信号に変換する第２及び第３のミキサと、第１及び第２の伝送線路とを備え、前記第１、第２及び第３のミキサの各々は、第１～第３の端子と、第１～第４のトランジスタを備えるギルバートセルミキサ構成の変調段と、第５及び第６のトランジスタを備える定電流源と、一方の線路端が前記第１の端子に接続されている不平衡伝送線路と、第１及び第２の平衡伝送線路と、第１及び第２の接地キャパシタとを備える不平衡平衡変換器とを備え、前記第１の平衡伝送線路の一方の線路端は、前記第１の接地キャパシタ及び前記第５のトランジスタのドレイン端子と接続されており、他方の線路端は前記第１及び第２のトランジスタのソース端子と接続されており、前記第２の平衡伝送線路の一方の線路端は、前記第２の接地キャパシタ及び前記第６のトランジスタのドレイン端子と接続されており、他方の線路端は前記第３及び第４のトランジスタのソース端子と接続されており、前記第１及び第３のトランジスタのドレイン端子は、前記第２の端子に接続されており、前記第２及び第４のトランジスタのドレイン端子は、前記第３の端子に接続されており、前記第１のミキサの前記第１の端子には前記入力信号が入力され、前記第１のミキサの前記第２及び第３の端子に前記第１及び第２の変調信号が出力され、前記第２のミキサの前記第１の端子は、前記第１の伝送線路を介して、前記第１のミキサの前記第２の端子に接続されており、前記第２のミキサの前記第２及び第３の端子には、前記第１及び第３の出力信号が出力され、前記第３のミキサの前記第１の端子は、前記第２の伝送線路を介して、前記第１のミキサの前記第３の端子に接続されており、前記第３のミキサの前記第２及び第３の端子には、前記第２及び第４の出力信号が出力される。 To achieve the above object, a semiconductor receiver according to an aspect of the present invention includes a first mixer that converts an input signal into first and second modulated signals having a phase difference of 180 ° from each other, and Second and third mixers for converting the first and second modulation signals into first to fourth output signals having phase differences of 0 °, 90 °, 180 ° and 270 °; Each of the first, second, and third mixers includes a first to third terminals, a modulation stage having a Gilbert cell mixer configuration that includes first to fourth transistors, A constant current source including fifth and sixth transistors; an unbalanced transmission line having one line end connected to the first terminal; first and second balanced transmission lines; And an unbalanced balanced converter comprising two grounded capacitors, the first balanced transmission. One line end of the line is connected to the first ground capacitor and the drain terminal of the fifth transistor, and the other line end is connected to the source terminal of the first and second transistors. One line end of the second balanced transmission line is connected to the second grounded capacitor and the drain terminal of the sixth transistor, and the other line end is connected to the third and fourth transistors. A drain terminal of the first and third transistors is connected to the second terminal, and a drain terminal of the second and fourth transistors is connected to the third terminal. The input signal is input to the first terminal of the first mixer, and the first and second modulation signals are input to the second and third terminals of the first mixer. Out The first terminal of the second mixer is connected to the second terminal of the first mixer via the first transmission line, and the second terminal of the second mixer is connected to the second terminal of the second mixer. The first and third output signals are output to the second and third terminals, and the first terminal of the third mixer is connected to the first mixer via the second transmission line. The second and fourth output signals are output to the second and third terminals of the third mixer.
　この構成によれば、本発明の一形態に係る半導体受信装置は、第１～第３のミキサを構成するトランジスタの縦積み数を低減できる。これにより、それぞれのミキサの高周波特性を向上できる。よって、当該半導体受信装置は、高周波特性を向上できる。また、第１及び第２の変調信号を不平衡平衡変換器で分配することで、第２及び第３のミキサへの差動信号の分配を実現できる。 According to this configuration, the semiconductor receiver according to an aspect of the present invention can reduce the number of transistors stacked in the first to third mixers. Thereby, the high frequency characteristic of each mixer can be improved. Therefore, the semiconductor receiving device can improve high frequency characteristics. Further, by distributing the first and second modulated signals by the unbalanced and balanced converter, it is possible to realize the distribution of the differential signal to the second and third mixers.
　また、前記第２のミキサが備える前記不平衡伝送線路の他方の線路端と、前記第３のミキサが備える前記不平衡伝送線路の他方の線路端とは接続されており、当該２つの他方の線路端は、当該２つの他方の線路端から等距離の地点で電源を介して接地されていてもよい。 In addition, the other line end of the unbalanced transmission line included in the second mixer and the other line end of the unbalanced transmission line included in the third mixer are connected, and the other of the two other The line end may be grounded via a power source at a point equidistant from the two other line ends.
　また、前記第２及び第３のミキサの各々において、前記第１及び第４のトランジスタのゲート端子は互いに接続されており、前記第２及び第３のトランジスタのゲート端子は互いに接続されており、前記第２及び第３のミキサの各々は、さらに、前記第１及び第３のトランジスタのドレイン端子に接続されている第１の抵抗素子と、前記第２及び第４のトランジスタのドレイン端子に接続されている第２の抵抗素子とを備えてもよい。 In each of the second and third mixers, the gate terminals of the first and fourth transistors are connected to each other, and the gate terminals of the second and third transistors are connected to each other, Each of the second and third mixers is further connected to a first resistance element connected to the drain terminals of the first and third transistors and to the drain terminals of the second and fourth transistors. And a second resistance element that is provided.
　また、前記不平衡平衡変換器は、さらに、前記第１の平衡伝送線路の前記他方の線路端と、前記第２の平衡伝送線路の前記他方の線路端との間に接続されているキャパシタを備えてもよい。 The unbalanced balanced converter further includes a capacitor connected between the other line end of the first balanced transmission line and the other line end of the second balanced transmission line. You may prepare.
　この構成によれば、不平衡平衡変換器を小型化できる。 This configuration can reduce the size of the unbalanced / balanced converter.
　また、前記第１の平衡伝送線路と、前記第２の平衡伝送線路と、前記不平衡伝送線路とは同一平面上に配置されていてもよい。 In addition, the first balanced transmission line, the second balanced transmission line, and the unbalanced transmission line may be arranged on the same plane.
　また、前記第１の平衡伝送線路と前記第２の平衡伝送線路とは同一平面上に配置されており、前記不平衡伝送線路は、前記第１及び第２の平衡伝送線路とは異なる層に配置されていてもよい。 Further, the first balanced transmission line and the second balanced transmission line are arranged on the same plane, and the unbalanced transmission line is in a different layer from the first and second balanced transmission lines. It may be arranged.
　なお、本発明は、このような半導体受信装置として実現できるだけでなく、このような半導体受信装置の機能の一部又は全てを実現する半導体集積回路（ＬＳＩ）として実現できる。 Note that the present invention can be realized not only as such a semiconductor receiver but also as a semiconductor integrated circuit (LSI) that realizes part or all of the functions of such a semiconductor receiver.
　以上より、本発明は、高周波特性を向上できる半導体受信装置を提供できる。 As described above, the present invention can provide a semiconductor receiver capable of improving high-frequency characteristics.
図１は、本発明の比較例に係る半導体受信装置の回路図である。FIG. 1 is a circuit diagram of a semiconductor receiver according to a comparative example of the present invention. 図２は、本発明の比較例に係る半導体受信装置のブロック図である。FIG. 2 is a block diagram of a semiconductor receiver according to a comparative example of the present invention. 図３は、本発明の実施形態に係る半導体受信装置のブロック図である。FIG. 3 is a block diagram of the semiconductor receiver according to the embodiment of the present invention. 図４は、本発明の実施形態に係る半導体受信装置の回路図である。FIG. 4 is a circuit diagram of the semiconductor receiver according to the embodiment of the present invention. 図５は、本発明の実施形態に係る変調器の回路図である。FIG. 5 is a circuit diagram of the modulator according to the embodiment of the present invention. 図６は、本発明の実施形態に係る直交復調器の回路図である。FIG. 6 is a circuit diagram of the quadrature demodulator according to the embodiment of the present invention. 図７は、本発明の実施形態に係るマーチャントバランの構成を示す図である。FIG. 7 is a diagram showing the configuration of the merchant balun according to the embodiment of the present invention. 図８は、本発明の実施形態に係るマーチャントバランの変形例の構成を示す図である。FIG. 8 is a diagram showing a configuration of a modified example of the merchant balun according to the embodiment of the present invention. 図９Ａは、本発明の実施形態に係るマーチャントバランの構造を示す斜視図である。FIG. 9A is a perspective view showing a structure of a merchant balun according to the embodiment of the present invention. 図９Ｂは、本発明の実施形態に係るマーチャントバランの構造を示す斜視図である。FIG. 9B is a perspective view showing the structure of the merchant balun according to the embodiment of the present invention. 図１０Ａは、本発明の実施形態に係るマーチャントバランの変形例の構造を示す斜視図である。FIG. 10A is a perspective view showing a structure of a modified example of the merchant balun according to the embodiment of the present invention. 図１０Ｂは、本発明の実施形態に係るマーチャントバランの変形例の構造を示す斜視図である。FIG. 10B is a perspective view showing a structure of a modified example of the merchant balun according to the embodiment of the present invention. 図１１Ａは、本発明の実施形態に係るマーチャントバランの変形例の構造を示す斜視図である。FIG. 11A is a perspective view showing a structure of a modified example of the merchant balun according to the embodiment of the present invention. 図１１Ｂは、本発明の実施形態に係るマーチャントバランの変形例の構造を示す斜視図である。FIG. 11B is a perspective view showing a structure of a modified example of the merchant balun according to the embodiment of the present invention. 図１２は、本発明の実施形態に係る半導体受信装置の変換利得のローカル信号パワー依存性を示すグラフである。FIG. 12 is a graph showing the local signal power dependence of the conversion gain of the semiconductor receiver according to the embodiment of the present invention. 図１３は、従来の直交復調器の回路図である。FIG. 13 is a circuit diagram of a conventional quadrature demodulator.
　本発明の実施形態を説明する前に、本発明の比較例に係る半導体受信装置について説明する。 Before describing the embodiment of the present invention, a semiconductor receiver according to a comparative example of the present invention will be described.
　（比較例）
　図１は、本発明の比較例に係る半導体受信装置の構成を示す図である。この半導体受信装置は、図１３に示す直交復調器１１２を含む。さらに、当該半導体受信装置は、変調器１０５を含む。なお、上述した図１３の説明と重複する説明は省略する。 (Comparative example)
FIG. 1 is a diagram showing a configuration of a semiconductor receiver according to a comparative example of the present invention. This semiconductor receiver includes a quadrature demodulator 112 shown in FIG. Further, the semiconductor receiving device includes a modulator 105. Note that a description overlapping the description of FIG. 13 described above is omitted.
　トランジスタＴｒ１０１、Ｔｒ１０２、Ｔｒ１０３、Ｔｒ１０４、Ｔｒ１０５及びＴｒ１０６はバイポーラトランジスタであり（電界効果トランジスタであっても構わない）、これらのトランジスタはギルバートセルミキサを形成するとともに、変調器１０５を構成する。この変調器１０５は、差動入力端子１０１及び１０２と、差動出力端子１０３及び１０４とを有する。 Transistors Tr101, Tr102, Tr103, Tr104, Tr105, and Tr106 are bipolar transistors (may be field effect transistors), and these transistors form a Gilbert cell mixer and constitute the modulator 105. The modulator 105 has differential input terminals 101 and 102 and differential output terminals 103 and 104.
　直交復調器１１２は、差動入力端子１０６及び１０７と、出力端子１０８、１０９、１１０及び１１１とを有する。出力端子１０８は、０°出力端子であり、出力端子１０９は１８０°出力端子であり、出力端子１１０は９０°出力端子であり、出力端子１１１は２７０°出力端子である。 The quadrature demodulator 112 has differential input terminals 106 and 107 and output terminals 108, 109, 110 and 111. The output terminal 108 is a 0 ° output terminal, the output terminal 109 is a 180 ° output terminal, the output terminal 110 is a 90 ° output terminal, and the output terminal 111 is a 270 ° output terminal.
　これらの出力端子から出力された信号は、ディジタルＩＣにて信号処理を施される。変調器１０５の出力端子１０３と直交復調器１１２の入力端子１０６とは、インピーダンスマッチング回路１１３を介して接続される。変調器１０５の出力端子１０４と直交復調器１１２の入力端子１０７とは、インピーダンスマッチング回路１１４を介して接続される。インピーダンスマッチング回路１１３及び１１４は、伝送線路のみで構成されるのが好ましいが、必要に応じてスタブ（オープン又はショート）、又は集中定数素子として扱えるスパイラルインダクタなどを使用しても構わない。 The signals output from these output terminals are subjected to signal processing by a digital IC. The output terminal 103 of the modulator 105 and the input terminal 106 of the quadrature demodulator 112 are connected via an impedance matching circuit 113. The output terminal 104 of the modulator 105 and the input terminal 107 of the quadrature demodulator 112 are connected via an impedance matching circuit 114. The impedance matching circuits 113 and 114 are preferably composed only of transmission lines, but a stub (open or short) or a spiral inductor that can be handled as a lumped element may be used as necessary.
　また、変調器１０５及び直交復調器１１２を構成するギルバートセルミキサは、定電流源を含む。この定電流源には、一般的には、カレントミラー構成のトランジスタが使用される。 Further, the Gilbert cell mixer constituting the modulator 105 and the quadrature demodulator 112 includes a constant current source. In general, a transistor having a current mirror configuration is used for the constant current source.
　また、図１の回路構成は図２のような簡単なブロックで表すことができる。 Further, the circuit configuration of FIG. 1 can be represented by a simple block as shown in FIG.
　しかしながら、上述したように、このギルバートセルミキサ構成では、トランジスタの増幅段及び変調段を２段縦積みにしている。さらに、当該ギルバートセルミキサ構成は、定電流源を構成するトランジスタを含むと３段縦積みである。よって、負荷抵抗の電圧降下も考慮すると、トランジスタ１段分のコレクタ－エミッタ間（電界効果トランジスタであればドレイン－ソース間）にかかる電圧は非常に小さくなる。これにより、相互コンダクタンス（ｇｍ）が大きく、高周波特性が良好な状態でトランジスタを動作させることが困難となる。 However, as described above, in this Gilbert cell mixer configuration, the transistor amplification stage and the modulation stage are vertically stacked. Further, the Gilbert cell mixer configuration is three-stage stacked when including the transistors constituting the constant current source. Therefore, in consideration of the voltage drop of the load resistance, the voltage applied between the collector and the emitter for one stage of the transistor (between the drain and the source in the case of a field effect transistor) becomes very small. This makes it difficult to operate the transistor with a high mutual conductance (gm) and good high frequency characteristics.
　また、図１の変調器１０５から２つの直交復調器１１２への接続配線の設計が課題となる。図１に示すように、インピーダンスマッチング回路１１３及び１１４により、変調器１０５の出力インピーダンスと、直交復調器１１２の入力インピーダンスとの整合を取ることが可能である。しかし、直交復調器１１２の入力端子１０６からＴｒ１０７とＴｒ１１４とに分配される配線と、入力端子１０７からＴｒ１０８とＴｒ１１３とに分配される配線とにより、Ｔｒ１０７とＴｒ１０８とに１８０°位相が異なる差動信号を入力し、かつＴｒ１１３とＴｒ１１４とに１８０°位相が異なる差動信号を入力できるようにレイアウトを施すことが困難である。特に準ミリ波及びミリ波帯のような超高周波領域では、配線などの伝送線路の長さによって位相がずれやすいので、この直交復調器１１２に入力する差動分配部分の設計には精度が求められる。 Also, the design of connection wiring from the modulator 105 of FIG. 1 to the two quadrature demodulator 112 becomes a problem. As shown in FIG. 1, the impedance matching circuits 113 and 114 can match the output impedance of the modulator 105 and the input impedance of the quadrature demodulator 112. However, the differential of 180 ° phase difference between Tr107 and Tr108 due to the wiring distributed from the input terminal 106 of the quadrature demodulator 112 to Tr107 and Tr114 and the wiring distributed from the input terminal 107 to Tr108 and Tr113. It is difficult to perform layout so that a differential signal having a phase difference of 180 ° can be input to Tr113 and Tr114. In particular, in the ultra-high frequency region such as the quasi-millimeter wave and the millimeter-wave band, the phase is likely to be shifted depending on the length of the transmission line such as the wiring. It is done.
　（実施形態）
　以下、本発明の実施形態に係る半導体受信装置について添付の図面を参照して説明する。なお、以下で説明する実施形態は、いずれも本発明の好ましい一具体例を示すものである。以下の実施形態で示される数値、構成要素、構成要素の配置位置及び接続形態は、一例であり、本発明を限定する主旨ではない。本発明は、請求の範囲だけによって限定される。よって、以下の実施形態における構成要素のうち、本発明の最上位概念を示す独立請求項に記載されていない構成要素については、本発明の課題を達成するのに必ずしも必要ではないが、より好ましい形態を構成するものとして説明される。 (Embodiment)
Hereinafter, a semiconductor receiver according to an embodiment of the present invention will be described with reference to the accompanying drawings. Note that each of the embodiments described below shows a preferred specific example of the present invention. The numerical values, constituent elements, arrangement positions and connection forms of the constituent elements shown in the following embodiments are merely examples, and are not intended to limit the present invention. The present invention is limited only by the claims. Therefore, among the constituent elements in the following embodiments, constituent elements that are not described in the independent claims showing the highest concept of the present invention are not necessarily required to achieve the object of the present invention, but are more preferable. It will be described as constituting a form.
　本実施形態に係る半導体受信装置では、変調器及び直交復調器に含まれるギルバートセルミキサの増幅段が、結合線路で構成されたマーチャントバラン（不平衡平衡変換器）に置き換えられる。また、変調器の出力端子とマーチャントバランの不平衡伝送線路の入力端とを接続する。これにより、当該半導体受信装置は、高周波特性を向上できるとともに、直交復調器への差動分配を実現できる。 In the semiconductor receiver according to the present embodiment, the amplification stage of the Gilbert cell mixer included in the modulator and the quadrature demodulator is replaced with a merchant balun (unbalanced balanced converter) configured by a coupled line. Further, the output terminal of the modulator is connected to the input end of the unbalanced transmission line of the merchant balun. As a result, the semiconductor receiving device can improve high-frequency characteristics and realize differential distribution to the quadrature demodulator.
　図３は、本発明の実施形態に係る半導体受信装置５０のブロック図である。図４は、半導体受信装置５０の回路図である。この半導体受信装置５０は、入力端子１と、変調器６と、直交復調器１５と、出力端子１１、１２、１３及び１４と、整合伝送線路１６及び１７とを備える。 FIG. 3 is a block diagram of the semiconductor receiver 50 according to the embodiment of the present invention. FIG. 4 is a circuit diagram of the semiconductor receiver 50. The semiconductor receiver 50 includes an input terminal 1, a modulator 6, a quadrature demodulator 15, output terminals 11, 12, 13 and 14, and matched transmission lines 16 and 17.
　半導体受信装置５０は、アンテナで受信され、低雑音増幅器（ＬＮＡ：Ｌｏｗ　Ｎｏｉｓｅ　Ａｍｐ）等を介して、入力された入力信号を処理する役割を担っている。この時、アンテナが差動配線構成である場合、サイズが大きくなる、及び、構成が複雑となることで損失が大きくなる、などの問題点が生じる。よって、アンテナは、シングルエンド構成であることが好ましい。 The semiconductor receiver 50 has a role of processing an input signal received by an antenna and input through a low noise amplifier (LNA: Low Noise Amp) or the like. At this time, when the antenna has a differential wiring configuration, there are problems such as an increase in size and a loss due to a complicated configuration. Therefore, it is preferable that the antenna has a single-ended configuration.
　図５は、変調器６の回路図である。この変調器６は、入力端子１と、マーチャントバラン２（以下、バラン２とも記す）と、ギルバートセルミキサ構成の変調段３（以下、変調段３とも記す）と、出力端子４及び５と、電流源３１とを備える。変調器６は、入力端子１に入力された入力信号を、互いに１８０°の位相差を有する第１及び第２の変調信号に変換し、変換した第１及び第２の変調信号を出力端子４及び５に出力する。また、変調器６は、本発明の第１のミキサに相当し、入力端子１、出力端子４及び５は、本発明の第１～第３の端子に相当する。 FIG. 5 is a circuit diagram of the modulator 6. The modulator 6 includes an input terminal 1, a merchant balun 2 (hereinafter also referred to as balun 2), a modulation stage 3 having a Gilbert cell mixer configuration (hereinafter also referred to as modulation stage 3), output terminals 4 and 5, A current source 31. The modulator 6 converts the input signal input to the input terminal 1 into first and second modulation signals having a phase difference of 180 ° from each other, and outputs the converted first and second modulation signals to the output terminal 4. And 5 are output. The modulator 6 corresponds to the first mixer of the present invention, and the input terminal 1 and the output terminals 4 and 5 correspond to the first to third terminals of the present invention.
　アンテナ及びＬＮＡを伝搬した入力信号は、入力端子１に入力される。 The input signal propagated through the antenna and the LNA is input to the input terminal 1.
　バラン２は結合線路で構成されており、不平衡伝送線路を有する。このバラン２は、入力端子１に入力されたシングル信号を、それぞれ１８０°の位相差を持つ差動信号に変換する。変換された差動信号は変調段３に入力される。 The balun 2 is composed of a coupled line and has an unbalanced transmission line. The balun 2 converts a single signal input to the input terminal 1 into a differential signal having a phase difference of 180 °. The converted differential signal is input to the modulation stage 3.
　変調段３は、電界効果トランジスタＴｒ１、Ｔｒ２、Ｔｒ３及びＴｒ４を備える。この変調段３は、バラン２で変換された差動信号を変調し、変調した差動信号（第１及び第２の変調信号）を、それぞれ出力端子４及び５へ伝搬する。また、電界効果トランジスタＴｒ１～Ｔｒ４は、本発明の第１～第４のトランジスタに相当する。 The modulation stage 3 includes field effect transistors Tr1, Tr2, Tr3 and Tr4. The modulation stage 3 modulates the differential signal converted by the balun 2 and propagates the modulated differential signals (first and second modulation signals) to the output terminals 4 and 5, respectively. The field effect transistors Tr1 to Tr4 correspond to the first to fourth transistors of the present invention.
　トランジスタＴｒ１及びＴｒ３のドレイン端子は、出力端子４に接続されている。トランジスタＴｒ２及びＴｒ４のドレイン端子は、出力端子５に接続されている。 The drain terminals of the transistors Tr1 and Tr3 are connected to the output terminal 4. The drain terminals of the transistors Tr2 and Tr4 are connected to the output terminal 5.
　電流源３１はバラン２の平衡伝送線路を介して、変調段３を構成する電界効果トランジスタに定電流を供給する。この電流源３１は、電界効果トランジスタＴｒ５及びＴｒ６を含む。例えば、トランジスタＴｒ５及びＴｒ６はカレントミラー回路を構成する。また、電界効果トランジスタＴｒ５及びＴｒ６は、本発明の第５及び第６のトランジスタに相当する。 The current source 31 supplies a constant current to the field effect transistor constituting the modulation stage 3 through the balanced transmission line of the balun 2. The current source 31 includes field effect transistors Tr5 and Tr6. For example, the transistors Tr5 and Tr6 constitute a current mirror circuit. The field effect transistors Tr5 and Tr6 correspond to the fifth and sixth transistors of the present invention.
　図６は直交復調器１５の回路図である。この直交復調器１５は、入力端子７及び８と、出力端子１１～１４と、ダウンコンバージョンミキサ３３ａ及び３３ｂ(以下、ミキサ３３ａ及び３３ｂとも記す)とを備える。変調器６から出力された信号は、入力端子７及び８に入力される。直交復調器１５は、変調器６により生成された第１及び第２の変調信号を、０°、９０°、１８０°及び２７０°の位相差を有する第１～第４の出力信号に変換し、変換した第１～第４の出力信号を出力端子１１～１４に出力する。 FIG. 6 is a circuit diagram of the quadrature demodulator 15. The orthogonal demodulator 15 includes input terminals 7 and 8, output terminals 11 to 14, and down- conversion mixers 33a and 33b (hereinafter also referred to as mixers 33a and 33b). The signal output from the modulator 6 is input to the input terminals 7 and 8. The quadrature demodulator 15 converts the first and second modulated signals generated by the modulator 6 into first to fourth output signals having phase differences of 0 °, 90 °, 180 °, and 270 °. The converted first to fourth output signals are output to the output terminals 11 to 14, respectively.
　ミキサ３３ａは、入力端子７と、出力端子１１及び１２と、マーチャントバラン９ａ（以下、バラン９ａとも記す）と、ギルバートセルミキサ構成の変調段１０ａ（以下、変調段１０ａとも記す）と、電流源３２ａとを備える。ミキサ３３ｂは、入力端子８と、出力端子１３及び１４と、マーチャントバラン９ｂ（以下、バラン９ｂとも記す）と、ギルバートセルミキサ構成の変調段１０ｂ（以下、変調段１０ｂとも記す）と、電流源３２ｂとを備える。また、ミキサ３３ａ及び３３ｂは、本発明の第２及び第３ミキサに相当する。また、入力端子７、出力端子１１及び１２は本発明の第１～第３の端子に相当する。同様に、入力端子８、出力端子１３及び１４は本発明の第１～第３の端子に相当する。 The mixer 33a includes an input terminal 7, output terminals 11 and 12, a merchant balun 9a (hereinafter also referred to as balun 9a), a modulation stage 10a (hereinafter also referred to as modulation stage 10a) having a Gilbert cell mixer configuration, a current source 32a. The mixer 33b includes an input terminal 8, output terminals 13 and 14, a merchant balun 9b (hereinafter also referred to as a balun 9b), a modulation stage 10b having a Gilbert cell mixer configuration (hereinafter also referred to as a modulation stage 10b), a current source 32b. The mixers 33a and 33b correspond to the second and third mixers of the present invention. The input terminal 7 and the output terminals 11 and 12 correspond to the first to third terminals of the present invention. Similarly, the input terminal 8 and the output terminals 13 and 14 correspond to the first to third terminals of the present invention.
　なお、２つのミキサ３３ａ及び３３ｂは、同じ回路構成であるため、以下では、ミキサ３３ａの構成のみを説明し、重複する説明は省略する。 Note that, since the two mixers 33a and 33b have the same circuit configuration, only the configuration of the mixer 33a will be described below, and redundant description will be omitted.
　バラン９ａは、結合線路で構成されており、不平衡伝送線路を有する。このバラン９ａは、本発明の不平衡平衡変換器に相当する。バラン９ａは、入力端子７（８）に入力されたシングル信号を差動信号に変換する。変換された差動信号は変調段１０ａ（１０ｂ）に入力される。 The balun 9a is composed of a coupled line and has an unbalanced transmission line. This balun 9a corresponds to the unbalanced balanced converter of the present invention. The balun 9a converts the single signal input to the input terminal 7 (8) into a differential signal. The converted differential signal is input to the modulation stage 10a (10b).
　変調段１０ａは、電界効果トランジスタＴｒ７、Ｔｒ８、Ｔｒ９及びＴｒ１０と、負荷抵抗Ｒ１及びＲ２と、出力端子１１及び１２（１３及び１４）を備える。ここで、電界効果トランジスタＴｒ７、Ｔｒ８、Ｔｒ９及びＴｒ１０は、本発明の第１～第４のトランジスタに相当する。負荷抵抗Ｒ１及びＲ２は、本発明の第１及び第２の抵抗素子に相当する。 The modulation stage 10a includes field effect transistors Tr7, Tr8, Tr9 and Tr10, load resistors R1 and R2, and output terminals 11 and 12 (13 and 14). Here, the field effect transistors Tr7, Tr8, Tr9 and Tr10 correspond to the first to fourth transistors of the present invention. The load resistors R1 and R2 correspond to the first and second resistance elements of the present invention.
　負荷抵抗Ｒ１は、トランジスタＴｒ７及びＴｒ９のドレイン端子と、電源との間に挿入されている。 The load resistor R1 is inserted between the drain terminals of the transistors Tr7 and Tr9 and the power supply.
　出力端子１１（１３）は、トランジスタＴｒ７のドレイン端子とトランジスタＴｒ９のドレイン端子との接続箇所と、負荷抵抗Ｒ１との間のノードに接続されている。 The output terminal 11 (13) is connected to a node between the connection point between the drain terminal of the transistor Tr7 and the drain terminal of the transistor Tr9 and the load resistor R1.
　負荷抵抗Ｒ２は、トランジスタＴｒ８及びＴｒ１０のドレイン端子と、電源との間に挿入されている。 The load resistor R2 is inserted between the drain terminals of the transistors Tr8 and Tr10 and the power supply.
　出力端子１２（１４）は、トランジスタＴｒ８のドレイン端子とトランジスタＴｒ１０のドレイン端子との接続箇所と、負荷抵抗Ｒ２との間のノードに接続されている。 The output terminal 12 (14) is connected to a node between the connection point between the drain terminal of the transistor Tr8 and the drain terminal of the transistor Tr10 and the load resistor R2.
　電流源３２ａ（３２ｂ）はバラン９ａ（９ｂ）の平衡伝送線路を介して、変調段１０ａ（１０ｂ）を構成する電界効果トランジスタに定電流を供給する。この電流源３２ａは、電界効果トランジスタＴｒ１１及びＴｒ１２を含む。例えば、トランジスタＴｒ１１及びＴｒ１２はカレントミラー回路を構成する。また、電界効果トランジスタＴｒ１１及びＴｒ１２は、本発明の第５及び第６のトランジスタに相当する。 The current source 32a (32b) supplies a constant current to the field effect transistors constituting the modulation stage 10a (10b) via the balanced transmission line of the balun 9a (9b). The current source 32a includes field effect transistors Tr11 and Tr12. For example, the transistors Tr11 and Tr12 constitute a current mirror circuit. The field effect transistors Tr11 and Tr12 correspond to the fifth and sixth transistors of the present invention.
　また、ミキサ３３ａの変調段１０ａに入力されるローカル差動信号と、ミキサ３３ｂの変調段１０ｂに入力されるローカル差動信号とは、９０°位相差を持つように設定される。 The local differential signal input to the modulation stage 10a of the mixer 33a and the local differential signal input to the modulation stage 10b of the mixer 33b are set to have a 90 ° phase difference.
　直交復調器１５は、ローカル発振器からの差動信号を、９０°移相器を用いて、０°、９０°、１８０°、２７０°の位相差を有する４つの信号に変換し、０°、１８０°の差動信号を変調段１０ａのローカル信号入力端子に、９０°、２７０°の差動信号を変調段１０ｂのローカル信号入力端子に入力する。９０°移相器には、抵抗及びキャパシタを利用したポリフェーズフィルター、又はλ／４伝送線路で構成されるブランチライン移相器などが一般的に用いられる。しかし、準ミリ波及びミリ波帯のような超高周波領域では、ポリフェーズフィルターにおける抵抗等での損失が大きいため、ブランチライン移相器を用いることが好ましい。 The quadrature demodulator 15 converts the differential signal from the local oscillator into four signals having a phase difference of 0 °, 90 °, 180 °, and 270 ° using a 90 ° phase shifter. The differential signal of 180 ° is input to the local signal input terminal of the modulation stage 10a, and the differential signal of 90 ° and 270 ° is input to the local signal input terminal of the modulation stage 10b. As the 90 ° phase shifter, a polyphase filter using a resistor and a capacitor, or a branch line phase shifter constituted by a λ / 4 transmission line is generally used. However, in an ultrahigh frequency region such as a quasi-millimeter wave and a millimeter wave band, it is preferable to use a branch line phase shifter because loss due to resistance or the like in the polyphase filter is large.
　これにより、出力端子１１から出力される信号の位相を０°とすれば、出力端子１２の信号位相は１８０°、出力端子１３の信号位相は９０°、出力端子１４の信号位相は２７０°となる。このように出力端子１１～１４の信号位相を設定することで、ディジタル信号処理部で直交信号処理を施すことが可能となる。 Thus, if the phase of the signal output from the output terminal 11 is 0 °, the signal phase of the output terminal 12 is 180 °, the signal phase of the output terminal 13 is 90 °, and the signal phase of the output terminal 14 is 270 °. Become. By setting the signal phases of the output terminals 11 to 14 in this way, it becomes possible to perform orthogonal signal processing in the digital signal processing unit.
　例えば、レーダシステム用途などでは、このような直交信号処理を施すことで、受信信号の位相に関わらず一定のレーダスペクトルを得ることができる。 For example, in radar system applications, by performing such orthogonal signal processing, a constant radar spectrum can be obtained regardless of the phase of the received signal.
　また、バラン９ａの不平衡伝送線路の入力端子７とは異なる側の線路端３５ａと、バラン９ｂの不平衡伝送線路の入力端子８とは異なる側の線路端３５ｂとは接続されている。さらに、線路端３５ａ及び３５ｂは、当該線路端３５ａと線路端３５ｂとから等距離の地点から電源３４を介して接地される。 Further, the line end 35a on the side different from the input terminal 7 of the unbalanced transmission line of the balun 9a and the line end 35b on the side different from the input terminal 8 of the unbalanced transmission line of the balun 9b are connected. Further, the line ends 35a and 35b are grounded via the power source 34 from a point equidistant from the line end 35a and the line end 35b.
　また、図４に示すように、変調器６の出力端子４と直交復調器１５の入力端子７とは、整合伝送線路１６を介して接続されている。変調器６の出力端子５と直交復調器１５の入力端子７とは整合伝送線路１７を介して接続されている。この整合伝送線路１６及び１７は、オープンスタブ或いはショートスタブ、又はスパイラルインダクタなどの受動素子が含まれていても構わない。 Further, as shown in FIG. 4, the output terminal 4 of the modulator 6 and the input terminal 7 of the quadrature demodulator 15 are connected via a matched transmission line 16. The output terminal 5 of the modulator 6 and the input terminal 7 of the quadrature demodulator 15 are connected via a matched transmission line 17. The matched transmission lines 16 and 17 may include passive elements such as an open stub, a short stub, or a spiral inductor.
　また、電源３４は、バラン９ａ及び９ｂの不平衡伝送線路と整合伝送線路１６及び１７とを介して、変調器６の変調段３に含まれる電界効果トランジスタ群のドレイン端子に接続される。バラン９ａ及び９ｂを同じ構成にし、さらに整合伝送線路１６及び１７を同じ長さ及び構成にすることで、変調段１０ａ及び１０ｂに入力される差動信号の位相、さらには強度を等しく設定できる。 The power source 34 is connected to the drain terminals of the field effect transistor group included in the modulation stage 3 of the modulator 6 via the unbalanced transmission lines of the baluns 9a and 9b and the matched transmission lines 16 and 17. By setting the baluns 9a and 9b to the same configuration and matching transmission lines 16 and 17 to the same length and configuration, the phase and further the intensity of the differential signals input to the modulation stages 10a and 10b can be set equal.
　図７は、マーチャントバラン２、９ａ及び９ｂの構成要素を詳しく表記した図である。このマーチャントバランは、シングル入力端子１８と差動出力端子１９及び２０とを有する。なお、端子１８が出力端子で、端子１９及び２０が入力端子であっても構わない。また、マーチャントバランは、不平衡伝送線路２１と、平衡伝送線路２２及び２３と、キャパシタ２４ａ、２４ｂ及び２４ｃとを有する。不平衡伝送線路２１は不平衡伝送線路２１Ａ及び２１Ｂを含む。ここでキャパシタ２４ｂ及び２４ｃは本発明の第１及び第２の接地キャパシタに相当する。 FIG. 7 is a diagram showing in detail the components of the merchant baluns 2, 9a and 9b. This merchant balun has a single input terminal 18 and differential output terminals 19 and 20. Note that the terminal 18 may be an output terminal, and the terminals 19 and 20 may be input terminals. The merchant balun includes an unbalanced transmission line 21, balanced transmission lines 22 and 23, and capacitors 24a, 24b, and 24c. The unbalanced transmission line 21 includes unbalanced transmission lines 21A and 21B. Here, the capacitors 24b and 24c correspond to the first and second grounded capacitors of the present invention.
　不平衡伝送線路２１は、一方の線路端がシングル入力端子１８に接続されている。 The unbalanced transmission line 21 has one line end connected to the single input terminal 18.
　平衡伝送線路２２の一方の線路端４２は、第１の接地キャパシタ２４ｂ及び第５のトランジスタ（Ｔｒ５又はＴｒ１１）のドレイン端子と接続されており、他方の線路端は、差動出力端子１９に接続されている。また、この差動出力端子１９は、第１及び第２のトランジスタ（Ｔｒ１及びＴｒ２、又は、Ｔｒ７及びＴｒ８）のソース端子と接続されている。 One line end 42 of the balanced transmission line 22 is connected to the drain terminal of the first ground capacitor 24b and the fifth transistor (Tr5 or Tr11), and the other line end is connected to the differential output terminal 19. Has been. The differential output terminal 19 is connected to the source terminals of the first and second transistors (Tr1 and Tr2 or Tr7 and Tr8).
　平衡伝送線路２３の一方の線路端４３は、第２の接地キャパシタ２４ｃ及び第６のトランジスタ（Ｔｒ６又はＴｒ１１）のドレイン端子と接続されており、他方の線路端は、差動出力端子２０に接続されている。また、この差動出力端子２０は、第３及び第４のトランジスタ（Ｔｒ３及びＴｒ４、又は、Ｔｒ９及びＴｒ１０）のソース端子と接続されている。 One line end 43 of the balanced transmission line 23 is connected to the second ground capacitor 24c and the drain terminal of the sixth transistor (Tr6 or Tr11), and the other line end is connected to the differential output terminal 20. Has been. The differential output terminal 20 is connected to the source terminals of the third and fourth transistors (Tr3 and Tr4 or Tr9 and Tr10).
　不平衡伝送線路２１Ａと平衡伝送線路２２とは、同じ長さであり、さらに誘電体層を介して平行に配置される。不平衡伝送線路２１Ｂと平衡伝送線路２３とに関しても同様である。 The unbalanced transmission line 21A and the balanced transmission line 22 have the same length, and are arranged in parallel via a dielectric layer. The same applies to the unbalanced transmission line 21B and the balanced transmission line 23.
　不平衡伝送線路２１Ａ及び２１Ｂと、平衡伝送線路２２及び２３とは、それぞれ使用周波数帯の波長λの１／４の長さである。準ミリ波及びミリ波のような超高周波帯では、波長が短いので、マーチャントバランのサイズも小さくすることができる。逆に低周波帯では、マーチャントバランのサイズが大幅に大きくなり、チップ内にマーチャントバランを構成することが困難となる。 The unbalanced transmission lines 21A and 21B and the balanced transmission lines 22 and 23 are each ¼ the wavelength λ of the used frequency band. In the ultra-high frequency band such as quasi-millimeter wave and millimeter wave, the wavelength is short, so the size of the merchant balun can be reduced. On the other hand, in the low frequency band, the size of the merchant balun becomes significantly large, and it becomes difficult to configure the merchant balun in the chip.
　不平衡伝送線路２１Ａ及び２１Ｂは、それぞれの長さよりも十分短い線路を用いて接続されることが好ましい。不平衡伝送線路２１の入力端子１８と異なる側の線路端４１と、さらに平衡伝送線路２２及び２３の出力端子１９及び２０とは異なる側の線路端４２及び４３とは、キャパシタ２４ａ、２４ｂ及び２４ｃを介して接地される。また、上述したように、このマーチャントバランを図６に示す直交復調器１５に用いる場合は、２つのマーチャントバランの不平衡伝送線路２１の線路端４１を、それぞれキャパシタ２４ａを介さずに接続し、当該２つの線路端４１をその中間地点から電源３４を介して接地する。 The unbalanced transmission lines 21A and 21B are preferably connected using lines that are sufficiently shorter than their respective lengths. The line end 41 on the side different from the input terminal 18 of the unbalanced transmission line 21 and the line ends 42 and 43 on the side different from the output terminals 19 and 20 of the balanced transmission lines 22 and 23 are capacitors 24a, 24b and 24c. Is grounded. Further, as described above, when this merchant balun is used in the quadrature demodulator 15 shown in FIG. 6, the line ends 41 of the unbalanced transmission lines 21 of the two merchant baluns are connected without passing through the capacitors 24a, respectively. The two line ends 41 are grounded from the intermediate point via the power source 34.
　図８は、マーチャントバラン２、９ａ及び９ｂの変形例を示す図である。図８に示すマーチャントバランは、図７に示す構成に加え、さらに、キャパシタ２５を備える。キャパシタ２５は、差動出力端子１９及び２０の間に接続されている。このようにキャパシタ２５を差動出力端子１９及び２０の間に挿入し、さらに入力端子１８のインピーダンスと、出力端子１９及び２０とのインピーダンスを調整することで、不平衡伝送線路２１Ａ及び２１Ｂと、平衡伝送線路２２及び２３との長さを使用周波数帯の波長λの１／４以下に設定することができる。これにより、マーチャントバランのサイズさらに小型化することが可能となる。 FIG. 8 is a view showing a modification of the merchant baluns 2, 9a and 9b. The merchant balun shown in FIG. 8 further includes a capacitor 25 in addition to the configuration shown in FIG. The capacitor 25 is connected between the differential output terminals 19 and 20. Thus, by inserting the capacitor 25 between the differential output terminals 19 and 20, and further adjusting the impedance of the input terminal 18 and the impedance of the output terminals 19 and 20, unbalanced transmission lines 21A and 21B, The length of the balanced transmission lines 22 and 23 can be set to ¼ or less of the wavelength λ of the used frequency band. Thereby, the size of the merchant balun can be further reduced.
　図９Ａは、マーチャントバランの構造を示す斜視図である。図９Ａに示すマーチャントバランでは、不平衡伝送線路２１と平衡伝送線路２２及び２３とは同一平面上に配置されている。キャパシタ２４ａ、２４ｂ及び２４ｃは、キャパシタ構成レイヤで形成されることが好ましい。キャパシタ２４ａ、２４ｂ及び２４ｃと、不平衡伝送線路２１、平衡伝送線路２２及び２３とは、必要があればビアホール等を介して接続される。 FIG. 9A is a perspective view showing the structure of the merchant balun. In the merchant balun shown in FIG. 9A, the unbalanced transmission line 21 and the balanced transmission lines 22 and 23 are arranged on the same plane. Capacitors 24a, 24b and 24c are preferably formed of a capacitor configuration layer. The capacitors 24a, 24b and 24c, the unbalanced transmission line 21, and the balanced transmission lines 22 and 23 are connected via via holes or the like if necessary.
　図９Ｂは、図９Ａで示したマーチャントバランの構造の変形例を示す図である。図９Ｂに示すマーチャントバランでは、不平衡伝送線路２１と、平衡伝送線路２２及び２３とは異なる配線層で形成される。つまり、平衡伝送線路２２及び２３は同一平面上に配置されており、不平衡伝送線路２１と、平衡伝送線路２２及び２３とは異なる層に配置されている。 FIG. 9B is a diagram showing a modification of the structure of the merchant balun shown in FIG. 9A. In the merchant balun shown in FIG. 9B, the unbalanced transmission line 21 and the balanced transmission lines 22 and 23 are formed of different wiring layers. That is, the balanced transmission lines 22 and 23 are arranged on the same plane, and the unbalanced transmission line 21 and the balanced transmission lines 22 and 23 are arranged in different layers.
　なお、不平衡伝送線路２１と、平衡伝送線路２２及び２３とはどちらが上位配線層で形成されていても構わない。また、不平衡伝送線路２１と、平衡伝送線路２２及び２３との間に、それぞれが形成される配線層とは異なる配線層が存在していても構わない。また、その異なる配線層の数が１層以上であっても構わない。ただし、不平衡伝送線路２１と、平衡伝送線路２２及び２３との間に存在する異なる配線層には、不平衡伝送線路２１と平衡伝送線路２２及び２３との電磁界結合に影響を与える領域内に、伝送線路等の受動素子を形成しない。 Note that either the unbalanced transmission line 21 or the balanced transmission lines 22 and 23 may be formed of an upper wiring layer. Further, a wiring layer different from the wiring layer formed between the unbalanced transmission line 21 and the balanced transmission lines 22 and 23 may exist. The number of different wiring layers may be one or more. However, the different wiring layers existing between the unbalanced transmission line 21 and the balanced transmission lines 22 and 23 are within a region that affects electromagnetic coupling between the unbalanced transmission line 21 and the balanced transmission lines 22 and 23. In addition, a passive element such as a transmission line is not formed.
　また、図８に示したように、図９Ａ及び図９Ｂに示すマーチャントバランの出力端子１９及び２０の間にキャパシタが挿入されていても構わない。 Further, as shown in FIG. 8, a capacitor may be inserted between the output terminals 19 and 20 of the merchant balun shown in FIGS. 9A and 9B.
　図１０Ａは、図９Ａで示したマーチャントバランの構造の変形例を示す図である。不平衡伝送線路２１Ａ、２１Ｂ、平衡伝送線路２２及び２３はそれぞれ２つの伝送線路で構成される。不平衡伝送線路２１Ａを構成する２本の伝送線路と、平衡伝送線路２２を構成する２本の伝送線路とはそれぞれ、交互に配置される。また、不平衡伝送線路２１Ｂを構成する２本の伝送線路と平衡伝送線路２３を構成する２本の伝送線路とはそれぞれ、交互に配置される。 FIG. 10A is a diagram showing a modification of the structure of the merchant balun shown in FIG. 9A. The unbalanced transmission lines 21A and 21B and the balanced transmission lines 22 and 23 are each composed of two transmission lines. The two transmission lines constituting the unbalanced transmission line 21A and the two transmission lines constituting the balanced transmission line 22 are alternately arranged. Further, the two transmission lines constituting the unbalanced transmission line 21B and the two transmission lines constituting the balanced transmission line 23 are alternately arranged.
　不平衡伝送線路２１Ａを構成する２本の伝送線路は、入力端子１８側で接続され、不平衡伝送線路２１Ｂを構成する２本の伝送線路は、キャパシタ２４ａを介して接地される線路端４１側で接続される。不平衡伝送線路２１Ａを構成する２本の伝送線路の入力端子１８とは異なる２つの線路端と、不平衡伝送線路２１Ｂを構成する２本の伝送線路の線路端４１とは異なる２つの線路端との、合わせて４つの線路端は互いに接続される。平衡伝送線路２２を構成する２本の伝送線路は、キャパシタ２４ｂを介して接地される線路端４２側で接続される。平衡伝送線路２３を構成する２本の伝送線路は、キャパシタ２４ｃを介した接地される線路端４３側で接続される。平衡伝送線路２２を構成する２本の伝送線路の線路端４２とは異なる線路端は互いに接続されるとともに、出力端子１９に接続される。平衡伝送線路２３を構成する２本の伝送線路の線路端４３とは異なる線路端は互いに接続されるとともに、出力端子２０に接続される。 The two transmission lines constituting the unbalanced transmission line 21A are connected on the input terminal 18 side, and the two transmission lines constituting the unbalanced transmission line 21B are grounded via the capacitor 24a. Connected with. Two line ends different from the input terminals 18 of the two transmission lines constituting the unbalanced transmission line 21A and two line ends different from the line ends 41 of the two transmission lines constituting the unbalanced transmission line 21B In total, the four line ends are connected to each other. The two transmission lines constituting the balanced transmission line 22 are connected on the line end 42 side that is grounded via the capacitor 24b. The two transmission lines constituting the balanced transmission line 23 are connected on the line end 43 side that is grounded via the capacitor 24c. The line ends different from the line ends 42 of the two transmission lines constituting the balanced transmission line 22 are connected to each other and to the output terminal 19. The line ends different from the line ends 43 of the two transmission lines constituting the balanced transmission line 23 are connected to each other and to the output terminal 20.
　また、不平衡伝送線路２１Ａ、２１Ｂ、平衡伝送線路２２及び２３は同一平面上に形成される。出力端子１９及び２０に接続される配線と、不平衡伝送線路２１Ａ及び２１Ｂを接続する配線とは同一平面上に形成するのは困難であるため、必要に応じてブリッジ配線を使用しても構わない。 The unbalanced transmission lines 21A and 21B and the balanced transmission lines 22 and 23 are formed on the same plane. Since it is difficult to form the wiring connected to the output terminals 19 and 20 and the wiring connecting the unbalanced transmission lines 21A and 21B on the same plane, a bridge wiring may be used as necessary. Absent.
　図１０Ｂは、図１０Ａで示したマーチャントバランの構造の変形例を示す図である。この構造は、不平衡伝送線路２１Ａ及び２１Ｂと、平衡伝送線路２２及び２３とがそれぞれ２つの伝送線路で構成されるという点は、図１０Ａに示す構造と同じである。 FIG. 10B is a diagram showing a modification of the structure of the merchant balun shown in FIG. 10A. This structure is the same as the structure shown in FIG. 10A in that the unbalanced transmission lines 21A and 21B and the balanced transmission lines 22 and 23 are each composed of two transmission lines.
　図１０Ｂに示す構造では、不平衡伝送線路２１Ａ及び２１Ｂと、平衡伝送線路２２及び２３とは異なる配線層で形成される。なお、不平衡伝送線路２１Ａ及び２１Ｂと、平衡伝送線路２２及び２３とはどちらが上位配線層で形成されていても構わない。また、不平衡伝送線路２１Ａ及び２１Ｂと、平衡伝送線路２２及び２３との間にそれぞれが形成される配線層とは異なる配線層が存在していても構わない。また、その異なる配線層数が１層以上であっても構わない。ただし、不平衡伝送線路２１と、平衡伝送線路２２及び２３との間に存在する異なる配線層には、不平衡伝送線路２１と平衡伝送線路２２及び２３との電磁界結合に影響を与える領域内に、伝送線路等の受動素子を形成しない。 In the structure shown in FIG. 10B, the unbalanced transmission lines 21A and 21B and the balanced transmission lines 22 and 23 are formed of different wiring layers. Note that whichever of the unbalanced transmission lines 21A and 21B and the balanced transmission lines 22 and 23 may be formed of an upper wiring layer. Further, a wiring layer different from the wiring layer formed between the unbalanced transmission lines 21A and 21B and the balanced transmission lines 22 and 23 may exist. Further, the number of different wiring layers may be one or more. However, the different wiring layers existing between the unbalanced transmission line 21 and the balanced transmission lines 22 and 23 are within a region that affects electromagnetic coupling between the unbalanced transmission line 21 and the balanced transmission lines 22 and 23. In addition, a passive element such as a transmission line is not formed.
　また、図８に示したように、図１０Ａ及び図１０Ｂに示すマーチャントバランの出力端子１９及び２０の間にキャパシタが挿入されていても構わない。 Also, as shown in FIG. 8, a capacitor may be inserted between the output terminals 19 and 20 of the merchant balun shown in FIGS. 10A and 10B.
　図１１Ａは、図９Ａのマーチャントバランの構造の変形例を示す図である。図１１Ａに示すマーチャントバランでは、入力端子１８に不平衡伝送線路２６が接続され、不平衡伝送線路２６の入力端子１８と異なる側の線路端は、キャパシタ２４ｄを介して接地される。不平衡伝送線路２６が、入力端子１８を介して、電界効果トランジスタに接続される場合は、当該線路端は、キャパシタ２４ｄではなく、電源３４を介して接地しても構わない。また、不平衡伝送線路２６は、図９Ａで示したマーチャントバランの不平衡伝送線路２１と同じ長さである。 FIG. 11A is a diagram showing a modification of the structure of the merchant balun in FIG. 9A. In the merchant balun shown in FIG. 11A, the unbalanced transmission line 26 is connected to the input terminal 18, and the line end on the side different from the input terminal 18 of the unbalanced transmission line 26 is grounded via the capacitor 24d. When the unbalanced transmission line 26 is connected to the field effect transistor via the input terminal 18, the line end may be grounded via the power source 34 instead of the capacitor 24d. The unbalanced transmission line 26 has the same length as the unbalanced transmission line 21 of the merchant balun shown in FIG. 9A.
　また、差動出力端子１９及び２０には、平衡伝送線路２７が接続される。平衡伝送線路２７は、図９Ａで示したマーチャントバランの平衡伝送線路２２及び２３を円状に形成した構成である。また、平衡伝送線路２７は、平衡伝送線路２２及び２３の出力端子１９及び２０とは異なる側の線路端４２及び４３をそれぞれ接続した構成である。平衡伝送線路２７は、当該平衡伝送線路２７の中点から、キャパシタ２４ｅを介して接地される。また、平衡伝送線路２７が、出力端子１９及び２０を介して、電界効果トランジスタに接続される場合は、平衡伝送線路２７の中点は、キャパシタ２４ｅではなく、電源３４を介して接地しても構わない。また、平衡伝送線路２７の長さは、図９Ａで示したマーチャントバランの平衡伝送線路２２及び２３の合計長さと同じである。 Further, a balanced transmission line 27 is connected to the differential output terminals 19 and 20. The balanced transmission line 27 has a configuration in which the balanced transmission lines 22 and 23 of the merchant balun shown in FIG. 9A are formed in a circular shape. The balanced transmission line 27 is configured by connecting line ends 42 and 43 on the side different from the output terminals 19 and 20 of the balanced transmission lines 22 and 23, respectively. The balanced transmission line 27 is grounded through the capacitor 24e from the middle point of the balanced transmission line 27. When the balanced transmission line 27 is connected to the field effect transistor via the output terminals 19 and 20, the middle point of the balanced transmission line 27 may be grounded via the power source 34 instead of the capacitor 24e. I do not care. The length of the balanced transmission line 27 is the same as the total length of the balanced transmission lines 22 and 23 of the merchant balun shown in FIG. 9A.
　このように、マーチャントバランを円形状に構成することで、マーチャントバランのサイズを小さくすることが可能となる。また、図１１Ａに示すマーチャントバランの不平衡伝送線路２６と平衡伝送線路２７とは同一平面上に形成される。 As described above, by configuring the merchant balun into a circular shape, the size of the merchant balun can be reduced. Further, the unbalanced transmission line 26 and the balanced transmission line 27 of the merchant balun shown in FIG. 11A are formed on the same plane.
　図１１Ｂは、図１１Ａのマーチャントバランの構造の変形例を示す図である。図１１Ｂに示す構造では、不平衡伝送線路２６と平衡伝送線路２７とは異なる配線層で形成される。なお、不平衡伝送線路２６と平衡伝送線路２７とはどちらが上位配線層で形成されていても構わない。また、不平衡伝送線路２６と平衡伝送線路２７との間に、それぞれが形成される配線層とは異なる配線層が存在していても構わない。また、その異なる配線層数が１層以上であっても構わない。ただし、不平衡伝送線路２６と、平衡伝送線路２７との間に存在する異なる配線層には、不平衡伝送線路２６と平衡伝送線路２７との電磁界結合に影響を与える領域内に、伝送線路等の受動素子を形成しない。 FIG. 11B is a diagram showing a modification of the structure of the merchant balun in FIG. 11A. In the structure shown in FIG. 11B, the unbalanced transmission line 26 and the balanced transmission line 27 are formed of different wiring layers. Note that either the unbalanced transmission line 26 or the balanced transmission line 27 may be formed of an upper wiring layer. Further, a wiring layer different from the wiring layer formed between the unbalanced transmission line 26 and the balanced transmission line 27 may exist. Further, the number of different wiring layers may be one or more. However, the different wiring layers existing between the unbalanced transmission line 26 and the balanced transmission line 27 are provided in the transmission line within a region that affects electromagnetic coupling between the unbalanced transmission line 26 and the balanced transmission line 27. Do not form passive elements such as.
　また、図８に示したように、図１１Ａ及び図１１Ｂのマーチャントバランの出力端子１９及び２０の間にキャパシタが挿入されていても構わない。 Also, as shown in FIG. 8, a capacitor may be inserted between the output terminals 19 and 20 of the merchant balun in FIGS. 11A and 11B.
　なお、図１１Ａ及び図１１Ｂに示すように、円形状のマーチャントバランを用いるのではなく、円形状の一次配線及び二次配線を用いた、磁界結合によって、一次配線から二次配線に信号を伝搬するトランスフォーマーを用いても構わない。 As shown in FIGS. 11A and 11B, a signal is propagated from the primary wiring to the secondary wiring by magnetic coupling using the circular primary wiring and the secondary wiring, instead of using the circular shaped merchant balun. You may use a transformer.
　図１２は、半導体受信装置５０における変換利得のローカル信号パワー依存性のシミュレーション結果を示すグラフである。図１２には、図４に示す本実施形態に係る半導体受信装置５０の変換利得２８と、図１に示す比較例に係る半導体受信装置の変換利得２９とを示している。なお、図１では、バイポーラトランジスタが記載されているが、図１２に示すシミュレーション結果は、図４で示した本実施形態に係る半導体受信装置５０と同じく電界効果トランジスタを使用した場合の変換利得２９である。 FIG. 12 is a graph showing a simulation result of the dependence of the conversion gain on the local signal power in the semiconductor receiver 50. FIG. 12 shows the conversion gain 28 of the semiconductor receiver 50 according to the present embodiment shown in FIG. 4 and the conversion gain 29 of the semiconductor receiver according to the comparative example shown in FIG. Although FIG. 1 shows a bipolar transistor, the simulation result shown in FIG. 12 shows that the conversion gain 29 is obtained when a field effect transistor is used as in the semiconductor receiver 50 according to the present embodiment shown in FIG. It is.
　ここで言うローカル信号とは、半導体受信装置に含まれる直交復調器のギルバートセルミキサ構成の変調段を構成する電界効果トランジスタのゲート端子に入力される信号を指している。両半導体受信装置の変換利得２８及び２９はそれぞれ飽和特性を示すが、飽和状態において、本実施形態に係る半導体受信装置５０の変換利得２８が、比較例に係る半導体受信装置の変換利得２９に比べて、約８ｄＢ高い。 Here, the local signal refers to a signal input to the gate terminal of the field effect transistor that constitutes the modulation stage of the Gilbert cell mixer configuration of the quadrature demodulator included in the semiconductor receiver. Although the conversion gains 28 and 29 of both semiconductor receivers each exhibit saturation characteristics, in the saturated state, the conversion gain 28 of the semiconductor receiver 50 according to the present embodiment is compared with the conversion gain 29 of the semiconductor receiver according to the comparative example. About 8 dB higher.
　利得が向上した要因としては、マーチャントバラン９ａ及び９ｂにより変調器６と直交復調器１５とを整合接続したことが挙げられる。また、本実施形態では、変調器６及び直交復調器１５のギルバートセルミキサを形成するトランジスタ増幅段を除去して、当該トランジスタ増幅段を、受動素子であるマーチャントバランに置き換えている。これにより、変調器６の変調段３、及び直交復調器１５の変調段１０ａ及び１０ｂに含まれるそれぞれのトランジスタのドレイン－ソース間電圧を大きくすることができる。よって、これらのトランジスタのｇｍが大きくなるバイアス条件でトランジスタを動作させることができることも利得の向上の要因として挙げられる。 The reason why the gain is improved is that the modulator 6 and the quadrature demodulator 15 are matched and connected by the merchant baluns 9a and 9b. Further, in this embodiment, the transistor amplification stage forming the Gilbert cell mixer of the modulator 6 and the quadrature demodulator 15 is removed, and the transistor amplification stage is replaced with a merchant balun that is a passive element. Thereby, the drain-source voltage of each transistor included in the modulation stage 3 of the modulator 6 and the modulation stages 10a and 10b of the quadrature demodulator 15 can be increased. Therefore, the fact that the transistors can be operated under a bias condition in which the gm of these transistors is large is also cited as a factor for improving the gain.
　なお、本実施形態において、半導体受信装置５０を構成するトランジスタは、電界効果トランジスタでなく、バイポーラトランジスタ等の他のトランジスタでも構わない。 In the present embodiment, the transistors constituting the semiconductor receiver 50 may be other transistors such as bipolar transistors instead of field effect transistors.
　また、本実施形態において、半導体受信装置５０を含むＩＣを構成する半導体基板はＳｉ系半導体であっても、ＧａＡｓなどの化合物半導体であっても構わない。 In this embodiment, the semiconductor substrate constituting the IC including the semiconductor receiver 50 may be a Si-based semiconductor or a compound semiconductor such as GaAs.
　Ｓｉ系半導体上にマーチャントバランのような受動素子を形成する場合は、Ｓｉプロセス上に厚膜の誘電体層及び配線層を追加した厚膜再配線構造を使用することが好ましい。厚膜の誘電体層を追加することにより、導電性Ｓｉ基板の影響を抑制できる。またはＳｉプロセスのトップメタルをグランドプレーンにし、そのグランドプレーン上にマーチャントバランなどの受動素子を形成することで、Ｓｉ基板の影響を遮断することが可能となる。このように導電性Ｓｉ基板の影響を抑制、又は遮断することで、準ミリ波及びミリ波帯のような超高周波帯での受動素子の損失を低減することができる。さらに、配線層を厚膜にすることで、導体損も低減できる。また、上記では、厚膜再配線構造を例に挙げたが、高周波用途として、Ｓｉプロセス内での厚膜化も進んでいる。Ｓｉプロセス内のＳｉ基板から離れている上位の配線層で、本実施形態の半導体受信装置５０に含まれるマーチャントバランを形成しても構わない。 When forming a passive element such as a merchant balun on a Si-based semiconductor, it is preferable to use a thick film rewiring structure in which a thick dielectric layer and a wiring layer are added on the Si process. By adding a thick dielectric layer, the influence of the conductive Si substrate can be suppressed. Alternatively, it is possible to block the influence of the Si substrate by forming the top metal of the Si process as a ground plane and forming a passive element such as a merchant balun on the ground plane. In this way, by suppressing or blocking the influence of the conductive Si substrate, it is possible to reduce the loss of the passive element in the ultrahigh frequency band such as the quasi-millimeter wave and the millimeter wave band. Furthermore, conductor loss can be reduced by making the wiring layer thick. In the above description, the thick film rewiring structure is taken as an example. However, as a high frequency application, the thick film is being increased in the Si process. The merchant balun included in the semiconductor receiver 50 of this embodiment may be formed by an upper wiring layer that is distant from the Si substrate in the Si process.
　また、本実施形態において、厚膜再配線構造を用いる場合、厚膜誘電体の材料は、比誘電率及び誘電損失が低い材料であることが好ましい。本実施形態では、厚膜誘電体の材料としてＢＣＢ（ベンゾシクロブテン）を想定している。なお、ＢＣＢの代わりに、ポリイミド、テトラフルオロエチレン又はポリフェニレンオキシド等を用いても構わない。 In the present embodiment, when the thick film rewiring structure is used, the material of the thick film dielectric is preferably a material having a low relative dielectric constant and dielectric loss. In this embodiment, BCB (benzocyclobutene) is assumed as a material for the thick film dielectric. In place of BCB, polyimide, tetrafluoroethylene, polyphenylene oxide, or the like may be used.
　以上、本発明に係る半導体受信装置について、実施形態に基づいて説明したが、本発明は、これらの実施形態に限定されるものではない。本発明の趣旨を逸脱しない限り、当業者が思いつく各種変形を本実施形態に施したもの、あるいは異なる実施形態における構成要素を組み合わせて構築される形態も、本発明の範囲内に含まれる。 As mentioned above, although the semiconductor receiver concerning the present invention was explained based on the embodiment, the present invention is not limited to these embodiments. Unless it deviates from the meaning of this invention, the form which made | forms this embodiment the various deformation | transformation which those skilled in the art think, or the structure constructed | assembled combining the component in different embodiment is also contained in the scope of the present invention.
　また、今回開示された実施形態はすべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は上記した説明ではなくて請求の範囲によって示され、請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。 Further, it should be considered that the embodiment disclosed this time is illustrative and not restrictive in all respects. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
　また、上記実施形態に係る半導体受信装置は典型的には集積回路であるＬＳＩとして実現される。これらは個別に１チップ化されてもよいし、一部又は全てを含むように１チップ化されてもよい。 The semiconductor receiver according to the above embodiment is typically realized as an LSI that is an integrated circuit. These may be individually made into one chip, or may be made into one chip so as to include a part or all of them.
　また、上記斜視図等において、各構成要素の角部及び辺を直線的に記載しているが、製造上の理由により、角部及び辺が丸みをおびたものも本発明に含まれる。 In addition, in the above perspective view and the like, the corners and sides of each component are linearly described, but those having rounded corners and sides are also included in the present invention for manufacturing reasons.
　また、上記で用いた数字は、全て本発明を具体的に説明するために例示するものであり、本発明は例示された数字に制限されない。また、トランジスタ等のｎ型及びｐ型等は、本発明を具体的に説明するために例示するものであり、これらを反転させることで、同等の結果を得ることも可能である。また、上記で示した各構成要素の材料は、全て本発明を具体的に説明するために例示するものであり、本発明は例示された材料に制限されない。また、構成要素間の接続関係は、本発明を具体的に説明するために例示するものであり、本発明の機能を実現する接続関係はこれに限定されない。 Further, all the numbers used above are illustrated for specifically explaining the present invention, and the present invention is not limited to the illustrated numbers. In addition, n-type and p-type transistors and the like are illustrated to specifically describe the present invention, and it is possible to obtain equivalent results by inverting them. Further, the materials of the constituent elements shown above are all exemplified for specifically explaining the present invention, and the present invention is not limited to the exemplified materials. In addition, the connection relationship between the components is exemplified for specifically explaining the present invention, and the connection relationship for realizing the function of the present invention is not limited to this.
　また、ブロック図における機能ブロックの分割は一例であり、複数の機能ブロックを一つの機能ブロックとして実現したり、一つの機能ブロックを複数に分割したり、一部の機能を他の機能ブロックに移してもよい。 In addition, division of functional blocks in the block diagram is an example, and a plurality of functional blocks can be realized as one functional block, a single functional block can be divided into a plurality of functions, or some functions can be transferred to other functional blocks. May be.
　また、上記回路図に示す回路構成は、一例であり、本発明は上記回路構成に限定されない。つまり、上記回路構成と同様に、本発明の特徴的な機能を実現できる回路も本発明に含まれる。例えば、上記回路構成と同様の機能を実現できる範囲で、ある素子に対して、直列又は並列に、スイッチング素子（トランジスタ）、抵抗素子、又は容量素子等の素子を接続したものも本発明に含まれる。言い換えると、上記実施形態における「接続される」とは、２つの端子（ノード）が直接接続される場合に限定されるものではなく、同様の機能が実現できる範囲において、当該２つの端子（ノード）が、素子を介して接続される場合も含む。 The circuit configuration shown in the circuit diagram is an example, and the present invention is not limited to the circuit configuration. That is, like the above circuit configuration, a circuit that can realize a characteristic function of the present invention is also included in the present invention. For example, the present invention includes a device in which a device such as a switching device (transistor), a resistor, or a capacitor is connected in series or in parallel to a certain device within a range in which a function similar to the above circuit configuration can be realized. It is. In other words, “connected” in the above-described embodiment is not limited to the case where two terminals (nodes) are directly connected, and the two terminals (nodes) can be realized within a range in which a similar function can be realized. ) Is connected via an element.
　本発明は、半導体受信装置に適用できる。また、本発明は、各種通信機器又はレーダ等の高周波半導体装置に定起用できる。 The present invention can be applied to a semiconductor receiver. In addition, the present invention can be routinely used for various communication devices or high-frequency semiconductor devices such as radar.
　１、７、８、１８、１０１、１０２、１０６、１０７　入力端子
　２、９ａ、９ｂ　バラン
　３、１０ａ、１０ｂ　変調段
　４、５、１１、１２、１３、１４、１９、２０、１０３、１０４、１０８、１０９、１１０、１１１　出力端子
　６、１０５　変調器
　１５、１１２　直交復調器
　１６、１７　整合伝送線路
　２１、２１Ａ、２１Ｂ、２６　不平衡伝送線路
　２２、２３、２７　平衡伝送線路
　２４ａ、２４ｂ、２４ｃ、２４ｄ、２４ｅ、２５　キャパシタ
　２８、２９　変換利得
　３１、３２ａ、３２ｂ　電流源
　３３ａ、３３ｂ　ミキサ
　３４　電源
　３５ａ、３５ｂ、４１、４２、４３　線路端
　５０　半導体受信装置
　１１３、１１４　インピーダンスマッチング回路
　Ｒ１、Ｒ２　負荷抵抗
　Ｔｒ１、Ｔｒ２、Ｔｒ３、Ｔｒ４、Ｔｒ５、Ｔｒ６、Ｔｒ７、Ｔｒ８、Ｔｒ９、Ｔｒ１０、Ｔｒ１１、Ｔｒ１２、Ｔｒ１０１、Ｔｒ１０２、Ｔｒ１０３、Ｔｒ１０４、Ｔｒ１０５、Ｔｒ１０６、Ｔｒ１０７、Ｔｒ１０８、Ｔｒ１０９、Ｔｒ１１０、Ｔｒ１１１、Ｔｒ１１２、Ｔｒ１１３、Ｔｒ１１４、Ｔｒ１１５、Ｔｒ１１６、Ｔｒ１１７、Ｔｒ１１８　トランジスタ 1, 7, 8, 18, 101, 102, 106, 107 Input terminal 2, 9a, 9b Balun 3, 10a, 10b Modulation stage 4, 5, 11, 12, 13, 14, 19, 20, 103, 104, 108, 109, 110, 111 Output terminal 6, 105 Modulator 15, 112 Quadrature demodulator 16, 17 Matched transmission line 21, 21A, 21B, 26 Unbalanced transmission line 22, 23, 27 Balanced transmission line 24a, 24b, 24c 24d, 24e, 25 Capacitor 28, 29 Conversion gain 31, 32a, 32b Current source 33a, 33b Mixer 34 Power supply 35a, 35b, 41, 42, 43 Line end 50 Semiconductor receiver 113, 114 Impedance matching circuit R1, R2 Load Resistors Tr1, Tr2, Tr3, Tr4, Tr5, Tr6, Tr7, Tr8, Tr9, T 10, Tr11, Tr12, Tr101, Tr102, Tr103, Tr104, Tr105, Tr106, Tr107, Tr108, Tr109, Tr110, Tr111, Tr112, Tr113, Tr114, Tr115, Tr116, Tr117, Tr118 transistor

Claims (6)

  1. 　入力信号を、互いに１８０°の位相差を有する第１及び第２の変調信号に変換する第１のミキサと、
    　前記第１及び第２の変調信号を、０°、９０°、１８０°及び２７０°の位相差を有する第１～第４の出力信号に変換する第２及び第３のミキサと、
    　第１及び第２の伝送線路とを備え、
    　前記第１、第２及び第３のミキサの各々は、
    　第１～第３の端子と、
    　第１～第４のトランジスタを備えるギルバートセルミキサ構成の変調段と、
    　第５及び第６のトランジスタを備える定電流源と、
    　一方の線路端が前記第１の端子に接続されている不平衡伝送線路と、第１及び第２の平衡伝送線路と、第１及び第２の接地キャパシタとを備える不平衡平衡変換器とを備え、
    　前記第１の平衡伝送線路の一方の線路端は、前記第１の接地キャパシタ及び前記第５のトランジスタのドレイン端子と接続されており、他方の線路端は前記第１及び第２のトランジスタのソース端子と接続されており、
    　前記第２の平衡伝送線路の一方の線路端は、前記第２の接地キャパシタ及び前記第６のトランジスタのドレイン端子と接続されており、他方の線路端は前記第３及び第４のトランジスタのソース端子と接続されており、
    　前記第１及び第３のトランジスタのドレイン端子は、前記第２の端子に接続されており、
    　前記第２及び第４のトランジスタのドレイン端子は、前記第３の端子に接続されており、
    　前記第１のミキサの前記第１の端子には前記入力信号が入力され、前記第１のミキサの前記第２及び第３の端子に前記第１及び第２の変調信号が出力され、
    　前記第２のミキサの前記第１の端子は、前記第１の伝送線路を介して、前記第１のミキサの前記第２の端子に接続されており、前記第２のミキサの前記第２及び第３の端子には、前記第１及び第３の出力信号が出力され、
    　前記第３のミキサの前記第１の端子は、前記第２の伝送線路を介して、前記第１のミキサの前記第３の端子に接続されており、前記第３のミキサの前記第２及び第３の端子には、前記第２及び第４の出力信号が出力される
    　半導体受信装置。     A first mixer for converting an input signal into first and second modulated signals having a phase difference of 180 ° from each other;
    Second and third mixers for converting the first and second modulation signals into first to fourth output signals having phase differences of 0 °, 90 °, 180 ° and 270 °;
    A first transmission line and a second transmission line;
    Each of the first, second and third mixers is
    First to third terminals;
    A modulation stage having a Gilbert cell mixer configuration comprising first to fourth transistors;
    A constant current source comprising fifth and sixth transistors;
    An unbalanced balanced converter comprising an unbalanced transmission line having one line end connected to the first terminal, first and second balanced transmission lines, and first and second grounded capacitors. Prepared,
    One line end of the first balanced transmission line is connected to the first grounded capacitor and the drain terminal of the fifth transistor, and the other line end is the source of the first and second transistors. Connected to the terminal,
    One line end of the second balanced transmission line is connected to the second grounded capacitor and the drain terminal of the sixth transistor, and the other line end is the source of the third and fourth transistors. Connected to the terminal,
    The drain terminals of the first and third transistors are connected to the second terminal,
    The drain terminals of the second and fourth transistors are connected to the third terminal,
    The input signal is input to the first terminal of the first mixer, and the first and second modulation signals are output to the second and third terminals of the first mixer,
    The first terminal of the second mixer is connected to the second terminal of the first mixer via the first transmission line, and the second and second terminals of the second mixer are connected to each other. The first and third output signals are output to a third terminal,
    The first terminal of the third mixer is connected to the third terminal of the first mixer via the second transmission line, and the second and third terminals of the third mixer are connected to each other. The semiconductor receiving device, wherein the second and fourth output signals are output to a third terminal.
  2. 　前記第２のミキサが備える前記不平衡伝送線路の他方の線路端と、前記第３のミキサが備える前記不平衡伝送線路の他方の線路端とは接続されており、当該２つの他方の線路端は、当該２つの他方の線路端から等距離の地点で電源を介して接地されている
    　請求項１記載の半導体受信装置。     The other line end of the unbalanced transmission line included in the second mixer is connected to the other line end of the unbalanced transmission line included in the third mixer, and the other two line ends. The semiconductor receiver according to claim 1, which is grounded via a power source at a point equidistant from the two other line ends.
  3. 　前記第２及び第３のミキサの各々において、前記第１及び第４のトランジスタのゲート端子は互いに接続されており、前記第２及び第３のトランジスタのゲート端子は互いに接続されており、
    　前記第２及び第３のミキサの各々は、さらに、
    　前記第１及び第３のトランジスタのドレイン端子に接続されている第１の抵抗素子と、
    　前記第２及び第４のトランジスタのドレイン端子に接続されている第２の抵抗素子とを備える
    　請求項１又は２記載の半導体受信装置。     In each of the second and third mixers, the gate terminals of the first and fourth transistors are connected to each other, and the gate terminals of the second and third transistors are connected to each other,
    Each of the second and third mixers further includes:
    A first resistance element connected to the drain terminals of the first and third transistors;
    The semiconductor receiving device according to claim 1, further comprising: a second resistance element connected to drain terminals of the second and fourth transistors.
  4. 　前記不平衡平衡変換器は、さらに、前記第１の平衡伝送線路の前記他方の線路端と、前記第２の平衡伝送線路の前記他方の線路端との間に接続されているキャパシタを備える
    　請求項１～３のいずれか１項に記載の半導体受信装置。     The unbalanced balanced converter further includes a capacitor connected between the other line end of the first balanced transmission line and the other line end of the second balanced transmission line. Item 4. The semiconductor receiver according to any one of Items 1 to 3.
  5. 　前記第１の平衡伝送線路と、前記第２の平衡伝送線路と、前記不平衡伝送線路とは同一平面上に配置されている
    　請求項１～４のいずれか１項に記載の半導体受信装置。     The semiconductor receiver according to any one of claims 1 to 4, wherein the first balanced transmission line, the second balanced transmission line, and the unbalanced transmission line are arranged on the same plane.
  6. 　前記第１の平衡伝送線路と前記第２の平衡伝送線路とは同一平面上に配置されており、
    　前記不平衡伝送線路は、前記第１及び第２の平衡伝送線路とは異なる層に配置されている
    　請求項１～４のいずれか１項に記載の半導体受信装置。     The first balanced transmission line and the second balanced transmission line are arranged on the same plane,
    The semiconductor receiver according to any one of claims 1 to 4, wherein the unbalanced transmission line is arranged in a different layer from the first and second balanced transmission lines.
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