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WO2013047457A1 - Method for manufacturing display device, and display device - Google Patents

Method for manufacturing display device, and display device Download PDF

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Publication number
WO2013047457A1
WO2013047457A1 PCT/JP2012/074437 JP2012074437W WO2013047457A1 WO 2013047457 A1 WO2013047457 A1 WO 2013047457A1 JP 2012074437 W JP2012074437 W JP 2012074437W WO 2013047457 A1 WO2013047457 A1 WO 2013047457A1
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WO
WIPO (PCT)
Prior art keywords
transparent electrode
layer
electrode layer
sub
ito
Prior art date
Application number
PCT/JP2012/074437
Other languages
French (fr)
Japanese (ja)
Inventor
庄治 岡崎
通 園田
宏充 勝井
哲憲 田中
Original Assignee
シャープ株式会社
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Publication of WO2013047457A1 publication Critical patent/WO2013047457A1/en

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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/621Providing a shape to conductive layers, e.g. patterning or selective deposition
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00Constructional details relating to the organic devices covered by this subclass
    • H10K2102/10Transparent electrodes, e.g. using graphene
    • H10K2102/101Transparent electrodes, e.g. using graphene comprising transparent conductive oxides [TCO]
    • H10K2102/103Transparent electrodes, e.g. using graphene comprising transparent conductive oxides [TCO] comprising indium oxides, e.g. ITO

Definitions

  • the present invention relates to a method for manufacturing a display device in which a transparent electrode layer is laminated on a reflective electrode layer in each sub-pixel, and the total film thickness of the transparent electrode layer is different between sub-pixels having different display colors, and It is related with such a display apparatus.
  • flat panel displays have been used in various products and fields, and further flat panel displays are required to have larger sizes, higher image quality, and lower power consumption.
  • an organic EL display device including an organic EL element using electroluminescence of an organic material (Electro-Luminescence: hereinafter referred to as “EL”) is an all-solid-state type, driven at a low voltage, As a flat panel display excellent in terms of high-speed response, self-luminous property, wide viewing angle characteristics, etc., it is attracting a lot of attention.
  • An organic EL display device has, for example, a configuration in which an organic EL element electrically connected to a TFT is provided on a substrate made of a glass substrate provided with a TFT (Thin Film Transistor). .
  • the organic EL element is a light-emitting element that can emit light with high luminance by low-voltage direct current drive, and has a structure in which a first electrode, an organic EL layer, and a second electrode are stacked in this order.
  • an organic EL element that emits red (R), green (G), and blue (B) is used as a sub-color.
  • R red
  • G green
  • B blue
  • a method of arranging pixels on a substrate and (2) a method of selecting a light emission color in each sub-pixel by combining a white light emitting organic EL element and a color filter are known.
  • the microcavity is a phenomenon in which emitted light undergoes multiple reflections between the anode and the cathode and resonates, resulting in a steep emission spectrum and amplification of the emission intensity at the peak wavelength.
  • the microcavity effect can be obtained, for example, by optimally designing the reflectance and film thickness of the anode and cathode, the layer thickness of the organic layer, and the like.
  • a method of laminating an organic EL layer including a light emitting layer and a transparent electrode layer between a reflective electrode and a semitransparent electrode can be mentioned.
  • the anode has a laminated structure of a reflective electrode layer and a transparent electrode layer, and the film thickness of the transparent electrode layer on the reflective electrode layer of the anode is changed for each subpixel.
  • a method is mentioned.
  • the anode has a laminated structure of a reflective electrode layer and a transparent electrode layer as described above, and after the organic EL layer is appropriately laminated, the cathode is made into a thin film, for example, as a semitransparent electrode.
  • a microcavity structure can be introduced into the organic EL element.
  • the spectrum of light emitted from the light emitting layer and emitted through the cathode becomes steeper than when the organic EL element does not have the microcavity structure.
  • the intensity of light emitted to the front is greatly increased.
  • Patent Documents 1 and 2 disclose an organic EL display device in which a microcavity structure is introduced into an organic EL element by laminating transparent electrode layers of the same material while changing the number of laminated layers for each sub-pixel.
  • the film thickness of the transparent electrode layer is appropriately set for each sub-pixel of each color.
  • the method of changing to is not known so far.
  • Patent Document 1 does not disclose a method for changing the film thickness of the transparent electrode for each sub-pixel of each color.
  • Patent Document 2 discloses the following method as a method of changing the film thickness of the transparent electrode for each sub-pixel of each color using the same material for the transparent electrode layer to be laminated.
  • transparent electrode layers and resist patterns are alternately laminated on the reflective electrode layer while changing the subpixels on which the resist pattern is laminated in the order of B ⁇ G ⁇ R.
  • the uppermost transparent electrode layer is etched using the resist pattern of the R subpixel as a mask, and when the resist pattern of the G subpixel is exposed, Using the resist pattern of the subpixel as a mask, the second transparent electrode layer from the top is etched.
  • all the transparent electrode layers are patterned by etching the transparent electrode layer of the lowermost layer using the resist pattern of the R, G, and B sub-pixels as a mask. To do.
  • the reflective electrode layer is etched and patterned using the resist pattern of the R, G, and B subpixels as a mask.
  • Patent Document 2 since the transparent electrode layer is laminated on the resist pattern, if the adhesiveness between the resist and the transparent electrode layer is not sufficient, film peeling of the transparent electrode layer occurs during the processing, resulting in a pattern defect or a process. There is a risk of contamination.
  • the following method can be considered.
  • FIGS. 13A to 13F are cross-sectional views showing an example of a method for changing the film thickness of the transparent electrode layer on the reflective electrode layer of the anode for each sub-pixel in the order of steps.
  • a reflective electrode layer 302 made of a reflective electrode material such as silver (Ag) is formed on a support substrate 301 by a sputtering method or the like.
  • a resist pattern (not shown) is formed by photolithography on each of the sub-pixels of each color on the reflective electrode layer 302. After etching the reflective electrode layer 302 using the resist pattern as a mask, the resist pattern is removed from the resist. Remove and clean with liquid.
  • the reflective electrode layer 302 is patterned so as to be separated for each sub-pixel of each color.
  • an IZO (Indium Zinc Oxide) film is formed as a transparent electrode layer to form an IZO layer 303.
  • a photoresist 311 is formed only on the R subpixel by lithography.
  • the exposed IZO layer 303 is removed by etching with oxalic acid, and then the photoresist 311 is peeled off, so that only the first sub-pixel of the R is removed.
  • a patterned IZO layer 303 is formed as the IZO layer.
  • an IZO film is formed again so as to cover the IZO layer 303 of the R subpixel and the reflective electrode layer 302 of the G and B subpixels, and the IZO layer 304 is formed. Further, a photoresist 312 is formed only on the R and G subpixels by photolithography.
  • the IZO layer 304 is etched with oxalic acid using the photoresist 312 as a mask, and the photoresist 312 is peeled off to form a second IZO layer on the sub-pixels R and G. Then, a patterned IZO layer 304 is formed.
  • the number of transparent electrode layers stacked is changed for each sub-pixel, for example, when the sub-pixel is composed of R, G, and B sub-pixels, at least three photo Lithography, etching, and resist stripping are required.
  • photolithography is required three times. . Including the patterning of the reflective electrode layer, photolithography is required four times. Further, in FIG. 13F, when a transparent electrode layer is further formed on the B pixel, photolithography is required once more.
  • the transparent electrode layer of the same material is used and the thickness of the electrode is changed for each sub-pixel, at least three times (photolithography for patterning of the reflective electrode layer). If this is included, an apparatus for performing photolithography, etching, and resist stripping at least four times is required. For this reason, the number of photolithography apparatuses (photo process apparatuses) for performing the above-described processing required in the production line increases.
  • Photolithography requires expensive equipment and materials. Therefore, if the thickness of the electrode is changed for each sub-pixel as described above, it leads to an increase in the cost of the entire device and an increase in footprint.
  • the reflective electrode layer is in an exposed state (that is, an exposed state), for example, if it is irradiated with ultraviolet rays in order to improve the wettability of the resist, it will oxidize and the reflection characteristics will decrease. Or the solvent resistance is low and the solvent may penetrate. For this reason, when such a reflective electrode layer consists of such a reflective electrode material, it is not desirable that the reflective electrode layer is exposed.
  • Patent Document 3 ITO having different crystallinity is laminated to form a patterned ITO on the patterned reflective electrode layer and patterned, and then amorphous ITO is laminated.
  • a method of changing the film thickness of the transparent electrode layer for each sub-pixel by photolithography twice is disclosed. That is, in Patent Document 3, if the patterning of the reflective electrode layer is included, the number of times of photolithography is three.
  • Patent Document 3 an ITO having crystallinity is formed and patterned on the first and third subpixels, and then amorphous ITO is stacked on the first subpixel and the second subpixel. Thus, the film thickness of the transparent electrode layer is changed for each sub-pixel by patterning.
  • Patent Document 3 a transparent electrode layer pattern having the same film thickness is formed on two sub-pixels each time photolithography is performed, and the sub-pixel that forms the transparent electrode layer pattern is changed for each photolithography. The number of lithography is reduced, and for this purpose, the ITO having crystallinity is etched to form a pattern of transparent electrode layers having the same film thickness on the two sub-pixels.
  • the present invention has been made in view of the above problems, and an object of the present invention is to provide a transparent electrode layer on a reflective electrode layer in each sub-pixel, and a reflective electrode between sub-pixels having different display colors.
  • an object of the present invention is to provide a transparent electrode layer on a reflective electrode layer in each sub-pixel, and a reflective electrode between sub-pixels having different display colors.
  • the number of times of photolithography is reduced.
  • a further object of the present invention is to provide a display device in which the transparent electrode layer has a different film thickness for each sub-pixel having a different display color and can be manufactured by a practical method.
  • a manufacturing method of a display device includes a reflective electrode layer and a reflective electrode layer on one electrode of a pair of electrodes that form an electric field in each subpixel.
  • a plurality of transparent electrode layers are formed on the reflective electrode layer in at least one sub-pixel, and the transparent electrode layer is formed between sub-pixels having different display colors.
  • Transparent electrode layer crystallization step, and transparent electrode material having lower etching resistance than first transparent electrode layer made of polycrystalline transparent electrode material on first transparent electrode layer made of polycrystalline transparent electrode material And a second transparent electrode layer stacking step of selectively etching and patterning the second transparent electrode layer by photolithography.
  • the first transparent electrode layer made of an amorphous transparent electrode material is formed above the reflective electrode layer, and the reflective electrode layer and the amorphous transparent electrode material are formed.
  • the first transparent electrode layer made of the polycrystalline transparent electrode material is formed on the reflective electrode layer without increasing the number of times of photolithography by collectively etching the first transparent electrode layer made of Can be stacked.
  • the first transparent electrode layer made of the amorphous transparent electrode material is converted into the first transparent electrode layer made of the polycrystalline transparent electrode material, and the film is formed thereon.
  • a transparent electrode layer is laminated
  • the first transparent electrode layer made of a polycrystalline transparent electrode material having a higher etching resistance than the second transparent electrode layer is formed below the second transparent electrode layer.
  • the lower first transparent electrode layer is not etched when the upper second transparent electrode layer is etched.
  • the first transparent electrode layer made of the polycrystalline transparent electrode material is laminated on each sub-pixel before the second transparent electrode layer is formed.
  • the second transparent electrode layer can be laminated on any subpixel.
  • the transparent electrode layer is formed on the reflective electrode layer of each subpixel, and photolithography necessary for changing the total film thickness of the transparent electrode layer in each subpixel.
  • the total film thickness of the transparent electrode layer can be arbitrarily changed for each sub-pixel by performing photolithography twice.
  • count of photolithography can be restrained to 3 times also including the etching of a reflective electrode layer.
  • the film thickness of the second transparent electrode layer in an arbitrary subpixel is set to the second transparent electrode in another subpixel. It can be set independently of the film thickness of the layer.
  • an ITO layer having crystallinity is separately formed and patterned in order to stack the transparent electrode layers, and the pattern of the transparent electrode layer having the same film thickness is formed on two sub-pixels every time photolithography is performed. Even if the transparent electrode layer is not formed, a transparent electrode layer is formed on the reflective electrode layer of each sub-pixel in two photolithography, and the transparent electrode layer on the reflective electrode layer is different for each sub-pixel having a different display color. Electrodes with different total film thicknesses can be formed.
  • the optical path length in each sub-pixel can be arbitrarily and easily adjusted without being restricted by the optical path length as in Patent Document 3. Therefore, according to the above method, the film thickness of the transparent electrode layer on the reflective electrode layer can be arbitrarily changed for each sub-pixel having a different display color by a smaller number of photolithography than the conventional method.
  • the cost can be reduced and the footprint can be reduced as compared with the conventional case.
  • the number of times of exposure, development, resist stripping and the like can be reduced, so there is no such fear. Further, the processing tact can be shortened.
  • the reflective electrode layer is in an exposed state (that is, an exposed state), for example, if it is irradiated with ultraviolet rays in order to improve the wettability of the resist, it will oxidize and the reflection characteristics will decrease. Or the solvent resistance is low and the solvent may penetrate. For this reason, when such a reflective electrode layer consists of such a reflective electrode material, it is not desirable that the reflective electrode layer is exposed.
  • the polycrystalline transparent electrode layer is formed on the reflective electrode layer in each sub-pixel as described above at an early stage in the manufacturing process. It can protect from the said factor which may impair the quality of a reflective electrode layer.
  • Patent Document 3 after patterning the reflective electrode layer, the first and third sub-pixels are formed and patterned with crystalline ITO.
  • Crystalline ITO has high solubility in the etching solution used for etching the reflective electrode layer. For this reason, when an ITO layer having crystallinity is directly formed on the reflective electrode layer and patterned by photolithography, the reflective electrode layer may not be tapered.
  • the first transparent electrode layer made of an amorphous transparent electrode material, patterning the reflective electrode layer together, and then converting it to a polycrystalline transparent electrode layer, Such a problem does not occur.
  • the transparent electrode layer is laminated on the reflective electrode layer in each subpixel, and the film thickness of the transparent electrode layer on the reflective electrode layer is changed between the subpixels having different display colors.
  • the number of times of photolithography can be reduced.
  • one of the pair of electrodes that form an electric field in each subpixel has a reflective electrode layer and the reflective electrode layer on the reflective electrode layer. At least one transparent electrode layer formed, and a plurality of the transparent electrode layers are formed on the reflective electrode layer in at least one sub-pixel, and the transparent electrode layer is formed between sub-pixels having different display colors. It is a display device with different overall film thickness, wherein the plurality of transparent electrode layers have different compositions, and the etching resistance of the lower transparent electrode layer is higher than the etching resistance of the upper transparent electrode layer. It is a feature.
  • Such a display device etches the lower transparent electrode layer and the upper transparent electrode layer without converting the transparent electrode layer made of the amorphous transparent electrode material into the transparent electrode layer made of the polycrystalline transparent electrode material.
  • the transparent electrode layers can be stacked using the difference in etching selectivity due to the difference in resistance.
  • the optical path length in each sub-pixel can be arbitrarily and easily adjusted with a short processing tact as compared with the case where transparent electrode layers made of the same transparent electrode material are stacked as in the prior art.
  • the present invention it is possible to provide a display device that can be manufactured by a practical method while the thickness of the transparent electrode layer is different for each sub-pixel having a different display color.
  • the first transparent electrode layer made of an amorphous transparent electrode material is formed above the reflective electrode layer, and the reflective electrode layer and the non-reflective electrode layer are formed.
  • the first transparent electrode layer made of a crystalline transparent electrode material is etched together.
  • the first transparent electrode layer made of the polycrystalline transparent electrode material can be laminated on the reflective electrode layer without increasing the number of times of photolithography.
  • the first transparent electrode layer made of an amorphous transparent electrode material is converted into a first transparent electrode layer made of a polycrystalline transparent electrode material, and the first transparent electrode layer is formed thereon.
  • a transparent electrode layer is laminated
  • the first transparent electrode made of a polycrystalline transparent electrode material which has a higher etching resistance than the second transparent electrode layer, is formed below the second transparent electrode layer.
  • the lower first transparent electrode layer is not etched when the upper second transparent electrode layer is etched.
  • the first transparent electrode layer made of the polycrystalline transparent electrode material is laminated on each sub-pixel before the second transparent electrode layer is formed.
  • the second transparent electrode layer can be laminated on any sub-pixel.
  • the transparent electrode layer is formed on the reflective electrode layer of each sub-pixel, and the photo required for changing the total film thickness of the transparent electrode layer in each sub-pixel.
  • the total film thickness of the transparent electrode layer can be arbitrarily changed for each sub-pixel by photolithography.
  • count of photolithography can be restrained to 3 times also including the etching of a reflective electrode layer.
  • the film thickness of the second transparent electrode layer in an arbitrary subpixel is set to the second transparent electrode in another subpixel. It can be set independently of the film thickness of the electrode layer.
  • the optical path length in each sub-pixel can be arbitrarily and easily adjusted without being restricted by the optical path length as in Patent Document 3. Therefore, according to said manufacturing method, the film thickness of the transparent electrode layer on a reflective electrode layer can be arbitrarily changed for every sub pixel from which a display color differs by the photolithography of the frequency
  • the display device includes a plurality of transparent electrode layers on the reflective electrode layer, and the total film thickness of the transparent electrode layer is different for each sub-pixel having a different display color.
  • the plurality of transparent electrode layers have different compositions, and the etching resistance of the lower transparent electrode layer is higher than the etching resistance of the upper transparent electrode layer.
  • Such a display device etches the lower transparent electrode layer and the upper transparent electrode layer without converting the transparent electrode layer made of the amorphous transparent electrode material into the transparent electrode layer made of the polycrystalline transparent electrode material.
  • the transparent electrode layers can be stacked using the difference in etching selectivity due to the difference in resistance.
  • the optical path length in each sub-pixel can be arbitrarily and easily adjusted with a short processing tact as compared with the case where transparent electrode layers made of the same transparent electrode material are stacked as in the prior art.
  • the present invention it is possible to provide a display device that can be manufactured by a practical method while the thickness of the transparent electrode layer is different for each sub-pixel having a different display color.
  • FIG. 1 is an exploded cross-sectional view illustrating a schematic configuration of a main part of an organic EL display device according to a first embodiment.
  • 3 is a plan view showing a schematic configuration of a support substrate in the organic EL display device according to Embodiment 1.
  • FIG. It is a top view which shows the structure of the principal part of the display area in the support substrate shown in FIG.
  • FIG. 5 is a cross-sectional view showing a schematic configuration of the organic EL display panel when the organic EL display panel according to the first embodiment is cut along line AA shown in FIG.
  • FIG. 1 is an exploded cross-sectional view illustrating a schematic configuration of a main part of an organic EL display device according to a first embodiment.
  • 3 is a plan view showing a schematic configuration of a support substrate in the organic EL display device according to Embodiment 1.
  • FIG. It is a top view which shows the structure of the principal part of the display area in the support substrate shown in FIG.
  • FIG. 5 is
  • 3 is a schematic diagram illustrating an image display method of the organic EL display device according to the first embodiment.
  • 3 is a flowchart illustrating an example of a manufacturing process of the organic EL display device according to the first embodiment in the order of processes.
  • 3 is a flowchart illustrating an example of a manufacturing process of the organic EL layer according to the first embodiment in order of processes.
  • (A) * (b) is a figure which shows typically schematic structure of a 1st electrode when producing an edge cover on the 1st electrode shown to (i) of FIG. 1, (a) is sectional drawing.
  • (B) is a plan view.
  • FIG. 5 is a cross-sectional view illustrating a schematic configuration of an organic EL display panel according to a third embodiment. It is a flowchart which shows an example of the manufacturing process of the organic electroluminescent layer shown in FIG. (A)-(f) is sectional drawing which shows an example of the method of changing the total film thickness of the transparent electrode layer on the reflective electrode layer of an anode for every sub pixel in order of a process.
  • FIG. 2 is an exploded sectional view showing a schematic configuration of a main part of the organic EL display device 100 according to the present embodiment.
  • the organic EL display device 100 includes a pixel unit 101 and a circuit unit 102.
  • the pixel unit 101 is composed of an organic EL display panel 1 (display panel).
  • the circuit unit 102 includes a circuit board provided with a drive circuit for driving the organic EL display device 100, an IC (Integrated Circuits) chip, and the like.
  • the organic EL display panel 1 has a configuration in which an organic EL element 20, a sealing resin layer 41, a filling resin layer 42, and a sealing substrate 50 are provided in this order on a support substrate 10 (deposition substrate, TFT substrate). have.
  • the support substrate 10 is made of a semiconductor substrate such as a TFT substrate.
  • the support substrate 10 has a structure in which a thin film transistor (TFT) 12 (see FIG. 5) is provided as an active element (drive element) on an insulating substrate 11.
  • TFT thin film transistor
  • the organic EL element 20 is connected to the TFT 12. On the organic EL element 20, a filling resin layer 42 having adhesiveness containing a desiccant is formed. The filling resin constituting the filling resin layer 42 is filled in a space surrounded by the support substrate 10, the sealing substrate 50, and the sealing resin layer 41.
  • the organic EL display device 100 may be a bottom emission type that emits light from the support substrate 10 side, or a top emission type that emits light from the sealing substrate 50 side.
  • the base substrate used for the support substrate 10 and the sealing substrate 50 for example, glass or plastic can be used.
  • a glass substrate such as an alkali-free glass substrate can be used.
  • the present invention is not limited to this, and an opaque material such as a metal plate can also be used as the substrate on the side that does not emit light.
  • a substrate on which a CF (Color Filter) layer is formed may be used as the sealing substrate 50.
  • a CF layer may be formed on the support substrate 10 side.
  • the spectrum of the light emitted from the organic EL element 20 can be adjusted by the CF layer.
  • the organic EL display device 100 is a top emission type
  • the present embodiment is not limited to this, and may be, for example, a bottom emission type as described above.
  • the sealing substrate 50 is provided with, for example, a CF layer 52, a BM (Black-Matrix) 53 (see FIG. 5), and the like on an insulating substrate 51. It has a configuration.
  • the organic EL element 20 includes a sealing resin layer provided in a frame-shaped sealing region L with the support substrate 10 on which the organic EL element 20 is laminated so that the organic EL element 20 is not damaged by moisture or oxygen.
  • the sealing substrate 50 is sealed between the pair of substrates (the support substrate 10 and the sealing substrate 50).
  • the organic EL element 20 is sealed between the support substrate 10 and the sealing substrate 50 as described above, thereby preventing oxygen and moisture from entering the organic EL element 20 from the outside. Has been.
  • a terminal portion region R3 in which the electrical wiring terminals 2 (electric connection portions, connection terminals) and the like are formed is provided outside the frame-shaped sealing region L in the support substrate 10.
  • the electrical wiring terminal 2 is a connection terminal to which the connection terminal 103 of the circuit unit 102 is connected, and is formed of a wiring material such as metal.
  • the circuit unit 102 is provided with wiring such as a flexible film cable, a drive circuit such as a driver, and the like.
  • the circuit unit 102 is connected to the organic EL display panel 1 through an electrical wiring terminal 2 provided in the terminal region R3.
  • FIG. 3 is a plan view showing a schematic configuration of the support substrate 10 in the organic EL display device 100.
  • a display region R1 As shown in FIG. 3, on one main surface which is an active surface (active element formation surface) of the support substrate 10, a display region R1, a second electrode connection region R2, a terminal region R3, and a frame-shaped seal are formed.
  • a stop region L is provided on one main surface which is an active surface (active element formation surface) of the support substrate 10.
  • the display region R1 (display unit) is provided at the center of the support substrate 10, and is formed in a rectangular shape, for example.
  • a pixel array including a plurality of sub-pixels 71 (see FIGS. 4 and 5) is formed.
  • the configuration of the display area R1 will be described in detail later.
  • the second electrode connection region R2 is a region to which the second electrode 31 (see FIG. 5) in the organic EL element 20 is connected.
  • the second electrode connection region R2 is formed on the outer side of the pair of sides of the pair of the display regions R1 and along the opposite sides.
  • connection portions 60 are formed in the second electrode connection regions R2.
  • the connection part 60 is a part to which the second electrode 31 is connected, and is formed of a metal material.
  • the sealing region L is formed in a frame shape so as to surround the display region R1 and the second electrode connection region R2.
  • the terminal portion region R3 is a region used for connection between the pixel portion 101 and the circuit portion 102.
  • the terminal region R3 is provided outside the frame-shaped sealing region L along the frame-shaped sealing region L.
  • the terminal region R3 is formed outside each second electrode connection region R2 and along each second electrode connection region R2. Further, the terminal region R3 is formed along the opposing sides on the outside of the other pair of sides in the display region R1 where the second electrode connection region R2 is not provided.
  • terminal region R3 does not have to exist on all sides, and may be formed concentrated on only one side, for example.
  • FIG. 4 is a plan view showing a configuration of a main part of the display region R1 in the support substrate 10, and FIG. 5 is an organic EL display panel when the organic EL display panel 1 is cut along line AA shown in FIG. 1 is a cross-sectional view showing a schematic configuration of 1.
  • FIG. 5 is an organic EL display panel when the organic EL display panel 1 is cut along line AA shown in FIG. 1 is a cross-sectional view showing a schematic configuration of 1.
  • the display region R1 is composed of a plurality of pixels 70 on which the organic EL elements 20 are formed.
  • Each pixel 70 is composed of a plurality of sub-pixels 71.
  • the organic EL display device 100 is a full-color active matrix organic EL display device.
  • a subpixel 71 that emits red (R) light hereinafter referred to as “subpixel 71R”).
  • Sub-pixel 71 that emits light in green (G) hereinafter referred to as “sub-pixel 71G”
  • sub-pixel 71B sub-pixel 71 that emits light in blue (B)
  • One pixel 70 is constituted by the two sub-pixels 71R, 71G, and 71B.
  • each of the sub-pixels 71R, 71G, and 71B has one of the X-axis direction (lateral direction) and the Y-axis direction (vertical direction) on the active surface of the support substrate 10 (for example, the X-axis direction).
  • the sub-pixels 71 having the same emission color are adjacent to each other, and the sub-pixels 71 having different emission colors are adjacent to each other in the other direction (for example, the Y-axis direction).
  • a plurality of signal lines 14 are arranged in the X-axis direction and the Y-axis direction in the display region R1.
  • the signal line 14 includes, for example, a plurality of lines for selecting pixels (gate lines), a plurality of lines for writing data (source lines), a plurality of lines for supplying power to the organic EL elements 20 (power supply lines), and the like. ing.
  • the gate line is laid along, for example, the X-axis direction, and the source line is laid along, for example, the Y-axis direction so as to intersect the gate line.
  • a gate line driving circuit (not shown) for driving the gate line is connected to the gate line
  • a data line driving circuit (not shown) for driving the source line is connected to the source line.
  • the sub-pixels 71 are arranged in a region surrounded by the signal lines 14. That is, a region surrounded by the signal lines 14 is one sub pixel 71, and a light emitting region 72 of each color is defined for each sub pixel 71.
  • These signal lines 14 are connected to an external circuit of the circuit unit 102 outside the display region R1. By inputting an electrical signal from the circuit unit 102 to the signal line 14, the organic EL element 20 disposed at the intersection of the signal line 14 can be driven (light emission).
  • Each of the subpixels 71R, 71G, and 71B is provided with a TFT 12 connected to the first electrode 21 in the organic EL element 20.
  • the signal line 14 is connected to the TFT 12 provided in each of the sub-pixels 71.
  • each subpixel 71 is provided with at least one TFT 12.
  • each sub-pixel 71 may further be formed with a capacitor for holding the written voltage and a compensation circuit for compensating for the characteristic variation of the TFT 12.
  • the emission intensity of each sub-pixel 71 is determined by scanning and selection using the signal line 14 and the TFT 12.
  • the organic EL display device 100 realizes image display by selectively causing the organic EL element 20 to emit light with a desired luminance using the TFT 12.
  • the support substrate 10 includes an insulating substrate 11 as a base substrate.
  • the support substrate 10 is formed on a transparent insulating substrate 11 such as a glass substrate, a TFT 12 (switching element) and a signal line 14, an interlayer insulating film 13 (flattening film), an edge
  • a transparent insulating substrate 11 such as a glass substrate
  • a TFT 12 switching element
  • a signal line 14 an interlayer insulating film 13 (flattening film)
  • an edge The cover 15 and the like are formed.
  • TFTs 12 are provided corresponding to the sub-pixels 71R, 71G, 71B, respectively.
  • the structure of the TFT is conventionally well known.
  • the TFT 12 is manufactured by a known method. Therefore, illustration and description of each layer in the TFT 12 are omitted.
  • the interlayer insulating film 13 is laminated over the entire area of the insulating substrate 11 on the insulating substrate 11 so as to cover the sub-pixels 71R, 71G, 71B and the signal lines 14.
  • the first electrode 21 in the organic EL element 20 is formed on the interlayer insulating film 13.
  • the interlayer insulating film 13 is provided with a contact hole 13 a for electrically connecting the first electrode 21 in the organic EL element 20 to the TFT 12. Thereby, the TFT 12 is electrically connected to the organic EL element 20 through the contact hole 13a.
  • the edge cover 15 has an end portion (pattern end portion) of the first electrode 21, and an organic EL layer 43 (to be described later) becomes thin or an electric field concentration occurs. This is an insulating layer (barrier) for preventing the electrode 31 from being short-circuited.
  • the edge cover 15 is formed on the interlayer insulating film 13 so as to cover the end portion (pattern end portion) of the first electrode 21.
  • the edge cover 15 is provided with openings 15R, 15G, and 15B for each of the sub-pixels 71R, 71G, and 71B.
  • the 1st electrode 21 is exposed in the part (opening part 15R * 15G * 15B) without the edge cover 15.
  • This exposed portion becomes the light emitting region 72 of each of the sub-pixels 71R, 71G, and 71B.
  • a full-color image display is realized as described above by using a light-emitting layer whose emission color is white (W) and introducing a microcavity structure in each sub-pixel 71.
  • the spectrum of the light emitted from the organic EL element 20 can be adjusted by the CF layer 52 by using the CF layer 52 together as described above.
  • the organic EL element 20 is a light emitting element that can emit light with high luminance by low-voltage direct current drive, and the first electrode 21, the organic EL layer 43, and the second electrode 31 are laminated in this order.
  • the first electrode 21 is a layer having a function of injecting (supplying) holes into the organic EL layer 43.
  • the first electrode 21 is connected to the TFT 12 through the contact hole 13a.
  • the second electrode 31 is a layer having a function of injecting (supplying) electrons into the organic EL layer 43.
  • a carrier transport layer (hole transport layer, electron transport layer) and a light emitting layer are laminated via the carrier generation layer.
  • the hole injection layer 22 are formed from the first electrode 21 side.
  • the first light-emitting layer 24, the electron transport layer 25, the carrier generation layer 26, the hole transport layer 27, the second light-emitting layer 28, the electron transport layer 29, and the electron injection layer 30 are formed in this order. Note that the emission colors of the first emission layer 24 and the second emission layer 28 are different, and W emission is obtained by superimposing these emission colors.
  • the combination of the emission colors include a combination of blue light and yellow (more preferably yellow (orange) having a peak intensity in green and red) light, a combination of blue light and yellow light, and the like.
  • W light emission is obtained by superimposing the three light emission colors by stacking the third light emission layer in addition to the first light emission layer 24 and the second light emission layer 28, Can be a combination of red light, blue light, and green light.
  • a blue light emitting layer is formed as the first light emitting layer 24, and an orange light emitting layer is formed as the second light emitting layer 28.
  • the microcavity effect is added to the mixing of the light emitted from the first light emitting layer 24 and the second light emitting layer 28.
  • Light is obtained by the organic EL element 20.
  • the CF layer 52 provided on the sealing substrate 50 by adjusting the light by the CF layer 52 provided on the sealing substrate 50, light having a desired spectrum can be extracted to the outside. In this way, color purity can be increased by combining the W light emitting layer, the microcavity effect, and the CF layer 52.
  • the hole injection layer 22 is a layer having a function of increasing the efficiency of hole injection from the first electrode 21 to the organic EL layer 43.
  • the electron injection layer 30 is a layer having a function of increasing the efficiency of electron injection from the second electrode 31 to the organic EL layer 43.
  • the hole transport layer 23 is a layer having a function of increasing the hole transport efficiency to the first light emitting layer 24, and the hole transport layer 27 is a function of increasing the hole transport efficiency to the second light emitting layer 28. It is a layer which has.
  • the electron transport layer 25 is a layer having a function of increasing the electron transport efficiency to the first light emitting layer 24, and the electron transport layer 29 is a layer having a function of increasing the electron transport efficiency to the second light emitting layer 28. is there.
  • the first light emitting layer 24 and the second light emitting layer 28 each have a function of emitting light by recombining holes injected from the first electrode 21 side and electrons injected from the second electrode 31 side. Is a layer.
  • the first light emitting layer 24 and the second light emitting layer 28 are each formed of a material having high light emission efficiency, such as a low molecular fluorescent dye or a metal complex.
  • the carrier generation layer 26 is a layer for supplying electrons to the first light emitting layer 24 side and holes to the second light emitting layer 28 side.
  • the hole transport layer, the light-emitting layer, and the electron transport layer are one unit, the unit on the first light-emitting layer 24 side and the unit on the second light-emitting layer 28 side are connected via the carrier generation layer 26. Will be.
  • the microcavity effect or the CF layer 52 or other methods are used. Since the emission color of the sub-pixel 71 is changed, it is not necessary to coat the light-emitting layer for each sub-pixel 71.
  • the second light emitting layer 28, the electron transport layer 29, the electron injection layer 30, and the second electrode 31 are uniform over the entire surface of the display region R1 in the support substrate 10 so as to cover the first electrode 21 and the edge cover 15. Is formed.
  • the hole transport layer, the light emitting layer, and the electron transport layer are one unit
  • the unit on the first light emitting layer 24 side and the unit on the second light emitting layer 28 side are the carrier generation layer 26.
  • the present embodiment is not limited to this example.
  • units having the third light emitting layer may be stacked in the same manner, or four or more units may be stacked.
  • it may have a stacked structure in which the second light emitting layer and the third light emitting layer are directly stacked.
  • a carrier blocking layer for blocking the flow of carriers such as holes and electrons may be inserted as necessary.
  • a hole blocking layer as a carrier blocking layer between the light emitting layer and the electron transporting layer, it is possible to prevent holes from escaping to the electron transporting layer and to improve the light emission efficiency.
  • an electron blocking layer as a carrier blocking layer between the light emitting layer and the hole transport layer, it is possible to prevent electrons from being released into the hole transport layer.
  • an electron injection layer can be inserted between the electron transport layer and the carrier generation layer.
  • the light emitting layer 24 and the second light emitting layer 28 are provided.
  • the first light emitting layer 24 and the second light emitting layer 28 are provided.
  • the case of providing at least two light emitting layers of the light-emitting layer 28 has been described as an example.
  • the organic layers other than the light emitting layer are not essential layers as the organic EL layer 43, and at least one light emitting layer may be provided. What is necessary is just to form the structure of the organic electroluminescent layer 43 suitably according to the characteristic of the organic electroluminescent element 20 requested
  • the organic EL element 20 may have, for example, the layer configuration shown in (9).
  • one layer has a plurality of functions.
  • the hole injection layer and the hole transport layer may be formed as independent layers as described above, or may be provided integrally with each other. That is, as the hole injection layer and the hole transport layer, a hole injection layer / hole transport layer in which the hole injection layer and the hole transport layer are integrated may be provided.
  • the electron transport layer and the electron injection layer may be formed as layers independent from each other as described above, or may be provided integrally as an electron transport layer / electron injection layer.
  • the stacking order is such that the first electrode 21 is an anode and the second electrode 31 is a cathode.
  • the stacking order of the organic EL layers 43 is reversed.
  • the bottom emission organic EL element 20 is formed by using the first electrode 21 as a translucent electrode and the second electrode 31 as a reflective electrode.
  • the top emission type organic EL element 20 is formed by using the first electrode 21 as a reflective electrode and the second electrode 31 as a translucent electrode.
  • the configuration of the organic EL element 20 is not limited to the above-described exemplary layer configuration, and a desired layer configuration can be adopted according to the required characteristics of the organic EL element 20.
  • FIG. 6 is a schematic diagram for explaining an image display method of the organic EL display device 100 according to the present embodiment.
  • the configuration of the main part on the optical path of the organic EL element 20 is shown in a simplified manner.
  • the organic EL element 20 according to the present embodiment has a microcavity structure.
  • the microcavity is a phenomenon in which emitted light undergoes multiple reflections between the anode and the cathode and resonates, resulting in a steep emission spectrum and amplification of the emission intensity at the peak wavelength.
  • the microcavity effect can be obtained, for example, by optimally designing the reflectance and film thickness of the anode and cathode, the film thickness of the organic layer, and the like.
  • the organic EL element 20 is a top emission type organic EL element.
  • the second electrode 31 on the side of taking out light emission as a cathode is a semitransparent electrode (semi-transmissive reflective electrode).
  • the first electrode 21 on the side that is an anode and does not extract light emission has the reflective electrode layer 111 and functions as a reflective electrode.
  • the light emitted from the light emitting layer (the first light emitting layer 24 and the second light emitting layer 28 in the example shown in FIG. 5) in the organic EL layer 43 provided between the first electrode 21 and the second electrode 31. Repeats reflection between the reflective electrode layer 111 and the second electrode 31 in the first electrode 21.
  • the transparent electrode layer 121 is provided on the reflective electrode layer 111, and the thickness of the transparent electrode layer 121 is changed for each of the sub-pixels 71R, 71G, and 71B, so that each of the sub-pixels 71R, 71G, and 71B.
  • the optical path lengths 73R, 73G, and 73B of the organic EL element 20 are changed.
  • the first electrode 21 is formed of only the reflective electrode layer 111 in the sub-pixel 71B, and the sub-pixels 71R and 71G are formed of the reflective electrode layer.
  • 111 and the transparent electrode layer 121, and the transparent electrode layer 121 on the reflective electrode layer 111 in the sub-pixels 71R and 71G is composed of one layer or two layers, so that the sub-pixels 71R, 71G, and 71B are transparent.
  • the film thickness of the electrode layer 121 is changed.
  • the microcavity effect can be changed and the emission color can be adjusted.
  • the optical path lengths 73R, 73G, and 73B of the organic EL element 20 in each of the sub-pixels 71R, 71G, and 71B that is, the optical distance of the optical path in the microcavity structure in each of the sub-pixels 71R, 71G, and 71B It is set to have a certain relationship with the wavelength.
  • the intensity of light having a wavelength that matches the optical path length is strengthened by resonance, and only the light having the same wavelength is emitted from the second electrode 31 side.
  • the intensity of the light having a wavelength other than the optical path length is reduced.
  • the optical path lengths 73R, 73G, and 73B are set to optical lengths corresponding to the color of the emitted light from the second electrode 31.
  • the optical path lengths 73R, 73G, and 73B are emission spectrum peaks of these colors of R, G, and B, respectively.
  • the optical path length 73R> the optical path length 73G> the optical path length 73B may not necessarily be shortened in this order, and other relationships may be provided.
  • the transparent electrode layer 121 overlapping the R light organic EL layer 43 is set to a thickness suitable for the R light resonance, and the transparent electrode layer 121 overlapping the G light organic EL layer 43 is suitable for the G light resonance.
  • the transparent electrode layer 121 is set to a thickness suitable for the resonance of the B light.
  • the first electrode 21 is formed by patterning corresponding to the individual sub-pixels 71R, 71G, and 71B by photolithography and etching after an electrode material is formed by sputtering or the like.
  • the first electrode 21 various conductive materials can be used. As described above, in the case of the bottom emission type organic EL element 20 that emits light to the insulating substrate 11 side, it needs to be translucent. is there.
  • the second electrode 31 needs to be translucent.
  • the organic EL element 20 is a top emission type, it is desirable to use an opaque electrode for the reflective electrode layer 111 in the first electrode 21.
  • the reflective electrode material used for the reflective electrode layer 111 for example, Ag (silver), an Ag alloy, Al (aluminum), an Al alloy, and a laminated body (laminated film) including layers made of these electrode materials are used. it can.
  • ITO Indium Tin Oxide
  • IZO Indium Zinc Oxide
  • GZO gallium-doped zinc oxide
  • a translucent electrode for the second electrode 31.
  • the translucent electrode for example, a metal translucent electrode alone or a laminate of a metal translucent electrode layer and a transparent electrode layer can be used, and silver is preferable from the viewpoint of reflectance and transmittance.
  • a sputtering method a vacuum deposition method, a CVD (chemical vapor deposition) method, a plasma CVD method, a printing method, or the like can be used.
  • the transparent electrode layer in the first electrode 21 or the second electrode 31 (the first electrode 21 in the examples shown in FIGS. 5 and 6) is used to control the emission color emitted by the difference in optical path length.
  • the microcavity structure is introduced into the sub-pixels 71R, 71G, and 71B by changing the thickness of the 121 to the sub-pixels 71R, 71G, and 71B.
  • a method for introducing a microcavity structure into the sub-pixels 71R, 71G, and 71B by changing the thickness of the transparent electrode layer 121 in this way will be described in detail later.
  • a known material can be used as a material of the organic EL layer 43.
  • the hole injection layer As a material of the hole injection layer, the hole transport layer, or the hole injection layer / hole transport layer, for example, anthracene, azatriphenylene, fluorenone, hydrazone, stilbene, triphenylene, benzine, styrylamine, triphenylamine, porphyrin, Linear or heterocyclic such as triazole, imidazole, oxadiazole, oxazole, polyarylalkane, phenylenediamine, arylamine, and derivatives thereof, thiophene compounds, polysilane compounds, vinylcarbazole compounds, aniline compounds Examples thereof include conjugated monomers, oligomers, and polymers.
  • anthracene azatriphenylene, fluorenone, hydrazone, stilbene, triphenylene, benzine, styrylamine, triphenylamine, porphyrin
  • Linear or heterocyclic such as triazole, imidazole,
  • Examples of the material for the electron transport layer, the electron injection layer, or the electron transport layer / electron injection layer include tris (8-quinolinolato) aluminum complex, oxadiazole derivative, triazole derivative, phenylquinoxaline derivative, silole derivative, and the like. .
  • a material having high luminous efficiency such as a low molecular fluorescent dye or a metal complex
  • a material having high luminous efficiency such as a low molecular fluorescent dye or a metal complex
  • a single material may be used for each light emitting layer, or a mixed material in which a certain material is used as a host material and another material is mixed as a guest material or a dopant may be used.
  • Materials for the carrier generation layer include metal oxides such as molybdenum oxide and vanadium pentoxide, or those co-deposited with aromatic hydrocarbons and carbazole derivatives, Au and Ag metal thin films, IZO and ITO, etc. Examples thereof include a transparent conductive layer (transparent electrode layer).
  • FIG. 7 is a flowchart showing an example of the manufacturing process of the organic EL display device 100 in the order of processes.
  • the stacking order described in the present embodiment is such that the first electrode 21 is an anode, the second electrode 31 is a cathode, the first electrode 21 is a cathode, and the second electrode 31 is. Is used as the anode, the material and thickness of the first electrode 21 and the second electrode 31 are reversed.
  • step S1 a TFT 12, a signal line 14, an interlayer insulating film 13, and a contact hole 13a are formed on the display region R1 of the insulating substrate 11 as shown in FIG. 5 by a known method.
  • the insulating substrate 11 is, for example, a glass substrate such as a non-alkali glass substrate having a thickness of 0.7 to 1.1 mm or a plastic substrate. Is used.
  • the sizes of the insulating substrate 11 in the X-axis direction and the Y-axis direction may be appropriately set according to the application and the like, and are not particularly limited.
  • a non-alkali glass substrate having a thickness of 0.7 mm is used.
  • the interlayer insulating film 13 and the contact hole 13a are formed by applying a photosensitive resin on the insulating substrate 11 on which the TFT 12, the signal line 14, and the like are formed by a known technique, and performing patterning by a photolithography technique.
  • the interlayer insulating film 13 a known photosensitive resin can be used.
  • the photosensitive resin include acrylic resin and polyimide resin.
  • the film thickness of the interlayer insulating film 13 is not particularly limited as long as the step due to the TFT 12 can be compensated. In the present embodiment, for example, an acrylic resin is formed with a film thickness of about 2 ⁇ m.
  • a pattern is formed so that signal lines 14 such as a gate line and a source line for driving the TFT 12 are led out to the terminal portion region R3. Further, in this step, for example, as shown in FIG. 3, the connection portion 60 is pattern-formed in the second electrode connection region R2.
  • step S2 the first electrodes 21 having different thicknesses are produced for the sub-pixels 71R, 71G, and 71B. Note that, as described above, a method of manufacturing the first electrode 21 when the organic EL display device 100 is a top emission type will be described in detail later.
  • step S3 the end portion (pattern end portion) of the first electrode 21 is covered on the interlayer insulating film 13, and the openings 15R, 15G are provided for the sub-pixels 71R, 71G, 71B as shown in FIG.
  • the edge cover 15 is produced so that 15B is formed.
  • a known photosensitive resin can be used for the edge cover 15.
  • the photosensitive resin include acrylic resin and polyimide resin.
  • the edge cover 15 compensates for the level difference due to the difference in the layer thickness of the first electrode 21 in the adjacent sub-pixel 71, and the first electrode 21 and the second electrode 31 are short-circuited at the end of the first electrode 21.
  • the height from the surface of the first electrode 21 in the sub-pixel 71R where the film thickness of the first electrode 21 is the thickest is set to about 1 ⁇ m, for example.
  • an edge cover made of acrylic resin having a height from the surface of the interlayer insulating film 13 of about 1.2 ⁇ m so that the height from the surface of the first electrode 21 in the sub-pixel 71R is about 1 ⁇ m. 15 was formed by patterning.
  • the support substrate 10 on which the first electrode 21 and the edge cover 15 are formed is manufactured.
  • step S4 the support substrate 10 that has undergone the above-described processes is subjected to oxygen plasma treatment as a vacuum baking for dehydration and surface cleaning of the first electrode 21, and then, as shown in FIG.
  • An organic EL layer 43 is formed on the entire surface of the display region R1 of the support substrate 10 so as to cover the one electrode 21 and the edge cover 15. A method for producing the organic EL layer 43 will be specifically described later.
  • the second electrode 31 is formed by a known method. Specifically, the second electrode 31 is formed on the entire surface of the display region R1, and is electrically connected to the connection portion 60 of the second electrode connection region R2, so that, for example, vapor deposition is performed so that these regions are exposed. A pattern is formed by a vapor deposition method using a mask for use. Note that the second electrode 31 can be manufactured using the same method as that for the organic EL layer 43.
  • the film thickness of the second electrode 31 is preferably 10 to 30 nm.
  • the film thickness of the second electrode 31 is less than 10 nm, light cannot be sufficiently reflected, and there is a possibility that the microcavity effect cannot be obtained sufficiently.
  • the film thickness of the second electrode 31 exceeds 30 nm, the light transmittance may decrease and the luminance may decrease.
  • Ag is formed with a thickness of 20 nm as the second electrode 31.
  • the organic EL element 20 including the first electrode 21, the organic EL layer 43, and the second electrode 31 was formed on the support substrate 10.
  • step S6 as shown in FIG. 2, the support substrate 10 on which the organic EL element 20 is formed and the sealing substrate 50 are bonded together with the sealing resin layer 41, and the organic EL element 20 is sealed. .
  • the organic EL element 20 can be sealed as follows, for example.
  • a sealing resin layer 41 is formed in a frame-shaped sealing region L surrounding the display region R1 and the second electrode connection region R2 in the support substrate 10 shown in FIG.
  • the filling resin layer 42 having adhesiveness containing a desiccant is filled.
  • an epoxy resin is used for the filling resin layer 42.
  • the film thickness of the filling resin layer 42 is, for example, 1 to 20 ⁇ m.
  • the support substrate 10 and the sealing substrate 50 are bonded together via the sealing resin layer 41.
  • the organic EL element 20 is sealed by the support substrate 10, the sealing substrate 50, the sealing resin layer 41, and the filling resin layer 42.
  • sealing substrate 50 for example, an insulating substrate such as a glass substrate or a plastic substrate having a plate thickness of 0.4 to 1.1 mm is used. In this embodiment, a non-alkali glass substrate having a thickness of 0.7 mm is used.
  • step S7 the circuit portion 102 is connected to the electric wiring terminal 2 in the terminal portion region R3 of the support substrate 10 through an ACF (Anisotropic Conductive Film) (not shown), for example.
  • the connection terminal 103 is connected. In this way, the organic EL display device 100 is manufactured.
  • the sizes of the sealing substrate 50 in the X-axis direction and the Y-axis direction may be appropriately adjusted according to the size of the target organic EL display device 100, and have substantially the same size as the insulating substrate 11 in the support substrate 10. After using the insulating substrate and sealing the organic EL element 20, it may be divided according to the size of the target organic EL display device 100.
  • FIG. 8 is a flowchart showing an example of a manufacturing process of the organic EL layer 43 in the order of processes.
  • the stacking order shown in FIG. 8 is such that the first electrode 21 is an anode, the second electrode 31 is a cathode, the first electrode 21 is a cathode, and the second electrode 31 is an anode.
  • the stacking order of the organic EL layer 43 is reversed.
  • vacuum deposition is used for the pattern formation.
  • the vapor deposition particles (film forming material) from the vapor deposition source are made so that the vapor deposition surface of the support substrate 10 to which the mask (open mask) having the entire display region R1 opened is closely fixed is opposed to the vapor deposition source. Then, vapor deposition is performed on the deposition surface through the opening of the mask. Thereby, the vapor deposition particles scattered from the vapor deposition source are uniformly vapor deposited on the entire surface of the display region R1 through the opening of the open mask.
  • the vapor deposition may be performed by, for example, attaching an open mask having the entire display region R1 opened to the support substrate 10 after alignment adjustment, and rotating the support substrate 10 and the open mask together.
  • the vapor deposition particles scattered from the vapor deposition source may be vapor-deposited on the display region R1 through the opening of the open mask, and the vapor deposition source is scanned with the support substrate 10 and the open mask fixedly adhered using the open mask. Scan deposition such as vapor deposition may be performed.
  • the vapor deposition on the entire surface of the display region R1 means that the vapor deposition is performed continuously between adjacent sub-pixels of different colors.
  • the vacuum deposition apparatus is set to a vacuum reach of 1.0 ⁇ 10 ⁇ 4 Pa or more by a vacuum pump. desirable. In other words, it is desirable that the pressure in the vacuum chamber is set to 1.0 ⁇ 10 ⁇ 4 Pa or less.
  • the average free path of the vapor-deposited particles can provide a necessary and sufficient value when the degree of vacuum is higher than 1.0 ⁇ 10 ⁇ 3 Pa.
  • the degree of vacuum is lower than 1.0 ⁇ 10 ⁇ 3 Pa, the mean free path is shortened, so that the vapor deposition particles are scattered and the arrival efficiency to the support substrate 10 which is the film formation substrate is lowered. Or vapor deposition particles adhere to an unnecessary area. For this reason, it is desirable that the vacuum chamber is set to the above-mentioned vacuum reachability.
  • step S12 using an open mask, the hole transport layer 23 is coated with the hole injection layer 22 in the same pattern as the hole injection layer 22 so as to cover the hole injection layer 22.
  • a pattern is formed (deposited) on the entire surface of the display region R1.
  • the hole injection layer 22 and the hole transport layer 23 are covered with the same pattern as the hole injection layer 22 and the hole transport layer 23 so as to cover the hole transport layer 23.
  • the first light emitting layer 24 (Step S13), the electron transport layer 25 (Step S14), the carrier generation layer 26 (Step S15), and the hole transport layer 27 (Step S16) are formed on the entire surface of the display region R1 in each step.
  • the second light emitting layer 28 (step S17), the electron transport layer 29 (step S18), and the electron injection layer 30 (step S19) are uniformly patterned (evaporated) in this order.
  • the film thickness of these organic EL layers 43 is set, for example, in the same manner as in the past.
  • the hole injection layer 22 and the hole transport layer 23 may be formed as independent layers as described above, or may be integrated as described above. Each film thickness is, for example, 1 to 100 nm. The total film thickness of the hole injection layer 22 and the hole transport layer 23 is, for example, 2 to 200 nm.
  • the electron transport layer 29 and the electron injection layer 30 may be formed as independent layers as described above, or may be integrated as described above.
  • the film thickness of each of the electron transport layer 25, the electron transport layer 29, and the electron injection layer 30 is, for example, 1 to 100 nm.
  • the total film thickness of the electron transport layer 29 and the electron injection layer 30 is, for example, 20 to 200 nm.
  • the film thickness of each of the first light emitting layer 24 and the second light emitting layer 28 is, for example, 10 to 100 nm.
  • the film thickness of the carrier generation layer 26 is, for example, 1 to 30 nm.
  • copper phthalocyanine having a thickness of 2 nm was formed as the hole injection layer 22.
  • NPB 4,4'-bis [N- (1-naphthyl) -N-phenylamino] biphenyl having a thickness of 30 nm was formed.
  • the electron transport layer 25 and the electron transport layer 29 oxadiazole derivatives each having a film thickness of 40 nm were formed. Further, as the electron injection layer 30, lithium fluoride having a thickness of 1 nm was formed.
  • the first light-emitting layer 24 and the second light-emitting layer 28 are films in which iridium complexes are used as guest materials and CBP (4,4′-N, N′-dicarbazole-biphenyl) is used as a host material.
  • the film was formed with a thickness of 30 nm.
  • the carrier generation layer 26 a film obtained by co-evaporating molybdenum oxide and NPB was formed to a thickness of 10 nm.
  • step S18 when laminating
  • step S21 a carrier generation layer
  • step S22 a hole transport layer
  • step S23 the third light emitting layer
  • step S24 are uniformly patterned (evaporated) in this order.
  • the material and film thickness of the carrier generation layer, the hole transport layer, the third light emitting layer, and the electron transport layer may be set in the same manner as the unit having the second light emitting layer 28, for example.
  • the first light-emitting layer 24 and the second light-emitting layer 28 are light-emitting layers having different emission colors, and the mixture of light emitted from the first light-emitting layer 24 and the second light-emitting layer 28 is a microcavity effect. As a result, the organic EL element 20 obtains the light.
  • FIGS. 1A to 1I are cross-sectional views showing an example of a method for manufacturing the first electrode 21 in the top emission type organic EL display device 100 shown in step S2 in order of steps.
  • amorphous ITO amorphous ITO (hereinafter referred to as “transparent electrode layer”) is formed on the support substrate 10 in which the interlayer insulating film 13 and the contact hole 13a shown in FIG. , "A-ITO") layer 110, reflective electrode layer 111 made of a reflective electrode material such as a metal material, and a-ITO layer 112 (first transparent electrode layer) which is a transparent electrode layer in this order.
  • the film is formed by a method or the like.
  • resist patterns 201R, 201G, and 201B are formed on the a-ITO layer 112 by photolithography for each of the sub-pixels 71R, 71G, and 71B. Thereafter, using the resist patterns 201R, 201G, and 201B as masks, the a-ITO layer 110, the reflective electrode layer 111, and the a-ITO layer 112 are etched as shown in FIG. 201R / 201G / 201B is stripped and washed with a resist stripper.
  • the a-ITO layer 110, the reflective electrode layer 111, and the a-ITO layer 112 are patterned so as to be separated into sub-pixels 71R, 71G, and 71B of the respective colors. . That is, the a-ITO layer 110, the reflective electrode layer 111, and the a-ITO layer 112, which are patterned for the sub-pixels 71R, 71G, and 71B of each color, are formed.
  • the reflective electrode material used for the reflective electrode layer 111 is preferably a reflective electrode material that does not undergo an electrolytic corrosion reaction with a-ITO.
  • a-ITO any one selected from the group consisting of Ag, an Ag alloy, and an Al alloy is used. be able to.
  • the thickness of the reflective electrode layer 111 is set to 50 to 200 nm, for example. In this embodiment mode, a silver alloy with an electrode thickness of 100 nm is formed as the reflective electrode layer 111.
  • the film thickness of the a-ITO layer 110 is set to 200 nm or less (0 to 200 nm), for example.
  • the film thickness of the a-ITO layer 112 is set to 5 to 50 nm, for example.
  • an a-ITO layer 110 with an electrode thickness of 100 nm and an a-ITO layer 112 with an electrode thickness of 20 nm are formed.
  • wet etching using, for example, a mixed solution of phosphoric acid, nitric acid, and acetic acid or ferric chloride is used as the etching solution.
  • a mixed solution of phosphoric acid, nitric acid, and acetic acid or ferric chloride is used as the etching solution.
  • monoisopropanolamine is used as the resist stripping solution.
  • the support substrate 10 is heat-treated (annealed) to crystallize the a-ITO layers 110 and 112 as shown in FIG.
  • treatment temperature and treatment time in the heat treatment may be set as appropriate so that the a-ITO layers 110 and 112 can be crystallized, and are not particularly limited.
  • a-ITO was converted to crystalline ITO (hereinafter referred to as “p-ITO”).
  • p-ITO crystalline ITO
  • the p-ITO layer 113, the reflective electrode layer 111, and the p-ITO layer 114 (first transparent electrode layer) are covered on the support substrate 10.
  • an a-ITO layer 115 (second transparent electrode layer) which is a transparent electrode layer is formed by sputtering, for example.
  • the film thickness of the a-ITO layer 115 is set to 40 to 120 nm, for example. In this embodiment, the a-ITO layer 115 having an electrode thickness of 80 nm is formed.
  • a resist pattern 202R is formed so as to cover the p-ITO layer 114.
  • the resist pattern 202R was formed wider than the pattern of the p-ITO layer 113 in the sub-pixel 71R so as to cover the pattern end of the p-ITO layer 113 below the reflective electrode layer 111 in plan view.
  • the resist pattern 202R overlaps with the reflective electrode layer 111 and the p-ITO layer 113 in plan view, and is larger than the reflective electrode layer 111 and the p-ITO layer 113 in plan view.
  • the protruding amount of the resist pattern 202R in plan view from the pattern end of the p-ITO layer 113 was set to 2 ⁇ m.
  • the a-ITO layer 115 not masked by the resist pattern 202R is wet-etched as shown in FIG. Strip and clean with a resist stripper.
  • oxalic acid is used as the etching solution.
  • the a-ITO layer 115 can be selectively etched.
  • the resist stripping solution a resist stripping solution similar to the resist stripping solution used in the etching shown in FIG.
  • the p-ITO layers 113 and 114 and the reflective electrode layer 111 are not etched by the etching solution (oxalic acid) or the etching rate is extremely low. Therefore, the p-ITO layers 113 and 114 and the reflective electrode layer 111 remain without being removed by the etching.
  • the support substrate 10 is heat-treated to crystallize the a-ITO layer 115 as shown in FIG.
  • treatment temperature and treatment time in the heat treatment may be set as appropriate so that the a-ITO layer 115 can be crystallized, and are not particularly limited.
  • the heat treatment was performed at 200 ° C. for 1 hour as in the process shown in FIG.
  • a-ITO was converted into p-ITO.
  • the a-ITO layer 115 in the sub-pixel 71R was converted to the p-ITO layer 116 as shown in FIG.
  • a transparent electrode layer is formed on the support substrate 10 so as to cover the transparent electrode layers and the reflective electrode layers 111 in the sub-pixels 71R, 71G, and 71B.
  • the ITO layer 117 is deposited, for example, by sputtering.
  • the film thickness of the a-ITO layer 117 is set to 20 to 60 nm, for example.
  • the film thickness of the a-ITO layer 117 is p-
  • the a-ITO layer 117 is formed so as to be smaller than the film thickness of the ITO layer 116 (the optical path length 73R in the sub-pixel 71R). Therefore, the thickness of the a-ITO layer 117 is set to 40 nm, which is smaller than the thickness of the p-ITO layer 116.
  • the p-ITO layer 113, the reflective electrode layer 111, the patterned p-ITO layer 113, and the reflective electrode layer 111 in a plan view by photolithography on the a-ITO layer 117 in the sub-pixel 71G.
  • a resist pattern 202G is formed so as to cover the a-ITO layer 117.
  • the resist pattern 202G was formed wider than the pattern of the p-ITO layer 113 in the sub-pixel 71G so as to cover the pattern end of the p-ITO layer 113 below the reflective electrode layer 111 in plan view.
  • the resist pattern 202G also overlaps with the reflective electrode layer 111 and the p-ITO layer 113 in plan view, and is larger than the reflective electrode layer 111 and the p-ITO layer 113 in plan view.
  • the amount of protrusion of the resist pattern 202G in plan view from the pattern end of the p-ITO layer 113 was set to 2 ⁇ m, like the resist pattern 202R.
  • an a-ITO layer 117 not masked with the resist pattern 202G is wet-etched as shown in FIG. Strip and clean with a resist stripper.
  • the etching solution and the stripping solution the same etching solution and stripping solution as the etching solution and stripping solution used in the etching shown in FIG. Thereby, the a-ITO layer 117 can be selectively etched.
  • the p-ITO layers 113, 114, and 116 and the reflective electrode layer 111 are not etched by the etching solution (oxalic acid), or the etching rate is extremely low. For this reason, the p-ITO layers 113, 114 and 116 and the reflective electrode layer 111 remain without being removed by the etching.
  • the etching solution oxalic acid
  • the support substrate 10 is heat-treated to crystallize the a-ITO layer 117 as shown in FIG.
  • treatment temperature and treatment time in the heat treatment may be set as appropriate so that the a-ITO layer 117 can be crystallized, and are not particularly limited.
  • the reflective electrode layer 111 includes a p-ITO layer 113 which is a transparent electrode layer below the reflective electrode layer 111 and a p-ITO layer which is a transparent electrode layer above the reflective electrode layer 111.
  • a first electrode 21 surrounded by 114 and 116 is formed.
  • the p-ITO layers 114 and 116 which are the transparent electrode layers above the reflective electrode layer 111, function as the transparent electrode layer 121 that forms the microcavity.
  • the film thicknesses of the p-ITO layers 113 and 116 are set so that the total film thickness of the p-ITO layers 113 and 116 becomes the optical path length 73R of the sub-pixel 71R.
  • the reflective electrode layer 111 includes a p-ITO layer 113 which is a transparent electrode layer below the reflective electrode layer 111 and a p-ITO layer 114 which is a transparent electrode layer above the reflective electrode layer 111. And the first electrode 21 surrounded by the p-ITO layer 118 having a thickness smaller than that of the p-ITO layer 116 is formed.
  • the p-ITO layers 114 and 118 which are the transparent electrode layers above the reflective electrode layer 111, function as the transparent electrode layer 121 that forms the microcavity.
  • the film thicknesses of the p-ITO layers 114 and 118 are set so that the total film thickness of the p-ITO layers 114 and 118 becomes the optical path length 73G of the sub-pixel 71G.
  • the reflective electrode layer 111 includes a p-ITO layer 113 that is a transparent electrode layer below the reflective electrode layer 111, and a p-ITO layer 114 that is a transparent electrode layer above the reflective electrode layer 111.
  • the first electrode 21 sandwiched between and is formed.
  • the p-ITO layer 114 which is the transparent electrode layer on the reflective electrode layer 111, functions as the transparent electrode layer 121 that forms the microcavity.
  • the film thickness of the p-ITO layer 114 is set so that the film thickness of the p-ITO layer 114 becomes the optical path length 73G of the sub-pixel 71G.
  • each of the sub-pixels 71R, 71G, 71B has a transparent electrode layer having a composition different from that of the ITO layer, such as a p-ITO layer (not shown) or an IZO layer. Furthermore, you may have the structure laminated
  • the a-ITO layer is formed, the patterning step of patterning the a-ITO layer by etching using photolithography, and the patterned a-ITO By repeating the crystallization step of converting the layer into a p-ITO layer, an arbitrary number of p-ITO layers can be stacked on an arbitrary sub-pixel.
  • the film thickness of the transparent electrode layer 121 can be changed for each of the sub-pixels 71R, 71G, and 71B of different colors.
  • the edge cover 15 is produced as shown in step S3.
  • FIG. 9A is a cross-sectional view schematically showing a schematic configuration of the first electrode 21 when the edge cover 15 is produced on the first electrode 21 in step S3
  • FIG. 4 is a plan view schematically showing a schematic configuration of the first electrode 21 when the edge cover 15 is produced on the first electrode 21 in step S3.
  • FIG. 9A is a cross-sectional view schematically showing a schematic configuration of the first electrode 21 when the edge cover 15 is produced on the first electrode 21 in step S3
  • FIG. 4 is a plan view schematically showing a schematic configuration of the first electrode 21 when the edge cover 15 is produced on the first electrode 21 in step S3.
  • FIG. 9A is a cross-sectional view schematically showing a schematic configuration of the first electrode 21 when the edge cover 15 is produced on the first electrode 21 in step S3
  • FIG. 4 is a plan view schematically showing a schematic configuration of the first electrode 21 when the edge cover 15 is produced on the first electrode 21 in step S3.
  • the resist pattern 202R is sub-pixel covered so as to cover the pattern end of the p-ITO layer 113 under the reflective electrode layer 111 in plan view. It is formed wider than the pattern of the p-ITO layer 113 in 71R.
  • the a-ITO layer 115 around the p-ITO layer 113 covered with the resist pattern 202R is not etched away by the etching in the step shown in FIG.
  • the patterned reflective electrode layer 111 and the p-ITO layer 113 remain so as to cover them.
  • the resist pattern 202G covers the pattern end of the p-ITO layer 113 below the reflective electrode layer 111 in plan view. It is formed wider than the pattern of each p-ITO layer 113 in the sub-pixel 71G.
  • the a-ITO layer 117 around the p-ITO layer 113 covered with the resist pattern 202G is not etched away by the etching in the step shown in FIG.
  • the patterned reflective electrode layer 111 and the p-ITO layer 113 remain so as to cover them.
  • a plurality of p-ITO layers are stacked on the reflective electrode layer 111 in the sub-pixels 71R and 71G, but the sub-pixel forming the resist pattern is changed.
  • a plurality of p-ITO layers can be stacked on the reflective electrode layer 111 in an arbitrary subpixel.
  • the p-ITO is formed on the sub-pixel 71B in the same manner as the process shown in FIG. 1D or FIG.
  • the reflective electrode layer 111 includes a p-ITO layer 113 which is a transparent electrode layer below the reflective electrode layer 111, and a reflective electrode layer
  • the first electrode 21 surrounded by the p-ITO layers 114 and 116, which are upper transparent electrode layers 111 can be obtained.
  • the a-ITO layer 112 (the first electrode) is formed as a transparent electrode layer made of an amorphous transparent electrode material above the reflective electrode layer 111 (for example, on the reflective electrode layer 111). After the transparent electrode layer is formed and etched together, the a-ITO layer 112 is converted into a transparent electrode layer made of a polycrystalline transparent electrode material (that is, the p-ITO layer 114).
  • the sub-pixels 71R and 71G are formed by laminating the transparent electrode layers by utilizing the difference in etching resistance with the a-ITO layers 115 and 117 (second transparent electrode layers) which are transparent electrode layers formed on the substrate. -The total film thickness of the said transparent electrode layer is changed between 71B.
  • the a-ITO layer 112 is formed above the reflective electrode layer 111, and the reflective electrode layer 111 and the a-ITO layer 112 are etched together.
  • the p-ITO layer 114 can be stacked on the reflective electrode layer 111 without increasing the number of times of photolithography.
  • the a-ITO layers 115 and 117 which are transparent electrode layers (second transparent electrode layers) having lower etching resistance than the p-ITO layer 114 (first transparent electrode layer) are formed.
  • the a-ITO layer 112 is laminated in advance on each of the subpixels 71R, 71G, 71B, so that the second transparent electrode layer can be laminated on any subpixel 71.
  • an ITO layer having crystallinity is separately formed and patterned in order to build up the transparent electrode layer, and the transparent electrode layer having the same film thickness is formed on two sub-pixels every time photolithography is performed. Even if the pattern is not formed, the total film thickness of the transparent electrode layer on the reflective electrode layer 111 (that is, the transparent electrode layer 121) for each of the sub-pixels 71R, 71G, and 71B having different display colors by photolithography twice.
  • the first electrode 21 having a different thickness can be formed.
  • the film thickness (the number of stacked layers) of the transparent electrode layer for each of the sub-pixels 71R, 71G, and 71B.
  • the film thickness of the transparent electrode layer 121 on the reflective electrode layer 111 can be arbitrarily changed for each of the sub-pixels 71R, 71G, and 71B by photolithography.
  • the number of photolithography can be suppressed to three even when the etching of the reflective electrode layer 111 is included.
  • the film thickness of the second transparent electrode layer in an arbitrary subpixel 71 is set to be equal to that of the second subpixel 71. It is possible to set the thickness independently of the transparent electrode layer.
  • the difference in etching selectivity between the transparent electrode layer made of an amorphous transparent electrode material and the transparent electrode layer made of a polycrystalline transparent electrode material (for example, as described above)
  • the transparent electrode layers in each color single layer are stacked using the difference in etching selectivity between the a-ITO layer and the p-ITO layer).
  • the etching resistance to the etching solution can be increased by converting the amorphous transparent electrode material into the polycrystalline transparent electrode material.
  • the optical path lengths 73R, 73G, and 73B in the sub-pixels 71R, 71G, and 71B are arbitrarily and easily adjusted without being restricted by the optical path length as in Patent Document 3. be able to.
  • the film thickness of the first electrode 21, in other words, the optical path length of the organic EL element 20 can be arbitrarily set for each sub-pixel 71 having a different display color by a smaller number of photolithography than conventional. Can be changed.
  • the photoresist stripping and baking steps increase, so that the surface of the reflective electrode layer is roughened or oxidized to reduce the reflection efficiency, or the electrode due to the rough surface of the reflective electrode. There was a risk that a leak would occur, resulting in a pixel defect.
  • the processing tact can be shortened.
  • the terminal portion of the reflective electrode layer 111 or the signal line 14 is formed of Ag
  • the Ag is in an exposed state (that is, an exposed state)
  • the support substrate 10 is provided to improve the wettability of the resist.
  • ultraviolet irradiation is performed, the exposed Ag is oxidized to silver oxide.
  • the terminal portion of the reflective electrode layer 111 or the signal line 14 is formed of Ag, it is not desirable that Ag is exposed when the ultraviolet rays are irradiated.
  • the reflective electrode layer 111 or the terminal portion of the signal line 14 is made of Al, Al has low solvent resistance, and there is a possibility that the solvent penetrates through the IZO layer.
  • the reflection electrode layer 111 and the terminal portion of the signal line 14 are covered with the p-ITO layer as described above.
  • the p-ITO layer formed on the lower layer or the upper layer of the reflective electrode layer 111 is also formed on the terminal portion of the signal line 14 such as the source line in the film formation process of the a-ITO layer.
  • the ITO layer By forming the ITO layer, it can be used as a protective film covering the terminal portion of the signal line 14 such as a source line.
  • these transparent electrode layers are laminated
  • the reflection electrode layer 111 and the terminal portion of the signal line 14 are covered with the p-ITO layers 113 and 114 at an early stage in the manufacturing process.
  • the reflective electrode layer 111 is protected from the above factors that may impair the quality of the reflective electrode layer 111, such as reducing the number of times or the area in which the terminal portions of the signal line 14 and the signal line 14 are immersed in the developer. be able to.
  • the resist patterns 202R and 202G are formed wider than the pattern of the p-ITO layer 113 in each of the sub-pixels 71R and 71G in plan view, and the reflective electrode layer 111 is formed as p-ITO as described above. The same effect can be obtained by sandwiching between layers or sealing with a p-ITO layer.
  • p-ITO is not only obtained by heat-treating a-ITO, but can also be formed directly by a film forming apparatus.
  • the flatness of the film is lowered due to the growth of crystal grains during the film formation, and pinholes between crystals are easily generated.
  • the organic EL element 20 is easily damaged due to a short circuit between the first electrode 21 and the second electrode 31.
  • the p-ITO layer is preferably converted into a p-ITO layer after the a-ITO layer is formed and then patterned.
  • the first electrode 21 is formed in a tapered shape by using an etching solution suitable for the electrode layer material.
  • an etching solution suitable for the electrode layer material By forming the first electrode 21 in a tapered shape, film peeling or film cracking of each layer in the first electrode 21 is difficult to occur.
  • ITO having crystallinity is formed and patterned on the first and third subpixels.
  • ITO having crystallinity is highly soluble in an etching solution used for etching the reflective electrode layer.
  • the reflective electrode layer may not be tapered.
  • the a-ITO layers 110 and 112 are formed and the reflective electrode layer 111 is patterned together. Such a problem does not occur because of the conversion to 114.
  • the thickness of the a-ITO layer 117 is made smaller than the thickness of the p-ITO layer 116 (that is, the optical path length 73R in the sub-pixel 71R).
  • the a-ITO layer 117 in the sub-pixel 71R is removed by etching in the process shown in FIG. 1H has been described as an example.
  • a resist pattern is formed on both the sub-pixels 71R and 71G in the step shown in FIG. 1G, and the a-ITO layer 117 in the sub-pixel 71R is not etched away in the step shown in FIG. When leaving, it is not always necessary to set the film thickness of the a-ITO layer 117 to be smaller than the film thickness of the p-ITO layer 116.
  • the p-ITO layer 118 having the same film thickness is formed in each of the sub-pixels 71R and 71G by crystallizing the a-ITO layer 117.
  • the resist pattern 202R is formed only on the sub-pixel 71R in the step shown in FIG. 1D, so that an a-ITO other than the sub-pixel 71R is formed as shown in FIG.
  • the layer 115 is removed, and the a-ITO layer 115 is stacked only on the sub-pixel 71R.
  • the film thickness of the a-ITO layer 112 is set so as to obtain a desired optical path length 73B, and the film thickness of the a-ITO layer 112 (in other words, from the desired optical path length 73G)
  • the film thickness of the a-ITO layer 117 is set to a film thickness obtained by subtracting the film thickness of the p-ITO layer 114), and the film thickness of the a-ITO layer 112 and the film of the a-ITO layer 117 from the desired optical path length 73R.
  • the optical path lengths 73R, 73G, and 73B of the sub-pixels 71R, 71G, and 71B can be set and changed arbitrarily and easily. .
  • the electrode thickness of the a-ITO layer 112 (p-ITO layer 114) is 20 nm
  • the electrode thickness of the a-ITO layer 115 (p-ITO layer 116) is 80 nm
  • the case where the electrode thickness of the a-ITO layer 117 (p-ITO layer 118) is 40 nm has been described as an example.
  • the above specific example is merely an example, and the present embodiment is not limited thereto. is not.
  • the electrode thickness of the a-ITO layer 112 (p-ITO layer 114) can be further increased depending on the design such as the film thickness design of the organic EL layer 43.
  • the adhesive filling resin layer 42 containing a desiccant is formed on the organic EL element 20, whereby the support substrate 10 and the sealing substrate 50 are bonded together.
  • the case where the organic EL element 20 is sealed has been described as an example.
  • the present embodiment is not limited to this.
  • a hollow structure in which an inert gas is sealed in the space may be used.
  • it may have a structure in which a desiccant is applied or pasted in the hollow structure.
  • a desiccant is applied or pasted in the hollow structure.
  • the present embodiment an example in which the organic EL element 20, the sealing resin layer 41, the filling resin layer 42, and the sealing substrate 50 are provided in this order on the support substrate 10 is an example. And explained. However, the present embodiment is not limited to this.
  • an inorganic film (not shown), a mixed organic / inorganic laminated film, or the like may be laminated on the organic EL element 20.
  • the sealing resin layer 41, the sealing substrate 50, and the filling resin layer 42 can be omitted if the sealing performance of the organic EL element 20 is sufficient only with an inorganic film or an organic / inorganic mixed laminated film.
  • the case where the organic EL element 20 is sealed by bonding the support substrate 10 and the sealing substrate 50 through the sealing resin layer 41 formed in the frame shape is an example. And explained.
  • the sealing method of the organic EL element 20 is not limited to this, and for example, frit glass (powder glass) is formed in a frame shape instead of the sealing resin, and the organic EL element 20 is sealed. May be.
  • one pixel 70 is configured by sub-pixels 71R, 71G, and 71B of three colors of R, G, and B has been described as an example.
  • the present embodiment is not limited to this.
  • One pixel 70 may be composed of sub-pixels 71 of three colors other than R, G, and B, such as cyan (C), magenta (M), and yellow (Y).
  • it may be composed of four or more sub-pixels 71 such as four-color sub-pixels 71 obtained by adding Y or the like to R, G, and B.
  • a transparent electrode layer having an arbitrary film thickness can be formed on an arbitrary sub-pixel 71 by stacking transparent electrode layers in each color single layer.
  • the number of transparent electrode layers on the reflective electrode layer 111 is not particularly limited, and can be arbitrarily set.
  • the reflective electrode is formed between the sub-pixels having different display colors by a smaller number of photolithography than the conventional case.
  • the number of transparent electrode layers on the layer and the total film thickness can be changed.
  • the active matrix organic EL display device 100 in which the TFT 12 is formed in each sub-pixel 71 is taken as an example.
  • the present embodiment is not limited to this, and as long as it is not affected by the driving method of the organic EL element 20, the manufacture of a passive matrix organic EL display device in which TFTs are not formed is also possible.
  • the present invention can be applied.
  • the display device using the organic EL element as the light emitting element is described as an example of the display device manufactured in this embodiment.
  • this embodiment is not limited to this, and can be widely applied to display devices using light-emitting elements that can be configured as microresonators such as inorganic EL elements.
  • the organic EL display device 100 according to the present embodiment is the same as that of the first embodiment except that the laminated structure of the first electrode 21 and the method for producing the first electrode 21 shown in step S2 are different from those of the first embodiment. It is. Therefore, in this embodiment, another manufacturing method and a stacked structure of the first electrode 21 shown in step S2 will be described.
  • FIGS. 10A to 10H show an example of processes from the production of the first electrode 21 in the top emission type organic EL display device 100 shown in step S2 to the production of the edge cover shown in step S3. It is sectional drawing shown to process order.
  • FIGS. 10 (a) to (c) are the same as the steps shown in FIGS. 1 (a) to (c). Therefore, the description of the steps shown in FIGS. 10A to 10C is omitted.
  • the p-ITO layer 113, the reflective electrode layer 111, and the p-ITO layer 113 are formed on the support substrate 10 as shown in FIG. 10D.
  • the film thickness of the IZO layer 131 is set to 20 to 60 nm, for example. In this embodiment mode, an IZO layer 131 with a thickness of 40 nm is formed.
  • the p-ITO layer 113, the reflective electrode layer 111, and the p-ITO layer 114 are formed on the IZO layer 131 in the sub-pixel 71R by photolithography in plan view.
  • a resist pattern 202R is formed so as to cover the surface.
  • the IZO layer 131 not masked by the resist pattern 202R is wet-etched using an etching solution, and then the resist pattern 202R is peeled and washed with a resist stripping solution.
  • the etching solution and the stripping solution the same etching solution and stripping solution as the etching solution and stripping solution used in the etching step shown in FIG.
  • oxalic acid is used as the etching solution.
  • the IZO layer 131 can be selectively etched.
  • the p-ITO layers 113 and 114 and the reflective electrode layer 111 are not etched by the etching solution (oxalic acid) or the etching rate is extremely low. Therefore, the p-ITO layers 113 and 114 and the reflective electrode layer 111 remain without being removed by the etching.
  • an IZO that is a transparent electrode layer is formed on the support substrate 10 so as to cover the transparent electrode layer 111 and the reflective electrode layer 111 in each of the sub-pixels 71R, 71G, and 71B.
  • the layer 132 is formed by sputtering, for example.
  • the film thickness of the IZO layer 132 is set to 20 to 60 nm, for example. In this embodiment, the thickness of the IZO layer 132 is 40 nm.
  • the patterned transparent electrode layer 111 and the reflective electrode layer 111 are covered on the IZO layer 132 in the subpixels 71R and 71G by photolithography in plan view. In this manner, resist patterns 203R and 203G are formed.
  • the resist pattern 203G is formed wider than the pattern of the p-ITO layer 113 in the sub-pixels 71R and 71G so as to cover the pattern end of the p-ITO layer 113 below the reflective electrode layer 111 in plan view. did.
  • the amount of protrusion of the resist pattern 203G in plan view from the pattern end of the p-ITO layer 113 was set to 2 ⁇ m, like the resist pattern 202R.
  • the resist pattern 203R was formed wider than the pattern of the IZO layer 131 in the sub-pixels 71R and 71G so as to cover the pattern end of the IZO layer 131 in plan view.
  • the amount of protrusion of the resist pattern 203G in plan view from the pattern end of the IZO layer 131 was set to 2 ⁇ m.
  • the IZO layer 132 not masked with the resist patterns 203R and 203G is wet-etched as shown in FIG. -203G is stripped and washed with a resist stripping solution.
  • the etching solution and the stripping solution the same etching solution and stripping solution as the etching solution and stripping solution used in the etching shown in FIG. Thereby, the IZO layer 132 can be selectively etched.
  • the p-ITO layers 113 and 114 and the reflective electrode layer 111 are not etched with the etching solution (oxalic acid) or the etching rate is extremely slow. Therefore, the p-ITO layers 113 and 114 and the reflective electrode layer 111 remain without being removed by the etching.
  • the reflective electrode layer 111 includes the p-ITO layer 113, which is a transparent electrode layer below the reflective electrode layer 111, and the reflective electrode layer 111.
  • the first electrode 21 surrounded by the p-ITO layer 114 and the IZO layers 131 and 132 which are upper transparent electrode layers is formed.
  • the reflective electrode layer 111 includes a p-ITO layer 113 which is a transparent electrode layer below the reflective electrode layer 111 and a p-ITO layer 114 which is a transparent electrode layer above the reflective electrode layer 111. Then, the first electrode 21 surrounded by the IZO layer 132 is formed.
  • the reflective electrode layer 111 includes a p-ITO layer 113 that is a transparent electrode layer below the reflective electrode layer 111, and a p-ITO layer 114 that is a transparent electrode layer above the reflective electrode layer 111.
  • the first electrode 21 sandwiched between and is formed.
  • the edge cover 15 is formed on the first electrode 21 in each of the sub-pixels 71R, 71G, 71B in step S3.
  • the p-ITO layer 114 and the IZO layers 131 and 132 that are the transparent electrode layers on the reflective electrode layer 111 function as the transparent electrode layer 121 that forms the microcavity.
  • the p-ITO layer 114 and the IZO layers 131 and 132 are formed such that the total film thickness of the p-ITO layer 114 and the IZO layers 131 and 132 becomes the optical path length 73R of the sub-pixel 71R.
  • the thickness is set.
  • the p-ITO layer 114 and the IZO layer 132 which are the transparent electrode layers above the reflective electrode layer 111, function as the transparent electrode layer 121 that forms the microcavity.
  • the film thicknesses of the p-ITO layer 114 and the IZO layer 132 are set so that the total film thickness of the p-ITO layer 114 and the IZO layer 132 becomes the optical path length 73G of the sub-pixel 71G. Yes.
  • the p-ITO layer 114 which is the transparent electrode layer on the reflective electrode layer 111, functions as the transparent electrode layer 121 that forms the microcavity.
  • the film thickness of the p-ITO layer 114 is set so that the film thickness of the p-ITO layer 114 becomes the optical path length 73G of the sub-pixel 71G.
  • the p-ITO layer 114 is formed on the p-ITO layer 114.
  • an IZO layer as a transparent electrode layer having lower etching resistance than that, and selectively etching and patterning the IZO layer by photolithography, the IZO layer can be stacked on an arbitrary subpixel.
  • an IZO layer having a lower etching resistance than the p-ITO layer 114 is formed, and the process of selectively etching and patterning the IZO layer by photolithography is repeated.
  • the IZO layer can be stacked on the sub-pixels.
  • this embodiment is not limited to this, and has a configuration in which a transparent electrode layer such as a p-ITO layer or an IZO layer (not shown) is further stacked on each of the sub-pixels 71R, 71G, and 71B. It may be.
  • a transparent electrode layer such as a p-ITO layer or an IZO layer (not shown) is further stacked on each of the sub-pixels 71R, 71G, and 71B. It may be.
  • the IZO layer 131 is laminated as a single layer in the step shown in FIG. 10D, but at this time, a plurality of layers including the IZO layer 131 having lower etching resistance than the p-ITO layer 114 are used.
  • the transparent electrode layer may be formed.
  • an a-ITO layer may be further formed on the IZO layer 131, and then the resist pattern 202R may be formed on the sub-pixel 71R.
  • the resist pattern 202R may be formed on the sub-pixel 71R after forming the a-ITO layer and the IZO layer in this order.
  • the a-ITO layer is formed as the transparent electrode layer having a lower etching resistance than the p-ITO layer 114 as described above, after the wet etching using the resist pattern 202R as a mask as in the first embodiment. Then, heat treatment may be performed to convert the a-ITO layer into a p-ITO layer.
  • a layer having a lower etching resistance than that of the p-ITO layer is laminated in a single layer or a plurality of layers, and wet etching is performed in the same manner as described above, so that further transparent electrode layers can be stacked. Needless to say, there is.
  • the reflective electrode is formed between the sub-pixels having different display colors by a smaller number of photolithography than the conventional case.
  • the number of transparent electrode layers on the layer and the total film thickness can be changed.
  • the difference in etching selectivity between the transparent electrode layer made of a polycrystalline transparent electrode material and the transparent electrode layer formed on the transparent electrode layer made of the polycrystalline transparent electrode material for example, as described above
  • the transparent electrode layer is stacked by utilizing the difference in etching selectivity between the p-ITO layer and the IZO layer (and the a-ITO layer).
  • the IZO layer 132 having the same film thickness is formed in each of the sub-pixels 71R and 71G.
  • the resist pattern 202R is formed only on the sub-pixel 71R in the step shown in FIG. 10D, so that the IZO layer 131 other than the sub-pixel 71R is formed as shown in FIG.
  • the IZO layer 131 is stacked only on the sub-pixel 71R.
  • the film thickness of the a-ITO layer 112 is set so as to obtain a desired optical path length 73B, and the film thickness of the a-ITO layer 112 (in other words, from the desired optical path length 73G)
  • the film thickness of the IZO layer 131 is set to the film thickness obtained by subtracting the film thickness of the p-ITO layer 114, and the film thickness of the a-ITO layer 112 and the film thickness of the IZO layer 131 are subtracted from the desired optical path length 73R.
  • the optical path lengths 73R, 73G, and 73B of the sub-pixels 71R, 71G, and 71B can be set and changed arbitrarily and easily.
  • the optical path lengths 73R, 73G, and 73B in the sub-pixels 71R, 71G, and 71B can be arbitrarily set by two photolithography without being restricted by the optical path length as in Patent Document 3. It can be easily adjusted.
  • the photo necessary for changing the film thickness (number of layers) of the transparent electrode layer for each of the subpixels 71R, 71G, and 71B As the number of times of lithography, the thickness of the first electrode 21 can be arbitrarily and easily changed for each sub-pixel 71 by performing photolithography twice.
  • the number of times of photolithography can be suppressed to three even if the etching of the reflective electrode layer 111 is included.
  • the p-ITO layer 114 can be formed as a transparent electrode layer also on the reflective electrode layer 111 of the sub-pixel 71B having the shortest optical path length without increasing the number of times of photolithography.
  • the film thickness of the first electrode 21, in other words, the optical path length of the organic EL element 20 can be arbitrarily changed for each sub-pixel 71 by a smaller number of photolithography than the conventional method.
  • the polycrystalline transparent electrode material without converting the transparent electrode layer made of the amorphous transparent electrode material into the transparent electrode layer made of the polycrystalline transparent electrode material, the polycrystalline transparent electrode material.
  • the difference in etching selectivity between the transparent electrode layer made of the transparent electrode layer and the transparent electrode layer formed on the transparent electrode layer made of the polycrystalline transparent electrode material for example, the etching of the p-ITO layer and the IZO layer as described above
  • the transparent electrode layer can be stacked using the difference in selectivity. Therefore, the processing tact can be further shortened.
  • the p-ITO layer formed on the lower layer or the upper layer of the reflective electrode layer 111 is also formed on the terminal portion of the signal line 14 such as the source line in the film forming process of the a-ITO layer.
  • the ITO layer By forming the ITO layer, it can be used as a protective film covering the terminal portion of the signal line 14 such as a source line.
  • the protective film which covers the terminal part of the signal line 14 by laminating
  • the protective film which covers the terminal part of the signal line 14 by laminating
  • Embodiments 1 and 2 differences from Embodiments 1 and 2 will be mainly described, and the same components as those used in Embodiments 1 and 2 have the same functions. A number is assigned and description thereof is omitted.
  • FIG. 11 is a cross-sectional view showing a schematic configuration of the organic EL display panel 1 according to the present embodiment.
  • An exploded sectional view showing a schematic configuration of a main part of the organic EL display device 100 according to the present embodiment is the same as FIG. 2, and a plan view showing a schematic configuration of the support substrate 10 in the organic EL display device 100 is a diagram. Same as 3.
  • the top view which shows the structure of the principal part of display area R1 in the support substrate 10 is the same as FIG.
  • FIG. 11 corresponds to a cross-sectional view showing a schematic configuration of the organic EL display panel 1 when the organic EL display panel 1 is cut along the line AA shown in FIG.
  • the method for forming the first electrode 21 shown in Embodiments 1 and 2 uses a separate coating method in which vapor deposition is performed for each color of the light emitting layer, so that a plurality of light emitting layers having different light emitting colors can be formed in the same plane. The same applies to the formation.
  • the organic EL element 20 including the light emitting layers 82R, 82G, and 82B for each color of RGB includes sub-pixels 71R, 71G, and 71B is arranged on the support substrate 10.
  • the TFT 12 is used to perform color image display by selectively causing the organic EL elements 20 to emit light with a desired luminance.
  • a plurality of light emitting layers 82R, 82G, and 82B having different emission colors are formed in the same plane as described above, and a microcavity structure is formed in each of the sub-pixels 71R, 71G, and 71B having different emission colors.
  • the CF layer 52 can be used to adjust the spectrum of light emitted from the organic EL element 20 as shown in FIG.
  • the organic EL display device 100 according to the present embodiment is the same as the organic EL display device 100 shown in FIG. 5 except that the stacked structure of the organic EL layer 43 in the organic EL element 20 is different as shown in FIG. It has a configuration.
  • Organic EL Element 20 In the organic EL display device 100 shown in FIG. 11, between the first electrode 21 and the second electrode 31, as the organic EL layer 43, for example, from the first electrode 21 side, for example, a hole injection layer / hole transport layer 81.
  • the light emitting layers 82R, 82G, and 82B and the electron transport layer / electron injection layer 83 are configured in this order.
  • the hole injection layer / hole transport layer and the electron transport layer / electron injection layer are as described in the first embodiment.
  • the hole injection layer / hole transport layer 81 and the electron transport layer / electron Description of the injection layer 83 is omitted.
  • the hole injection layer / hole transport layer 81 is uniformly formed over the entire surface of the display region R ⁇ b> 1 on the support substrate 10 so as to cover the first electrode 21 and the edge cover 15. .
  • light emitting layers 82R, 82G, and 82B are formed corresponding to the sub-pixels 71R, 71G, and 71B, respectively.
  • the light emitting layers 82R, 82G, and 82B emit light by recombining holes injected from the first electrode 21 side with electrons injected from the second electrode 31 side. Also in the present embodiment, the light emitting layers 82R, 82G, and 82B are each formed of a material having high luminous efficiency, such as a low molecular fluorescent dye or a metal complex.
  • the electron transport layer / electron injection layer 83 covers the light emitting layers 82R / 82G / 82B and the hole injection layer / hole transport layer 81 so as to cover the light emitting layers 82R / 82G / 82B and the hole injection layer / hole transport layer 81. On the upper surface, it is uniformly formed over the entire surface of the display region R1 in the support substrate 10.
  • the hole injection layer / hole transport layer 81 is provided as the hole injection layer and the hole transport layer is illustrated as an example, and the electron transport layer and As an electron injection layer, the case where an electron transport layer / electron injection layer 83 is provided is shown as an example.
  • this embodiment is not limited to this, and the hole injection layer and the hole transport layer may be formed as independent layers.
  • the electron transport layer and the electron injection layer may be formed as independent layers.
  • the organic layers other than the light emitting layers 82R, 82G, and 82B are not essential layers as the organic EL layer 43, and may be appropriately formed according to the required characteristics of the organic EL element 20.
  • one layer may have a plurality of functions.
  • a carrier blocking layer can be added to the organic EL layer 43 as necessary.
  • a hole blocking layer as a carrier blocking layer between the light emitting layers 82R, 82G, and 82B and the electron transport layer / electron injection layer 83, holes escape to the electron transport layer / electron injection layer 83. Can be prevented and the luminous efficiency can be improved.
  • layers other than the first electrode 21 (anode), the second electrode 31 (cathode), and the light emitting layers 82R, 82G, and 82B may be inserted as appropriate.
  • First electrode / light emitting layer / second electrode (2) First electrode / hole transport layer / light emitting layer / electron transport layer / second electrode (3) First electrode / hole transport layer / light emitting layer / Hole blocking layer / electron transport layer / second electrode (4) first electrode / hole transport layer / light emitting layer / hole blocking layer / electron transport layer / electron injection layer / second electrode (5) first electrode / Hole injection layer / hole transport layer / light emitting layer / electron transport layer / electron injection layer / second electrode (6) first electrode / hole injection layer / hole transport layer / light emitting layer / hole blocking layer / electron Transport layer / second electrode (7) first electrode / hole injection layer / hole transport layer / light emitting layer / hole blocking layer / electron transport layer / electron injection layer / second electrode (8) first electrode / positive Hole injection layer / hole transport layer / second electrode (2) First electrode / hole transport layer / light emitting layer / electron transport layer / second electrode (3) First electrode /
  • the outline of the manufacturing process flow of the organic EL display device 100 is as described with reference to FIG. Even in the present embodiment, when the first electrode 21 is a cathode and the second electrode 31 is an anode, the material and thickness of the first electrode 21 and the second electrode 31 are reversed.
  • FIG. 12 is a flowchart illustrating an example of a manufacturing process of the organic EL layer 43 illustrated in FIG. 11 in the order of processes.
  • the support substrate 10 that has been subjected to oxygen plasma treatment as a vacuum bake for dehydration and surface cleaning of the first electrode 21 in step S4 shown in FIG.
  • the hole injection layer / hole transport layer 81 (hole injection layer / hole transport layer) is applied to the entire surface of the display region R1 of the support substrate 10 so as to cover the first electrode 21 and the edge cover 15.
  • a pattern is formed by a vacuum deposition method (step S31).
  • the hole injection / hole transport layer 81 is uniformly formed over the entire surface of the display region R1 in the support substrate 10. Therefore, like the hole injection layer 22 and the hole transport layer 23 in the first embodiment, film formation is performed using an open mask in which the entire surface of the display region R1 is opened as a mask for vapor deposition.
  • the organic EL element 20 is selectively made to emit light with a desired luminance by using the TFT 12. Display an image.
  • the organic EL display device 100 it is necessary to form the light emitting layers 82R, 82G, and 82B made of organic light emitting materials that emit light of each color in a predetermined pattern for each organic EL element 20. .
  • the light-emitting layers 82R, 82G, and 82B are formed by separate vapor deposition by a vacuum vapor deposition method using a fine mask having an opening only in a region where a light emitting material of a desired display color is vapor-deposited as a vapor deposition mask ( Step S32). Thereby, a pattern film corresponding to each of the sub-pixels 71R, 71G, and 71B is formed.
  • an electron transport layer / electron injection layer is formed on the support substrate 10 on which the light emitting layers 82R, 82G, and 82B are formed, using an open mask having the entire display region R1 opened as a mask for vapor deposition, by a vacuum vapor deposition method.
  • 83 (electron transport layer / electron injection layer) (step S33) and the second electrode 31 (step S5) are sequentially formed on the entire surface of the pixel region.
  • a vacuum deposition apparatus similar to the conventional one can be used for the vapor deposition. Note that conditions such as a preferable vacuum arrival rate are as described in the first embodiment. Therefore, the details and illustration of the vacuum vapor deposition apparatus and the vapor deposition method are omitted.
  • the material and film thickness of the hole injection layer / hole transport layer and electron transport layer / electron injection layer used as the hole injection layer / hole transport layer 81 and the electron transport layer / electron injection layer 83 Is as described in the first embodiment.
  • each of the light emitting layers 82R, 82G, and 82B may be made of a single material having a different emission color.
  • the film thickness of the light emitting layers 82R, 82G, and 82B is, for example, 10 to 100 nm.
  • the first electrode 21 has a laminated structure of the reflective electrode layer 111 and the transparent electrode layer 121 as in the first embodiment, so that the organic EL element 20 has a microcavity.
  • the structure is introduced.
  • the thicknesses of the light emitting layers 82R, 82G, and 82B are set to the same thickness.
  • the optical path lengths 73R, 73G, and 73B are set as in the first and second embodiments.
  • the materials and film thicknesses of the hole injection / hole transport layer 81, the electron transport / electron injection layer 83, and the light-emitting layers 82R, 82G, and 82B can be set in the same manner as in the past. For this reason, in the present embodiment, description of specific materials and film thicknesses of the hole injection layer / hole transport layer 81, the electron transport layer / electron injection layer 83, and the light emitting layers 82R, 82G, and 82B is omitted. .
  • the first electrode 21 has a laminated structure of the reflective electrode layer 111 and the transparent electrode layer 121, so that the organic EL element 20 has a microcavity structure. It has been introduced.
  • the light emitting layers 82R, 82G, and 82B can be formed to have the same thin film thickness as in the case of using the W light emitting layer as in the first to seventh embodiments. Therefore, the processing tact can be shortened.
  • the organic EL element 20 can obtain light in which the microcavity effect is added to the mixture of the light emitted from the light emitting layers 82R, 82G, and 82B. Further, by adjusting the light by the CF layer 52 provided on the sealing substrate 50, light having a desired spectrum can be extracted to the outside. Therefore, also in this embodiment, color purity can be improved by combining the light emitting layers 82R, 82G, and 82B, the microcavity effect, and the CF layer 52 using the separate coating method.
  • the thickness of the transparent electrode layer 121 in the first electrode 21 is changed for each of the sub-pixels 71R, 71G, and 71B in the same manner as in the first and second embodiments. Needless to say, the same effect as 2 can be obtained.
  • the first transparent electrode layer made of an amorphous transparent electrode material is formed over the reflective electrode layer and etched together. After that, the first transparent electrode layer made of the amorphous transparent electrode material is converted into the first transparent electrode layer made of the polycrystalline transparent electrode material, and the second transparent electrode layer formed thereon is formed.
  • This is a method of changing the total film thickness of the transparent electrode layer between the sub-pixels by laminating the transparent electrode layer using the difference in etching resistance.
  • one electrode of the pair of electrodes that form an electric field in each subpixel is formed on the reflective electrode layer and the reflective electrode layer.
  • At least one transparent electrode layer, and a plurality of the transparent electrode layers are formed on the reflective electrode layer in at least one sub-pixel, and the entire transparent electrode layer is arranged between sub-pixels having different display colors.
  • a method of manufacturing a display device having different film thicknesses the step of forming a reflective electrode layer, and the formation of a first transparent electrode layer made of an amorphous transparent electrode material above the reflective electrode layer
  • a first transparent electrode layer forming step and a patterning step of patterning the first transparent electrode layer made of the amorphous transparent electrode material and the reflective electrode layer together by photolithography.
  • a first transparent electrode layer crystal that crystallizes the first transparent electrode layer made of the amorphous transparent electrode material patterned in the patterning step and converts it into a first transparent electrode layer made of a polycrystalline transparent electrode material.
  • a second electrode made of a transparent electrode material having lower etching resistance than the first transparent electrode layer made of the polycrystalline transparent electrode material on the first transparent electrode layer made of the polycrystalline transparent electrode material.
  • the transparent electrode layer is laminated on the reflective electrode layer in each subpixel, and the film thickness of the transparent electrode layer on the reflective electrode layer is arbitrarily changed between the subpixels having different display colors.
  • the number of times of photolithography can be reduced.
  • the second transparent electrode layer stacking step is performed a plurality of times by changing subpixels forming the resist pattern, and the second transparent electrode layer is selected by photolithography.
  • patterning is performed by etching, a resist pattern is formed only on one subpixel, and the second transparent electrode layer is etched using the resist pattern as a mask. It is preferable to include the process of forming the pattern of 2 transparent electrode layers.
  • the number of photolithography required to change the total film thickness of the transparent electrode layer is two photolithography, and the total film thickness of the transparent electrode layer is
  • the thickness of the second transparent electrode layer in any sub-pixel can be set independently of the thickness of the second transparent electrode layer in other sub-pixels. It becomes possible.
  • the optical path length in each sub-pixel can be adjusted arbitrarily and easily.
  • the second transparent electrode layer is a transparent electrode layer made of an amorphous transparent electrode material
  • the second transparent electrode layer laminating step includes the amorphous electrode layer.
  • a second transparent electrode layer forming step for forming a second transparent electrode layer made of a transparent electrode material, and patterning by etching the second transparent electrode layer made of the amorphous transparent electrode material by photolithography The second transparent electrode layer patterning step and the patterned second transparent electrode layer made of the amorphous transparent electrode material are crystallized to be converted into a second transparent electrode layer made of a polycrystalline transparent electrode material.
  • the transparent electrode layer made of a transparent electrode material polycrystalline be any number lamination.
  • the transparent electrode layer using the difference in etching selectivity between the transparent electrode layer made of an amorphous transparent electrode material and the transparent electrode layer made of a polycrystalline transparent electrode material is used. Stack up.
  • the film thickness of each transparent electrode layer can be set independently of the film thickness of the transparent electrode layer in other subpixels, and the optical path length in each subpixel can be set arbitrarily and It can be adjusted easily.
  • the first and second transparent electrode layers are preferably indium tin oxide.
  • Amorphous indium tin oxide can be easily converted to polycrystalline indium tin oxide by heat treatment.
  • the polycrystalline indium tin oxide has higher etching resistance than the amorphous indium tin oxide, and the amorphous indium tin oxide etching step (second transparent electrode layer patterning step, second transparent electrode layer lamination) In step (5), etching is not performed or the etching rate is extremely low. For this reason, only the amorphous indium tin oxide can be selectively etched in the etching process of amorphous indium tin oxide.
  • the reflective electrode layer and the polycrystalline transparent electrode material are formed on the second transparent electrode layer made of the amorphous transparent electrode material in a plan view.
  • a resist pattern is formed which overlaps with the first transparent electrode layer and is larger than the first transparent electrode layer made of the reflective electrode layer and the polycrystalline transparent electrode material in plan view, the resist pattern It is preferable that the second transparent electrode layer is etched and patterned using as a mask.
  • the reflective electrode layer is in an exposed state (that is, an exposed state), for example, when ultraviolet irradiation is performed to increase the wettability of the resist, it is oxidized and the reflection specification is reduced. The solvent resistance is low, and there is a possibility that the solvent may penetrate. For this reason, when such a reflective electrode layer consists of such a reflective electrode material, it is not desirable that the reflective electrode layer is exposed.
  • the reflective electrode layer can be surrounded by the first transparent electrode layer and the second transparent electrode layer made of a polycrystalline transparent electrode material, at the time of manufacturing the display device, The reflective electrode layer can be protected from the above factors that may impair the quality of the reflective electrode layer.
  • the second transparent electrode layer is preferably a layer made of a transparent electrode material having a composition different from that of the first transparent electrode layer.
  • the 1st transparent electrode layer which consists of a polycrystalline transparent electrode material without converting the transparent electrode layer which consists of an amorphous transparent electrode material into the transparent electrode layer which consists of a polycrystalline transparent electrode material
  • the transparent electrode layers can be stacked using the difference in etching selectivity due to the difference in etching resistance between the second transparent electrode layer and the second transparent electrode layer.
  • the first transparent electrode layer is indium tin oxide and the second transparent electrode layer is indium zinc oxide.
  • Amorphous indium tin oxide can be easily converted to polycrystalline indium tin oxide by heat treatment.
  • Polycrystalline indium tin oxide has higher etching resistance than indium zinc oxide, and when etching indium zinc oxide in the second transparent electrode layer etching step (second transparent electrode layer stacking step), It is not etched or the etching rate is extremely slow. For this reason, in the etching process of the second transparent electrode layer, only the second transparent electrode layer made of indium zinc oxide is selectively etched.
  • the reflective electrode layer and the first transparent electrode layer made of the polycrystalline transparent electrode material are overlapped with each other in a plan view, and the reflective electrode layer is seen in a plan view.
  • the second transparent electrode layer is preferably etched using a resist pattern formed larger than the first transparent electrode layer made of the polycrystalline transparent electrode material as a mask.
  • the reflective electrode layer can be surrounded by a first transparent electrode layer and a second transparent electrode layer made of a polycrystalline transparent electrode material.
  • the reflective electrode layer is preferably made of any one selected from the group consisting of silver, a silver alloy, and an aluminum alloy.
  • the pair of electrodes is an anode and a cathode
  • the one electrode is an anode
  • the anode, the cathode, and the anode, the cathode, and the organic electroluminescence layer are sandwiched between the anode and the cathode. It is preferable to form an organic electroluminescence layer.
  • the optical path length of the organic electroluminescence element in which the organic electroluminescence layer is sandwiched between the anode and the cathode can be easily changed for each sub-pixel having a different emission color.
  • an organic electroluminescence element having a microcavity structure can be obtained. Therefore, due to the microcavity effect, color purity, light emission chromaticity, light emission efficiency, and the like in a display device using the organic electroluminescence element can be improved.
  • one electrode of the pair of electrodes forming an electric field in each subpixel is formed on the reflective electrode layer and the reflective electrode layer.
  • a plurality of transparent electrode layers are formed on the reflective electrode layer in at least one subpixel, and the entire transparent electrode layer is arranged between subpixels having different display colors.
  • the plurality of transparent electrode layers have different compositions, and the etching resistance of the lower transparent electrode layer is higher than the etching resistance of the upper transparent electrode layer.
  • the lower transparent electrode layer is preferably made of polycrystalline indium tin oxide
  • the upper transparent electrode layer is preferably made of indium zinc oxide.
  • Amorphous indium tin oxide can be easily converted to polycrystalline indium tin oxide by heat treatment.
  • Polycrystalline indium tin oxide has higher etching resistance than indium zinc oxide, and is not etched or has a significantly slower etching rate when etching indium zinc oxide. For this reason, only the transparent electrode layer made of indium zinc oxide can be selectively etched.
  • the reflective electrode layer is preferably made of any one selected from the group consisting of silver, a silver alloy, and an aluminum alloy.
  • the reflective electrode layer is made of the reflective electrode material, there is no such fear. Therefore, the reflective electrode material is suitable for the reflective electrode material in the reflective electrode layer.
  • the upper transparent electrode layer covers a surface of the lower transparent electrode layer and a side surface of the reflective electrode layer.
  • the reflective electrode layer is in an exposed state (that is, an exposed state), for example, when ultraviolet irradiation is performed to increase the wettability of the resist, it is oxidized and the reflection specification is reduced. The solvent resistance is low, and there is a possibility that the solvent may penetrate. For this reason, when such a reflective electrode layer consists of such a reflective electrode material, it is not desirable that the reflective electrode layer is exposed.
  • the present invention can be suitably used for a display device using a light emitting element that can be configured as a microresonator such as an organic EL element or an inorganic EL element, and a manufacturing method thereof.
  • a light emitting element that can be configured as a microresonator such as an organic EL element or an inorganic EL element, and a manufacturing method thereof.
  • Organic EL Display Panel 2 Electrical Wiring Terminal 10 Support Substrate 11 Insulating Substrate 12 TFT 13 Interlayer Insulating Film 13a Contact Hole 14 Signal Line 15 Edge Cover 15R / 15G / 15B Opening 20 Organic EL Element 21 First Electrode 22 Hole Injection Layer 23 Hole Transport Layer 24 First Light-Emitting Layer 25 Electron Transport Layer 26 Carrier Generation Layer 27 hole transport layer 28 second light emitting layer 29 electron transport layer 30 electron injection layer 31 second electrode 41 sealing resin layer 42 filling resin layer 43 organic EL layer 50 sealing substrate 51 insulating substrate 52 CF layer 53 BM 60 connection portion 70 pixel 71 sub pixel 71R / 71G / 71B sub pixel 72 light emitting region 73R / 73G / 73B optical path length 81 hole injection layer / hole transport layer 82R / 82G / 82B light emission layer 83 electron transport layer / electron injection layer 100 Organic EL display device 101 Pixel unit 102 Circuit unit 103 Connection terminal 110 a-ITO layer 111 Reflect

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Abstract

An a-ITO layer (112) is formed above a reflection electrode layer (111) and the layers are etched together; the a-ITO layer (112) is then converted to a p-ITO layer (114); and the difference in etching resistance between the p-ITO layer (114) and a transparent electrode layer formed above the p-ITO layer is used to layer the transparent electrode layer and to vary the thickness of the transparent electrode layer (121) between subpixels (71R, 71G, 71B).

Description

表示装置の製造方法および表示装置Display device manufacturing method and display device
 本発明は、各サブ画素における反射電極層上に透明電極層が積層されているとともに、表示色が異なるサブ画素間で透明電極層の合計の膜厚が異なっている表示装置の製造方法およびそのような表示装置に関するものである。 The present invention relates to a method for manufacturing a display device in which a transparent electrode layer is laminated on a reflective electrode layer in each sub-pixel, and the total film thickness of the transparent electrode layer is different between sub-pixels having different display colors, and It is related with such a display apparatus.
 近年、様々な商品や分野でフラットパネルディスプレイが活用されており、フラットパネルディスプレイのさらなる大型化、高画質化、低消費電力化が求められている。 In recent years, flat panel displays have been used in various products and fields, and further flat panel displays are required to have larger sizes, higher image quality, and lower power consumption.
 そのような状況下において、有機材料の電界発光(Electro Luminescence:エレクトロルミネッセンス、以下「EL」と記す)を利用した有機EL素子を備えた有機EL表示装置は、全固体型で、低電圧駆動、高速応答性、自発光性、広視野角特性等の点で優れたフラットパネルディスプレイとして、高い注目を浴びている。 Under such circumstances, an organic EL display device including an organic EL element using electroluminescence of an organic material (Electro-Luminescence: hereinafter referred to as “EL”) is an all-solid-state type, driven at a low voltage, As a flat panel display excellent in terms of high-speed response, self-luminous property, wide viewing angle characteristics, etc., it is attracting a lot of attention.
 有機EL表示装置は、例えば、TFT(Thin Film Transistor:薄膜トランジスタ)が設けられたガラス基板等からなる基板上に、TFTに電気的に接続された有機EL素子が設けられた構成を有している。 An organic EL display device has, for example, a configuration in which an organic EL element electrically connected to a TFT is provided on a substrate made of a glass substrate provided with a TFT (Thin Film Transistor). .
 有機EL素子は、低電圧直流駆動による高輝度発光が可能な発光素子であり、第1電極、有機EL層、第2電極が、この順に積層された構造を有している。 The organic EL element is a light-emitting element that can emit light with high luminance by low-voltage direct current drive, and has a structure in which a first electrode, an organic EL layer, and a second electrode are stacked in this order.
 このような有機EL素子を用いた有機EL表示装置をフルカラー化するための方式としては、例えば、(1)赤(R)、緑(G)、青(B)に発光する有機EL素子をサブ画素として基板上に配列する方式、(2)白色発光の有機EL素子とカラーフィルタとを組み合わせて各サブ画素における発光色を選択する方式が知られている。 As a method for full-coloring an organic EL display device using such an organic EL element, for example, (1) an organic EL element that emits red (R), green (G), and blue (B) is used as a sub-color. A method of arranging pixels on a substrate and (2) a method of selecting a light emission color in each sub-pixel by combining a white light emitting organic EL element and a color filter are known.
 近年、これらの方式において、マイクロキャビティ効果により発光の色度や発光効率を向上させる方法が提案されている(例えば、特許文献1、2参照)。 Recently, in these methods, methods for improving the chromaticity of light emission and light emission efficiency by the microcavity effect have been proposed (for example, see Patent Documents 1 and 2).
 マイクロキャビティとは、発光した光が陽極と陰極との間で多重反射し、共振することで発光スペクトルが急峻になり、また、ピーク波長の発光強度が増幅される現象である。 The microcavity is a phenomenon in which emitted light undergoes multiple reflections between the anode and the cathode and resonates, resulting in a steep emission spectrum and amplification of the emission intensity at the peak wavelength.
 マイクロキャビティ効果は、例えば、陽極や陰極の反射率および膜厚、有機層の層厚等を最適に設計することで得ることができる。 The microcavity effect can be obtained, for example, by optimally designing the reflectance and film thickness of the anode and cathode, the layer thickness of the organic layer, and the like.
 有機EL素子に、このような共振構造、つまりマイクロキャビティ構造を導入する方法としては、例えば、発光色毎に各サブ画素における有機EL素子の光路長を変える方法が知られている。 As a method for introducing such a resonance structure, that is, a microcavity structure into an organic EL element, for example, a method of changing the optical path length of the organic EL element in each sub-pixel for each emission color is known.
 発光色毎に各サブ画素における有機EL素子の光路長を変える方法としては、反射電極と半透明電極との間に、発光層を含む有機EL層と透明電極層とを積層する方法が挙げられる。 As a method of changing the optical path length of the organic EL element in each sub-pixel for each emission color, a method of laminating an organic EL layer including a light emitting layer and a transparent electrode layer between a reflective electrode and a semitransparent electrode can be mentioned. .
 すなわち、例えば、トップエミッション型の有機EL素子の場合、陽極を、反射電極層と透明電極層との積層構造とし、サブ画素毎に、陽極の反射電極層上の透明電極層の膜厚を変える方法が挙げられる。 That is, for example, in the case of a top emission type organic EL element, the anode has a laminated structure of a reflective electrode layer and a transparent electrode layer, and the film thickness of the transparent electrode layer on the reflective electrode layer of the anode is changed for each subpixel. A method is mentioned.
 トップエミッション型の有機EL素子の場合、このように陽極を、反射電極層と透明電極層との積層構造とし、有機EL層を適宜積層した後、陰極に、半透明電極として、例えば薄膜にした半透明の銀等を用いることで、有機EL素子にマイクロキャビティ構造を導入することができる。 In the case of a top emission type organic EL element, the anode has a laminated structure of a reflective electrode layer and a transparent electrode layer as described above, and after the organic EL layer is appropriately laminated, the cathode is made into a thin film, for example, as a semitransparent electrode. By using translucent silver or the like, a microcavity structure can be introduced into the organic EL element.
 このように有機EL素子にマイクロキャビティ構造を導入すると、発光層から発光され、陰極を通して出射された光のスペクトルは、有機EL素子がマイクロキャビティ構造を有していない場合よりも急峻になり、また、正面への出射強度が大きく増大する。 When the microcavity structure is introduced into the organic EL element as described above, the spectrum of light emitted from the light emitting layer and emitted through the cathode becomes steeper than when the organic EL element does not have the microcavity structure. The intensity of light emitted to the front is greatly increased.
 特許文献1、2には、同一材料の透明電極層を、サブ画素毎に積層数を変えて積層することで有機EL素子にマイクロキャビティ構造を導入した有機EL表示装置が開示されている。 Patent Documents 1 and 2 disclose an organic EL display device in which a microcavity structure is introduced into an organic EL element by laminating transparent electrode layers of the same material while changing the number of laminated layers for each sub-pixel.
日本国公開特許公報「特開2007-280677号公報(2007年10月25日公開)」Japanese Patent Publication “Japanese Patent Laid-Open No. 2007-280677 (published on Oct. 25, 2007)” 日本国公開特許公報「特開2005-116516号公報(2005年4月28日公開)」Japanese Patent Publication “Japanese Patent Laid-Open No. 2005-116516 (published April 28, 2005)” 日本国公開特許公報「特開2009-129604号公報(2009年6月11日公開)」Japanese Patent Publication “JP 2009-129604 A” (published on June 11, 2009)
 しかしながら、上記したように透明電極層の膜厚を変えることでマイクロキャビティ効果を変化させ、発光色を調整する方式の有機EL表示装置では、透明電極層の膜厚を各色のサブ画素毎に適切に変更する方法は、これまで知られていない。 However, in the organic EL display device that adjusts the emission color by changing the microcavity effect by changing the film thickness of the transparent electrode layer as described above, the film thickness of the transparent electrode layer is appropriately set for each sub-pixel of each color. The method of changing to is not known so far.
 なお、特許文献1には、各色のサブ画素毎に透明電極の膜厚を変更するための方法は開示されていない。 Note that Patent Document 1 does not disclose a method for changing the film thickness of the transparent electrode for each sub-pixel of each color.
 一方、特許文献2には、積層する透明電極層に同一材料を使用して各色のサブ画素毎に透明電極の膜厚を変更する方法として、以下の方法が開示されている。 On the other hand, Patent Document 2 discloses the following method as a method of changing the film thickness of the transparent electrode for each sub-pixel of each color using the same material for the transparent electrode layer to be laminated.
 まず、レジストパターンを積層するサブ画素を、B→G→Rの順に変更しながら、反射電極層上に、透明電極層とレジストパターンとを交互に積層する。 First, transparent electrode layers and resist patterns are alternately laminated on the reflective electrode layer while changing the subpixels on which the resist pattern is laminated in the order of B → G → R.
 次いで、Rのサブ画素にレジストパターンを積層した後、Rのサブ画素のレジストパターンをマスクとして最上層の透明電極層をエッチングし、Gのサブ画素のレジストパターンが露出したところで、RおよびGのサブ画素のレジストパターンをマスクにして、上から2番目の透明電極層をエッチングする。 Next, after a resist pattern is stacked on the R subpixel, the uppermost transparent electrode layer is etched using the resist pattern of the R subpixel as a mask, and when the resist pattern of the G subpixel is exposed, Using the resist pattern of the subpixel as a mask, the second transparent electrode layer from the top is etched.
 その後、Bのサブ画素のレジストパターンが露出したところで、R、G、Bのサブ画素のレジストパターンをマスクにして、最下層の透明電極層をエッチングすることで、全ての透明電極層をパターン形成する。 After that, when the resist pattern of the B sub-pixel is exposed, all the transparent electrode layers are patterned by etching the transparent electrode layer of the lowermost layer using the resist pattern of the R, G, and B sub-pixels as a mask. To do.
 最後に、R、G、Bのサブ画素のレジストパターンをマスクにして、反射電極層をエッチングしてパターニングする。 Finally, the reflective electrode layer is etched and patterned using the resist pattern of the R, G, and B subpixels as a mask.
 しかしながら、特許文献2では、レジストパターン上に透明電極層を積層するため、レジストと透明電極層との密着性が十分でないと、処理中に透明電極層の膜剥がれが生じて、パターン不良や工程汚染を招く危険性がある。 However, in Patent Document 2, since the transparent electrode layer is laminated on the resist pattern, if the adhesiveness between the resist and the transparent electrode layer is not sufficient, film peeling of the transparent electrode layer occurs during the processing, resulting in a pattern defect or a process. There is a risk of contamination.
 また、レジストが積層された基板をスパッタ装置内に投入すると、ゴミ等の異物が付着し、歩留が低下するおそれがあるとともに、欠陥や膜厚ムラ、膜質ムラ(光学的性質の面内分布)を引き起こす可能性がある。 In addition, if a substrate with a resist layer is put into the sputtering apparatus, foreign substances such as dust adhere to it, which may reduce the yield, and defects, film thickness unevenness, film quality unevenness (in-plane distribution of optical properties) ).
 また、特許文献2に記載されているようにレジストパターン上に透明電極を積層する場合、レジストパターンの厚みが厚いと、レジストパターンの陰になる部分が大きくなり、この陰になる部分で透明電極層に欠陥が生じたり、膜厚ムラが発生したりするおそれがある。このため、透明電極層を各色のサブ画素に最適な膜厚に設定することは困難であり、また、高精細のパターンでサブ画素を形成することができない。 In addition, when a transparent electrode is laminated on a resist pattern as described in Patent Document 2, if the thickness of the resist pattern is thick, a portion that is shaded by the resist pattern becomes large. There is a possibility that defects may occur in the layer or unevenness in film thickness may occur. For this reason, it is difficult to set the transparent electrode layer to an optimum film thickness for each color sub-pixel, and the sub-pixel cannot be formed with a high-definition pattern.
 このため、透明電極層を単純に積層するだけでは、各色のサブ画素毎に透明電極の膜厚を変更することは困難である。 For this reason, it is difficult to change the film thickness of the transparent electrode for each sub-pixel of each color by simply laminating the transparent electrode layer.
 各色のサブ画素毎に透明電極の膜厚を変更する方法としては、例えば、以下の方法が考えられる。 As a method of changing the film thickness of the transparent electrode for each sub-pixel of each color, for example, the following method can be considered.
 図13の(a)~(f)は、サブ画素毎に、陽極の反射電極層上の透明電極層の膜厚を変更する方法の一例を、工程順に示す断面図である。 FIGS. 13A to 13F are cross-sectional views showing an example of a method for changing the film thickness of the transparent electrode layer on the reflective electrode layer of the anode for each sub-pixel in the order of steps.
 以下に、図13の(a)~(f)を参照して、上記したようにサブ画素毎に、陽極の反射電極層上の透明電極層の膜厚を変更する方法について説明する。 Hereinafter, a method for changing the thickness of the transparent electrode layer on the reflective electrode layer of the anode for each sub-pixel will be described with reference to FIGS. 13A to 13F.
 まず、図13の(a)に示すように、支持基板301上に、銀(Ag)等の反射電極材料からなる反射電極層302を、スパッタリング法等により成膜する。 First, as shown in FIG. 13A, a reflective electrode layer 302 made of a reflective electrode material such as silver (Ag) is formed on a support substrate 301 by a sputtering method or the like.
 次いで、上記反射電極層302上に、各色のサブ画素毎に、フォトリソグラフィにより図示しないレジストパターンを形成し、これらレジストパターンをマスクとして反射電極層302をエッチングした後、これらレジストパターンを、レジスト剥離液により剥離洗浄する。 Next, a resist pattern (not shown) is formed by photolithography on each of the sub-pixels of each color on the reflective electrode layer 302. After etching the reflective electrode layer 302 using the resist pattern as a mask, the resist pattern is removed from the resist. Remove and clean with liquid.
 これにより、図13の(b)に示すように、反射電極層302を、各色のサブ画素毎に分離するようにパターニングする。 Thereby, as shown in FIG. 13B, the reflective electrode layer 302 is patterned so as to be separated for each sub-pixel of each color.
 次に、図13の(c)に示すように、反射電極層302上に、透明電極層として例えばIZO(Indium Zinc Oxide:インジウム亜鉛酸化物)を成膜してIZO層303を形成し、フォトリソグラフィにより、Rのサブ画素のみにフォトレジスト311を形成する。 Next, as shown in FIG. 13C, on the reflective electrode layer 302, for example, an IZO (Indium Zinc Oxide) film is formed as a transparent electrode layer to form an IZO layer 303. A photoresist 311 is formed only on the R subpixel by lithography.
 次いで、図13の(d)に示すように、シュウ酸により、露出しているIZO層303をエッチングして除去した後、フォトレジスト311を剥離することで、Rのサブ画素にのみ、第1のIZO層として、パターン化されたIZO層303を形成する。 Next, as shown in FIG. 13D, the exposed IZO layer 303 is removed by etching with oxalic acid, and then the photoresist 311 is peeled off, so that only the first sub-pixel of the R is removed. A patterned IZO layer 303 is formed as the IZO layer.
 その後、図13の(e)に示すように、Rのサブ画素のIZO層303、並びに、GおよびBのサブ画素の反射電極層302を覆うように再びIZOを成膜してIZO層304を形成し、さらに、フォトリソグラフィにより、RおよびGのサブ画素のみにフォトレジスト312を形成する。 Thereafter, as shown in FIG. 13E, an IZO film is formed again so as to cover the IZO layer 303 of the R subpixel and the reflective electrode layer 302 of the G and B subpixels, and the IZO layer 304 is formed. Further, a photoresist 312 is formed only on the R and G subpixels by photolithography.
 その後、図13の(f)に示すように、フォトレジスト312をマスクとしてシュウ酸によりIZO層304をエッチングし、フォトレジスト312を剥離することで、サブ画素RおよびGに第2のIZO層として、パターン化されたIZO層304を形成する。 Thereafter, as shown in FIG. 13F, the IZO layer 304 is etched with oxalic acid using the photoresist 312 as a mask, and the photoresist 312 is peeled off to form a second IZO layer on the sub-pixels R and G. Then, a patterned IZO layer 304 is formed.
 このように、マイクロキャビティ効果を得るために、サブ画素毎に透明電極層の積層数を変えようとすると、例えば、サブ画素がR、G、Bのサブ画素からなる場合、少なくとも3回のフォトリソグラフィおよびエッチング、レジスト剥離が必要となる。 Thus, in order to obtain the microcavity effect, if the number of transparent electrode layers stacked is changed for each sub-pixel, for example, when the sub-pixel is composed of R, G, and B sub-pixels, at least three photo Lithography, etching, and resist stripping are required.
 言い換えれば、陽極の反射電極層上の透明電極層の膜厚をサブ画素毎に変更するためには、図13の(a)~(f)に示すように、フォトリソグラフィが3回必要となる。なお、反射電極層のパターニングを含めれば、フォトリソグラフィが4回必要となる。また、図13の(f)において、Bの画素にさらに透明電極層を形成する場合には、フォトリソグラフィがさらに1回余分に必要となる。 In other words, in order to change the film thickness of the transparent electrode layer on the reflective electrode layer of the anode for each subpixel, as shown in FIGS. 13A to 13F, photolithography is required three times. . Including the patterning of the reflective electrode layer, photolithography is required four times. Further, in FIG. 13F, when a transparent electrode layer is further formed on the B pixel, photolithography is required once more.
 したがって、上記したようにマイクロキャビティ効果を得るために、同一材料の透明電極層を用いてサブ画素毎に電極の厚みを変えようとすると、少なくとも3回(反射電極層のパターニングのためのフォトリソグラフィを含めれば、少なくとも4回)のフォトリソグラフィおよびエッチング、レジスト剥離を行うための装置が必要となる。このため、製造ラインにおいて必要とされる、上記処理を行うためのフォトリソグラフィ装置(フォトプロセス装置)の数が多くなる。 Therefore, in order to obtain the microcavity effect as described above, if the transparent electrode layer of the same material is used and the thickness of the electrode is changed for each sub-pixel, at least three times (photolithography for patterning of the reflective electrode layer). If this is included, an apparatus for performing photolithography, etching, and resist stripping at least four times is required. For this reason, the number of photolithography apparatuses (photo process apparatuses) for performing the above-described processing required in the production line increases.
 フォトリソグラフィでは、高価な装置や材料を必要とする。したがって、上記したようにサブ画素毎に電極の厚みを変えようとすると、装置全体のコストアップおよびフットプリントの増加に繋がる。 Photolithography requires expensive equipment and materials. Therefore, if the thickness of the electrode is changed for each sub-pixel as described above, it leads to an increase in the cost of the entire device and an increase in footprint.
 さらには、フォトリソグラフィは、一定時間の現像処理やベーク処理等を必要とするため、処理タクトを短くすることが困難である。 Furthermore, since photolithography requires development processing and baking processing for a certain time, it is difficult to shorten the processing tact.
 このため、フォトリソグラフィの回数は、できる限り少ない方が望ましい。 Therefore, it is desirable that the number of times of photolithography is as small as possible.
 また、上記したようにフォトレジストの剥離およびベークを繰り返す場合、その繰り返し回数が多くなると、反射電極層の表面が荒れたり酸化したりして反射効率が低下してしまう。また、反射電極の表面荒れによる電極間リークが発生し、画素欠陥になるおそれがある。 Also, as described above, when the photoresist is repeatedly peeled and baked, if the number of repetitions increases, the surface of the reflective electrode layer is roughened or oxidized, and the reflection efficiency is lowered. In addition, there is a possibility that an inter-electrode leak occurs due to the rough surface of the reflective electrode, resulting in a pixel defect.
 また、反射電極材料の種類によっては、上記反射電極層が剥き出しの状態(つまり、露出状態)にあると、例えばレジストのぬれ性を高めるために紫外線照射を行うと酸化して反射特定が低下したり、溶剤耐性が低く、溶剤が染み込んだりする可能性がある。このため、このような反射電極層が、このような反射電極材料からなる場合、反射電極層が剥き出しの状態となることは望ましくない。 Also, depending on the type of the reflective electrode material, if the reflective electrode layer is in an exposed state (that is, an exposed state), for example, if it is irradiated with ultraviolet rays in order to improve the wettability of the resist, it will oxidize and the reflection characteristics will decrease. Or the solvent resistance is low and the solvent may penetrate. For this reason, when such a reflective electrode layer consists of such a reflective electrode material, it is not desirable that the reflective electrode layer is exposed.
 このため、各サブ画素の反射電極層上に透明電極層を積層しようとすると、このためのフォトリソグラフィが必要になることから、さらにフォトリソグラフィの回数が増加する。 For this reason, if a transparent electrode layer is to be laminated on the reflective electrode layer of each sub-pixel, photolithography for this purpose is required, and the number of photolithography increases further.
 なお、特許文献3には、結晶性の異なるITOを積層することにより、パターン化された反射電極層上に、結晶性を有するITOを成膜してパターニングした後、非晶質のITOを積層することにより、2回のフォトリソグラフィでサブ画素毎に透明電極層の膜厚を変更する手法が開示されている。すなわち、特許文献3では、反射電極層のパターニングを含めれば、フォトリソグラフィの回数は3回である。 In Patent Document 3, ITO having different crystallinity is laminated to form a patterned ITO on the patterned reflective electrode layer and patterned, and then amorphous ITO is laminated. Thus, a method of changing the film thickness of the transparent electrode layer for each sub-pixel by photolithography twice is disclosed. That is, in Patent Document 3, if the patterning of the reflective electrode layer is included, the number of times of photolithography is three.
 しかしながら、特許文献3では、第1および第3のサブ画素に結晶性を有するITOを成膜してパターニングした後、第1のサブ画素と第2のサブ画素とに非晶質のITOを積層してパターニングすることにより、サブ画素毎に透明電極層の膜厚を変更している。 However, in Patent Document 3, an ITO having crystallinity is formed and patterned on the first and third subpixels, and then amorphous ITO is stacked on the first subpixel and the second subpixel. Thus, the film thickness of the transparent electrode layer is changed for each sub-pixel by patterning.
 すなわち、特許文献3は、フォトリソグラフィの度に2つのサブ画素に同じ膜厚の透明電極層のパターンを形成し、フォトリソグラフィ毎に透明電極層のパターンを形成するサブ画素を変更することでフォトリソグラフィの回数を減らしており、このために、結晶性を有するITOをエッチングして2つのサブ画素に同じ膜厚の透明電極層のパターンを形成している。 That is, in Patent Document 3, a transparent electrode layer pattern having the same film thickness is formed on two sub-pixels each time photolithography is performed, and the sub-pixel that forms the transparent electrode layer pattern is changed for each photolithography. The number of lithography is reduced, and for this purpose, the ITO having crystallinity is etched to form a pattern of transparent electrode layers having the same film thickness on the two sub-pixels.
 このため、特許文献3では、2つの透明電極層の膜厚の組み合わせで各サブ画素の光路長が決定される。したがって、光路長の設定には制約があり、光路長を任意に変更することは困難である。 For this reason, in Patent Document 3, the optical path length of each sub-pixel is determined by the combination of the film thicknesses of the two transparent electrode layers. Therefore, there are restrictions on the setting of the optical path length, and it is difficult to arbitrarily change the optical path length.
 本発明は、上記問題点に鑑みなされたものであり、本発明の目的は、各サブ画素における反射電極層上に透明電極層が積層されているとともに、表示色が異なるサブ画素間で反射電極層上の透明電極層の膜厚を任意に変更することができる実用的な表示装置の製造方法を提供するとともに、フォトリソグラフィの回数を削減することにある。また、本発明のさらなる目的は、表示色が異なるサブ画素毎に透明電極層の膜厚が異なるとともに実用的な方法で製造が可能な表示装置を提供することにある。 The present invention has been made in view of the above problems, and an object of the present invention is to provide a transparent electrode layer on a reflective electrode layer in each sub-pixel, and a reflective electrode between sub-pixels having different display colors. In addition to providing a practical display device manufacturing method capable of arbitrarily changing the film thickness of the transparent electrode layer on the layer, the number of times of photolithography is reduced. A further object of the present invention is to provide a display device in which the transparent electrode layer has a different film thickness for each sub-pixel having a different display color and can be manufactured by a practical method.
 本発明にかかる表示装置の製造方法は、上記の課題を解決するために、各サブ画素における、電界を形成する対の電極のうち、一方の電極が、反射電極層と、該反射電極層上に形成された少なくとも一層の透明電極層とを備えるとともに、少なくとも1つのサブ画素における反射電極層上に、上記透明電極層が複数形成されており、表示色が異なるサブ画素間で上記透明電極層の全体の膜厚が異なる表示装置の製造方法であって、反射電極層を成膜する工程と、上記反射電極層よりも上層に、非晶質の透明電極材料からなる第1の透明電極層を成膜する第1の透明電極層成膜工程と、上記非晶質の透明電極材料からなる第1の透明電極層および上記反射電極層を一括してフォトリソグラフィによりエッチングしてパターニングするパターニング工程と、上記パターニング工程でパターニングした上記非晶質の透明電極材料からなる第1の透明電極層を結晶化して多結晶の透明電極材料からなる第1の透明電極層に転化させる第1の透明電極層結晶化工程と、上記多結晶の透明電極材料からなる第1の透明電極層上に、上記多結晶の透明電極材料からなる第1の透明電極層よりもエッチング耐性が低い透明電極材料からなる第2の透明電極層を成膜し、フォトリソグラフィにより上記第2の透明電極層を選択的にエッチングしてパターニングする第2の透明電極層積層工程とを含むことを特徴としている。 In order to solve the above-described problem, a manufacturing method of a display device according to the present invention includes a reflective electrode layer and a reflective electrode layer on one electrode of a pair of electrodes that form an electric field in each subpixel. A plurality of transparent electrode layers are formed on the reflective electrode layer in at least one sub-pixel, and the transparent electrode layer is formed between sub-pixels having different display colors. And a first transparent electrode layer made of an amorphous transparent electrode material in an upper layer than the reflective electrode layer. A first transparent electrode layer forming step for forming a film, and a pattern pattern in which the first transparent electrode layer made of the amorphous transparent electrode material and the reflective electrode layer are collectively etched and patterned by photolithography. A first transparent electrode layer made of the amorphous transparent electrode material patterned in the patterning step and converted into a first transparent electrode layer made of a polycrystalline transparent electrode material. Transparent electrode layer crystallization step, and transparent electrode material having lower etching resistance than first transparent electrode layer made of polycrystalline transparent electrode material on first transparent electrode layer made of polycrystalline transparent electrode material And a second transparent electrode layer stacking step of selectively etching and patterning the second transparent electrode layer by photolithography.
 このように、本発明によれば、反射電極層よりも上層に非晶質の透明電極材料からなる第1の透明電極層を成膜して、上記反射電極層および非晶質の透明電極材料からなる第1の透明電極層を一括してエッチングすることで、フォトリソグラフィの回数を増加させることなく、上記反射電極層上に、上記多結晶の透明電極材料からなる第1の透明電極層を積層することができる。 As described above, according to the present invention, the first transparent electrode layer made of an amorphous transparent electrode material is formed above the reflective electrode layer, and the reflective electrode layer and the amorphous transparent electrode material are formed. The first transparent electrode layer made of the polycrystalline transparent electrode material is formed on the reflective electrode layer without increasing the number of times of photolithography by collectively etching the first transparent electrode layer made of Can be stacked.
 また、上記の方法によれば、非晶質の透明電極材料からなる第1の透明電極層を多結晶の透明電極材料からなる第1の透明電極層に転化させ、その上に成膜される第2の透明電極層とのエッチング耐性の違いを利用して透明電極層を積層する。 Further, according to the above method, the first transparent electrode layer made of the amorphous transparent electrode material is converted into the first transparent electrode layer made of the polycrystalline transparent electrode material, and the film is formed thereon. A transparent electrode layer is laminated | stacked using the difference in etching tolerance with a 2nd transparent electrode layer.
 上記の方法によれば、このように、上記第2の透明電極層の下層に、上記第2の透明電極層よりもエッチング耐性が高い、多結晶の透明電極材料からなる第1の透明電極層が積層されていることで、上層となる第2の透明電極層をエッチングするときに下層の第1の透明電極層がエッチングされない。しかも、上記の方法によれば、上記第2の透明電極層を成膜する前に、各サブ画素に、上記多結晶の透明電極材料からなる第1の透明電極層が積層されていることで、任意のサブ画素に上記第2の透明電極層を積層することができる。 According to the above method, the first transparent electrode layer made of a polycrystalline transparent electrode material having a higher etching resistance than the second transparent electrode layer is formed below the second transparent electrode layer. As a result of being laminated, the lower first transparent electrode layer is not etched when the upper second transparent electrode layer is etched. In addition, according to the above method, the first transparent electrode layer made of the polycrystalline transparent electrode material is laminated on each sub-pixel before the second transparent electrode layer is formed. The second transparent electrode layer can be laminated on any subpixel.
 このため、上記の方法によれば、各サブ画素の反射電極層上に透明電極層が形成されているとともに、各サブ画素における透明電極層の合計の膜厚を変更するために必要なフォトリソグラフィの回数としては2回のフォトリソグラフィで、上記透明電極層の合計の膜厚を、サブ画素毎に任意に変更することができる。また、上記の方法によれば、反射電極層のエッチングを含めても、フォトリソグラフィの回数を3回に抑えることができる。 For this reason, according to the above method, the transparent electrode layer is formed on the reflective electrode layer of each subpixel, and photolithography necessary for changing the total film thickness of the transparent electrode layer in each subpixel. The total film thickness of the transparent electrode layer can be arbitrarily changed for each sub-pixel by performing photolithography twice. Moreover, according to said method, the frequency | count of photolithography can be restrained to 3 times also including the etching of a reflective electrode layer.
 このため、上記の方法によれば、上記したようにフォトリソグラフィの回数を減らしたとしても、任意のサブ画素における第2の透明電極層の膜厚を、他のサブ画素における第2の透明電極層の膜厚とは独立して設定することが可能となる。 Therefore, according to the above method, even if the number of times of photolithography is reduced as described above, the film thickness of the second transparent electrode layer in an arbitrary subpixel is set to the second transparent electrode in another subpixel. It can be set independently of the film thickness of the layer.
 つまり、特許文献3のように、透明電極層を積み上げるために結晶性を有するITO層を別途成膜してパターニングするとともにフォトリソグラフィの度に2つのサブ画素に同じ膜厚の透明電極層のパターンを形成しなくても、2回のフォトリソグラフィで、各サブ画素の反射電極層上に透明電極層が形成されているとともに表示色が異なるサブ画素毎に上記反射電極層上の透明電極層の合計の膜厚が異なる電極を形成することができる。 That is, as in Patent Document 3, an ITO layer having crystallinity is separately formed and patterned in order to stack the transparent electrode layers, and the pattern of the transparent electrode layer having the same film thickness is formed on two sub-pixels every time photolithography is performed. Even if the transparent electrode layer is not formed, a transparent electrode layer is formed on the reflective electrode layer of each sub-pixel in two photolithography, and the transparent electrode layer on the reflective electrode layer is different for each sub-pixel having a different display color. Electrodes with different total film thicknesses can be formed.
 このため、上記の方法によれば、特許文献3のように光路長の制約を受けることなく、各サブ画素における光路長を、任意かつ容易に調整することができる。したがって、上記の方法によれば、従来よりも少ない回数のフォトリソグラフィで、表示色が異なるサブ画素毎に反射電極層上の透明電極層の膜厚を任意に変更することができる。 Therefore, according to the above method, the optical path length in each sub-pixel can be arbitrarily and easily adjusted without being restricted by the optical path length as in Patent Document 3. Therefore, according to the above method, the film thickness of the transparent electrode layer on the reflective electrode layer can be arbitrarily changed for each sub-pixel having a different display color by a smaller number of photolithography than the conventional method.
 この結果、従来よりもコストダウンおよびフットプリントの低減を図ることができる。 As a result, the cost can be reduced and the footprint can be reduced as compared with the conventional case.
 また、従来の方法では、フォトレジストの剥離およびベーク工程が多くなるため、反射電極層の表面が荒れたり酸化したりして反射効率が低下したり、反射電極層の表面荒れによる電極間リークが発生し、画素欠陥になるおそれがあった。 In addition, in the conventional method, since the photoresist stripping and baking processes are increased, the surface of the reflective electrode layer is roughened or oxidized, resulting in a decrease in reflection efficiency, or leakage between electrodes due to the rough surface of the reflective electrode layer. There was a risk of pixel defects.
 しかしながら、上記の方法によれば、露光、現像、レジスト剥離処理等の回数を低減させることができるので、そのようなおそれがない。また、処理タクトを短くすることができる。 However, according to the above method, the number of times of exposure, development, resist stripping and the like can be reduced, so there is no such fear. Further, the processing tact can be shortened.
 また、反射電極材料の種類によっては、上記反射電極層が剥き出しの状態(つまり、露出状態)にあると、例えばレジストのぬれ性を高めるために紫外線照射を行うと酸化して反射特定が低下したり、溶剤耐性が低く、溶剤が染み込んだりする可能性がある。このため、このような反射電極層が、このような反射電極材料からなる場合、反射電極層が剥き出しの状態となることは望ましくない。 Also, depending on the type of the reflective electrode material, if the reflective electrode layer is in an exposed state (that is, an exposed state), for example, if it is irradiated with ultraviolet rays in order to improve the wettability of the resist, it will oxidize and the reflection characteristics will decrease. Or the solvent resistance is low and the solvent may penetrate. For this reason, when such a reflective electrode layer consists of such a reflective electrode material, it is not desirable that the reflective electrode layer is exposed.
 しかしながら、上記の方法によれば、製造工程における早い段階で、上記したように各サブ画素における反射電極層上に上記多結晶の透明電極層が形成されることで、上記反射電極層を、該反射電極層の品質を損なうおそれがある上記要因から保護することができる。 However, according to the above method, the polycrystalline transparent electrode layer is formed on the reflective electrode layer in each sub-pixel as described above at an early stage in the manufacturing process. It can protect from the said factor which may impair the quality of a reflective electrode layer.
 また、特許文献3では、反射電極層をパターニングした後、第1および第3のサブ画素に結晶性を有するITOを成膜してパターニングしている。 In Patent Document 3, after patterning the reflective electrode layer, the first and third sub-pixels are formed and patterned with crystalline ITO.
 結晶性を有するITOは、反射電極層のエッチングに使用されるエッチング液に対する溶解性が高い。このため、反射電極層上に結晶性を有するITO層を直接成膜してフォトリソグラフィによりパターン化すると、反射電極層がテーパ状でなくなるおそれがある。 Crystalline ITO has high solubility in the etching solution used for etching the reflective electrode layer. For this reason, when an ITO layer having crystallinity is directly formed on the reflective electrode layer and patterned by photolithography, the reflective electrode layer may not be tapered.
 しかしながら、上記の方法によれば、非晶質の透明電極材料からなる第1の透明電極層を成膜して反射電極層をともにパターニングしてから多結晶の透明電極層に転化させることで、そのような問題が生じることもない。 However, according to the above method, by forming the first transparent electrode layer made of an amorphous transparent electrode material, patterning the reflective electrode layer together, and then converting it to a polycrystalline transparent electrode layer, Such a problem does not occur.
 このように、上記の方法によれば、各サブ画素における反射電極層上に透明電極層が積層されているとともに、表示色が異なるサブ画素間で反射電極層上の透明電極層の膜厚を任意に変更することができる実用的な表示装置の製造方法を提供するとともに、フォトリソグラフィの回数を削減することができる。 Thus, according to the above method, the transparent electrode layer is laminated on the reflective electrode layer in each subpixel, and the film thickness of the transparent electrode layer on the reflective electrode layer is changed between the subpixels having different display colors. In addition to providing a practical display device manufacturing method that can be arbitrarily changed, the number of times of photolithography can be reduced.
 また、本発明にかかる表示装置は、上記の課題を解決するために、各サブ画素における、電界を形成する対の電極のうち、一方の電極が、反射電極層と、該反射電極層上に形成された少なくとも一層の透明電極層とを備えるとともに、少なくとも1つのサブ画素における反射電極層上に、上記透明電極層が複数形成されており、表示色が異なるサブ画素間で上記透明電極層の全体の膜厚が異なる表示装置であって、上記複数の透明電極層は、互いに異なる組成を有し、下層の透明電極層のエッチング耐性が、上層の透明電極層のエッチング耐性よりも高いことを特徴としている。 Further, in order to solve the above-described problem, in the display device according to the present invention, one of the pair of electrodes that form an electric field in each subpixel has a reflective electrode layer and the reflective electrode layer on the reflective electrode layer. At least one transparent electrode layer formed, and a plurality of the transparent electrode layers are formed on the reflective electrode layer in at least one sub-pixel, and the transparent electrode layer is formed between sub-pixels having different display colors. It is a display device with different overall film thickness, wherein the plurality of transparent electrode layers have different compositions, and the etching resistance of the lower transparent electrode layer is higher than the etching resistance of the upper transparent electrode layer. It is a feature.
 このような表示装置は、非結晶の透明電極材料からなる透明電極層を多結晶の透明電極材料からなる透明電極層に転化させることなく、下層の透明電極層と上層の透明電極層とのエッチング耐性の違いによるエッチング選択性の違いを利用して、透明電極層の積み上げを行うことができる。 Such a display device etches the lower transparent electrode layer and the upper transparent electrode layer without converting the transparent electrode layer made of the amorphous transparent electrode material into the transparent electrode layer made of the polycrystalline transparent electrode material. The transparent electrode layers can be stacked using the difference in etching selectivity due to the difference in resistance.
 このため、従来のように同じ透明電極材料からなる透明電極層を積み上げる場合と比較して、短い処理タクトで、各サブ画素における光路長を、任意かつ容易に調整することができる。 For this reason, the optical path length in each sub-pixel can be arbitrarily and easily adjusted with a short processing tact as compared with the case where transparent electrode layers made of the same transparent electrode material are stacked as in the prior art.
 したがって、本発明によれば、表示色が異なるサブ画素毎に透明電極層の膜厚が異なるとともに実用的な方法で製造が可能な表示装置を提供することができる。 Therefore, according to the present invention, it is possible to provide a display device that can be manufactured by a practical method while the thickness of the transparent electrode layer is different for each sub-pixel having a different display color.
 以上のように、本発明にかかる表示装置の製造方法では、反射電極層よりも上層に非晶質の透明電極材料からなる第1の透明電極層を成膜して、上記反射電極層および非晶質の透明電極材料からなる第1の透明電極層を一括してエッチングする。 As described above, in the method for manufacturing a display device according to the present invention, the first transparent electrode layer made of an amorphous transparent electrode material is formed above the reflective electrode layer, and the reflective electrode layer and the non-reflective electrode layer are formed. The first transparent electrode layer made of a crystalline transparent electrode material is etched together.
 このため、上記の製造方法によれば、フォトリソグラフィの回数を増加させることなく、上記反射電極層上に、上記多結晶の透明電極材料からなる第1の透明電極層を積層することができる。 For this reason, according to the manufacturing method, the first transparent electrode layer made of the polycrystalline transparent electrode material can be laminated on the reflective electrode layer without increasing the number of times of photolithography.
 また、本発明にかかる表示装置の製造方法では、非晶質の透明電極材料からなる第1の透明電極層を多結晶の透明電極材料からなる第1の透明電極層に転化させ、その上に成膜される第2の透明電極層とのエッチング耐性の違いを利用して透明電極層を積層する。 In the method for manufacturing a display device according to the present invention, the first transparent electrode layer made of an amorphous transparent electrode material is converted into a first transparent electrode layer made of a polycrystalline transparent electrode material, and the first transparent electrode layer is formed thereon. A transparent electrode layer is laminated | stacked using the difference in etching tolerance with the 2nd transparent electrode layer formed into a film.
 上記の製造方法によれば、このように、上記第2の透明電極層の下層に、上記第2の透明電極層よりもエッチング耐性が高い、多結晶の透明電極材料からなる第1の透明電極層が積層されていることで、上層となる第2の透明電極層をエッチングするときに下層の第1の透明電極層がエッチングされない。しかも、上記の製造方法によれば、上記第2の透明電極層を成膜する前に、各サブ画素に、上記多結晶の透明電極材料からなる第1の透明電極層が積層されていることで、任意のサブ画素に上記第2の透明電極層を積層することができる。 According to the above manufacturing method, the first transparent electrode made of a polycrystalline transparent electrode material, which has a higher etching resistance than the second transparent electrode layer, is formed below the second transparent electrode layer. By laminating the layers, the lower first transparent electrode layer is not etched when the upper second transparent electrode layer is etched. In addition, according to the above manufacturing method, the first transparent electrode layer made of the polycrystalline transparent electrode material is laminated on each sub-pixel before the second transparent electrode layer is formed. Thus, the second transparent electrode layer can be laminated on any sub-pixel.
 このため、上記の製造方法によれば、各サブ画素の反射電極層上に透明電極層が形成されているとともに、各サブ画素における透明電極層の合計の膜厚を変更するために必要なフォトリソグラフィの回数としては2回のフォトリソグラフィで、上記透明電極層の合計の膜厚を、サブ画素毎に任意に変更することができる。また、上記の製造方法によれば、反射電極層のエッチングを含めても、フォトリソグラフィの回数を3回に抑えることができる。 For this reason, according to the above manufacturing method, the transparent electrode layer is formed on the reflective electrode layer of each sub-pixel, and the photo required for changing the total film thickness of the transparent electrode layer in each sub-pixel. As the number of times of lithography, the total film thickness of the transparent electrode layer can be arbitrarily changed for each sub-pixel by photolithography. Moreover, according to said manufacturing method, the frequency | count of photolithography can be restrained to 3 times also including the etching of a reflective electrode layer.
 このため、上記の製造方法によれば、上記したようにフォトリソグラフィの回数を減らしたとしても、任意のサブ画素における第2の透明電極層の膜厚を、他のサブ画素における第2の透明電極層の膜厚とは独立して設定することが可能となる。 Therefore, according to the above manufacturing method, even if the number of times of photolithography is reduced as described above, the film thickness of the second transparent electrode layer in an arbitrary subpixel is set to the second transparent electrode in another subpixel. It can be set independently of the film thickness of the electrode layer.
 このため、上記の製造方法によれば、特許文献3のように光路長の制約を受けることなく、各サブ画素における光路長を、任意かつ容易に調整することができる。したがって、上記の製造方法によれば、従来よりも少ない回数のフォトリソグラフィで、表示色が異なるサブ画素毎に反射電極層上の透明電極層の膜厚を任意に変更することができる。 Therefore, according to the above manufacturing method, the optical path length in each sub-pixel can be arbitrarily and easily adjusted without being restricted by the optical path length as in Patent Document 3. Therefore, according to said manufacturing method, the film thickness of the transparent electrode layer on a reflective electrode layer can be arbitrarily changed for every sub pixel from which a display color differs by the photolithography of the frequency | count of less than before.
 また、以上のように、本発明にかかる表示装置は、反射電極層上に複数の透明電極層が設けられており、表示色が異なるサブ画素毎に、上記透明電極層の全体の膜厚が異なる表示装置であって、上記複数の透明電極層は、互いに異なる組成を有し、下層の透明電極層のエッチング耐性が、上層の透明電極層のエッチング耐性よりも高い。 Further, as described above, the display device according to the present invention includes a plurality of transparent electrode layers on the reflective electrode layer, and the total film thickness of the transparent electrode layer is different for each sub-pixel having a different display color. In the different display devices, the plurality of transparent electrode layers have different compositions, and the etching resistance of the lower transparent electrode layer is higher than the etching resistance of the upper transparent electrode layer.
 このような表示装置は、非結晶の透明電極材料からなる透明電極層を多結晶の透明電極材料からなる透明電極層に転化させることなく、下層の透明電極層と上層の透明電極層とのエッチング耐性の違いによるエッチング選択性の違いを利用して、透明電極層の積み上げを行うことができる。 Such a display device etches the lower transparent electrode layer and the upper transparent electrode layer without converting the transparent electrode layer made of the amorphous transparent electrode material into the transparent electrode layer made of the polycrystalline transparent electrode material. The transparent electrode layers can be stacked using the difference in etching selectivity due to the difference in resistance.
 このため、従来のように同じ透明電極材料からなる透明電極層を積み上げる場合と比較して、短い処理タクトで、各サブ画素における光路長を、任意かつ容易に調整することができる。 For this reason, the optical path length in each sub-pixel can be arbitrarily and easily adjusted with a short processing tact as compared with the case where transparent electrode layers made of the same transparent electrode material are stacked as in the prior art.
 したがって、本発明によれば、表示色が異なるサブ画素毎に透明電極層の膜厚が異なるとともに実用的な方法で製造が可能な表示装置を提供することができる。 Therefore, according to the present invention, it is possible to provide a display device that can be manufactured by a practical method while the thickness of the transparent electrode layer is different for each sub-pixel having a different display color.
(a)~(i)は、実施の形態1にかかるトップエミッション型の有機EL表示装置における第1電極の作製方法の一例を工程順に示す断面図である。(A)-(i) is sectional drawing which shows an example of the manufacturing method of the 1st electrode in the top emission type organic electroluminescence display concerning Embodiment 1 in order of a process. 実施の形態1にかかる有機EL表示装置の要部の概略構成を示す分解断面図である。1 is an exploded cross-sectional view illustrating a schematic configuration of a main part of an organic EL display device according to a first embodiment. 実施の形態1にかかる有機EL表示装置における支持基板の概略構成を示す平面図である。3 is a plan view showing a schematic configuration of a support substrate in the organic EL display device according to Embodiment 1. FIG. 図3に示す支持基板における表示領域の要部の構成を示す平面図である。It is a top view which shows the structure of the principal part of the display area in the support substrate shown in FIG. 実施の形態1にかかる有機EL表示パネルを図4に示すA-A線で切断したときの有機EL表示パネルの概略構成を示す断面図である。FIG. 5 is a cross-sectional view showing a schematic configuration of the organic EL display panel when the organic EL display panel according to the first embodiment is cut along line AA shown in FIG. 実施の形態1にかかる有機EL表示装置の画像表示方法について説明する模式図である。FIG. 3 is a schematic diagram illustrating an image display method of the organic EL display device according to the first embodiment. 実施の形態1にかかる有機EL表示装置の製造工程の一例を工程順に示すフローチャートである。3 is a flowchart illustrating an example of a manufacturing process of the organic EL display device according to the first embodiment in the order of processes. 実施の形態1にかかる有機EL層の作製工程の一例を工程順に示すフローチャートである。3 is a flowchart illustrating an example of a manufacturing process of the organic EL layer according to the first embodiment in order of processes. (a)・(b)は、図1の(i)に示す第1電極上にエッジカバーを作製したときの第1電極の概略構成を模式的に示す図であり、(a)は断面図であり、(b)は平面図である。(A) * (b) is a figure which shows typically schematic structure of a 1st electrode when producing an edge cover on the 1st electrode shown to (i) of FIG. 1, (a) is sectional drawing. (B) is a plan view. (a)~(h)は、実施の形態2にかかるトップエミッション型の有機EL表示装置00における第1電極の作製からエッジカバーの作製までの工程の一例を、工程順に示す断面図である。(A)-(h) is sectional drawing which shows an example of the process from preparation of the 1st electrode in the top emission type organic EL display apparatus 00 concerning Embodiment 2 to preparation of an edge cover in order of a process. 実施の形態3にかかる有機EL表示パネルの概略構成を示す断面図である。FIG. 5 is a cross-sectional view illustrating a schematic configuration of an organic EL display panel according to a third embodiment. 図11に示す有機EL層の作製工程の一例を工程順に示すフローチャートである。It is a flowchart which shows an example of the manufacturing process of the organic electroluminescent layer shown in FIG. (a)~(f)は、サブ画素毎に、陽極の反射電極層上の透明電極層の合計の膜厚を変更する方法の一例を、工程順に示す断面図である。(A)-(f) is sectional drawing which shows an example of the method of changing the total film thickness of the transparent electrode layer on the reflective electrode layer of an anode for every sub pixel in order of a process.
 以下、本発明の実施の一形態について、詳細に説明する。 Hereinafter, an embodiment of the present invention will be described in detail.
 〔実施の形態1〕
 本実施の形態について図1の(a)~(i)ないし図9の(a)・(b)に基づいて説明すれば以下の通りである。
[Embodiment 1]
This embodiment will be described below with reference to FIGS. 1A to 1I to 9A and 9B.
 <有機EL表示装置の概略構成>
 まず、有機EL表示装置の概略構成について説明する。
<Schematic configuration of organic EL display device>
First, a schematic configuration of the organic EL display device will be described.
 図2は、本実施の形態にかかる有機EL表示装置100の要部の概略構成を示す分解断面図である。 FIG. 2 is an exploded sectional view showing a schematic configuration of a main part of the organic EL display device 100 according to the present embodiment.
 図2に示すように、本実施の形態にかかる有機EL表示装置100は、画素部101と回路部102とを備えている。 As shown in FIG. 2, the organic EL display device 100 according to the present embodiment includes a pixel unit 101 and a circuit unit 102.
 画素部101は、有機EL表示パネル1(表示パネル)で構成されている。また、回路部102は、有機EL表示装置100を駆動する駆動回路等が設けられた回路基板やIC(集積回路:Integrated Circuits)チップ等で構成されている。 The pixel unit 101 is composed of an organic EL display panel 1 (display panel). The circuit unit 102 includes a circuit board provided with a drive circuit for driving the organic EL display device 100, an IC (Integrated Circuits) chip, and the like.
 有機EL表示パネル1は、支持基板10(被成膜基板、TFT基板)上に、有機EL素子20および封止樹脂層41、充填樹脂層42、封止基板50が、この順に設けられた構成を有している。 The organic EL display panel 1 has a configuration in which an organic EL element 20, a sealing resin layer 41, a filling resin layer 42, and a sealing substrate 50 are provided in this order on a support substrate 10 (deposition substrate, TFT substrate). have.
 支持基板10は、TFT基板等の半導体基板からなり、例えば、絶縁基板11上に、能動素子(駆動素子)としてTFT(薄膜トランジスタ:Thin Film Transistor)12(図5参照)等が設けられた構成を有している。 The support substrate 10 is made of a semiconductor substrate such as a TFT substrate. For example, the support substrate 10 has a structure in which a thin film transistor (TFT) 12 (see FIG. 5) is provided as an active element (drive element) on an insulating substrate 11. Have.
 有機EL素子20は、TFT12に接続されている。有機EL素子20上には、乾燥剤を含有した接着性を有する充填樹脂層42が形成されている。充填樹脂層42を構成する充填樹脂は、支持基板10、封止基板50、および封止樹脂層41で囲まれた空間に充填されている。 The organic EL element 20 is connected to the TFT 12. On the organic EL element 20, a filling resin layer 42 having adhesiveness containing a desiccant is formed. The filling resin constituting the filling resin layer 42 is filled in a space surrounded by the support substrate 10, the sealing substrate 50, and the sealing resin layer 41.
 なお、有機EL表示装置100は、支持基板10側から光を射出するボトムエミッション型であってもよく、封止基板50側から光を射出するトップエミッション型であってもよい。 The organic EL display device 100 may be a bottom emission type that emits light from the support substrate 10 side, or a top emission type that emits light from the sealing substrate 50 side.
 支持基板10および封止基板50に用いられるベース基板としては、例えばガラスやプラスチック等を用いることができる。一例として、例えば、無アルカリガラス基板等のガラス基板を用いることができる。 As the base substrate used for the support substrate 10 and the sealing substrate 50, for example, glass or plastic can be used. As an example, for example, a glass substrate such as an alkali-free glass substrate can be used.
 但し、これに限定されるものではなく、光を射出しない側の基板としては、金属板等の不透明材料を用いることもできる。 However, the present invention is not limited to this, and an opaque material such as a metal plate can also be used as the substrate on the side that does not emit light.
 トップエミッション型の場合、封止基板50としては、CF(カラーフィルタ:Color Filter)層が形成された基板を用いてもよい。また、ボトムエミッション型の場合、支持基板10側にCF層を形成していてもよい。 In the case of a top emission type, a substrate on which a CF (Color Filter) layer is formed may be used as the sealing substrate 50. In the case of the bottom emission type, a CF layer may be formed on the support substrate 10 side.
 このようにCF層を併用する場合、有機EL素子20から出射した光のスペクトルをCF層によって調整することができる。 Thus, when the CF layer is used together, the spectrum of the light emitted from the organic EL element 20 can be adjusted by the CF layer.
 以下、本実施の形態では、有機EL表示装置100がトップエミッション型である場合を例に挙げて説明する。しかしながら、本実施の形態はこれに限定されるものではなく、上記したように例えばボトムエミッション型であってもよい。 Hereinafter, in the present embodiment, a case where the organic EL display device 100 is a top emission type will be described as an example. However, the present embodiment is not limited to this, and may be, for example, a bottom emission type as described above.
 本実施の形態にかかる封止基板50は、図2に示すように、例えば、絶縁基板51上に、CF層52およびBM(ブラックマトリクス:Black Matrix)53(図5参照)等が設けられた構成を有している。 As shown in FIG. 2, the sealing substrate 50 according to the present embodiment is provided with, for example, a CF layer 52, a BM (Black-Matrix) 53 (see FIG. 5), and the like on an insulating substrate 51. It has a configuration.
 有機EL素子20は、該有機EL素子20が水分や酸素によって損傷しないように、該有機EL素子20が積層された支持基板10を、枠状の封止領域Lに設けられた封止樹脂層41および充填樹脂層42を介して封止基板50と貼り合わせることで、これら一対の基板(支持基板10、封止基板50)間に封入されている。 The organic EL element 20 includes a sealing resin layer provided in a frame-shaped sealing region L with the support substrate 10 on which the organic EL element 20 is laminated so that the organic EL element 20 is not damaged by moisture or oxygen. By being bonded to the sealing substrate 50 via 41 and the filling resin layer 42, the sealing substrate 50 is sealed between the pair of substrates (the support substrate 10 and the sealing substrate 50).
 有機EL表示パネル1は、このように有機EL素子20が支持基板10と封止基板50との間に封入されていることで、有機EL素子20への酸素や水分の外部からの浸入が防止されている。 In the organic EL display panel 1, the organic EL element 20 is sealed between the support substrate 10 and the sealing substrate 50 as described above, thereby preventing oxygen and moisture from entering the organic EL element 20 from the outside. Has been.
 また、支持基板10における枠状の封止領域Lの外側には、電気配線端子2(電気接続部、接続端子)等が形成された端子部領域R3が設けられている。 Further, outside the frame-shaped sealing region L in the support substrate 10, a terminal portion region R3 in which the electrical wiring terminals 2 (electric connection portions, connection terminals) and the like are formed is provided.
 電気配線端子2は、回路部102の接続端子103が接続される接続端子であり、金属等の配線材料により形成されている。 The electrical wiring terminal 2 is a connection terminal to which the connection terminal 103 of the circuit unit 102 is connected, and is formed of a wiring material such as metal.
 回路部102には、例えば、フレキシブルフィルムケーブル等の配線や、ドライバ等の駆動回路等が設けられている。 The circuit unit 102 is provided with wiring such as a flexible film cable, a drive circuit such as a driver, and the like.
 回路部102は、図2に示すように、端子部領域R3に設けられた電気配線端子2を介して有機EL表示パネル1と接続されている。 As shown in FIG. 2, the circuit unit 102 is connected to the organic EL display panel 1 through an electrical wiring terminal 2 provided in the terminal region R3.
 <支持基板10の構成>
 ここで、端子部領域R3を含む、支持基板10における各領域について、図3を参照して以下に説明する。
<Configuration of Support Substrate 10>
Here, each area | region in the support substrate 10 including terminal part area | region R3 is demonstrated below with reference to FIG.
 図3は、有機EL表示装置100における支持基板10の概略構成を示す平面図である。 FIG. 3 is a plan view showing a schematic configuration of the support substrate 10 in the organic EL display device 100.
 図3に示すように、支持基板10の能動面(能動素子形成面)である一方の主面には、表示領域R1、第2電極接続領域R2、端子部領域R3、および、枠状の封止領域Lが設けられている。 As shown in FIG. 3, on one main surface which is an active surface (active element formation surface) of the support substrate 10, a display region R1, a second electrode connection region R2, a terminal region R3, and a frame-shaped seal are formed. A stop region L is provided.
 <表示領域R1>
 表示領域R1(表示部)は、支持基板10の中央部に設けられており、例えば矩形状に形成されている。表示領域R1には、複数のサブ画素71(図4および図5参照)からなる画素アレイが形成されている。なお、表示領域R1の構成については後で詳述する。
<Display area R1>
The display region R1 (display unit) is provided at the center of the support substrate 10, and is formed in a rectangular shape, for example. In the display region R1, a pixel array including a plurality of sub-pixels 71 (see FIGS. 4 and 5) is formed. The configuration of the display area R1 will be described in detail later.
 <第2電極接続領域R2>
 第2電極接続領域R2は、有機EL素子20における第2電極31(図5参照)が接続される領域である。第2電極接続領域R2は、例えば、表示領域R1の2組の対となる辺のうち、一方の組の対となる辺の外側に、それぞれ対向する辺に沿って形成されている。
<Second electrode connection region R2>
The second electrode connection region R2 is a region to which the second electrode 31 (see FIG. 5) in the organic EL element 20 is connected. For example, the second electrode connection region R2 is formed on the outer side of the pair of sides of the pair of the display regions R1 and along the opposite sides.
 これら第2電極接続領域R2には、それぞれ接続部60(接続電極)が形成されている。接続部60は、第2電極31が接続される部分であり、金属材料により形成されている。 These connection portions 60 (connection electrodes) are formed in the second electrode connection regions R2. The connection part 60 is a part to which the second electrode 31 is connected, and is formed of a metal material.
 <封止領域L>
 封止領域Lには、上記したように、支持基板10と封止基板50とを貼り合わせるための封止樹脂層41が形成されている。
<Sealing region L>
As described above, the sealing resin layer 41 for bonding the support substrate 10 and the sealing substrate 50 is formed in the sealing region L.
 封止領域Lは、図3に示すように、表示領域R1および第2電極接続領域R2を囲むように枠状に形成されている。 As shown in FIG. 3, the sealing region L is formed in a frame shape so as to surround the display region R1 and the second electrode connection region R2.
 <端子部領域R3>
 端子部領域R3は、上記したように、画素部101と回路部102との接続に用いられる領域である。端子部領域R3は、枠状の封止領域Lの外側に、この枠状の封止領域Lに沿って設けられている。
<Terminal part region R3>
As described above, the terminal portion region R3 is a region used for connection between the pixel portion 101 and the circuit portion 102. The terminal region R3 is provided outside the frame-shaped sealing region L along the frame-shaped sealing region L.
 具体的には、図3に示すように、端子部領域R3は、各第2電極接続領域R2の外側に、各第2電極接続領域R2に沿って形成されている。また、端子部領域R3は、表示領域R1における、上記第2電極接続領域R2が設けられていない、他方の組の対となる辺の外側に、それぞれ対向する辺に沿って形成されている。 Specifically, as shown in FIG. 3, the terminal region R3 is formed outside each second electrode connection region R2 and along each second electrode connection region R2. Further, the terminal region R3 is formed along the opposing sides on the outside of the other pair of sides in the display region R1 where the second electrode connection region R2 is not provided.
 なお、端子部領域R3は、全ての辺に存在している必要はなく、例えば、何れか一辺のみに集中して形成されていてもよい。 Note that the terminal region R3 does not have to exist on all sides, and may be formed concentrated on only one side, for example.
 <表示領域R1の構成>
 次に、表示領域R1の構成について説明する。
<Configuration of display region R1>
Next, the configuration of the display area R1 will be described.
 図4は、支持基板10における表示領域R1の要部の構成を示す平面図であり、図5は、有機EL表示パネル1を図4に示すA-A線で切断したときの有機EL表示パネル1の概略構成を示す断面図である。 4 is a plan view showing a configuration of a main part of the display region R1 in the support substrate 10, and FIG. 5 is an organic EL display panel when the organic EL display panel 1 is cut along line AA shown in FIG. 1 is a cross-sectional view showing a schematic configuration of 1. FIG.
 図4および図5に示すように、表示領域R1は、有機EL素子20が形成された複数の画素70で構成されている。 As shown in FIGS. 4 and 5, the display region R1 is composed of a plurality of pixels 70 on which the organic EL elements 20 are formed.
 各画素70は、それぞれ、複数のサブ画素71で構成されている。有機EL表示装置100は、フルカラーのアクティブマトリクス型の有機EL表示装置であり、例えば、図5に示すように、赤(R)色に発光するサブ画素71(以下、「サブ画素71R」と記す)、緑(G)色に発光するサブ画素71(以下、「サブ画素71G」と記す)、青(B)色に発光するサブ画素71(以下、「サブ画素71B」と記す)の、3つのサブ画素71R・71G・71Bで1つの画素70が構成されている。 Each pixel 70 is composed of a plurality of sub-pixels 71. The organic EL display device 100 is a full-color active matrix organic EL display device. For example, as shown in FIG. 5, a subpixel 71 that emits red (R) light (hereinafter referred to as “subpixel 71R”). ), Sub-pixel 71 that emits light in green (G) (hereinafter referred to as “sub-pixel 71G”), and sub-pixel 71 that emits light in blue (B) (hereinafter referred to as “sub-pixel 71B”). One pixel 70 is constituted by the two sub-pixels 71R, 71G, and 71B.
 表示領域R1には、これらR、G、Bの各色の発光色を有する有機EL素子20からなる各色のサブ画素71が、マトリクス状に配列されている。本実施の形態では、各サブ画素71R・71G・71Bは、支持基板10の能動面におけるX軸方向(横方向)およびY軸方向(縦方向)のうちの一方の方向(例えばX軸方向)に、同じ発光色のサブ画素71が隣り合い、他方の方向(例えばY軸方向)に、異なる発光色のサブ画素71が隣り合うように配列されている。 In the display region R1, sub-pixels 71 of each color composed of the organic EL elements 20 having the emission colors of R, G, and B are arranged in a matrix. In the present embodiment, each of the sub-pixels 71R, 71G, and 71B has one of the X-axis direction (lateral direction) and the Y-axis direction (vertical direction) on the active surface of the support substrate 10 (for example, the X-axis direction). In addition, the sub-pixels 71 having the same emission color are adjacent to each other, and the sub-pixels 71 having different emission colors are adjacent to each other in the other direction (for example, the Y-axis direction).
 図4および図5に示すように、表示領域R1には、X軸方向およびY軸方向に、複数の信号線14(配線)が配されている。 As shown in FIGS. 4 and 5, a plurality of signal lines 14 (wirings) are arranged in the X-axis direction and the Y-axis direction in the display region R1.
 信号線14は、例えば、画素を選択する複数の線(ゲート線)、データを書き込む複数の線(ソース線)、有機EL素子20に電力を供給する複数の線(電源線)等から構成されている。 The signal line 14 includes, for example, a plurality of lines for selecting pixels (gate lines), a plurality of lines for writing data (source lines), a plurality of lines for supplying power to the organic EL elements 20 (power supply lines), and the like. ing.
 なお、ゲート線は、例えばX軸方向に沿って敷設されており、ソース線は、ゲート線と交差するように、例えばY軸方向に沿って敷設されている。 The gate line is laid along, for example, the X-axis direction, and the source line is laid along, for example, the Y-axis direction so as to intersect the gate line.
 また、ゲート線には、ゲート線を駆動する図示しないゲート線駆動回路が接続され、ソース線には、ソース線を駆動する図示しないデータ線駆動回路が接続されている。 Further, a gate line driving circuit (not shown) for driving the gate line is connected to the gate line, and a data line driving circuit (not shown) for driving the source line is connected to the source line.
 各サブ画素71は、これら信号線14で囲まれた領域に配列されている。すなわち、これら信号線14で囲まれた領域が1つのサブ画素71であり、サブ画素71毎に、各色の発光領域72が画成されている。 The sub-pixels 71 are arranged in a region surrounded by the signal lines 14. That is, a region surrounded by the signal lines 14 is one sub pixel 71, and a light emitting region 72 of each color is defined for each sub pixel 71.
 これら信号線14は、表示領域R1の外で、回路部102の外部回路と接続されている。回路部102から信号線14に対して電気信号を入力することで、信号線14の交差部に配された有機EL素子20を駆動(発光)させることができる。 These signal lines 14 are connected to an external circuit of the circuit unit 102 outside the display region R1. By inputting an electrical signal from the circuit unit 102 to the signal line 14, the organic EL element 20 disposed at the intersection of the signal line 14 can be driven (light emission).
 各サブ画素71R・71G・71Bには、有機EL素子20における第1電極21に接続されたTFT12がそれぞれ設けられている。 Each of the subpixels 71R, 71G, and 71B is provided with a TFT 12 connected to the first electrode 21 in the organic EL element 20.
 信号線14は、これら各サブ画素71に設けられたTFT12に接続されている。アクティブマトリクス型の場合、各サブ画素71には、少なくとも1つのTFT12が配されている。 The signal line 14 is connected to the TFT 12 provided in each of the sub-pixels 71. In the case of the active matrix type, each subpixel 71 is provided with at least one TFT 12.
 なお、各サブ画素71には、書き込まれた電圧を保持するキャパシタや、TFT12の特性バラつきを補償するための補償回路がさらに形成されていてもよい。 Note that each sub-pixel 71 may further be formed with a capacitor for holding the written voltage and a compensation circuit for compensating for the characteristic variation of the TFT 12.
 各サブ画素71の発光強度は、信号線14およびTFT12による走査および選択により決定される。有機EL表示装置100は、TFT12を用いて、有機EL素子20を選択的に所望の輝度で発光させることにより画像表示を実現している。 The emission intensity of each sub-pixel 71 is determined by scanning and selection using the signal line 14 and the TFT 12. The organic EL display device 100 realizes image display by selectively causing the organic EL element 20 to emit light with a desired luminance using the TFT 12.
 <支持基板10の断面構成>
 図4および図5に示すように、支持基板10は、ベース基板として絶縁基板11を備えている。
<Cross-sectional structure of support substrate 10>
As shown in FIGS. 4 and 5, the support substrate 10 includes an insulating substrate 11 as a base substrate.
 図5に示すように、表示領域R1において、支持基板10は、ガラス基板等の透明な絶縁基板11上に、TFT12(スイッチング素子)および信号線14、層間絶縁膜13(平坦化膜)、エッジカバー15等が形成された構成を有している。 As shown in FIG. 5, in the display region R <b> 1, the support substrate 10 is formed on a transparent insulating substrate 11 such as a glass substrate, a TFT 12 (switching element) and a signal line 14, an interlayer insulating film 13 (flattening film), an edge The cover 15 and the like are formed.
 絶縁基板11上には、信号線14が設けられているとともに、各サブ画素71R・71G・71Bに対応して、それぞれTFT12が設けられている。なお、TFTの構成は従来よく知られている。また、TFT12は既知の方法にて作製される。したがって、TFT12における各層の図示並びに説明は省略する。 On the insulating substrate 11, signal lines 14 are provided, and TFTs 12 are provided corresponding to the sub-pixels 71R, 71G, 71B, respectively. The structure of the TFT is conventionally well known. The TFT 12 is manufactured by a known method. Therefore, illustration and description of each layer in the TFT 12 are omitted.
 層間絶縁膜13は、各サブ画素71R・71G・71Bおよび信号線14を覆うように、絶縁基板11上に、絶縁基板11の全領域に渡って積層されている。 The interlayer insulating film 13 is laminated over the entire area of the insulating substrate 11 on the insulating substrate 11 so as to cover the sub-pixels 71R, 71G, 71B and the signal lines 14.
 層間絶縁膜13上には、有機EL素子20における第1電極21が形成されている。 The first electrode 21 in the organic EL element 20 is formed on the interlayer insulating film 13.
 また、層間絶縁膜13には、有機EL素子20における第1電極21をTFT12に電気的に接続するためのコンタクトホール13aが設けられている。これにより、TFT12は、コンタクトホール13aを介して、有機EL素子20に電気的に接続されている。 The interlayer insulating film 13 is provided with a contact hole 13 a for electrically connecting the first electrode 21 in the organic EL element 20 to the TFT 12. Thereby, the TFT 12 is electrically connected to the organic EL element 20 through the contact hole 13a.
 エッジカバー15は、第1電極21の端部(パターン端部)で、後述する有機EL層43が薄くなったり電界集中が起こったりすることで、有機EL素子20における第1電極21と第2電極31とが短絡することを防止するための絶縁層(障壁)である。 The edge cover 15 has an end portion (pattern end portion) of the first electrode 21, and an organic EL layer 43 (to be described later) becomes thin or an electric field concentration occurs. This is an insulating layer (barrier) for preventing the electrode 31 from being short-circuited.
 エッジカバー15は、層間絶縁膜13上に、第1電極21の端部(パターン端部)を被覆するように形成されている。 The edge cover 15 is formed on the interlayer insulating film 13 so as to cover the end portion (pattern end portion) of the first electrode 21.
 エッジカバー15には、サブ画素71R・71G・71B毎に開口部15R・15G・15Bが設けられている。これにより、第1電極21は、図5に示すように、エッジカバー15のない部分(開口部15R・15G・15B)で露出している。この露出部分が各サブ画素71R・71G・71Bの発光領域72となる。 The edge cover 15 is provided with openings 15R, 15G, and 15B for each of the sub-pixels 71R, 71G, and 71B. Thereby, as shown in FIG. 5, the 1st electrode 21 is exposed in the part (opening part 15R * 15G * 15B) without the edge cover 15. As shown in FIG. This exposed portion becomes the light emitting region 72 of each of the sub-pixels 71R, 71G, and 71B.
 <有機EL素子20の構成>
 本実施の形態では、発光色が白(W)色の発光層を使用し、各サブ画素71にマイクロキャビティ構造を導入することで上記したようにフルカラーの画像表示を実現している。
<Configuration of Organic EL Element 20>
In the present embodiment, a full-color image display is realized as described above by using a light-emitting layer whose emission color is white (W) and introducing a microcavity structure in each sub-pixel 71.
 このとき、前記したようにCF層52を併用することで、有機EL素子20から出射した光のスペクトルをCF層52によって調整することができる。 At this time, the spectrum of the light emitted from the organic EL element 20 can be adjusted by the CF layer 52 by using the CF layer 52 together as described above.
 有機EL素子20は、低電圧直流駆動による高輝度発光が可能な発光素子であり、第1電極21、有機EL層43、第2電極31が、この順に積層されている。 The organic EL element 20 is a light emitting element that can emit light with high luminance by low-voltage direct current drive, and the first electrode 21, the organic EL layer 43, and the second electrode 31 are laminated in this order.
 第1電極21は、上記有機EL層43に正孔を注入(供給)する機能を有する層である。第1電極21は、コンタクトホール13aを介してTFT12と接続されている。 The first electrode 21 is a layer having a function of injecting (supplying) holes into the organic EL layer 43. The first electrode 21 is connected to the TFT 12 through the contact hole 13a.
 また、第2電極31は、上記有機EL層43に電子を注入(供給)する機能を有する層である。 The second electrode 31 is a layer having a function of injecting (supplying) electrons into the organic EL layer 43.
 このようにW発光の発光層とCF層52とを組み合わせる場合、キャリア発生層を介してキャリア輸送層(正孔輸送層、電子輸送層)および発光層が積層される。 In this way, when the W light emitting layer and the CF layer 52 are combined, a carrier transport layer (hole transport layer, electron transport layer) and a light emitting layer are laminated via the carrier generation layer.
 具体的には、第1電極21と第2電極31との間には、図5に示すように、有機EL層43として、第1電極21側から、正孔注入層22、正孔輸送層23、第1発光層24、電子輸送層25、キャリア発生層26、正孔輸送層27、第2発光層28、電子輸送層29、および電子注入層30が、この順に形成されている。なお、第1発光層24および第2発光層28の発光色は異なっており、それらの発光色の重ね合わせにより、W発光が得られる。 Specifically, between the first electrode 21 and the second electrode 31, as shown in FIG. 5, as the organic EL layer 43, the hole injection layer 22, the hole transport layer are formed from the first electrode 21 side. 23, the first light-emitting layer 24, the electron transport layer 25, the carrier generation layer 26, the hole transport layer 27, the second light-emitting layer 28, the electron transport layer 29, and the electron injection layer 30 are formed in this order. Note that the emission colors of the first emission layer 24 and the second emission layer 28 are different, and W emission is obtained by superimposing these emission colors.
 上記発光色の組み合わせとしては、例えば、青色光と黄色(より好ましくは緑色と赤色とにピーク強度を持つ黄色(橙色))光との組み合わせ、青色光と黄色光との組み合わせ等が挙げられる。また、後述するように第1発光層24および第2発光層28に加えて第3発光層を積層することで3色の発光色の重ね合わせによりW発光を得る場合、上記発光色の組み合わせとしては、赤色光、青色光、緑色光の組み合わせが挙げられる。 Examples of the combination of the emission colors include a combination of blue light and yellow (more preferably yellow (orange) having a peak intensity in green and red) light, a combination of blue light and yellow light, and the like. In addition, as described later, in the case where W light emission is obtained by superimposing the three light emission colors by stacking the third light emission layer in addition to the first light emission layer 24 and the second light emission layer 28, Can be a combination of red light, blue light, and green light.
 なお、本実施の形態では、第1発光層24として青色の発光色の発光層を形成し、第2発光層28として橙色の発光色の発光層を形成した。 In the present embodiment, a blue light emitting layer is formed as the first light emitting layer 24, and an orange light emitting layer is formed as the second light emitting layer 28.
 このように発光層として第1発光層24および第2発光層28を積層する場合、第1発光層24および第2発光層28から出射された光の混合に対してマイクロキャビティ効果が加味された光が有機EL素子20により得られる。またその光を、封止基板50に設けられたCF層52によって調整することで、所望のスペクトルを有する光を外部に取り出すことができる。このようにW発光の発光層とマイクロキャビティ効果とCF層52とを組み合わせることで、色純度を高めることができる。 As described above, when the first light emitting layer 24 and the second light emitting layer 28 are stacked as the light emitting layer, the microcavity effect is added to the mixing of the light emitted from the first light emitting layer 24 and the second light emitting layer 28. Light is obtained by the organic EL element 20. Further, by adjusting the light by the CF layer 52 provided on the sealing substrate 50, light having a desired spectrum can be extracted to the outside. In this way, color purity can be increased by combining the W light emitting layer, the microcavity effect, and the CF layer 52.
 正孔注入層22は、第1電極21から有機EL層43への正孔注入効率を高める機能を有する層である。一方、電子注入層30は、第2電極31から有機EL層43への電子注入効率を高める機能を有する層である。 The hole injection layer 22 is a layer having a function of increasing the efficiency of hole injection from the first electrode 21 to the organic EL layer 43. On the other hand, the electron injection layer 30 is a layer having a function of increasing the efficiency of electron injection from the second electrode 31 to the organic EL layer 43.
 また、正孔輸送層23は、第1発光層24への正孔輸送効率を高める機能を有する層であり、正孔輸送層27は、第2発光層28への正孔輸送効率を高める機能を有する層である。 The hole transport layer 23 is a layer having a function of increasing the hole transport efficiency to the first light emitting layer 24, and the hole transport layer 27 is a function of increasing the hole transport efficiency to the second light emitting layer 28. It is a layer which has.
 一方、電子輸送層25は、第1発光層24への電子輸送効率を高める機能を有する層であり、電子輸送層29は、第2発光層28への電子輸送効率を高める機能を有する層である。 On the other hand, the electron transport layer 25 is a layer having a function of increasing the electron transport efficiency to the first light emitting layer 24, and the electron transport layer 29 is a layer having a function of increasing the electron transport efficiency to the second light emitting layer 28. is there.
 第1発光層24および第2発光層28は、それぞれ、第1電極21側から注入された正孔と第2電極31側から注入された電子とを再結合させて光を出射する機能を有する層である。第1発光層24および第2発光層28は、それぞれ、低分子蛍光色素、金属錯体等の、発光効率が高い材料で形成されている。 The first light emitting layer 24 and the second light emitting layer 28 each have a function of emitting light by recombining holes injected from the first electrode 21 side and electrons injected from the second electrode 31 side. Is a layer. The first light emitting layer 24 and the second light emitting layer 28 are each formed of a material having high light emission efficiency, such as a low molecular fluorescent dye or a metal complex.
 また、キャリア発生層26は、第1発光層24側に電子を、第2発光層28側に正孔を供給するための層である。 The carrier generation layer 26 is a layer for supplying electrons to the first light emitting layer 24 side and holes to the second light emitting layer 28 side.
 すなわち、正孔輸送層、発光層および電子輸送層を1ユニットと考えれば、第1発光層24側のユニットと、第2発光層28側のユニットとが、キャリア発生層26を介して接続されていることになる。 That is, assuming that the hole transport layer, the light-emitting layer, and the electron transport layer are one unit, the unit on the first light-emitting layer 24 side and the unit on the second light-emitting layer 28 side are connected via the carrier generation layer 26. Will be.
 このようにW発光の発光層(例えば第1発光層24および第2発光層28)とCF層52とを組み合わせた有機EL表示装置100では、マイクロキャビティ効果あるいはCF層52あるいはその他の方法で各サブ画素71の発光色を変更するため、発光層をサブ画素71毎に塗り分ける必要はない。 As described above, in the organic EL display device 100 in which the W light emitting layer (for example, the first light emitting layer 24 and the second light emitting layer 28) and the CF layer 52 are combined, the microcavity effect or the CF layer 52 or other methods are used. Since the emission color of the sub-pixel 71 is changed, it is not necessary to coat the light-emitting layer for each sub-pixel 71.
 このため、本実施の形態では、図5に示すように、正孔注入層22、正孔輸送層23、第1発光層24、電子輸送層25、キャリア発生層26、正孔輸送層27、第2発光層28、電子輸送層29、電子注入層30、および第2電極31は、第1電極21およびエッジカバー15を覆うように、支持基板10における表示領域R1の全面に渡って一様に形成されている。 Therefore, in the present embodiment, as shown in FIG. 5, a hole injection layer 22, a hole transport layer 23, a first light emitting layer 24, an electron transport layer 25, a carrier generation layer 26, a hole transport layer 27, The second light emitting layer 28, the electron transport layer 29, the electron injection layer 30, and the second electrode 31 are uniform over the entire surface of the display region R1 in the support substrate 10 so as to cover the first electrode 21 and the edge cover 15. Is formed.
 なお、図5では、正孔輸送層、発光層および電子輸送層を1ユニットとしたときに、第1発光層24側のユニットと、第2発光層28側のユニットとが、キャリア発生層26を介して接続されている場合を例に挙げて説明したが、本実施の形態はこれに限定されるものではない。 In FIG. 5, when the hole transport layer, the light emitting layer, and the electron transport layer are one unit, the unit on the first light emitting layer 24 side and the unit on the second light emitting layer 28 side are the carrier generation layer 26. However, the present embodiment is not limited to this example.
 例えば、第3の発光層を有するユニットを同様に積層してもよいし、4つ以上のユニットを積層することもできる。 For example, units having the third light emitting layer may be stacked in the same manner, or four or more units may be stacked.
 また、第2の発光層と第3の発光層とが直接積層された積層構造を有していてもよい。 In addition, it may have a stacked structure in which the second light emitting layer and the third light emitting layer are directly stacked.
 さらには、図示していないが、必要に応じて、正孔、電子といったキャリアの流れをせき止めるキャリアブロッキング層が挿入されていてもよい。例えば、発光層と電子輸送層との間にキャリアブロッキング層として正孔ブロッキング層を追加することで、正孔が電子輸送層に抜けるのを阻止し、発光効率を向上することができる。同様に、発光層と正孔輸送層との間にキャリアブロッキング層として電子ブロッキング層を追加することで、電子が正孔輸送層に抜けるのを阻止することができる。 Furthermore, although not shown, a carrier blocking layer for blocking the flow of carriers such as holes and electrons may be inserted as necessary. For example, by adding a hole blocking layer as a carrier blocking layer between the light emitting layer and the electron transporting layer, it is possible to prevent holes from escaping to the electron transporting layer and to improve the light emission efficiency. Similarly, by adding an electron blocking layer as a carrier blocking layer between the light emitting layer and the hole transport layer, it is possible to prevent electrons from being released into the hole transport layer.
 また、電子輸送層とキャリア発生層との間に電子注入層を挿入することもできる。 Also, an electron injection layer can be inserted between the electron transport layer and the carrier generation layer.
 有機EL素子20の構成の一例としては、例えば、下記(1)~(8)に示すような層構成およびこれらの層の組み合わせを採用することができる。
(1)第1電極/正孔注入層/正孔輸送層/発光層(第1発光層)/電子輸送層/キャリア発生層/正孔輸送層/発光層(第2発光層)/電子輸送層/電子注入層/第2電極
(2)第1電極/正孔注入層/正孔輸送層/発光層(第1発光層)/電子輸送層/電子注入層/キャリア発生層/正孔輸送層/発光層(第2発光層)/電子輸送層/電子注入層/第2電極
(3)第1電極/正孔注入層/正孔輸送層/発光層(第1発光層)/正孔ブロッキング層/電子輸送層/キャリア発生層/正孔輸送層/発光層(第2発光層)/正孔ブロッキング層/電子輸送層/電子注入層/第2電極
(4)第1電極/正孔注入層/正孔輸送層/電子ブロッキング層/発光層(第1発光層)/正孔ブロッキング層/電子輸送層/電子注入層/キャリア発生層/正孔輸送層/電子ブロッキング層/発光層(第2発光層)/正孔ブロッキング層/電子輸送層/電子注入層/第2電極
(5)第1電極/正孔注入層/正孔輸送層/発光層(第1発光層)/電子輸送層/キャリア発生層/正孔輸送層/発光層(第2発光層)/電子輸送層/キャリア発生層/正孔輸送層/発光層(第3発光層)/電子輸送層/電子注入層/第2電極
(6)第1電極/正孔注入層/正孔輸送層/電子ブロッキング層/発光層(第1発光層)/正孔ブロッキング層/電子輸送層/電子注入層/キャリア発生層/正孔輸送層/電子ブロッキング層/発光層(第2発光層)/正孔ブロッキング層/電子輸送層/電子注入層/キャリア発生層/正孔輸送層/電子ブロッキング層/発光層(第3発光層)/正孔ブロッキング層/電子輸送層/電子注入層/第2電極
(7)第1電極/正孔注入層/正孔輸送層/発光層(第1発光層)/電子輸送層/キャリア発生層/正孔輸送層/発光層(第2発光層)/発光層(第3発光層)/電子輸送層/電子注入層/第2電極
(8)第1電極/正孔注入層/正孔輸送層/電子ブロッキング層/発光層(第1発光層)/正孔ブロッキング層/電子輸送層/電子注入層/キャリア発生層/正孔輸送層/電子ブロッキング層/発光層(第2発光層)/発光層(第3発光層)/正孔ブロッキング層/電子輸送層/電子注入層/第2電極
 また、本実施の形態では、キャリア発生層を介してキャリア輸送層(正孔輸送層、電子輸送層)およびW発光の発光層(第1発光層24、第2発光層28)を設けるものとし、W発光の発光層として、第1発光層24および第2発光層28の少なくとも2つの発光層を設けた場合を例に挙げて説明した。
As an example of the configuration of the organic EL element 20, for example, a layer configuration as shown in the following (1) to (8) and a combination of these layers can be adopted.
(1) First electrode / hole injection layer / hole transport layer / light emitting layer (first light emitting layer) / electron transport layer / carrier generation layer / hole transport layer / light emitting layer (second light emitting layer) / electron transport Layer / electron injection layer / second electrode (2) first electrode / hole injection layer / hole transport layer / light emitting layer (first light emitting layer) / electron transport layer / electron injection layer / carrier generation layer / hole transport Layer / light emitting layer (second light emitting layer) / electron transport layer / electron injection layer / second electrode (3) first electrode / hole injection layer / hole transport layer / light emitting layer (first light emitting layer) / hole Blocking layer / electron transport layer / carrier generation layer / hole transport layer / light emitting layer (second light emitting layer) / hole blocking layer / electron transport layer / electron injection layer / second electrode (4) first electrode / hole Injection layer / hole transport layer / electron blocking layer / light emitting layer (first light emitting layer) / hole blocking layer / electron transport layer / electron injection layer / carrier generation layer / hole Sending layer / electron blocking layer / light emitting layer (second light emitting layer) / hole blocking layer / electron transport layer / electron injection layer / second electrode (5) first electrode / hole injection layer / hole transport layer / light emission Layer (first light-emitting layer) / electron transport layer / carrier generation layer / hole transport layer / light-emitting layer (second light-emitting layer) / electron transport layer / carrier generation layer / hole transport layer / light-emitting layer (third light-emitting layer) ) / Electron transport layer / electron injection layer / second electrode (6) first electrode / hole injection layer / hole transport layer / electron blocking layer / light emitting layer (first light emitting layer) / hole blocking layer / electron transport Layer / electron injection layer / carrier generation layer / hole transport layer / electron blocking layer / light emitting layer (second light emitting layer) / hole blocking layer / electron transport layer / electron injection layer / carrier generation layer / hole transport layer / Electron blocking layer / light emitting layer (third light emitting layer) / hole blocking layer / electron transport layer / electron Incoming layer / second electrode (7) first electrode / hole injection layer / hole transport layer / light emitting layer (first light emitting layer) / electron transport layer / carrier generation layer / hole transport layer / light emitting layer (second Light emitting layer) / light emitting layer (third light emitting layer) / electron transport layer / electron injection layer / second electrode (8) first electrode / hole injection layer / hole transport layer / electron blocking layer / light emitting layer (first Light emitting layer) / hole blocking layer / electron transport layer / electron injection layer / carrier generation layer / hole transport layer / electron blocking layer / light emitting layer (second light emitting layer) / light emitting layer (third light emitting layer) / hole Blocking layer / electron transport layer / electron injection layer / second electrode In the present embodiment, the carrier transport layer (hole transport layer, electron transport layer) and the W light-emitting layer (first layer) are interposed through the carrier generation layer. The light emitting layer 24 and the second light emitting layer 28) are provided. As the light emitting layer for W light emission, the first light emitting layer 24 and the second light emitting layer 28) are provided. The case of providing at least two light emitting layers of the light-emitting layer 28 has been described as an example.
 しかしながら、発光層以外の有機層は有機EL層43として必須の層ではなく、また、発光層は、少なくとも1つ設けられていればよい。有機EL層43の構成は、要求される有機EL素子20の特性に応じて適宜形成すればよい。 However, the organic layers other than the light emitting layer are not essential layers as the organic EL layer 43, and at least one light emitting layer may be provided. What is necessary is just to form the structure of the organic electroluminescent layer 43 suitably according to the characteristic of the organic electroluminescent element 20 requested | required.
 したがって、上記有機EL素子20は、一例として、例えば、(9)に示す層構成を有していてもよい。
(9)第1電極/正孔注入層/正孔輸送層/発光層(第1発光層)/電子輸送層/電子注入層/第2電極
 また、一つの層が複数の機能を有していてもよく、例えば、正孔注入層と正孔輸送層とは、上記したように互いに独立した層として形成されていてもよく、互いに一体化して設けられていてもよい。すなわち、正孔注入層および正孔輸送層として、正孔注入層と正孔輸送層とが一体化された正孔注入層兼正孔輸送層を設けてもよい。
Therefore, the organic EL element 20 may have, for example, the layer configuration shown in (9).
(9) First electrode / hole injection layer / hole transport layer / light emitting layer (first light emitting layer) / electron transport layer / electron injection layer / second electrode Further, one layer has a plurality of functions. For example, the hole injection layer and the hole transport layer may be formed as independent layers as described above, or may be provided integrally with each other. That is, as the hole injection layer and the hole transport layer, a hole injection layer / hole transport layer in which the hole injection layer and the hole transport layer are integrated may be provided.
 同様に、電子輸送層と電子注入層とは、上記したように互いに独立した層として形成されていてもよく、電子輸送層兼電子注入層として、互いに一体化して設けられていてもよい。 Similarly, the electron transport layer and the electron injection layer may be formed as layers independent from each other as described above, or may be provided integrally as an electron transport layer / electron injection layer.
 なお、上記積層順は、第1電極21を陽極とし、第2電極31を陰極としたものである。第1電極21を陰極とし、第2電極31を陽極とする場合には、有機EL層43の積層順は反転する。 Note that the stacking order is such that the first electrode 21 is an anode and the second electrode 31 is a cathode. When the first electrode 21 is a cathode and the second electrode 31 is an anode, the stacking order of the organic EL layers 43 is reversed.
 なお、第1電極21を半透明電極とし、第2電極31を反射電極とすることで、ボトムエミッション型の有機EL素子20が形成される。 The bottom emission organic EL element 20 is formed by using the first electrode 21 as a translucent electrode and the second electrode 31 as a reflective electrode.
 一方、第1電極21を反射電極とし、第2電極31を半透明電極とすることで、トップエミッション型の有機EL素子20が形成される。 On the other hand, the top emission type organic EL element 20 is formed by using the first electrode 21 as a reflective electrode and the second electrode 31 as a translucent electrode.
 なお、有機EL素子20の構成は上記例示の層構成に限定されるものではなく、要求される有機EL素子20の特性に応じて所望の層構成を採用することができる。 Note that the configuration of the organic EL element 20 is not limited to the above-described exemplary layer configuration, and a desired layer configuration can be adopted according to the required characteristics of the organic EL element 20.
 <画像表示方法>
 図6は、本実施の形態にかかる有機EL表示装置100の画像表示方法について説明する模式図である。なお、図6では、有機EL素子20の光路にかかる要部の構成を簡略化して示している。
<Image display method>
FIG. 6 is a schematic diagram for explaining an image display method of the organic EL display device 100 according to the present embodiment. In FIG. 6, the configuration of the main part on the optical path of the organic EL element 20 is shown in a simplified manner.
 本実施の形態にかかる有機EL素子20は、マイクロキャビティ構造を有している。 The organic EL element 20 according to the present embodiment has a microcavity structure.
 マイクロキャビティとは、発光した光が陽極と陰極との間で多重反射し、共振することで発光スペクトルが急峻になり、また、ピーク波長の発光強度が増幅される現象である。 The microcavity is a phenomenon in which emitted light undergoes multiple reflections between the anode and the cathode and resonates, resulting in a steep emission spectrum and amplification of the emission intensity at the peak wavelength.
 マイクロキャビティ効果は、例えば、陽極や陰極の反射率および膜厚、有機層の膜厚等を最適に設計することで得ることができる。 The microcavity effect can be obtained, for example, by optimally designing the reflectance and film thickness of the anode and cathode, the film thickness of the organic layer, and the like.
 本実施の形態にかかる有機EL素子20は、トップエミッション型の有機EL素子であり、図6に示すように、陰極であり発光を取り出す側の第2電極31が半透明電極(半透過反射電極)として機能し、陽極であり発光を取り出さない側の第1電極21が、反射電極層111を有することで反射電極として機能する。 The organic EL element 20 according to the present embodiment is a top emission type organic EL element. As shown in FIG. 6, the second electrode 31 on the side of taking out light emission as a cathode is a semitransparent electrode (semi-transmissive reflective electrode). The first electrode 21 on the side that is an anode and does not extract light emission has the reflective electrode layer 111 and functions as a reflective electrode.
 このため、第1電極21と第2電極31との間に設けられた有機EL層43における発光層(図5に示す例では第1発光層24および第2発光層28)から発光された光は、第1電極21における反射電極層111と第2電極31との間で反射を繰り返す。 For this reason, the light emitted from the light emitting layer (the first light emitting layer 24 and the second light emitting layer 28 in the example shown in FIG. 5) in the organic EL layer 43 provided between the first electrode 21 and the second electrode 31. Repeats reflection between the reflective electrode layer 111 and the second electrode 31 in the first electrode 21.
 このとき、図6に示すように、発光色毎に、各サブ画素71R・71G・71Bにおける有機EL素子20の光路長73R・73G・73Bを変えることで、上記発光層から発光した光が第1電極21の反射層と第2電極31との間で往復し、特定波長の光の強度が増幅される。 At this time, as shown in FIG. 6, by changing the optical path lengths 73R, 73G, and 73B of the organic EL element 20 in each of the sub-pixels 71R, 71G, and 71B for each emission color, It reciprocates between the reflective layer of the 1 electrode 21 and the 2nd electrode 31, and the intensity | strength of the light of a specific wavelength is amplified.
 本実施の形態では、反射電極層111上に透明電極層121を設け、この透明電極層121の膜厚をサブ画素71R・71G・71B毎に変更することで、各サブ画素71R・71G・71Bにおける有機EL素子20の光路長73R・73G・73Bを変更している。 In the present embodiment, the transparent electrode layer 121 is provided on the reflective electrode layer 111, and the thickness of the transparent electrode layer 121 is changed for each of the sub-pixels 71R, 71G, and 71B, so that each of the sub-pixels 71R, 71G, and 71B. The optical path lengths 73R, 73G, and 73B of the organic EL element 20 are changed.
 具体的には、本実施の形態では、図5および図6に示すように、第1電極21を、サブ画素71Bでは反射電極層111のみで形成し、サブ画素71R・71Gを、反射電極層111と透明電極層121との積層構造とし、サブ画素71R・71Gにおける反射電極層111上の透明電極層121を1層または2層で構成することで、各サブ画素71R・71G・71Bにおける透明電極層121の膜厚を変更している。 Specifically, in the present embodiment, as shown in FIGS. 5 and 6, the first electrode 21 is formed of only the reflective electrode layer 111 in the sub-pixel 71B, and the sub-pixels 71R and 71G are formed of the reflective electrode layer. 111 and the transparent electrode layer 121, and the transparent electrode layer 121 on the reflective electrode layer 111 in the sub-pixels 71R and 71G is composed of one layer or two layers, so that the sub-pixels 71R, 71G, and 71B are transparent. The film thickness of the electrode layer 121 is changed.
 このように、各サブ画素71R・71G・71Bにおける透明電極層121の膜厚を変更することで、マイクロキャビティ効果を変化させ、発光色を調整することができる。 Thus, by changing the film thickness of the transparent electrode layer 121 in each of the sub-pixels 71R, 71G, and 71B, the microcavity effect can be changed and the emission color can be adjusted.
 各サブ画素71R・71G・71Bにおける有機EL素子20の光路長73R・73G・73B、すなわち、各サブ画素71R・71G・71Bにおけるマイクロキャビティ構造内での光路の光学距離は、共振させるべき光の波長と一定関係を有するように設定される。 The optical path lengths 73R, 73G, and 73B of the organic EL element 20 in each of the sub-pixels 71R, 71G, and 71B, that is, the optical distance of the optical path in the microcavity structure in each of the sub-pixels 71R, 71G, and 71B It is set to have a certain relationship with the wavelength.
 つまり、上記したように各サブ画素71R・71G・71Bにおける第1電極21の反射電極層111と第2電極31との間の距離を調整することで、光路長が一致した波長の光の強度が共振によって強まり、第2電極31側から、波長の一致した光のみが出射される。一方、それ以外の光路長のずれた波長の光は強度が弱まる。 That is, as described above, by adjusting the distance between the reflective electrode layer 111 of the first electrode 21 and the second electrode 31 in each of the sub-pixels 71R, 71G, and 71B, the intensity of light having a wavelength that matches the optical path length. Is strengthened by resonance, and only the light having the same wavelength is emitted from the second electrode 31 side. On the other hand, the intensity of the light having a wavelength other than the optical path length is reduced.
 したがって、これら光路長73R・73G・73Bは、第2電極31からの放出光の色に応じた光学長に設定される。 Therefore, the optical path lengths 73R, 73G, and 73B are set to optical lengths corresponding to the color of the emitted light from the second electrode 31.
 本実施の形態に示すように、例えば、サブ画素71における表示色が、R、G、Bである場合、各光路長73R・73G・73Bは、これらR、G、Bの各色の発光スペクトルピーク波長に一致するように、各光路長73R・73G・73Bが、光路長73R>光路長73G>光路長73Bの順に短くなるように、各サブ画素71R・71G・71Bにおける透明電極層121の膜厚が設定される。 As shown in the present embodiment, for example, when the display colors in the sub-pixel 71 are R, G, and B, the optical path lengths 73R, 73G, and 73B are emission spectrum peaks of these colors of R, G, and B, respectively. The film of the transparent electrode layer 121 in each of the sub-pixels 71R, 71G, and 71B so that the optical path lengths 73R, 73G, and 73B become shorter in order of the optical path length 73R> the optical path length 73G> the optical path length 73B so as to match the wavelength. Thickness is set.
 但し、各光の共振に適した光路長は複数存在するため、必ずしも光路長73R>光路長73G>光路長73Bの順に短くならなくてもよく、それ以外の関係をもたせることも可能である。 However, since there are a plurality of optical path lengths suitable for the resonance of each light, the optical path length 73R> the optical path length 73G> the optical path length 73B may not necessarily be shortened in this order, and other relationships may be provided.
 すなわち、R光の有機EL層43に重なる透明電極層121は、R光の共振に適した厚さに設定され、G光の有機EL層43に重なる透明電極層121はG光の共振に適した厚さに設定され、B光の有機EL層43に重なる透明電極層121はB光の共振に適した厚さに設定される。これにより、色純度が高い光を放出することができ、有機EL表示装置100の色再現性を向上させることができる。 That is, the transparent electrode layer 121 overlapping the R light organic EL layer 43 is set to a thickness suitable for the R light resonance, and the transparent electrode layer 121 overlapping the G light organic EL layer 43 is suitable for the G light resonance. The transparent electrode layer 121 is set to a thickness suitable for the resonance of the B light. Thereby, light with high color purity can be emitted, and the color reproducibility of the organic EL display device 100 can be improved.
 <有機EL表示装置100の製造方法>
 次に、本実施の形態にかかる有機EL表示装置100の製造方法について説明する。
<Method for Manufacturing Organic EL Display Device 100>
Next, a method for manufacturing the organic EL display device 100 according to the present embodiment will be described.
 まず、有機EL素子20における各層の材料および積層方法の概略について説明する。 First, the outline of the material of each layer and the lamination method in the organic EL element 20 will be described.
 <有機EL素子20における各層の材料および積層方法の概略>
 第1電極21は、電極材料をスパッタ法等で形成した後、フォトリソグラフィ技術およびエッチング等により、個々のサブ画素71R・71G・71Bに対応してパターン形成される。
<Outline of Material and Laminating Method of Each Layer in Organic EL Element 20>
The first electrode 21 is formed by patterning corresponding to the individual sub-pixels 71R, 71G, and 71B by photolithography and etching after an electrode material is formed by sputtering or the like.
 第1電極21としては、様々な導電性材料を用いることができるが、上記したように、絶縁基板11側に光を放射するボトムエミッション型の有機EL素子20の場合、半透明である必要がある。 As the first electrode 21, various conductive materials can be used. As described above, in the case of the bottom emission type organic EL element 20 that emits light to the insulating substrate 11 side, it needs to be translucent. is there.
 一方、絶縁基板11とは反対側から光を放射するトップエミッション型の有機EL素子20の場合には、第2電極31が半透明である必要がある。 On the other hand, in the case of the top emission type organic EL element 20 that emits light from the side opposite to the insulating substrate 11, the second electrode 31 needs to be translucent.
 有機EL素子20がトップエミッション型である場合、第1電極21における反射電極層111には、不透明な電極を用いることが望ましい。反射電極層111に用いられる反射電極材料としては、例えば、Ag(銀)、Ag合金、Al(アルミニウム)、Al合金、およびこれら電極材料からなる層を含む積層体(積層膜)を用いることができる。 When the organic EL element 20 is a top emission type, it is desirable to use an opaque electrode for the reflective electrode layer 111 in the first electrode 21. As the reflective electrode material used for the reflective electrode layer 111, for example, Ag (silver), an Ag alloy, Al (aluminum), an Al alloy, and a laminated body (laminated film) including layers made of these electrode materials are used. it can.
 また、透明電極層121に用いられる透明電極材料としては、ITO(Indium Tin Oxide:インジウム錫酸化物)、IZO(Indium Zinc Oxide:インジウム亜鉛酸化物)、ガリウム添加酸化亜鉛(GZO)等を用いることができる。 In addition, as a transparent electrode material used for the transparent electrode layer 121, ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), gallium-doped zinc oxide (GZO), or the like is used. Can do.
 一方、第2電極31には、半透明電極を用いることが望ましい。半透明電極としては、例えば、金属の半透明電極単体、金属の半透明電極層と透明電極層との積層体を用いることができるが、反射率・透過率の観点から、銀が好ましい。 On the other hand, it is desirable to use a translucent electrode for the second electrode 31. As the translucent electrode, for example, a metal translucent electrode alone or a laminate of a metal translucent electrode layer and a transparent electrode layer can be used, and silver is preferable from the viewpoint of reflectance and transmittance.
 また、第1電極21および第2電極31の積層方法としては、スパッタ法、真空蒸着法、CVD(chemical vapor deposition、化学蒸着)法、プラズマCVD法、印刷法等を用いることができる。 Further, as a method of laminating the first electrode 21 and the second electrode 31, a sputtering method, a vacuum deposition method, a CVD (chemical vapor deposition) method, a plasma CVD method, a printing method, or the like can be used.
 本実施の形態では、光路長の差によって出射される発光色を制御するために、第1電極21または第2電極31(図5および図6に示す例では第1電極21)における透明電極層121の厚みをサブ画素71R・71G・71Bに変更することで、サブ画素71R・71G・71Bにマイクロキャビティ構造を導入している。 In the present embodiment, the transparent electrode layer in the first electrode 21 or the second electrode 31 (the first electrode 21 in the examples shown in FIGS. 5 and 6) is used to control the emission color emitted by the difference in optical path length. The microcavity structure is introduced into the sub-pixels 71R, 71G, and 71B by changing the thickness of the 121 to the sub-pixels 71R, 71G, and 71B.
 なお、このように透明電極層121の厚みを変更することでサブ画素71R・71G・71Bにマイクロキャビティ構造を導入する方法については、後で詳述する。 A method for introducing a microcavity structure into the sub-pixels 71R, 71G, and 71B by changing the thickness of the transparent electrode layer 121 in this way will be described in detail later.
 有機EL層43の材料としては、既知の材料を用いることができる。 As a material of the organic EL layer 43, a known material can be used.
 正孔注入層、正孔輸送層、あるいは正孔注入層兼正孔輸送層の材料としては、例えば、アントラセン、アザトリフェニレン、フルオレノン、ヒドラゾン、スチルベン、トリフェニレン、ベンジン、スチリルアミン、トリフェニルアミン、ポルフィリン、トリアゾール、イミダゾール、オキサジアゾール、オキザゾール、ポリアリールアルカン、フェニレンジアミン、アリールアミン、およびこれらの誘導体、チオフェン系化合物、ポリシラン系化合物、ビニルカルバゾール系化合物、アニリン系化合物等の鎖状式あるいは複素環式共役系のモノマー、オリゴマー、またはポリマー等が挙げられる。 As a material of the hole injection layer, the hole transport layer, or the hole injection layer / hole transport layer, for example, anthracene, azatriphenylene, fluorenone, hydrazone, stilbene, triphenylene, benzine, styrylamine, triphenylamine, porphyrin, Linear or heterocyclic such as triazole, imidazole, oxadiazole, oxazole, polyarylalkane, phenylenediamine, arylamine, and derivatives thereof, thiophene compounds, polysilane compounds, vinylcarbazole compounds, aniline compounds Examples thereof include conjugated monomers, oligomers, and polymers.
 電子輸送層、電子注入層、あるいは電子輸送層兼電子注入層の材料としては、例えば、トリス(8-キノリノラト)アルミニウム錯体、オキサジアゾール誘導体、トリアゾール誘導体、フェニルキノキサリン誘導体、シロール誘導体等が挙げられる。 Examples of the material for the electron transport layer, the electron injection layer, or the electron transport layer / electron injection layer include tris (8-quinolinolato) aluminum complex, oxadiazole derivative, triazole derivative, phenylquinoxaline derivative, silole derivative, and the like. .
 発光層の材料としては、低分子蛍光色素、金属錯体等の発光効率が高い材料が用いられる。例えば、アントラセン、ナフタレン、インデン、フェナントレン、ピレン、ナフタセン、トリフェニレン、ペリレン、ピセン、フルオランテン、アセフェナントリレン、ペンタフェン、ペンタセン、コロネン、ブタジエン、クマリン、アクリジン、スチルベン、およびこれらの誘導体、トリス(8-キノリノラト)アルミニウム錯体、ビス(ベンゾキノリノラト)ベリリウム錯体、トリ(ジベンゾイルメチル)フェナントロリンユーロピウム錯体、ジトルイルビニルビフェニル、ヒドロキシフェニルオキサゾール、ヒドロキシフェニルチアゾール等が挙げられる。 As the material of the light emitting layer, a material having high luminous efficiency such as a low molecular fluorescent dye or a metal complex is used. For example, anthracene, naphthalene, indene, phenanthrene, pyrene, naphthacene, triphenylene, perylene, picene, fluoranthene, acephenanthrylene, pentaphen, pentacene, coronene, butadiene, coumarin, acridine, stilbene, and their derivatives, tris (8- Quinolinolato) aluminum complex, bis (benzoquinolinolato) beryllium complex, tri (dibenzoylmethyl) phenanthroline europium complex, ditoluylvinylbiphenyl, hydroxyphenyloxazole, hydroxyphenylthiazole and the like.
 なお、発光層には、それぞれ、単一の材料を用いてもよく、ある材料をホスト材料とし、他の材料をゲスト材料またはドーパントとして混ぜ込んだ混合材料を用いてもよい。 Note that a single material may be used for each light emitting layer, or a mixed material in which a certain material is used as a host material and another material is mixed as a guest material or a dopant may be used.
 キャリア発生層の材料としては、酸化モリブデンや五酸化バナジウム等の金属酸化物、あるいはそれらと芳香族炭化水素やカルバゾール誘導体等とを共蒸着したもの、AuやAgの金属薄膜、IZOやITO等の透明導電層(透明電極層)、等が挙げられる。 Materials for the carrier generation layer include metal oxides such as molybdenum oxide and vanadium pentoxide, or those co-deposited with aromatic hydrocarbons and carbazole derivatives, Au and Ag metal thin films, IZO and ITO, etc. Examples thereof include a transparent conductive layer (transparent electrode layer).
 <有機EL表示装置100の製造方法>
 次に、有機EL表示装置100の製造方法について説明する。
<Method for Manufacturing Organic EL Display Device 100>
Next, a method for manufacturing the organic EL display device 100 will be described.
 但し、本実施の形態に記載されている各構成要素の寸法、材質、形状等はあくまで一実施の形態に過ぎず、これによって本発明の範囲が限定解釈されるべきではない。 However, the dimensions, materials, shapes, and the like of each component described in the present embodiment are merely one embodiment, and the scope of the present invention should not be construed as being limited thereto.
 まず、図7を参照して、有機EL表示装置100の製造工程の流れの概要について説明する。 First, referring to FIG. 7, an outline of the flow of the manufacturing process of the organic EL display device 100 will be described.
 図7は、有機EL表示装置100の製造工程の一例を工程順に示すフローチャートである。 FIG. 7 is a flowchart showing an example of the manufacturing process of the organic EL display device 100 in the order of processes.
 また、前記したように、本実施の形態に記載の積層順は、第1電極21を陽極とし、第2電極31を陰極としたものであり、第1電極21を陰極とし、第2電極31を陽極とする場合には、第1電極21と第2電極31とで、その材料並びに厚みが反転する。 Further, as described above, the stacking order described in the present embodiment is such that the first electrode 21 is an anode, the second electrode 31 is a cathode, the first electrode 21 is a cathode, and the second electrode 31 is. Is used as the anode, the material and thickness of the first electrode 21 and the second electrode 31 are reversed.
 まず、ステップS1において、既知の方法で、絶縁基板11の表示領域R1上に、図5に示すように、TFT12、信号線14、層間絶縁膜13、およびコンタクトホール13aを形成する。 First, in step S1, a TFT 12, a signal line 14, an interlayer insulating film 13, and a contact hole 13a are formed on the display region R1 of the insulating substrate 11 as shown in FIG. 5 by a known method.
 本実施の形態のようにトップエミッション型の有機EL表示装置100を製造する場合、絶縁基板11としては、例えば、板厚0.7~1.1mmの無アルカリガラス基板等のガラス基板あるいはプラスチック基板が用いられる。 When the top emission type organic EL display device 100 is manufactured as in the present embodiment, the insulating substrate 11 is, for example, a glass substrate such as a non-alkali glass substrate having a thickness of 0.7 to 1.1 mm or a plastic substrate. Is used.
 なお、絶縁基板11のX軸方向およびY軸方向の大きさは、用途等に応じて適宜設定すればよく、特に限定されるものではない。なお、本実施の形態では、板厚0.7mmの無アルカリガラス基板を使用した。 Note that the sizes of the insulating substrate 11 in the X-axis direction and the Y-axis direction may be appropriately set according to the application and the like, and are not particularly limited. In this embodiment, a non-alkali glass substrate having a thickness of 0.7 mm is used.
 層間絶縁膜13およびコンタクトホール13aは、公知の技術でTFT12並びに信号線14等が形成された絶縁基板11上に感光性樹脂を塗布し、フォトリソグラフィ技術によりパターニングを行うことで形成される。 The interlayer insulating film 13 and the contact hole 13a are formed by applying a photosensitive resin on the insulating substrate 11 on which the TFT 12, the signal line 14, and the like are formed by a known technique, and performing patterning by a photolithography technique.
 なお、層間絶縁膜13としては、既知の感光性樹脂を用いることができる。上記感光性樹脂としては、例えば、アクリル樹脂やポリイミド樹脂等が挙げられる。層間絶縁膜13の膜厚としては、TFT12による段差を補償することができればよく、特に限定されるものではない。本実施の形態では、例えば、アクリル樹脂を、約2μmの膜厚で成膜した。 As the interlayer insulating film 13, a known photosensitive resin can be used. Examples of the photosensitive resin include acrylic resin and polyimide resin. The film thickness of the interlayer insulating film 13 is not particularly limited as long as the step due to the TFT 12 can be compensated. In the present embodiment, for example, an acrylic resin is formed with a film thickness of about 2 μm.
 なお、この工程で、TFT12を駆動するためのゲートラインおよびソースライン等の信号線14が端子部領域R3まで引き出されるようにパターン形成される。また、この工程で、例えば、図3に示すように、第2電極接続領域R2に、接続部60をパターン形成する。 In this step, a pattern is formed so that signal lines 14 such as a gate line and a source line for driving the TFT 12 are led out to the terminal portion region R3. Further, in this step, for example, as shown in FIG. 3, the connection portion 60 is pattern-formed in the second electrode connection region R2.
 次に、ステップS2において、サブ画素71R・71G・71B毎に厚みの異なる第1電極21を作製する。なお、上記したように有機EL表示装置100がトップエミッション型である場合の第1電極21の作製方法については、後で詳述する。 Next, in step S2, the first electrodes 21 having different thicknesses are produced for the sub-pixels 71R, 71G, and 71B. Note that, as described above, a method of manufacturing the first electrode 21 when the organic EL display device 100 is a top emission type will be described in detail later.
 その後、ステップS3で、層間絶縁膜13上に、第1電極21の端部(パターン端部)を被覆するとともに、図4に示すようにサブ画素71R・71G・71B毎に開口部15R・15G・15Bが形成されるようにエッジカバー15を作製する。 Thereafter, in step S3, the end portion (pattern end portion) of the first electrode 21 is covered on the interlayer insulating film 13, and the openings 15R, 15G are provided for the sub-pixels 71R, 71G, 71B as shown in FIG. The edge cover 15 is produced so that 15B is formed.
 層間絶縁膜13同様、エッジカバー15には、既知の感光性樹脂を用いることができる。上記感光性樹脂としては、例えば、アクリル樹脂やポリイミド樹脂等が挙げられる。 As with the interlayer insulating film 13, a known photosensitive resin can be used for the edge cover 15. Examples of the photosensitive resin include acrylic resin and polyimide resin.
 エッジカバー15は、隣り合うサブ画素71における第1電極21の層厚の違いによる段差を補償するとともに、上記第1電極21の端部で、第1電極21と第2電極31とが短絡することを防止するために、第1電極21の膜厚が最も厚いサブ画素71Rにおける第1電極21の表面からの高さが、例えば約1μmとなるように設定される。 The edge cover 15 compensates for the level difference due to the difference in the layer thickness of the first electrode 21 in the adjacent sub-pixel 71, and the first electrode 21 and the second electrode 31 are short-circuited at the end of the first electrode 21. In order to prevent this, the height from the surface of the first electrode 21 in the sub-pixel 71R where the film thickness of the first electrode 21 is the thickest is set to about 1 μm, for example.
 本実施の形態では、サブ画素71Rにおける第1電極21の表面からの高さが約1μmとなるように、層間絶縁膜13の表面からの高さが約1.2μmのアクリル樹脂からなるエッジカバー15をパターニング形成した。 In the present embodiment, an edge cover made of acrylic resin having a height from the surface of the interlayer insulating film 13 of about 1.2 μm so that the height from the surface of the first electrode 21 in the sub-pixel 71R is about 1 μm. 15 was formed by patterning.
 以上の工程により、第1電極21およびエッジカバー15が形成された支持基板10が作製される。 Through the above steps, the support substrate 10 on which the first electrode 21 and the edge cover 15 are formed is manufactured.
 次に、ステップS4で、上記のような工程を経た支持基板10に対し、脱水のための減圧ベークおよび第1電極21の表面洗浄として酸素プラズマ処理を施した後、図5に示すように第1電極21およびエッジカバー15を被覆するように、支持基板10の表示領域R1の全面に有機EL層43を作製する。なお、有機EL層43の作製方法については後で具体的に説明する。 Next, in step S4, the support substrate 10 that has undergone the above-described processes is subjected to oxygen plasma treatment as a vacuum baking for dehydration and surface cleaning of the first electrode 21, and then, as shown in FIG. An organic EL layer 43 is formed on the entire surface of the display region R1 of the support substrate 10 so as to cover the one electrode 21 and the edge cover 15. A method for producing the organic EL layer 43 will be specifically described later.
 その後、ステップS5で、既知の方法で、第2電極31を形成する。具体的には、第2電極31を、表示領域R1の全面に形成するとともに、第2電極接続領域R2の接続部60と電気的に接続するため、それらの領域が露出するように、例えば蒸着用のマスクを用いた蒸着法によりパターン形成する。なお、第2電極31の作製には、有機EL層43と同様の方法を用いることができる。 Thereafter, in step S5, the second electrode 31 is formed by a known method. Specifically, the second electrode 31 is formed on the entire surface of the display region R1, and is electrically connected to the connection portion 60 of the second electrode connection region R2, so that, for example, vapor deposition is performed so that these regions are exposed. A pattern is formed by a vapor deposition method using a mask for use. Note that the second electrode 31 can be manufactured using the same method as that for the organic EL layer 43.
 第2電極31の膜厚は、10~30nmであることが好ましい。第2電極31の膜厚が10nm未満の場合には光の反射が十分行えず、マイクロキャビティ効果を十分得ることができないおそれがある。一方、第2電極31の膜厚が30nmを超える場合には、光の透過率が下がって輝度が低下するおそれがある。本実施の形態では、第2電極31としてAgを20nmの膜厚で形成した。 The film thickness of the second electrode 31 is preferably 10 to 30 nm. When the film thickness of the second electrode 31 is less than 10 nm, light cannot be sufficiently reflected, and there is a possibility that the microcavity effect cannot be obtained sufficiently. On the other hand, when the film thickness of the second electrode 31 exceeds 30 nm, the light transmittance may decrease and the luminance may decrease. In the present embodiment, Ag is formed with a thickness of 20 nm as the second electrode 31.
 これにより、支持基板10上に、第1電極21、有機EL層43、および第2電極31からなる有機EL素子20を形成した。 Thereby, the organic EL element 20 including the first electrode 21, the organic EL layer 43, and the second electrode 31 was formed on the support substrate 10.
 次いで、ステップS6で、図2に示すように、有機EL素子20が形成された支持基板10と封止基板50とを、封止樹脂層41にて貼り合わせ、有機EL素子20の封入を行う。 Next, in step S6, as shown in FIG. 2, the support substrate 10 on which the organic EL element 20 is formed and the sealing substrate 50 are bonded together with the sealing resin layer 41, and the organic EL element 20 is sealed. .
 また、有機EL素子20の封入は、例えば、以下のようにして行うことができる。 Moreover, the organic EL element 20 can be sealed as follows, for example.
 まず、図3に示す支持基板10における表示領域R1および第2電極接続領域R2を囲む枠状の封止領域Lに、図2に示すように封止樹脂層41を形成する。 First, as shown in FIG. 2, a sealing resin layer 41 is formed in a frame-shaped sealing region L surrounding the display region R1 and the second electrode connection region R2 in the support substrate 10 shown in FIG.
 次いで、支持基板10と封止樹脂層41とで囲まれた空間に、第2電極31を覆うように、酸素や水分が外部から有機EL素子20内に浸入することを阻止する保護膜として、乾燥剤を含有した接着性を有する充填樹脂層42を充填する。 Next, as a protective film that prevents oxygen and moisture from entering the organic EL element 20 from the outside so as to cover the second electrode 31 in the space surrounded by the support substrate 10 and the sealing resin layer 41, The filling resin layer 42 having adhesiveness containing a desiccant is filled.
 充填樹脂層42には、例えば、エポキシ樹脂等が用いられる。充填樹脂層42の膜厚は、例えば1~20μmである。 For example, an epoxy resin is used for the filling resin layer 42. The film thickness of the filling resin layer 42 is, for example, 1 to 20 μm.
 その後、この封止樹脂層41を介して、支持基板10と封止基板50とを貼り合わせる。 Thereafter, the support substrate 10 and the sealing substrate 50 are bonded together via the sealing resin layer 41.
 これにより、支持基板10と封止基板50と封止樹脂層41および充填樹脂層42とにより、有機EL素子20が密封される。 Thereby, the organic EL element 20 is sealed by the support substrate 10, the sealing substrate 50, the sealing resin layer 41, and the filling resin layer 42.
 封止基板50としては、例えば、0.4~1.1mmの板厚を有するガラス基板あるいはプラスチック基板等の絶縁基板が用いられる。なお、本実施の形態では、板厚0.7mmの無アルカリガラス基板を用いた。 As the sealing substrate 50, for example, an insulating substrate such as a glass substrate or a plastic substrate having a plate thickness of 0.4 to 1.1 mm is used. In this embodiment, a non-alkali glass substrate having a thickness of 0.7 mm is used.
 その後、ステップS7において、図2に示すように、支持基板10の端子部領域R3の電気配線端子2に、例えば図示しないACF(Anisotropic Conductive Film:異方性導電膜)を介して、回路部102の接続端子103を接続する。このようにして、有機EL表示装置100が製造される。 Thereafter, in step S7, as shown in FIG. 2, the circuit portion 102 is connected to the electric wiring terminal 2 in the terminal portion region R3 of the support substrate 10 through an ACF (Anisotropic Conductive Film) (not shown), for example. The connection terminal 103 is connected. In this way, the organic EL display device 100 is manufactured.
 なお、封止基板50のX軸方向およびY軸方向の大きさは、目的とする有機EL表示装置100のサイズにより適宜調整してもよく、支持基板10における絶縁基板11と略同一のサイズの絶縁基板を使用し、有機EL素子20を封止した後で、目的とする有機EL表示装置100のサイズに従って分断してもよい。 Note that the sizes of the sealing substrate 50 in the X-axis direction and the Y-axis direction may be appropriately adjusted according to the size of the target organic EL display device 100, and have substantially the same size as the insulating substrate 11 in the support substrate 10. After using the insulating substrate and sealing the organic EL element 20, it may be divided according to the size of the target organic EL display device 100.
 <有機EL層43の作製工程の流れ>
 次に、図5に示す構成を有する有機EL表示装置100を例に挙げて、ステップS4における有機EL層43の作製工程の流れの概要について説明する。
<Flow of manufacturing process of organic EL layer 43>
Next, taking the organic EL display device 100 having the configuration shown in FIG. 5 as an example, an outline of the flow of the manufacturing process of the organic EL layer 43 in step S4 will be described.
 図8は、有機EL層43の作製工程の一例を工程順に示すフローチャートである。 FIG. 8 is a flowchart showing an example of a manufacturing process of the organic EL layer 43 in the order of processes.
 但し、図8に示す積層順は、第1電極21を陽極とし、第2電極31を陰極としたものであり、第1電極21を陰極とし、第2電極31を陽極とする場合には、有機EL層43の積層順は反転する。 However, the stacking order shown in FIG. 8 is such that the first electrode 21 is an anode, the second electrode 31 is a cathode, the first electrode 21 is a cathode, and the second electrode 31 is an anode. The stacking order of the organic EL layer 43 is reversed.
 図7に示すステップS4では、脱水のための減圧ベークおよび第1電極21の表面洗浄として酸素プラズマ処理が施された支持基板10に対し、図8に示すように、まず、正孔注入層22を、第1電極21およびエッジカバー15を被覆するように、支持基板10の表示領域R1の全面に、蒸着によりパターン形成する(ステップS11)。 In step S4 shown in FIG. 7, as shown in FIG. 8, first, the hole injection layer 22 is applied to the support substrate 10 that has been subjected to oxygen plasma treatment as a vacuum baking for dehydration and surface cleaning of the first electrode 21. Is formed by vapor deposition on the entire surface of the display region R1 of the support substrate 10 so as to cover the first electrode 21 and the edge cover 15 (step S11).
 上記パターン形成には、例えば真空蒸着法が用いられる。真空蒸着法では、表示領域R1の全面が開口したマスク(オープンマスク)が密着固定された支持基板10の被蒸着面を蒸着源に対向させて、蒸着源からの蒸着粒子(成膜材料)を、マスクの開口を通して被蒸着面に蒸着させる。これにより、蒸着源より飛散した蒸着粒子を、オープンマスクの開口部を通じて表示領域R1の全面に均一に蒸着させる。 For example, vacuum deposition is used for the pattern formation. In the vacuum vapor deposition method, the vapor deposition particles (film forming material) from the vapor deposition source are made so that the vapor deposition surface of the support substrate 10 to which the mask (open mask) having the entire display region R1 opened is closely fixed is opposed to the vapor deposition source. Then, vapor deposition is performed on the deposition surface through the opening of the mask. Thereby, the vapor deposition particles scattered from the vapor deposition source are uniformly vapor deposited on the entire surface of the display region R1 through the opening of the open mask.
 なお、上記蒸着は、例えば、表示領域R1の全面が開口したオープンマスクを、支持基板10に対しアライメント調整を行った後に密着して貼り合わせ、支持基板10とオープンマスクとを共に回転させながら、蒸着源より飛散した蒸着粒子を、オープンマスクの開口部を通じて表示領域R1に蒸着させてもよく、上記オープンマスクを使用し、支持基板10とオープンマスクとが密着固定された状態で蒸着源を走査して蒸着するようなスキャン蒸着を行ってもよい。 In addition, the vapor deposition may be performed by, for example, attaching an open mask having the entire display region R1 opened to the support substrate 10 after alignment adjustment, and rotating the support substrate 10 and the open mask together. The vapor deposition particles scattered from the vapor deposition source may be vapor-deposited on the display region R1 through the opening of the open mask, and the vapor deposition source is scanned with the support substrate 10 and the open mask fixedly adhered using the open mask. Scan deposition such as vapor deposition may be performed.
 なお、ここで表示領域R1の全面に蒸着とは、隣接した色の異なるサブ画素間に渡って途切れなく蒸着することを意味する。 Here, the vapor deposition on the entire surface of the display region R1 means that the vapor deposition is performed continuously between adjacent sub-pixels of different colors.
 上記蒸着には、従来と同様の真空蒸着装置を用いることができる。したがって、ここでは、真空蒸着装置並びに蒸着方法の詳細については、その説明並びに図示を省略する。 For the above vapor deposition, a vacuum vapor deposition apparatus similar to the conventional one can be used. Therefore, the description and illustration of the vacuum vapor deposition apparatus and the vapor deposition method are omitted here.
 なお、上記したように真空蒸着装置を用いて蒸着膜を成膜する場合、該真空蒸着装置は、真空ポンプによって、1.0×10-4Pa以上の真空到達率に設定されていることが望ましい。言い換えれば、真空チャンバ内の圧力は、1.0×10-4Pa以下に設定されていることが望ましい。 As described above, when a deposited film is formed using a vacuum deposition apparatus, the vacuum deposition apparatus is set to a vacuum reach of 1.0 × 10 −4 Pa or more by a vacuum pump. desirable. In other words, it is desirable that the pressure in the vacuum chamber is set to 1.0 × 10 −4 Pa or less.
 蒸着粒子の平均自由行程は、1.0×10-3Paよりも高い真空度となることで、必要十分な値が得られる。一方、真空度が1.0×10-3Paよりも低いと、同平均自由行程が短くなるため、蒸着粒子が散乱されて、被成膜基板である支持基板10への到達効率が低下したり、不要な領域へ蒸着粒子が付着したりする。このため、真空チャンバは、上記真空到達率に設定されていることが望ましい。 The average free path of the vapor-deposited particles can provide a necessary and sufficient value when the degree of vacuum is higher than 1.0 × 10 −3 Pa. On the other hand, when the degree of vacuum is lower than 1.0 × 10 −3 Pa, the mean free path is shortened, so that the vapor deposition particles are scattered and the arrival efficiency to the support substrate 10 which is the film formation substrate is lowered. Or vapor deposition particles adhere to an unnecessary area. For this reason, it is desirable that the vacuum chamber is set to the above-mentioned vacuum reachability.
 次いで、ステップS12において、オープンマスクを使用し、正孔輸送層23を、正孔注入層22を被覆するように、正孔注入層22と同じパターンで、正孔注入層22と同様にして、表示領域R1の全面にパターン形成(蒸着)する。 Next, in step S12, using an open mask, the hole transport layer 23 is coated with the hole injection layer 22 in the same pattern as the hole injection layer 22 so as to cover the hole injection layer 22. A pattern is formed (deposited) on the entire surface of the display region R1.
 その後、オープンマスクを使用し、上記正孔輸送層23を被覆するように、正孔注入層22および正孔輸送層23と同じパターンで、正孔注入層22および正孔輸送層23と同様にして、表示領域R1の全面に、各ステップで、第1発光層24(ステップS13)、電子輸送層25(ステップS14)、キャリア発生層26(ステップS15)、正孔輸送層27(ステップS16)、第2発光層28(ステップS17)、電子輸送層29(ステップS18)、電子注入層30(ステップS19)を、この順に、一様にパターン形成(蒸着)する。 Thereafter, using an open mask, the hole injection layer 22 and the hole transport layer 23 are covered with the same pattern as the hole injection layer 22 and the hole transport layer 23 so as to cover the hole transport layer 23. The first light emitting layer 24 (Step S13), the electron transport layer 25 (Step S14), the carrier generation layer 26 (Step S15), and the hole transport layer 27 (Step S16) are formed on the entire surface of the display region R1 in each step. The second light emitting layer 28 (step S17), the electron transport layer 29 (step S18), and the electron injection layer 30 (step S19) are uniformly patterned (evaporated) in this order.
 これら有機EL層43の膜厚は、例えば従来と同様に設定される。 The film thickness of these organic EL layers 43 is set, for example, in the same manner as in the past.
 なお、正孔注入層22と正孔輸送層23とは、上記したように独立した層として形成されていてもよく、前記したように一体化されていてもよい。各々の膜厚としては、例えば、1~100nmである。また、正孔注入層22と正孔輸送層23との合計の膜厚は、例えば2~200nmである。 The hole injection layer 22 and the hole transport layer 23 may be formed as independent layers as described above, or may be integrated as described above. Each film thickness is, for example, 1 to 100 nm. The total film thickness of the hole injection layer 22 and the hole transport layer 23 is, for example, 2 to 200 nm.
 また、電子輸送層29と電子注入層30とは、上記したように独立した層として形成されていてもよく、前記したように一体化されていてもよい。 Further, the electron transport layer 29 and the electron injection layer 30 may be formed as independent layers as described above, or may be integrated as described above.
 電子輸送層25、電子輸送層29、電子注入層30の各々の膜厚としては、例えば、1~100nmである。また、電子輸送層29と電子注入層30との合計の膜厚は、例えば20~200nmである。 The film thickness of each of the electron transport layer 25, the electron transport layer 29, and the electron injection layer 30 is, for example, 1 to 100 nm. The total film thickness of the electron transport layer 29 and the electron injection layer 30 is, for example, 20 to 200 nm.
 第1発光層24および第2発光層28の各々の膜厚は、例えば、10~100nmである。 The film thickness of each of the first light emitting layer 24 and the second light emitting layer 28 is, for example, 10 to 100 nm.
 また、キャリア発生層26の膜厚は、例えば、1~30nmである。 The film thickness of the carrier generation layer 26 is, for example, 1 to 30 nm.
 本実施の形態では、正孔注入層22として膜厚2nmの銅フタロシアニンを成膜した。また、正孔輸送層23として、膜厚30nmのNPB(4,4’-ビス[N-(1-ナフチル)-N-フェニルアミノ]ビフェニル)を成膜した。 In this embodiment, copper phthalocyanine having a thickness of 2 nm was formed as the hole injection layer 22. As the hole transport layer 23, NPB (4,4'-bis [N- (1-naphthyl) -N-phenylamino] biphenyl) having a thickness of 30 nm was formed.
 また、電子輸送層25および電子輸送層29として、それぞれ膜厚40nmのオキサジアゾール誘導体を成膜した。また、電子注入層30として、膜厚1nmのフッ化リチウムを成膜した。 Further, as the electron transport layer 25 and the electron transport layer 29, oxadiazole derivatives each having a film thickness of 40 nm were formed. Further, as the electron injection layer 30, lithium fluoride having a thickness of 1 nm was formed.
 また、第1発光層24および第2発光層28として、それぞれイリジウム錯体をゲスト材料とし、ホスト材料としてCBP(4,4’-N,N’-ジカルバゾール-ビフェニル)を共蒸着したものを膜厚30nmで成膜した。また、キャリア発生層26として、酸化モリブデンとNPBとを共蒸着したものを、膜厚10nmで成膜した。 The first light-emitting layer 24 and the second light-emitting layer 28 are films in which iridium complexes are used as guest materials and CBP (4,4′-N, N′-dicarbazole-biphenyl) is used as a host material. The film was formed with a thickness of 30 nm. In addition, as the carrier generation layer 26, a film obtained by co-evaporating molybdenum oxide and NPB was formed to a thickness of 10 nm.
 なお、第3発光層を有するユニットを積層する場合、例えば、ステップS18とステップS19との間に、二点鎖線で示すように、キャリア発生層(ステップS21)、正孔輸送層(ステップS22)、第3発光層(ステップS23)、電子輸送層(ステップS24)を、この順に、一様にパターン形成(蒸着)する。 In addition, when laminating | stacking the unit which has a 3rd light emitting layer, as shown with a dashed-two dotted line between step S18 and step S19, for example, a carrier generation layer (step S21) and a hole transport layer (step S22) The third light emitting layer (step S23) and the electron transport layer (step S24) are uniformly patterned (evaporated) in this order.
 この場合のキャリア発生層、正孔輸送層、第3発光層、電子輸送層の材料および膜厚としては、例えば、第2発光層28を有するユニットと同様に設定すればよい。 In this case, the material and film thickness of the carrier generation layer, the hole transport layer, the third light emitting layer, and the electron transport layer may be set in the same manner as the unit having the second light emitting layer 28, for example.
 このような有機EL表示装置100において、信号線14からの信号入力によりTFT12をON(オン)させると、第1電極21から有機EL層43へホール(正孔)が注入される。一方で、第2電極31から有機EL層43に電子が注入され、正孔と電子とが各発光層内で再結合し、再結合した正孔および電子がエネルギーを失活する際に、光として出射される。 In such an organic EL display device 100, when the TFT 12 is turned on by a signal input from the signal line 14, holes are injected from the first electrode 21 to the organic EL layer 43. On the other hand, when electrons are injected from the second electrode 31 into the organic EL layer 43, the holes and electrons recombine in each light emitting layer, and the recombined holes and electrons deactivate the energy. Is emitted.
 本実施の形態では、第1発光層24および第2発光層28は、異なる発光色の発光層であり、第1発光層24および第2発光層28から出射された光の混合がマイクロキャビティ効果を受けた結果の光が有機EL素子20により得られる。 In the present embodiment, the first light-emitting layer 24 and the second light-emitting layer 28 are light-emitting layers having different emission colors, and the mixture of light emitted from the first light-emitting layer 24 and the second light-emitting layer 28 is a microcavity effect. As a result, the organic EL element 20 obtains the light.
 <第1電極21の作製方法>
 次に、トップエミッション型の有機EL表示装置100における第1電極21の作製方法(すなわち、サブ画素71毎に光路長が異なる電極の作製方法)について説明する。
<Method for Manufacturing First Electrode 21>
Next, a manufacturing method of the first electrode 21 in the top emission type organic EL display device 100 (that is, a manufacturing method of an electrode having a different optical path length for each subpixel 71) will be described.
 図1の(a)~(i)は、ステップS2に示す、トップエミッション型の有機EL表示装置100における第1電極21の作製方法の一例を工程順に示す断面図である。 FIGS. 1A to 1I are cross-sectional views showing an example of a method for manufacturing the first electrode 21 in the top emission type organic EL display device 100 shown in step S2 in order of steps.
 まず、図5に示す層間絶縁膜13およびコンタクトホール13aが形成された支持基板10上に、図1の(a)に示すように、透明電極層である非晶質(アモルファス)のITO(以下、「a-ITO」と記す)層110、金属材料等の反射電極材料からなる反射電極層111、透明電極層であるa-ITO層112(第1の透明電極層)を、この順に、スパッタリング法等により成膜する。 First, as shown in FIG. 1A, amorphous ITO (amorphous) ITO (hereinafter referred to as “transparent electrode layer”) is formed on the support substrate 10 in which the interlayer insulating film 13 and the contact hole 13a shown in FIG. , "A-ITO") layer 110, reflective electrode layer 111 made of a reflective electrode material such as a metal material, and a-ITO layer 112 (first transparent electrode layer) which is a transparent electrode layer in this order. The film is formed by a method or the like.
 次いで、上記a-ITO層112上に、サブ画素71R・71G・71B毎に、フォトリソグラフィによりレジストパターン201R・201G・201Bを形成する。その後、各レジストパターン201R・201G・201Bをマスクとして、a-ITO層110、反射電極層111、およびa-ITO層112を、図1の(b)に示すようにエッチングした後、これらレジストパターン201R・201G・201Bを、レジスト剥離液により剥離洗浄する。 Next, resist patterns 201R, 201G, and 201B are formed on the a-ITO layer 112 by photolithography for each of the sub-pixels 71R, 71G, and 71B. Thereafter, using the resist patterns 201R, 201G, and 201B as masks, the a-ITO layer 110, the reflective electrode layer 111, and the a-ITO layer 112 are etched as shown in FIG. 201R / 201G / 201B is stripped and washed with a resist stripper.
 これにより、図1の(b)に示すように、a-ITO層110、反射電極層111、およびa-ITO層112を、各色のサブ画素71R・71G・71B毎に分離するようにパターニングする。すなわち、各色のサブ画素71R・71G・71B毎にパターン化された、a-ITO層110、反射電極層111、およびa-ITO層112を形成する。 As a result, as shown in FIG. 1B, the a-ITO layer 110, the reflective electrode layer 111, and the a-ITO layer 112 are patterned so as to be separated into sub-pixels 71R, 71G, and 71B of the respective colors. . That is, the a-ITO layer 110, the reflective electrode layer 111, and the a-ITO layer 112, which are patterned for the sub-pixels 71R, 71G, and 71B of each color, are formed.
 上記反射電極層111に用いられる反射電極材料としては、a-ITOと電食反応しない反射電極材料が好ましく、例えば、Ag、Ag合金、およびAl合金からなる群より選ばれる何れか1種を用いることができる。 The reflective electrode material used for the reflective electrode layer 111 is preferably a reflective electrode material that does not undergo an electrolytic corrosion reaction with a-ITO. For example, any one selected from the group consisting of Ag, an Ag alloy, and an Al alloy is used. be able to.
 また、反射電極層111の厚みは、例えば、50~200nmに設定される。本実施の形態では、反射電極層111として、電極厚100nmの銀合金を成膜した。 The thickness of the reflective electrode layer 111 is set to 50 to 200 nm, for example. In this embodiment mode, a silver alloy with an electrode thickness of 100 nm is formed as the reflective electrode layer 111.
 また、a-ITO層110の膜厚は、例えば200nm以下(0~200nm)に設定される。a-ITO層112の膜厚は、例えば5~50nmに設定される。本実施の形態では、電極厚100nmのa-ITO層110および電極厚20nmのa-ITO層112を成膜した。 The film thickness of the a-ITO layer 110 is set to 200 nm or less (0 to 200 nm), for example. The film thickness of the a-ITO layer 112 is set to 5 to 50 nm, for example. In this embodiment, an a-ITO layer 110 with an electrode thickness of 100 nm and an a-ITO layer 112 with an electrode thickness of 20 nm are formed.
 なお、上記エッチングには、エッチング液として、例えば、リン酸・硝酸・酢酸の混合液や塩化第二鉄等のエッチング液を用いたウェットエッチングが用いられる。また、レジスト剥離液には、例えば、モノイソプロパノールアミン等が用いられる。 In the above etching, wet etching using, for example, a mixed solution of phosphoric acid, nitric acid, and acetic acid or ferric chloride is used as the etching solution. In addition, for example, monoisopropanolamine is used as the resist stripping solution.
 その後、上記支持基板10を熱処理(アニール)することにより、図1の(c)に示すように、a-ITO層110・112を結晶化させる。 Thereafter, the support substrate 10 is heat-treated (annealed) to crystallize the a-ITO layers 110 and 112 as shown in FIG.
 なお、上記熱処理における処理温度並びに処理時間は、a-ITO層110・112を結晶化させることができるように適宜設定すればよく、特に限定されるものではない。 Note that the treatment temperature and treatment time in the heat treatment may be set as appropriate so that the a-ITO layers 110 and 112 can be crystallized, and are not particularly limited.
 本実施の形態では、200℃で1時間、熱処理を行った。これにより、a-ITOが結晶性のITO(以下、「p-ITO」と記す)に転化した。この結果、各サブ画素71R・71G・71Bにおけるa-ITO層110・112が、図1の(c)に示すように、p-ITO層113・114に転化した。 In this embodiment, heat treatment was performed at 200 ° C. for 1 hour. As a result, a-ITO was converted to crystalline ITO (hereinafter referred to as “p-ITO”). As a result, the a-ITO layers 110 and 112 in the sub-pixels 71R, 71G, and 71B were converted into p- ITO layers 113 and 114 as shown in FIG.
 なお、a-ITOからp-ITOへの転化においては、膜厚の減少等はなく、a-ITOの成膜時の膜厚が維持される。 Note that in the conversion from a-ITO to p-ITO, there is no decrease in film thickness, and the film thickness at the time of film formation of a-ITO is maintained.
 次に、図1の(d)に示すように、上記支持基板10上に、上記p-ITO層113、反射電極層111、およびp-ITO層114(第1の透明電極層)を覆うように、透明電極層であるa-ITO層115(第2の透明電極層)を、例えばスパッタリングにより成膜する。 Next, as shown in FIG. 1 (d), the p-ITO layer 113, the reflective electrode layer 111, and the p-ITO layer 114 (first transparent electrode layer) are covered on the support substrate 10. Then, an a-ITO layer 115 (second transparent electrode layer) which is a transparent electrode layer is formed by sputtering, for example.
 a-ITO層115の膜厚は、例えば40~120nmに設定される。本実施の形態では、電極厚80nmのa-ITO層115を成膜した。 The film thickness of the a-ITO layer 115 is set to 40 to 120 nm, for example. In this embodiment, the a-ITO layer 115 having an electrode thickness of 80 nm is formed.
 次いで、図1の(d)に示すように、サブ画素71Rにおけるa-ITO層115上に、フォトリソグラフィにより、平面視で、パターン化された上記p-ITO層113、反射電極層111、およびp-ITO層114を覆うように、レジストパターン202Rを形成する。 Next, as shown in FIG. 1D, on the a-ITO layer 115 in the sub-pixel 71R, the p-ITO layer 113, the reflective electrode layer 111, and the patterned electrode layer 113 in a plan view by photolithography, and A resist pattern 202R is formed so as to cover the p-ITO layer 114.
 このとき、レジストパターン202Rは、平面視で、反射電極層111の下層のp-ITO層113のパターン端部を覆うように、サブ画素71Rにおけるp-ITO層113のパターンよりも広く形成した。 At this time, the resist pattern 202R was formed wider than the pattern of the p-ITO layer 113 in the sub-pixel 71R so as to cover the pattern end of the p-ITO layer 113 below the reflective electrode layer 111 in plan view.
 言い換えれば、レジストパターン202Rは、平面視で、上記反射電極層111およびp-ITO層113と重畳し、かつ、平面視で、上記反射電極層111およびp-ITO層113よりも大きく形成した。 In other words, the resist pattern 202R overlaps with the reflective electrode layer 111 and the p-ITO layer 113 in plan view, and is larger than the reflective electrode layer 111 and the p-ITO layer 113 in plan view.
 なお、p-ITO層113のパターン端部からの平面視でのレジストパターン202Rのはみ出し量は、それぞれ2μmに設定した。 The protruding amount of the resist pattern 202R in plan view from the pattern end of the p-ITO layer 113 was set to 2 μm.
 その後、レジストパターン202Rをマスクとして、エッチング液を用いて、レジストパターン202Rでマスクされていないa-ITO層115を、図1の(e)に示すようにウェットエッチングした後、レジストパターン202Rを、レジスト剥離液により剥離洗浄する。 Thereafter, using the resist pattern 202R as a mask, the a-ITO layer 115 not masked by the resist pattern 202R is wet-etched as shown in FIG. Strip and clean with a resist stripper.
 上記エッチング液としては、例えばシュウ酸が用いられる。これにより、a-ITO層115を選択的にエッチングすることができる。また、レジスト剥離液には、図1の(b)に示すエッチングで用いたレジスト剥離液と同様のレジスト剥離液を用いることができる。 For example, oxalic acid is used as the etching solution. Thereby, the a-ITO layer 115 can be selectively etched. As the resist stripping solution, a resist stripping solution similar to the resist stripping solution used in the etching shown in FIG.
 このとき、p-ITO層113・114および反射電極層111は、上記エッチング液(シュウ酸)でエッチングされないか、または、エッチング速度が著しく遅い。このため、p-ITO層113・114および反射電極層111は、上記エッチングにより除去されずに残る。 At this time, the p- ITO layers 113 and 114 and the reflective electrode layer 111 are not etched by the etching solution (oxalic acid) or the etching rate is extremely low. Therefore, the p- ITO layers 113 and 114 and the reflective electrode layer 111 remain without being removed by the etching.
 これにより、図1の(e)に示すように、レジストパターン202Rでマスクされていた、サブ画素71Rのa-ITO層115以外のa-ITO層115のみが除去される。 Thereby, as shown in FIG. 1E, only the a-ITO layer 115 other than the a-ITO layer 115 of the sub-pixel 71R masked by the resist pattern 202R is removed.
 その後、上記支持基板10を熱処理することにより、図1の(f)に示すように、a-ITO層115を結晶化させる。 Thereafter, the support substrate 10 is heat-treated to crystallize the a-ITO layer 115 as shown in FIG.
 なお、上記熱処理における処理温度並びに処理時間は、a-ITO層115を結晶化させることができるように適宜設定すればよく、特に限定されるものではない。 Note that the treatment temperature and treatment time in the heat treatment may be set as appropriate so that the a-ITO layer 115 can be crystallized, and are not particularly limited.
 本実施の形態では、図1の(c)に示す工程と同様に、200℃で1時間、熱処理を行った。これにより、a-ITOがp-ITOに転化した。この結果、サブ画素71Rにおけるa-ITO層115が、図1の(f)に示すように、p-ITO層116に転化した。 In the present embodiment, the heat treatment was performed at 200 ° C. for 1 hour as in the process shown in FIG. Thereby, a-ITO was converted into p-ITO. As a result, the a-ITO layer 115 in the sub-pixel 71R was converted to the p-ITO layer 116 as shown in FIG.
 次に、図1の(g)に示すように、上記支持基板10上に、各サブ画素71R・71G・71Bにおける各透明電極層および反射電極層111を覆うように、透明電極層であるa-ITO層117を、例えばスパッタリングにより成膜する。 Next, as shown in FIG. 1G, a transparent electrode layer is formed on the support substrate 10 so as to cover the transparent electrode layers and the reflective electrode layers 111 in the sub-pixels 71R, 71G, and 71B. The ITO layer 117 is deposited, for example, by sputtering.
 a-ITO層117の膜厚は、例えば20~60nmに設定される。本実施の形態では、後述するように、図1の(h)に示す工程でサブ画素71Rにおけるa-ITO層117をエッチングにより除去することから、a-ITO層117の膜厚が、p-ITO層116の膜厚(サブ画素71Rにおける光路長73R)よりも小さくなるようにa-ITO層117を成膜する。このため、a-ITO層117の膜厚を、p-ITO層116の膜厚よりも小さい40nmに設定した。 The film thickness of the a-ITO layer 117 is set to 20 to 60 nm, for example. In this embodiment, as described later, since the a-ITO layer 117 in the sub-pixel 71R is removed by etching in the step shown in FIG. 1H, the film thickness of the a-ITO layer 117 is p- The a-ITO layer 117 is formed so as to be smaller than the film thickness of the ITO layer 116 (the optical path length 73R in the sub-pixel 71R). Therefore, the thickness of the a-ITO layer 117 is set to 40 nm, which is smaller than the thickness of the p-ITO layer 116.
 続いて、図1の(g)に示すように、サブ画素71Gにおけるa-ITO層117上に、フォトリソグラフィにより、平面視で、パターン化された上記p-ITO層113、反射電極層111、およびa-ITO層117を覆うように、レジストパターン202Gを形成する。 Subsequently, as shown in FIG. 1G, the p-ITO layer 113, the reflective electrode layer 111, the patterned p-ITO layer 113, and the reflective electrode layer 111 in a plan view by photolithography on the a-ITO layer 117 in the sub-pixel 71G. A resist pattern 202G is formed so as to cover the a-ITO layer 117.
 このとき、レジストパターン202Gは、平面視で、反射電極層111の下層のp-ITO層113のパターン端部を覆うように、サブ画素71Gにおけるp-ITO層113のパターンよりも広く形成した。 At this time, the resist pattern 202G was formed wider than the pattern of the p-ITO layer 113 in the sub-pixel 71G so as to cover the pattern end of the p-ITO layer 113 below the reflective electrode layer 111 in plan view.
 つまり、レジストパターン202Gもまた、平面視で、上記反射電極層111およびp-ITO層113と重畳し、かつ、平面視で、上記反射電極層111およびp-ITO層113よりも大きく形成した。 That is, the resist pattern 202G also overlaps with the reflective electrode layer 111 and the p-ITO layer 113 in plan view, and is larger than the reflective electrode layer 111 and the p-ITO layer 113 in plan view.
 なお、p-ITO層113のパターン端部からの平面視でのレジストパターン202Gのはみ出し量は、レジストパターン202Rと同じく、それぞれ2μmに設定した。 Note that the amount of protrusion of the resist pattern 202G in plan view from the pattern end of the p-ITO layer 113 was set to 2 μm, like the resist pattern 202R.
 その後、レジストパターン202Gをマスクとして、エッチング液を用いて、レジストパターン202Gでマスクされていないa-ITO層117を、図1の(h)に示すようにウェットエッチングした後、レジストパターン202Gを、レジスト剥離液により剥離洗浄する。 Thereafter, using the resist pattern 202G as a mask, an a-ITO layer 117 not masked with the resist pattern 202G is wet-etched as shown in FIG. Strip and clean with a resist stripper.
 なお、上記エッチング液および剥離液には、図1の(e)に示すエッチングで用いたエッチング液および剥離液と同様のエッチング液および剥離液を用いることができる。これにより、a-ITO層117を選択的にエッチングすることができる。 Note that as the etching solution and the stripping solution, the same etching solution and stripping solution as the etching solution and stripping solution used in the etching shown in FIG. Thereby, the a-ITO layer 117 can be selectively etched.
 このとき、p-ITO層113・114・116および反射電極層111は、上記エッチング液(シュウ酸)でエッチングされないか、または、エッチング速度が著しく遅い。このため、p-ITO層113・114・116および反射電極層111は、上記エッチングにより除去されずに残る。 At this time, the p- ITO layers 113, 114, and 116 and the reflective electrode layer 111 are not etched by the etching solution (oxalic acid), or the etching rate is extremely low. For this reason, the p- ITO layers 113, 114 and 116 and the reflective electrode layer 111 remain without being removed by the etching.
 これにより、図1の(h)に示すように、レジストパターン202Gでマスクされていた、サブ画素71Gのa-ITO層117以外のa-ITO層117のみが除去される。 Thereby, as shown in FIG. 1H, only the a-ITO layer 117 other than the a-ITO layer 117 of the sub-pixel 71G, which has been masked by the resist pattern 202G, is removed.
 その後、上記支持基板10を熱処理することにより、図1の(i)に示すように、a-ITO層117を結晶化させる。 Thereafter, the support substrate 10 is heat-treated to crystallize the a-ITO layer 117 as shown in FIG.
 なお、上記熱処理における処理温度並びに処理時間は、a-ITO層117を結晶化させることができるように適宜設定すればよく、特に限定されるものではない。 Note that the treatment temperature and treatment time in the heat treatment may be set as appropriate so that the a-ITO layer 117 can be crystallized, and are not particularly limited.
 ここでも、図1の(c)に示す工程と同様に、200℃で1時間、熱処理を行った。これにより、サブ画素71Gにおけるa-ITO層117が、図1の(i)に示すように、p-ITO層118に転化した。 Here, similarly to the process shown in FIG. 1C, heat treatment was performed at 200 ° C. for 1 hour. As a result, the a-ITO layer 117 in the sub-pixel 71G was converted to the p-ITO layer 118 as shown in FIG.
 これにより、サブ画素71Rには、反射電極層111が、反射電極層111の下層の透明電極層であるp-ITO層113と、反射電極層111の上層の透明電極層であるp-ITO層114・116とで囲まれた第1電極21が形成される。 Thereby, in the sub-pixel 71R, the reflective electrode layer 111 includes a p-ITO layer 113 which is a transparent electrode layer below the reflective electrode layer 111 and a p-ITO layer which is a transparent electrode layer above the reflective electrode layer 111. A first electrode 21 surrounded by 114 and 116 is formed.
 なお、反射電極層111の上層の透明電極層であるp-ITO層114・116は、マイクロキャビティを形成する透明電極層121として機能する。 Note that the p- ITO layers 114 and 116, which are the transparent electrode layers above the reflective electrode layer 111, function as the transparent electrode layer 121 that forms the microcavity.
 このため、サブ画素71Rでは、p-ITO層113・116の合計の膜厚が、サブ画素71Rの光路長73Rとなるように各p-ITO層113・116の膜厚が設定されている。 For this reason, in the sub-pixel 71R, the film thicknesses of the p- ITO layers 113 and 116 are set so that the total film thickness of the p- ITO layers 113 and 116 becomes the optical path length 73R of the sub-pixel 71R.
 また、サブ画素71Gには、反射電極層111が、反射電極層111の下層の透明電極層であるp-ITO層113と、反射電極層111の上層の透明電極層であるp-ITO層114、およびp-ITO層116よりも膜厚が小さいp-ITO層118とで囲まれた第1電極21が形成される。 In the sub-pixel 71G, the reflective electrode layer 111 includes a p-ITO layer 113 which is a transparent electrode layer below the reflective electrode layer 111 and a p-ITO layer 114 which is a transparent electrode layer above the reflective electrode layer 111. And the first electrode 21 surrounded by the p-ITO layer 118 having a thickness smaller than that of the p-ITO layer 116 is formed.
 サブ画素71Gでは、反射電極層111の上層の透明電極層であるp-ITO層114・118が、マイクロキャビティを形成する透明電極層121として機能する。 In the subpixel 71G, the p- ITO layers 114 and 118, which are the transparent electrode layers above the reflective electrode layer 111, function as the transparent electrode layer 121 that forms the microcavity.
 このため、サブ画素71Gでは、p-ITO層114・118の合計の膜厚がサブ画素71Gの光路長73Gとなるように各p-ITO層114・118の膜厚が設定されている。 Therefore, in the sub-pixel 71G, the film thicknesses of the p- ITO layers 114 and 118 are set so that the total film thickness of the p- ITO layers 114 and 118 becomes the optical path length 73G of the sub-pixel 71G.
 また、サブ画素71Bには、反射電極層111が、反射電極層111の下層の透明電極層であるp-ITO層113と、反射電極層111の上層の透明電極層であるp-ITO層114とで挟持された第1電極21が形成される。 In the sub-pixel 71B, the reflective electrode layer 111 includes a p-ITO layer 113 that is a transparent electrode layer below the reflective electrode layer 111, and a p-ITO layer 114 that is a transparent electrode layer above the reflective electrode layer 111. The first electrode 21 sandwiched between and is formed.
 サブ画素71Bでは、反射電極層111の上層の透明電極層であるp-ITO層114が、マイクロキャビティを形成する透明電極層121として機能する。 In the subpixel 71B, the p-ITO layer 114, which is the transparent electrode layer on the reflective electrode layer 111, functions as the transparent electrode layer 121 that forms the microcavity.
 このため、サブ画素71Bでは、p-ITO層114の膜厚がサブ画素71Gの光路長73Gとなるようにp-ITO層114の膜厚が設定されている。 Therefore, in the sub-pixel 71B, the film thickness of the p-ITO layer 114 is set so that the film thickness of the p-ITO layer 114 becomes the optical path length 73G of the sub-pixel 71G.
 但し、本実施の形態はこれに限定されるものではなく、各サブ画素71R・71G・71Bに、図示しないp-ITO層、あるいはIZO層のようにITO層とは組成が異なる透明電極層がさらに積層された構成を有していてもよい。 However, the present embodiment is not limited to this, and each of the sub-pixels 71R, 71G, 71B has a transparent electrode layer having a composition different from that of the ITO layer, such as a p-ITO layer (not shown) or an IZO layer. Furthermore, you may have the structure laminated | stacked.
 以上のように、本実施の形態によれば、上記したようにa-ITO層の成膜工程と、上記a-ITO層をフォトリソグラフィによりエッチングしてパターニングするパターニング工程と、パターニングしたa-ITO層をp-ITO層に転化させる結晶化工程とを繰り返すことで、任意のサブ画素に、p-ITO層を任意の数積層することができる。 As described above, according to the present embodiment, as described above, the a-ITO layer is formed, the patterning step of patterning the a-ITO layer by etching using photolithography, and the patterned a-ITO By repeating the crystallization step of converting the layer into a p-ITO layer, an arbitrary number of p-ITO layers can be stacked on an arbitrary sub-pixel.
 以上の処理を経ることによって、図1の(i)に示すように、異なる色のサブ画素71R・71G・71B毎に、透明電極層121の膜厚を変えることができる。 Through the above processing, as shown in FIG. 1I, the film thickness of the transparent electrode layer 121 can be changed for each of the sub-pixels 71R, 71G, and 71B of different colors.
 本実施の形態では、このようにして第1電極21を形成した後、ステップS3に示すように、エッジカバー15を作製する。 In the present embodiment, after forming the first electrode 21 in this way, the edge cover 15 is produced as shown in step S3.
 図9の(a)は、ステップS3で第1電極21上にエッジカバー15を作製したときの第1電極21の概略構成を模式的に示す断面図であり、図9の(b)は、ステップS3で第1電極21上にエッジカバー15を作製したときの第1電極21の概略構成を模式的に示す平面図である。 FIG. 9A is a cross-sectional view schematically showing a schematic configuration of the first electrode 21 when the edge cover 15 is produced on the first electrode 21 in step S3, and FIG. 4 is a plan view schematically showing a schematic configuration of the first electrode 21 when the edge cover 15 is produced on the first electrode 21 in step S3. FIG.
 本実施の形態では、図1の(d)に示したように、レジストパターン202Rを、平面視で、反射電極層111の下層のp-ITO層113のパターン端部を覆うように、サブ画素71Rにおけるp-ITO層113のパターンよりも広く形成している。 In the present embodiment, as shown in FIG. 1D, the resist pattern 202R is sub-pixel covered so as to cover the pattern end of the p-ITO layer 113 under the reflective electrode layer 111 in plan view. It is formed wider than the pattern of the p-ITO layer 113 in 71R.
 このため、本実施の形態では、図1の(e)に示す工程におけるエッチングにより、レジストパターン202Rで覆われた、p-ITO層113の周囲のa-ITO層115が、エッチング除去されずに、図9の(a)・(b)に示すように、パターン化された反射電極層111およびp-ITO層113を覆うように残る。 Therefore, in this embodiment, the a-ITO layer 115 around the p-ITO layer 113 covered with the resist pattern 202R is not etched away by the etching in the step shown in FIG. As shown in FIGS. 9A and 9B, the patterned reflective electrode layer 111 and the p-ITO layer 113 remain so as to cover them.
 また、本実施の形態では、図1の(g)に示したように、レジストパターン202Gは、平面視で、反射電極層111の下層のp-ITO層113のパターン端部を覆うように、サブ画素71Gにおける各p-ITO層113のパターンよりも広く形成している。 In this embodiment, as shown in FIG. 1G, the resist pattern 202G covers the pattern end of the p-ITO layer 113 below the reflective electrode layer 111 in plan view. It is formed wider than the pattern of each p-ITO layer 113 in the sub-pixel 71G.
 このため、本実施の形態では、図1の(h)に示す工程におけるエッチングにより、レジストパターン202Gで覆われた、p-ITO層113の周囲のa-ITO層117が、エッチング除去されずに、図9の(a)・(b)に示すように、パターン化された反射電極層111およびp-ITO層113を覆うように残る。 Therefore, in this embodiment, the a-ITO layer 117 around the p-ITO layer 113 covered with the resist pattern 202G is not etched away by the etching in the step shown in FIG. As shown in FIGS. 9A and 9B, the patterned reflective electrode layer 111 and the p-ITO layer 113 remain so as to cover them.
 このため、本実施の形態では、図1の(e)あるいは図1の(h)に示す工程の後、各サブ画素71R・71Gでは、反射電極層111の上層のみならずその側面も露出しない。 For this reason, in this embodiment, after the step shown in FIG. 1E or FIG. 1H, in each of the sub-pixels 71R and 71G, not only the upper layer of the reflective electrode layer 111 but also the side surfaces thereof are not exposed. .
 なお、図1の(a)~(i)に示す工程では、サブ画素71R・71Gにおける反射電極層111上に複数層のp-ITO層を積層したが、レジストパターンを形成するサブ画素を変更することで、任意のサブ画素における反射電極層111上に、複数層のp-ITO層を積層することができることは言うまでもない。 In the steps shown in FIGS. 1A to 1I, a plurality of p-ITO layers are stacked on the reflective electrode layer 111 in the sub-pixels 71R and 71G, but the sub-pixel forming the resist pattern is changed. Thus, it goes without saying that a plurality of p-ITO layers can be stacked on the reflective electrode layer 111 in an arbitrary subpixel.
 また、反射電極層111上に積層するp-ITO層の積層数を増加させる場合、図1の(d)あるいは図1の(g)に示す工程と同様にしてサブ画素71B上にp-ITO層を形成することで、サブ画素71R・71Gのみならず、サブ画素71Bにおいても、反射電極層111が、反射電極層111の下層の透明電極層であるp-ITO層113と、反射電極層111の上層の透明電極層であるp-ITO層114・116とで囲まれた第1電極21を得ることができる。 Further, when the number of p-ITO layers stacked on the reflective electrode layer 111 is increased, the p-ITO is formed on the sub-pixel 71B in the same manner as the process shown in FIG. 1D or FIG. By forming the layer, not only in the subpixels 71R and 71G but also in the subpixel 71B, the reflective electrode layer 111 includes a p-ITO layer 113 which is a transparent electrode layer below the reflective electrode layer 111, and a reflective electrode layer Thus, the first electrode 21 surrounded by the p- ITO layers 114 and 116, which are upper transparent electrode layers 111, can be obtained.
 <効果>
 以上のように、本実施の形態では、反射電極層111よりも上層(例えば反射電極層111上)に、非晶質の透明電極材料からなる透明電極層としてa-ITO層112(第1の透明電極層)を成膜して一括してエッチングした後、該a-ITO層112を、多結晶の透明電極材料からなる透明電極層(つまり、p-ITO層114)に転化させ、その上に成膜される透明電極層であるa-ITO層115・117(第2の透明電極層)とのエッチング耐性の違いを利用して透明電極層を積層することにより、各サブ画素71R・71G・71B間で上記透明電極層の合計の膜厚を変更する。
<Effect>
As described above, in the present embodiment, the a-ITO layer 112 (the first electrode) is formed as a transparent electrode layer made of an amorphous transparent electrode material above the reflective electrode layer 111 (for example, on the reflective electrode layer 111). After the transparent electrode layer is formed and etched together, the a-ITO layer 112 is converted into a transparent electrode layer made of a polycrystalline transparent electrode material (that is, the p-ITO layer 114). The sub-pixels 71R and 71G are formed by laminating the transparent electrode layers by utilizing the difference in etching resistance with the a-ITO layers 115 and 117 (second transparent electrode layers) which are transparent electrode layers formed on the substrate. -The total film thickness of the said transparent electrode layer is changed between 71B.
 このように、本実施の形態によれば、上記したように反射電極層111よりも上層にa-ITO層112を成膜して、反射電極層111およびa-ITO層112を一括してエッチングすることで、フォトリソグラフィの回数を増加させることなく、反射電極層111上に、p-ITO層114を積層することができる。 Thus, according to the present embodiment, as described above, the a-ITO layer 112 is formed above the reflective electrode layer 111, and the reflective electrode layer 111 and the a-ITO layer 112 are etched together. Thus, the p-ITO layer 114 can be stacked on the reflective electrode layer 111 without increasing the number of times of photolithography.
 また、本実施の形態によれば、p-ITO層114(第1の透明電極層)よりもエッチング耐性が低い透明電極層(第2の透明電極層)であるa-ITO層115・117を成膜する前に、各サブ画素71R・71G・71Bにa-ITO層112が予め積層されていることで、任意のサブ画素71に、上記第2の透明電極層を積層することができる。 In addition, according to the present embodiment, the a-ITO layers 115 and 117 which are transparent electrode layers (second transparent electrode layers) having lower etching resistance than the p-ITO layer 114 (first transparent electrode layer) are formed. Before the film formation, the a-ITO layer 112 is laminated in advance on each of the subpixels 71R, 71G, 71B, so that the second transparent electrode layer can be laminated on any subpixel 71.
 このため、特許文献3のように、透明電極層を積み上げるために結晶性を有するITO層を別途成膜してパターニングするとともにフォトリソグラフィの度に2つのサブ画素に同じ膜厚の透明電極層のパターンを形成しなくても、2回のフォトリソグラフィで、表示色が異なるサブ画素71R・71G・71B毎に、反射電極層111上の透明電極層の合計の膜厚(つまり、透明電極層121の膜厚)が異なる第1電極21を形成することができる。 Therefore, as in Patent Document 3, an ITO layer having crystallinity is separately formed and patterned in order to build up the transparent electrode layer, and the transparent electrode layer having the same film thickness is formed on two sub-pixels every time photolithography is performed. Even if the pattern is not formed, the total film thickness of the transparent electrode layer on the reflective electrode layer 111 (that is, the transparent electrode layer 121) for each of the sub-pixels 71R, 71G, and 71B having different display colors by photolithography twice. The first electrode 21 having a different thickness can be formed.
 すなわち、本実施の形態によれば、図1の(d)・(g)に示すようにサブ画素71R・71G・71B毎に透明電極層の膜厚(積層数)を変更するために必要なフォトリソグラフィの回数としては2回のフォトリソグラフィで、反射電極層111上の透明電極層121の膜厚を、サブ画素71R・71G・71B毎に任意に変更することができる。また、本実施の形態によれば、反射電極層111のエッチングを含めても、フォトリソグラフィの回数を3回に抑えることができる。 That is, according to this embodiment, as shown in FIGS. 1D and 1G, it is necessary to change the film thickness (the number of stacked layers) of the transparent electrode layer for each of the sub-pixels 71R, 71G, and 71B. As the number of times of photolithography, the film thickness of the transparent electrode layer 121 on the reflective electrode layer 111 can be arbitrarily changed for each of the sub-pixels 71R, 71G, and 71B by photolithography. Further, according to the present embodiment, the number of photolithography can be suppressed to three even when the etching of the reflective electrode layer 111 is included.
 このため、本実施の形態によれば、上記したようにフォトリソグラフィの回数を減らしたとしても、任意のサブ画素71における第2の透明電極層の膜厚を、他のサブ画素71における第2の透明電極層の膜厚とは独立して設定することが可能となる。 Therefore, according to the present embodiment, even if the number of times of photolithography is reduced as described above, the film thickness of the second transparent electrode layer in an arbitrary subpixel 71 is set to be equal to that of the second subpixel 71. It is possible to set the thickness independently of the transparent electrode layer.
 このことから、本実施の形態では、上記したように非結晶の透明電極材料からなる透明電極層と多結晶の透明電極材料からなる透明電極層とのエッチング選択性の違い(例えば上記したようにa-ITO層とp-ITO層とのエッチング選択性の違い)を利用して、各色単層での透明電極層の積み上げを行っている。 Therefore, in this embodiment, as described above, the difference in etching selectivity between the transparent electrode layer made of an amorphous transparent electrode material and the transparent electrode layer made of a polycrystalline transparent electrode material (for example, as described above) The transparent electrode layers in each color single layer are stacked using the difference in etching selectivity between the a-ITO layer and the p-ITO layer).
 本実施の形態によれば、非結晶の透明電極材料を多結晶の透明電極材料に転化させることで、エッチング液に対するエッチング耐性を高めることができる。 According to the present embodiment, the etching resistance to the etching solution can be increased by converting the amorphous transparent electrode material into the polycrystalline transparent electrode material.
 このため、本実施の形態によれば、特許文献3のように光路長の制約を受けることなく、各サブ画素71R・71G・71Bにおける光路長73R・73G・73Bを、任意かつ容易に調整することができる。 For this reason, according to the present embodiment, the optical path lengths 73R, 73G, and 73B in the sub-pixels 71R, 71G, and 71B are arbitrarily and easily adjusted without being restricted by the optical path length as in Patent Document 3. be able to.
 したがって、本実施の形態によれば、従来よりも少ない回数のフォトリソグラフィで、第1電極21の膜厚、言い換えれば、有機EL素子20の光路長を、表示色が異なるサブ画素71毎に任意に変更することができる。 Therefore, according to the present embodiment, the film thickness of the first electrode 21, in other words, the optical path length of the organic EL element 20 can be arbitrarily set for each sub-pixel 71 having a different display color by a smaller number of photolithography than conventional. Can be changed.
 したがって、従来よりもコストダウンおよびフットプリントの低減を図ることができる。 Therefore, the cost can be reduced and the footprint can be reduced as compared with the conventional case.
 また、前記したように従来の方法では、フォトレジストの剥離およびベーク工程が多くなるため、反射電極層の表面が荒れたり酸化したりして反射効率が低下したり、反射電極の表面荒れによる電極間リークが発生し、画素欠陥になるおそれがあった。 In addition, as described above, in the conventional method, the photoresist stripping and baking steps increase, so that the surface of the reflective electrode layer is roughened or oxidized to reduce the reflection efficiency, or the electrode due to the rough surface of the reflective electrode. There was a risk that a leak would occur, resulting in a pixel defect.
 しかしながら、本実施の形態によれば、露光、現像、レジスト剥離処理等の回数を低減させることができるので、そのようなおそれがなく、有機EL用基板である支持基板10の品質を向上させることができる。また、処理タクトを短くすることができる。 However, according to the present embodiment, since the number of times of exposure, development, resist stripping, and the like can be reduced, there is no such fear, and the quality of the support substrate 10 that is an organic EL substrate is improved. Can do. Further, the processing tact can be shortened.
 また、反射電極層111あるいは信号線14の端子部がAgで形成されている場合、Agが剥き出しの状態(つまり、露出状態)にあると、例えばレジストのぬれ性を高めるために支持基板10に紫外線照射を行うと、剥き出しのAgが酸化して酸化銀になる。 Further, when the terminal portion of the reflective electrode layer 111 or the signal line 14 is formed of Ag, if the Ag is in an exposed state (that is, an exposed state), for example, the support substrate 10 is provided to improve the wettability of the resist. When ultraviolet irradiation is performed, the exposed Ag is oxidized to silver oxide.
 このため、反射電極層111あるいは信号線14の端子部がAgで形成されている場合、紫外線照射を行う場合に紫外線照射時にAgが剥き出し状態にあることは望ましくない。 For this reason, when the terminal portion of the reflective electrode layer 111 or the signal line 14 is formed of Ag, it is not desirable that Ag is exposed when the ultraviolet rays are irradiated.
 また、反射電極層111あるいは信号線14の端子部がAlで形成されている場合、Alは溶剤耐性が低く、IZO層を通じて溶剤が染み込む可能性もある。 Further, when the reflective electrode layer 111 or the terminal portion of the signal line 14 is made of Al, Al has low solvent resistance, and there is a possibility that the solvent penetrates through the IZO layer.
 このため、何れの場合にも、反射電極層111および信号線14の端子部は、上記したようにp-ITO層で覆われていることが望ましい。 For this reason, in any case, it is desirable that the reflection electrode layer 111 and the terminal portion of the signal line 14 are covered with the p-ITO layer as described above.
 本実施の形態によれば、反射電極層111の下層または上層に形成されたp-ITO層は、a-ITO層の成膜工程で、ソース線等の信号線14の端子部上にもa-ITO層を成膜することで、ソース線等の信号線14の端子部を覆う保護膜として用いることができる。 According to the present embodiment, the p-ITO layer formed on the lower layer or the upper layer of the reflective electrode layer 111 is also formed on the terminal portion of the signal line 14 such as the source line in the film formation process of the a-ITO layer. By forming the ITO layer, it can be used as a protective film covering the terminal portion of the signal line 14 such as a source line.
 なお、反射電極層111上に積層した他の透明電極層についても、これら透明電極層をソース線等の信号線14の端子部上に積層することで、信号線14の端子部を覆う保護膜として用いることができる。 In addition, also about the other transparent electrode layer laminated | stacked on the reflective electrode layer 111, these transparent electrode layers are laminated | stacked on the terminal parts of signal lines 14, such as a source line, and the protective film which covers the terminal part of the signal lines 14 Can be used as
 また、本実施の形態によれば、反射電極層111および信号線14の端子部が、製造工程における早い段階でp-ITO層113・114で覆われていることで、例えば、これら反射電極層111および信号線14の端子部が現像液に浸される回数あるいは領域を低減することができる等、上記反射電極層111を、該反射電極層111の品質を損なうおそれがある上記要因から保護することができる。 In addition, according to the present embodiment, the reflection electrode layer 111 and the terminal portion of the signal line 14 are covered with the p- ITO layers 113 and 114 at an early stage in the manufacturing process. The reflective electrode layer 111 is protected from the above factors that may impair the quality of the reflective electrode layer 111, such as reducing the number of times or the area in which the terminal portions of the signal line 14 and the signal line 14 are immersed in the developer. be able to.
 また、上記したように、レジストパターン202R・202Gを、平面視で、各サブ画素71R・71Gにおけるp-ITO層113のパターンよりも広く形成して上記したように反射電極層111をp-ITO層で挟持、あるいは、p-ITO層で封止することで、同様の効果を得ることができる。 Further, as described above, the resist patterns 202R and 202G are formed wider than the pattern of the p-ITO layer 113 in each of the sub-pixels 71R and 71G in plan view, and the reflective electrode layer 111 is formed as p-ITO as described above. The same effect can be obtained by sandwiching between layers or sealing with a p-ITO layer.
 なお、p-ITOは、a-ITOを熱処理することによって得られるだけでなく、直接成膜装置によってp-ITOを形成することができる。しかしながら、p-ITOを直接成膜すると、成膜中の結晶粒の成長により膜の平坦性が低下したり、結晶間のピンホールが発生したりし易くなる。膜の平坦性が低くなると、第1電極21と第2電極31との短絡により有機EL素子20が損傷しやすくなる。またピンホールが発生していると、そこからエッチング液や現像液等が染み込み、下層の膜を損傷させるおそれがある。このため、p-ITO層は、a-ITO層を成膜した後、パターン化してからp-ITO層に転化させることが望ましい。 Note that p-ITO is not only obtained by heat-treating a-ITO, but can also be formed directly by a film forming apparatus. However, when p-ITO is formed directly, the flatness of the film is lowered due to the growth of crystal grains during the film formation, and pinholes between crystals are easily generated. When the flatness of the film is lowered, the organic EL element 20 is easily damaged due to a short circuit between the first electrode 21 and the second electrode 31. In addition, if a pinhole is generated, the etching solution or the developer may permeate there, and the underlying film may be damaged. For this reason, the p-ITO layer is preferably converted into a p-ITO layer after the a-ITO layer is formed and then patterned.
 また、図1の(b)~(j)に示すように、第1電極21は、電極層材料に適したエッチング液を用いることでテーパ状に形成される。第1電極21をテーパ状に形成することで、第1電極21における各層の膜剥がれや膜割れが生じ難くなる。 Also, as shown in FIGS. 1B to 1J, the first electrode 21 is formed in a tapered shape by using an etching solution suitable for the electrode layer material. By forming the first electrode 21 in a tapered shape, film peeling or film cracking of each layer in the first electrode 21 is difficult to occur.
 特許文献3では、反射電極層をパターニングした後、第1および第3のサブ画素に結晶性を有するITOを成膜してパターニングしている。しかしながら、結晶性を有するITOは、反射電極層のエッチングに使用されるエッチング液に対する溶解性が高い。 In Patent Document 3, after patterning the reflective electrode layer, ITO having crystallinity is formed and patterned on the first and third subpixels. However, ITO having crystallinity is highly soluble in an etching solution used for etching the reflective electrode layer.
 このため、反射電極層上に結晶性を有するITO層を直接成膜してフォトリソグラフィによりパターン化すると、反射電極層がテーパ状でなくなるおそれがある。 For this reason, when an ITO layer having crystallinity is directly formed on the reflective electrode layer and patterned by photolithography, the reflective electrode layer may not be tapered.
 一方、上記問題点を回避するために反射電極層と結晶性を有するITO層とを別々にパターニングすると、フォトリソグラフィの回数が増加する。 On the other hand, if the reflective electrode layer and the crystalline ITO layer are separately patterned in order to avoid the above problems, the number of times of photolithography increases.
 しかしながら、本実施の形態によれば、上記したようにa-ITO層110・112を成膜して反射電極層111をともにパターニングしてからa-ITO層110・112をp-ITO層113・114に転化させていることから、そのような問題が生じることもない。 However, according to the present embodiment, as described above, the a-ITO layers 110 and 112 are formed and the reflective electrode layer 111 is patterned together. Such a problem does not occur because of the conversion to 114.
 <フォトリソグラフィの変形例>
 なお、本実施の形態では、図1の(g)に示すようにa-ITO層117の膜厚をp-ITO層116の膜厚(つまり、サブ画素71Rにおける光路長73R)よりも小さくし、図1の(h)に示す工程でサブ画素71Rにおけるa-ITO層117をエッチングにより除去する場合を例に挙げて説明した。
<Modified example of photolithography>
In the present embodiment, as shown in FIG. 1G, the thickness of the a-ITO layer 117 is made smaller than the thickness of the p-ITO layer 116 (that is, the optical path length 73R in the sub-pixel 71R). The case where the a-ITO layer 117 in the sub-pixel 71R is removed by etching in the process shown in FIG. 1H has been described as an example.
 しかしながら、本実施の形態は、これに限定されるものではない。図1の(g)に示す工程でサブ画素71R・71Gの両方にレジストパターンを形成し、図1の(h)に示す工程でサブ画素71Rにおけるa-ITO層117をエッチン除去せずにそのまま残す場合には、a-ITO層117の膜厚をp-ITO層116の膜厚よりも小さく設定する必要は必ずしもない。 However, the present embodiment is not limited to this. A resist pattern is formed on both the sub-pixels 71R and 71G in the step shown in FIG. 1G, and the a-ITO layer 117 in the sub-pixel 71R is not etched away in the step shown in FIG. When leaving, it is not always necessary to set the film thickness of the a-ITO layer 117 to be smaller than the film thickness of the p-ITO layer 116.
 この場合、サブ画素71R・71Gに、それぞれa-ITO層117を結晶化してなる、同じ膜厚のp-ITO層118が形成される。 In this case, the p-ITO layer 118 having the same film thickness is formed in each of the sub-pixels 71R and 71G by crystallizing the a-ITO layer 117.
 しかしながら、本実施の形態では、図1の(d)に示す工程でサブ画素71Rにのみレジストパターン202Rを形成することで、図1の(e)に示すようにサブ画素71R以外のa-ITO層115を除去し、サブ画素71Rにのみa-ITO層115を積み上げている。 However, in this embodiment, the resist pattern 202R is formed only on the sub-pixel 71R in the step shown in FIG. 1D, so that an a-ITO other than the sub-pixel 71R is formed as shown in FIG. The layer 115 is removed, and the a-ITO layer 115 is stacked only on the sub-pixel 71R.
 このため、本実施の形態によれば、所望の光路長73Bが得られるようにa-ITO層112の膜厚を設定し、所望の光路長73Gからa-ITO層112の膜厚(言い換えれば、p-ITO層114の膜厚)を差し引いた膜厚にa-ITO層117の膜厚を設定し、所望の光路長73Rからa-ITO層112の膜厚とa-ITO層117の膜厚とを差し引いた膜厚にa-ITO層115の膜厚を設定することで、任意かつ容易に各サブ画素71R・71G・71Bの光路長73R・73G・73Bを設定・変更することができる。 Therefore, according to the present embodiment, the film thickness of the a-ITO layer 112 is set so as to obtain a desired optical path length 73B, and the film thickness of the a-ITO layer 112 (in other words, from the desired optical path length 73G) The film thickness of the a-ITO layer 117 is set to a film thickness obtained by subtracting the film thickness of the p-ITO layer 114), and the film thickness of the a-ITO layer 112 and the film of the a-ITO layer 117 from the desired optical path length 73R. By setting the film thickness of the a-ITO layer 115 to the film thickness minus the thickness, the optical path lengths 73R, 73G, and 73B of the sub-pixels 71R, 71G, and 71B can be set and changed arbitrarily and easily. .
 なお、本実施の形態では、具体例として、a-ITO層112(p-ITO層114)の電極厚を20nmとし、a-ITO層115(p-ITO層116)の電極厚を80nmとし、a-ITO層117(p-ITO層118)の電極厚を40nmとした場合を例に挙げて説明したが、上記具体例はあくまでも一例であり、本実施の形態は、これに限定されるものではない。 In this embodiment, as a specific example, the electrode thickness of the a-ITO layer 112 (p-ITO layer 114) is 20 nm, the electrode thickness of the a-ITO layer 115 (p-ITO layer 116) is 80 nm, The case where the electrode thickness of the a-ITO layer 117 (p-ITO layer 118) is 40 nm has been described as an example. However, the above specific example is merely an example, and the present embodiment is not limited thereto. is not.
 例えば、有機EL層43の膜厚設計等、設計次第で、a-ITO層112(p-ITO層114)の電極厚をさらに大きくすることもできる。 For example, the electrode thickness of the a-ITO layer 112 (p-ITO layer 114) can be further increased depending on the design such as the film thickness design of the organic EL layer 43.
 <有機EL素子20の封止方法の変形例>
 また、本実施の形態では、上記したように、乾燥剤を含有した接着性の充填樹脂層42を有機EL素子20上に形成することで、支持基板10と封止基板50との貼り合せ、並びに、有機EL素子20の封入を行う場合を例に挙げて説明した。
<Modification of sealing method of organic EL element 20>
Further, in the present embodiment, as described above, the adhesive filling resin layer 42 containing a desiccant is formed on the organic EL element 20, whereby the support substrate 10 and the sealing substrate 50 are bonded together. In addition, the case where the organic EL element 20 is sealed has been described as an example.
 しかしながら、本実施の形態はこれに限定されるものではない。支持基板10、封止基板50、および封止樹脂層41で囲まれた空間に封止樹脂を充填する代わりに、上記空間に不活性ガスを封入した中空構造としてもよい。また、それに加えて、中空構造内に乾燥剤を塗布あるいは貼付した構造を有していてもよい。但し、封止基板50側から光を射出する場合、乾燥剤によって遮光されないようにする必要がある。 However, the present embodiment is not limited to this. Instead of filling the space surrounded by the support substrate 10, the sealing substrate 50, and the sealing resin layer 41 with the sealing resin, a hollow structure in which an inert gas is sealed in the space may be used. In addition, it may have a structure in which a desiccant is applied or pasted in the hollow structure. However, when light is emitted from the sealing substrate 50 side, it is necessary to prevent light from being blocked by the desiccant.
 また、本実施の形態では、支持基板10上に、有機EL素子20および封止樹脂層41、充填樹脂層42、封止基板50が、この順に設けられた構成を有している場合を例に挙げて説明した。しかしながら、本実施の形態はこれに限定されるものではない。 In the present embodiment, an example in which the organic EL element 20, the sealing resin layer 41, the filling resin layer 42, and the sealing substrate 50 are provided in this order on the support substrate 10 is an example. And explained. However, the present embodiment is not limited to this.
 例えば、有機EL素子20の封止性能をより向上するために、有機EL素子20の上に、図示しない無機膜や有機・無機の混合積層膜等が積層されていてもよい。 For example, in order to further improve the sealing performance of the organic EL element 20, an inorganic film (not shown), a mixed organic / inorganic laminated film, or the like may be laminated on the organic EL element 20.
 さらに、無機膜や有機・無機の混合積層膜等だけで有機EL素子20の封止性能が十分であれば、封止樹脂層41や封止基板50、充填樹脂層42を省くこともできる。 Furthermore, the sealing resin layer 41, the sealing substrate 50, and the filling resin layer 42 can be omitted if the sealing performance of the organic EL element 20 is sufficient only with an inorganic film or an organic / inorganic mixed laminated film.
 また、本実施の形態では、枠状に形成された封止樹脂層41を介して、支持基板10と封止基板50とを貼り合わせることによって、有機EL素子20の封止を行う場合を例に挙げて説明した。 Moreover, in this Embodiment, the case where the organic EL element 20 is sealed by bonding the support substrate 10 and the sealing substrate 50 through the sealing resin layer 41 formed in the frame shape is an example. And explained.
 しかしながら、有機EL素子20の封止方法はこれに限定されるものではなく、例えば封止樹脂の代わりにフリットガラス(粉末ガラス)を枠状に形成して、有機EL素子20の封止を行ってもよい。 However, the sealing method of the organic EL element 20 is not limited to this, and for example, frit glass (powder glass) is formed in a frame shape instead of the sealing resin, and the organic EL element 20 is sealed. May be.
 <画素構成の変形例>
 また、本実施の形態では、1つの画素70が、R、G、Bの3色のサブ画素71R・71G・71Bで構成されている場合を例に挙げて説明した。しかしながら、本実施の形態はこれに限定されるものではない。1つの画素70は、シアン(C)、マゼンタ(M)、イエロー(Y)等、R、G、B以外の3色のサブ画素71で構成されていてもよい。
<Variation of pixel configuration>
Further, in the present embodiment, the case where one pixel 70 is configured by sub-pixels 71R, 71G, and 71B of three colors of R, G, and B has been described as an example. However, the present embodiment is not limited to this. One pixel 70 may be composed of sub-pixels 71 of three colors other than R, G, and B, such as cyan (C), magenta (M), and yellow (Y).
 また、例えば、R、G、BにY等を加えた4色のサブ画素71等、4色以上のサブ画素71で構成されていてもよい。 Further, for example, it may be composed of four or more sub-pixels 71 such as four-color sub-pixels 71 obtained by adding Y or the like to R, G, and B.
 本実施の形態によれば、上記したように、下層となるp-ITO(第1の透明電極層)とその上層のa-ITO層(第2の透明電極層)とのエッチング選択性の違いを利用して、例えば各色単層での透明電極層の積み上げを行うことで、任意のサブ画素71に任意の膜厚の透明電極層を形成することができる。 According to the present embodiment, as described above, the difference in etching selectivity between the lower p-ITO (first transparent electrode layer) and the upper a-ITO layer (second transparent electrode layer). For example, a transparent electrode layer having an arbitrary film thickness can be formed on an arbitrary sub-pixel 71 by stacking transparent electrode layers in each color single layer.
 なお、本実施の形態において、反射電極層111上の透明電極層の積層数は特に限定されるものではなく、任意に設定することができる。 In the present embodiment, the number of transparent electrode layers on the reflective electrode layer 111 is not particularly limited, and can be arbitrarily set.
 何れの場合にも、本実施の形態によれば、同じ数の透明電極層を積層する場合と比較すれば、従来よりも少ない回数のフォトリソグラフィで、表示色が異なるサブ画素間で、反射電極層上の透明電極層の積層数や合計の膜厚を変更することができる。 In any case, according to the present embodiment, as compared with the case where the same number of transparent electrode layers are stacked, the reflective electrode is formed between the sub-pixels having different display colors by a smaller number of photolithography than the conventional case. The number of transparent electrode layers on the layer and the total film thickness can be changed.
 また、本実施の形態では、上記したように、TFT12を各サブ画素71に形成したアクティブマトリクス型の有機EL表示装置100を例に挙げている。しかしながら、本実施の形態はこれに限定されるものではなく、有機EL素子20の駆動方式に影響されないようであれば、TFTが形成されていないパッシブマトリクス型の有機EL表示装置の製造についても、本発明を適用することができる。 In this embodiment, as described above, the active matrix organic EL display device 100 in which the TFT 12 is formed in each sub-pixel 71 is taken as an example. However, the present embodiment is not limited to this, and as long as it is not affected by the driving method of the organic EL element 20, the manufacture of a passive matrix organic EL display device in which TFTs are not formed is also possible. The present invention can be applied.
 <有機EL層43の作製方法の変形例>
 また、本実施の形態では、有機EL層43を真空蒸着法により作製する場合を例に挙げて説明した。しかしながら、有機EL層43の作製方法はこれに限定されるものではなく、インクジェット法、レーザ転写法等、従来公知の有機膜の成膜方法を適宜選択・採用することができることは、言うまでもない。
<Modification of Method for Manufacturing Organic EL Layer 43>
Moreover, in this Embodiment, the case where the organic electroluminescent layer 43 was produced by the vacuum evaporation method was mentioned as an example, and was demonstrated. However, the manufacturing method of the organic EL layer 43 is not limited to this, and it goes without saying that a conventionally known organic film forming method such as an ink jet method or a laser transfer method can be appropriately selected and adopted.
 <表示装置の変形例>
 また、本実施の形態では、本実施の形態で製造される表示装置として、発光素子に有機EL素子を用いた表示装置を例に挙げて説明した。しかしながら、本実施の形態はこれに限定されるものではなく、例えば無機EL素子のような微小共振器として構成することが可能な発光素子を用いた表示装置にも広く適用が可能である。
<Modification of display device>
Further, in this embodiment, the display device using the organic EL element as the light emitting element is described as an example of the display device manufactured in this embodiment. However, this embodiment is not limited to this, and can be widely applied to display devices using light-emitting elements that can be configured as microresonators such as inorganic EL elements.
 〔実施の形態2〕
 本実施の形態について主に図10の(a)~(h)に基づいて説明すれば、以下の通りである。
[Embodiment 2]
The following describes the present embodiment mainly based on FIGS. 10A to 10H.
 なお、本実施の形態では、主に、実施の形態1との相違点について説明するものとし、実施の形態1で用いた構成要素と同一の機能を有する構成要素には同一の番号を付し、その説明を省略する。 In the present embodiment, differences from the first embodiment will be mainly described. Components having the same functions as those used in the first embodiment are denoted by the same reference numerals. The description is omitted.
 本実施の形態にかかる有機EL表示装置100は、第1電極21の積層構造およびステップS2に示す第1電極21の作製方法が実施の形態1と異なることを除けば、実施の形態1と同じである。そこで、本実施の形態では、ステップS2に示す、第1電極21の他の作製方法および積層構造について説明する。 The organic EL display device 100 according to the present embodiment is the same as that of the first embodiment except that the laminated structure of the first electrode 21 and the method for producing the first electrode 21 shown in step S2 are different from those of the first embodiment. It is. Therefore, in this embodiment, another manufacturing method and a stacked structure of the first electrode 21 shown in step S2 will be described.
 <第1電極21の作製方法>
 図10の(a)~(h)は、ステップS2に示す、トップエミッション型の有機EL表示装置100における第1電極21の作製から、ステップS3に示すエッジカバーの作製までの工程の一例を、工程順に示す断面図である。
<Method for Manufacturing First Electrode 21>
FIGS. 10A to 10H show an example of processes from the production of the first electrode 21 in the top emission type organic EL display device 100 shown in step S2 to the production of the edge cover shown in step S3. It is sectional drawing shown to process order.
 本実施の形態において、図10の(a)~(c)に示す工程は、図1の(a)~(c)に示す工程と同じである。したがって、図10の(a)~(c)に示す工程については、その説明を省略する。 In the present embodiment, the steps shown in FIGS. 10 (a) to (c) are the same as the steps shown in FIGS. 1 (a) to (c). Therefore, the description of the steps shown in FIGS. 10A to 10C is omitted.
 本実施の形態では、図10の(c)に示す工程の後、図10の(d)に示すように、上記支持基板10上に、上記p-ITO層113、反射電極層111、およびp-ITO層114(第1の透明電極層)を覆うように、透明電極層であるIZO層131(第2の透明電極層)を、例えばスパッタリングにより成膜する。 In the present embodiment, after the step shown in FIG. 10C, the p-ITO layer 113, the reflective electrode layer 111, and the p-ITO layer 113 are formed on the support substrate 10 as shown in FIG. 10D. -An IZO layer 131 (second transparent electrode layer), which is a transparent electrode layer, is formed by sputtering, for example, so as to cover the ITO layer 114 (first transparent electrode layer).
 IZO層131の膜厚は、例えば20~60nmに設定される。本実施の形態では、膜厚40nmのIZO層131を成膜した。 The film thickness of the IZO layer 131 is set to 20 to 60 nm, for example. In this embodiment mode, an IZO layer 131 with a thickness of 40 nm is formed.
 続いて、図10の(d)に示すように、サブ画素71RにおけるIZO層131上に、フォトリソグラフィにより、平面視で、上記p-ITO層113、反射電極層111、およびp-ITO層114を覆うように、レジストパターン202Rを形成する。 Subsequently, as shown in FIG. 10D, the p-ITO layer 113, the reflective electrode layer 111, and the p-ITO layer 114 are formed on the IZO layer 131 in the sub-pixel 71R by photolithography in plan view. A resist pattern 202R is formed so as to cover the surface.
 その後、レジストパターン202Rをマスクとして、エッチング液を用いて、レジストパターン202RでマスクされていないIZO層131をウェットエッチングした後、レジストパターン202Rを、レジスト剥離液により剥離洗浄する。 Thereafter, using the resist pattern 202R as a mask, the IZO layer 131 not masked by the resist pattern 202R is wet-etched using an etching solution, and then the resist pattern 202R is peeled and washed with a resist stripping solution.
 なお、上記エッチング液および剥離液には、図1の(e)に示すエッチング工程で用いたエッチング液および剥離液と同様のエッチング液および剥離液を用いることができる。上記エッチング液には、例えばシュウ酸が用いられる。これにより、IZO層131を選択的にエッチングすることができる。 Note that as the etching solution and the stripping solution, the same etching solution and stripping solution as the etching solution and stripping solution used in the etching step shown in FIG. For example, oxalic acid is used as the etching solution. Thereby, the IZO layer 131 can be selectively etched.
 このとき、p-ITO層113・114および反射電極層111は、上記エッチング液(シュウ酸)でエッチングされないか、または、エッチング速度が著しく遅い。このため、p-ITO層113・114および反射電極層111は、上記エッチングにより除去されずに残る。 At this time, the p- ITO layers 113 and 114 and the reflective electrode layer 111 are not etched by the etching solution (oxalic acid) or the etching rate is extremely low. Therefore, the p- ITO layers 113 and 114 and the reflective electrode layer 111 remain without being removed by the etching.
 これにより、図10の(e)に示すように、レジストパターン202Rでマスクされた、サブ画素71RのIZO層131以外のIZO層131のみが除去される。 Thereby, as shown in FIG. 10E, only the IZO layer 131 other than the IZO layer 131 of the sub-pixel 71R masked by the resist pattern 202R is removed.
 次に、図10の(f)に示すように、上記支持基板10上に、各サブ画素71R・71G・71Bにおける各透明電極層および反射電極層111を覆うように、透明電極層であるIZO層132を、例えばスパッタリングにより成膜する。 Next, as shown in FIG. 10 (f), an IZO that is a transparent electrode layer is formed on the support substrate 10 so as to cover the transparent electrode layer 111 and the reflective electrode layer 111 in each of the sub-pixels 71R, 71G, and 71B. The layer 132 is formed by sputtering, for example.
 IZO層132の膜厚は、例えば20~60nmに設定される。本実施の形態では、IZO層132の膜厚を40nmとした。 The film thickness of the IZO layer 132 is set to 20 to 60 nm, for example. In this embodiment, the thickness of the IZO layer 132 is 40 nm.
 続いて、図10の(f)に示すように、サブ画素71R・71GにおけるIZO層132上に、フォトリソグラフィにより、平面視で、パターン化された上記各透明電極層および反射電極層111を覆うように、レジストパターン203R・203Gを形成する。 10F, the patterned transparent electrode layer 111 and the reflective electrode layer 111 are covered on the IZO layer 132 in the subpixels 71R and 71G by photolithography in plan view. In this manner, resist patterns 203R and 203G are formed.
 このとき、レジストパターン203Gは、平面視で、反射電極層111の下層のp-ITO層113のパターン端部を覆うように、サブ画素71R・71Gにおけるp-ITO層113のパターンよりも広く形成した。 At this time, the resist pattern 203G is formed wider than the pattern of the p-ITO layer 113 in the sub-pixels 71R and 71G so as to cover the pattern end of the p-ITO layer 113 below the reflective electrode layer 111 in plan view. did.
 なお、p-ITO層113のパターン端部からの平面視でのレジストパターン203Gのはみ出し量は、レジストパターン202Rと同じく、それぞれ2μmに設定した。 Note that the amount of protrusion of the resist pattern 203G in plan view from the pattern end of the p-ITO layer 113 was set to 2 μm, like the resist pattern 202R.
 また、レジストパターン203Rは、平面視で、IZO層131のパターン端部を覆うように、サブ画素71R・71GにおけるIZO層131のパターンよりも広く形成した。 Further, the resist pattern 203R was formed wider than the pattern of the IZO layer 131 in the sub-pixels 71R and 71G so as to cover the pattern end of the IZO layer 131 in plan view.
 なお、IZO層131のパターン端部からの平面視でのレジストパターン203Gのはみ出し量は、それぞれ2μmに設定した。 Note that the amount of protrusion of the resist pattern 203G in plan view from the pattern end of the IZO layer 131 was set to 2 μm.
 その後、レジストパターン203R・203Gをマスクとして、エッチング液を用いて、レジストパターン203R・203GでマスクされていないIZO層132を、図10の(g)に示すようにウェットエッチングした後、レジストパターン203R・203Gを、レジスト剥離液により剥離洗浄する。 After that, using the resist patterns 203R and 203G as a mask, the IZO layer 132 not masked with the resist patterns 203R and 203G is wet-etched as shown in FIG. -203G is stripped and washed with a resist stripping solution.
 なお、上記エッチング液および剥離液には、図10の(e)に示すエッチングで用いたエッチング液および剥離液と同様のエッチング液および剥離液を用いることができる。これにより、IZO層132を選択的にエッチングすることができる。 Note that as the etching solution and the stripping solution, the same etching solution and stripping solution as the etching solution and stripping solution used in the etching shown in FIG. Thereby, the IZO layer 132 can be selectively etched.
 このとき、前記したように、p-ITO層113・114および反射電極層111は、上記エッチング液(シュウ酸)でエッチングされないか、または、エッチング速度が著しく遅い。このため、p-ITO層113・114および反射電極層111は、上記エッチングにより除去されずに残る。 At this time, as described above, the p- ITO layers 113 and 114 and the reflective electrode layer 111 are not etched with the etching solution (oxalic acid) or the etching rate is extremely slow. Therefore, the p- ITO layers 113 and 114 and the reflective electrode layer 111 remain without being removed by the etching.
 これにより、図10の(g)に示すように、レジストパターン203R・203Gでマスクされていた、サブ画素71R・71GのIZO層132以外のIZO層132のみが除去される。 Thereby, as shown in FIG. 10G, only the IZO layer 132 other than the IZO layer 132 of the sub-pixels 71R and 71G, which has been masked by the resist patterns 203R and 203G, is removed.
 これにより、図10の(g)に示すように、サブ画素71Rには、反射電極層111が、反射電極層111の下層の透明電極層であるp-ITO層113と、反射電極層111の上層の透明電極層であるp-ITO層114およびIZO層131・132とで囲まれた第1電極21が形成される。 As a result, as shown in FIG. 10G, in the sub-pixel 71R, the reflective electrode layer 111 includes the p-ITO layer 113, which is a transparent electrode layer below the reflective electrode layer 111, and the reflective electrode layer 111. The first electrode 21 surrounded by the p-ITO layer 114 and the IZO layers 131 and 132 which are upper transparent electrode layers is formed.
 また、サブ画素71Gには、反射電極層111が、反射電極層111の下層の透明電極層であるp-ITO層113と、反射電極層111の上層の透明電極層であるp-ITO層114およびIZO層132とで囲まれた第1電極21が形成される。 In the sub-pixel 71G, the reflective electrode layer 111 includes a p-ITO layer 113 which is a transparent electrode layer below the reflective electrode layer 111 and a p-ITO layer 114 which is a transparent electrode layer above the reflective electrode layer 111. Then, the first electrode 21 surrounded by the IZO layer 132 is formed.
 また、サブ画素71Bには、反射電極層111が、反射電極層111の下層の透明電極層であるp-ITO層113と、反射電極層111の上層の透明電極層であるp-ITO層114とで挟持された第1電極21が形成される。 In the sub-pixel 71B, the reflective electrode layer 111 includes a p-ITO layer 113 that is a transparent electrode layer below the reflective electrode layer 111, and a p-ITO layer 114 that is a transparent electrode layer above the reflective electrode layer 111. The first electrode 21 sandwiched between and is formed.
 その後、図10の(h)に示すように、ステップS3で、上記各サブ画素71R・71G・71Bにおける第1電極21上にエッジカバー15を作製する。 Thereafter, as shown in FIG. 10H, the edge cover 15 is formed on the first electrode 21 in each of the sub-pixels 71R, 71G, 71B in step S3.
 本実施の形態では、反射電極層111の上層の透明電極層であるp-ITO層114およびIZO層131・132は、マイクロキャビティを形成する透明電極層121として機能する。 In the present embodiment, the p-ITO layer 114 and the IZO layers 131 and 132 that are the transparent electrode layers on the reflective electrode layer 111 function as the transparent electrode layer 121 that forms the microcavity.
 このため、サブ画素71Rでは、p-ITO層114およびIZO層131・132の合計の膜厚が、サブ画素71Rの光路長73Rとなるようにp-ITO層114およびIZO層131・132の膜厚が設定されている。 Therefore, in the sub-pixel 71R, the p-ITO layer 114 and the IZO layers 131 and 132 are formed such that the total film thickness of the p-ITO layer 114 and the IZO layers 131 and 132 becomes the optical path length 73R of the sub-pixel 71R. The thickness is set.
 また、サブ画素71Gでは、反射電極層111の上層の透明電極層であるp-ITO層114およびIZO層132が、マイクロキャビティを形成する透明電極層121として機能する。 In the sub-pixel 71G, the p-ITO layer 114 and the IZO layer 132, which are the transparent electrode layers above the reflective electrode layer 111, function as the transparent electrode layer 121 that forms the microcavity.
 このため、サブ画素71Gでは、p-ITO層114およびIZO層132の合計の膜厚がサブ画素71Gの光路長73Gとなるようにp-ITO層114およびIZO層132の膜厚が設定されている。 Therefore, in the sub-pixel 71G, the film thicknesses of the p-ITO layer 114 and the IZO layer 132 are set so that the total film thickness of the p-ITO layer 114 and the IZO layer 132 becomes the optical path length 73G of the sub-pixel 71G. Yes.
 また、サブ画素71Bでは、反射電極層111の上層の透明電極層であるp-ITO層114が、マイクロキャビティを形成する透明電極層121として機能する。 In the sub-pixel 71B, the p-ITO layer 114, which is the transparent electrode layer on the reflective electrode layer 111, functions as the transparent electrode layer 121 that forms the microcavity.
 このため、サブ画素71Bでは、p-ITO層114の膜厚がサブ画素71Gの光路長73Gとなるようにp-ITO層114の膜厚が設定されている。 Therefore, in the sub-pixel 71B, the film thickness of the p-ITO layer 114 is set so that the film thickness of the p-ITO layer 114 becomes the optical path length 73G of the sub-pixel 71G.
 以上のように、本実施の形態によれば、上記したようにa-ITO層112を結晶化してp-ITO層114に転化させた後、p-ITO層114上に、p-ITO層114よりもエッチング耐性が低い透明電極層としてIZO層を成膜し、フォトリソグラフィにより該IZO層を選択的にエッチングしてパターニングすることで、任意のサブ画素に、IZO層を積み上げることができる。 As described above, according to the present embodiment, after the a-ITO layer 112 is crystallized and converted into the p-ITO layer 114 as described above, the p-ITO layer 114 is formed on the p-ITO layer 114. By forming an IZO layer as a transparent electrode layer having lower etching resistance than that, and selectively etching and patterning the IZO layer by photolithography, the IZO layer can be stacked on an arbitrary subpixel.
 これにより、少なくとも2つのサブ画素間で透明電極層の積層数を変更することができる。 This makes it possible to change the number of laminated transparent electrode layers between at least two subpixels.
 また、本実施の形態によれば、p-ITO層114よりもエッチング耐性が低いIZO層を成膜し、フォトリソグラフィにより該IZO層を選択的にエッチングしてパターニングする工程を繰り返すことで、所望のサブ画素に、IZO層を積み上げることができる。 Further, according to the present embodiment, an IZO layer having a lower etching resistance than the p-ITO layer 114 is formed, and the process of selectively etching and patterning the IZO layer by photolithography is repeated. The IZO layer can be stacked on the sub-pixels.
 <変形例>
 但し、本実施の形態はこれに限定されるものではなく、各サブ画素71R・71G・71Bに、図示しないp-ITO層もしくはIZO層のような透明電極層がさらに積層された構成を有していてもよい。
<Modification>
However, this embodiment is not limited to this, and has a configuration in which a transparent electrode layer such as a p-ITO layer or an IZO layer (not shown) is further stacked on each of the sub-pixels 71R, 71G, and 71B. It may be.
 例えば、本実施の形態では、図10の(d)に示す工程でIZO層131を単層で積層したが、このとき、p-ITO層114よりもエッチング耐性が低い、IZO層131を含む複数の透明電極層の成膜を行ってもよい。 For example, in this embodiment, the IZO layer 131 is laminated as a single layer in the step shown in FIG. 10D, but at this time, a plurality of layers including the IZO layer 131 having lower etching resistance than the p-ITO layer 114 are used. The transparent electrode layer may be formed.
 例えば、図10の(d)に示す工程で、IZO層131上にさらにa-ITO層を成膜してからサブ画素71Rにレジストパターン202Rを形成してもよく、IZO層131上に、さらにa-ITO層およびIZO層をこの順に成膜してからサブ画素71Rにレジストパターン202Rを形成してもよい。 For example, in the step shown in FIG. 10D, an a-ITO layer may be further formed on the IZO layer 131, and then the resist pattern 202R may be formed on the sub-pixel 71R. The resist pattern 202R may be formed on the sub-pixel 71R after forming the a-ITO layer and the IZO layer in this order.
 なお、上記したようにp-ITO層114よりもエッチング耐性が低い透明電極層としてa-ITO層を形成する場合には、実施の形態1のように、レジストパターン202Rをマスクとするウェットエッチング後に、熱処理を行い、上記a-ITO層をp-ITO層に転化させればよい。 In the case where the a-ITO layer is formed as the transparent electrode layer having a lower etching resistance than the p-ITO layer 114 as described above, after the wet etching using the resist pattern 202R as a mask as in the first embodiment. Then, heat treatment may be performed to convert the a-ITO layer into a p-ITO layer.
 なお、同様の方法が、図10の(e)および図10の(f)に示す工程にも適用できることは勿論の他、さらに、図10の(g)に示す工程と図10の(h)に示す工程との間に、p-ITO層よりもエッチング耐性が低い層を、単層もしくは複数層積層して、上記と同様にしてウェットエッチングすることで、さらに透明電極層の積み上げが可能であることは、言うまでもない。 Note that the same method can be applied to the steps shown in FIGS. 10E and 10F, as well as the step shown in FIG. 10G and FIG. 10H. Between the steps shown in (1), a layer having a lower etching resistance than that of the p-ITO layer is laminated in a single layer or a plurality of layers, and wet etching is performed in the same manner as described above, so that further transparent electrode layers can be stacked. Needless to say, there is.
 何れの場合にも、本実施の形態によれば、同じ数の透明電極層を積層する場合と比較すれば、従来よりも少ない回数のフォトリソグラフィで、表示色が異なるサブ画素間で、反射電極層上の透明電極層の積層数や合計の膜厚を変更することができる。 In any case, according to the present embodiment, as compared with the case where the same number of transparent electrode layers are stacked, the reflective electrode is formed between the sub-pixels having different display colors by a smaller number of photolithography than the conventional case. The number of transparent electrode layers on the layer and the total film thickness can be changed.
 <効果>
 本実施の形態では、多結晶の透明電極材料からなる透明電極層と、該多結晶の透明電極材料からなる透明電極層上に形成された透明電極層とのエッチング選択性の違い、例えば上記したようにp-ITO層とIZO層(およびa-ITO層)とのエッチング選択性の違いを利用して透明電極層の積み上げを行う。
<Effect>
In the present embodiment, the difference in etching selectivity between the transparent electrode layer made of a polycrystalline transparent electrode material and the transparent electrode layer formed on the transparent electrode layer made of the polycrystalline transparent electrode material, for example, as described above As described above, the transparent electrode layer is stacked by utilizing the difference in etching selectivity between the p-ITO layer and the IZO layer (and the a-ITO layer).
 なお、図10の(g)に示す例では、サブ画素71R・71Gに、同じ膜厚のIZO層132がそれぞれ形成される。 In the example shown in FIG. 10G, the IZO layer 132 having the same film thickness is formed in each of the sub-pixels 71R and 71G.
 しかしながら、本実施の形態では、図10の(d)に示す工程でサブ画素71Rにのみレジストパターン202Rを形成することで、図10の(e)に示すようにサブ画素71R以外のIZO層131を除去し、サブ画素71RにのみIZO層131を積み上げている。 However, in the present embodiment, the resist pattern 202R is formed only on the sub-pixel 71R in the step shown in FIG. 10D, so that the IZO layer 131 other than the sub-pixel 71R is formed as shown in FIG. The IZO layer 131 is stacked only on the sub-pixel 71R.
 このため、本実施の形態によれば、所望の光路長73Bが得られるようにa-ITO層112の膜厚を設定し、所望の光路長73Gからa-ITO層112の膜厚(言い換えれば、p-ITO層114の膜厚)を差し引いた膜厚にIZO層131の膜厚を設定し、所望の光路長73Rからa-ITO層112の膜厚とIZO層131の膜厚とを差し引いた膜厚にIZO層132の膜厚を設定することで、任意かつ容易に各サブ画素71R・71G・71Bの光路長73R・73G・73Bを設定・変更することができる。 Therefore, according to the present embodiment, the film thickness of the a-ITO layer 112 is set so as to obtain a desired optical path length 73B, and the film thickness of the a-ITO layer 112 (in other words, from the desired optical path length 73G) The film thickness of the IZO layer 131 is set to the film thickness obtained by subtracting the film thickness of the p-ITO layer 114, and the film thickness of the a-ITO layer 112 and the film thickness of the IZO layer 131 are subtracted from the desired optical path length 73R. By setting the film thickness of the IZO layer 132 to the desired film thickness, the optical path lengths 73R, 73G, and 73B of the sub-pixels 71R, 71G, and 71B can be set and changed arbitrarily and easily.
 したがって、本実施の形態でも、特許文献3のように光路長の制約を受けることなく、2回のフォトリソグラフィで、各サブ画素71R・71G・71Bにおける光路長73R・73G・73Bを、任意かつ容易に調整することが可能である。 Therefore, also in this embodiment, the optical path lengths 73R, 73G, and 73B in the sub-pixels 71R, 71G, and 71B can be arbitrarily set by two photolithography without being restricted by the optical path length as in Patent Document 3. It can be easily adjusted.
 このため、本実施の形態でも、図10の(d)・(g)に示すようにサブ画素71R・71G・71B毎に透明電極層の膜厚(積層数)を変更するために必要なフォトリソグラフィの回数としては2回のフォトリソグラフィで、第1電極21の厚みを、サブ画素71毎に任意かつ容易に変更することができる。 For this reason, also in this embodiment, as shown in (d) and (g) of FIG. 10, the photo necessary for changing the film thickness (number of layers) of the transparent electrode layer for each of the subpixels 71R, 71G, and 71B. As the number of times of lithography, the thickness of the first electrode 21 can be arbitrarily and easily changed for each sub-pixel 71 by performing photolithography twice.
 また、本実施の形態でも、上記したように、反射電極層111のエッチングを含めても、フォトリソグラフィの回数を3回に抑えることができる。しかも、フォトリソグラフィの回数を増加させることなく、光路長が最も短いサブ画素71Bの反射電極層111上にも透明電極層としてp-ITO層114を形成することができる。 Also in this embodiment, as described above, the number of times of photolithography can be suppressed to three even if the etching of the reflective electrode layer 111 is included. Moreover, the p-ITO layer 114 can be formed as a transparent electrode layer also on the reflective electrode layer 111 of the sub-pixel 71B having the shortest optical path length without increasing the number of times of photolithography.
 したがって、従来よりも少ない回数のフォトリソグラフィで、第1電極21の膜厚、言い換えれば、有機EL素子20の光路長を、サブ画素71毎に任意に変更することができる。 Therefore, the film thickness of the first electrode 21, in other words, the optical path length of the organic EL element 20 can be arbitrarily changed for each sub-pixel 71 by a smaller number of photolithography than the conventional method.
 しかも、本実施の形態によれば、非結晶の透明電極材料からなる透明電極層を多結晶の透明電極材料からなる透明電極層に転化させることなく、上記したように、多結晶の透明電極材料からなる透明電極層と、該多結晶の透明電極材料からなる透明電極層上に形成された透明電極層とのエッチング選択性の違い、例えば上記したようにp-ITO層とIZO層とのエッチング選択性の違いを利用して透明電極層の積み上げを行うことができる。したがって、処理タクトをさらに短くすることができる。 Moreover, according to the present embodiment, as described above, without converting the transparent electrode layer made of the amorphous transparent electrode material into the transparent electrode layer made of the polycrystalline transparent electrode material, the polycrystalline transparent electrode material The difference in etching selectivity between the transparent electrode layer made of the transparent electrode layer and the transparent electrode layer formed on the transparent electrode layer made of the polycrystalline transparent electrode material, for example, the etching of the p-ITO layer and the IZO layer as described above The transparent electrode layer can be stacked using the difference in selectivity. Therefore, the processing tact can be further shortened.
 また、本実施の形態でも、反射電極層111の下層または上層に形成されたp-ITO層は、a-ITO層の成膜工程で、ソース線等の信号線14の端子部上にもa-ITO層を成膜することで、ソース線等の信号線14の端子部を覆う保護膜として用いることができる。 Also in this embodiment, the p-ITO layer formed on the lower layer or the upper layer of the reflective electrode layer 111 is also formed on the terminal portion of the signal line 14 such as the source line in the film forming process of the a-ITO layer. By forming the ITO layer, it can be used as a protective film covering the terminal portion of the signal line 14 such as a source line.
 また、反射電極層111上に積層した他の透明電極層についても、これら透明電極層をソース線等の信号線14の端子部上に積層することで、信号線14の端子部を覆う保護膜として用いることができる。 Moreover, also about the other transparent electrode layer laminated | stacked on the reflective electrode layer 111, the protective film which covers the terminal part of the signal line 14 by laminating | stacking these transparent electrode layers on the terminal parts of signal lines 14, such as a source line. Can be used as
 〔実施の形態3〕
 本実施の形態について主に図11および図12に基づいて説明すれば、以下の通りである。
[Embodiment 3]
This embodiment will be described as follows mainly based on FIG. 11 and FIG.
 なお、本実施の形態では、主に、実施の形態1、2との相違点について説明するものとし、実施の形態1、2で用いた構成要素と同一の機能を有する構成要素には同一の番号を付し、その説明を省略する。 In this embodiment, differences from Embodiments 1 and 2 will be mainly described, and the same components as those used in Embodiments 1 and 2 have the same functions. A number is assigned and description thereof is omitted.
 図11は、本実施の形態にかかる有機EL表示パネル1の概略構成を示す断面図である。なお、本実施の形態にかかる有機EL表示装置100の要部の概略構成を示す分解断面図は図2と同じであり、有機EL表示装置100における支持基板10の概略構成を示す平面図は図3と同じである。また、支持基板10における表示領域R1の要部の構成を示す平面図は図4と同じである。図11は、有機EL表示パネル1を図4に示すA-A線で切断したときの有機EL表示パネル1の概略構成を示す断面図に相当する。 FIG. 11 is a cross-sectional view showing a schematic configuration of the organic EL display panel 1 according to the present embodiment. An exploded sectional view showing a schematic configuration of a main part of the organic EL display device 100 according to the present embodiment is the same as FIG. 2, and a plan view showing a schematic configuration of the support substrate 10 in the organic EL display device 100 is a diagram. Same as 3. Moreover, the top view which shows the structure of the principal part of display area R1 in the support substrate 10 is the same as FIG. FIG. 11 corresponds to a cross-sectional view showing a schematic configuration of the organic EL display panel 1 when the organic EL display panel 1 is cut along the line AA shown in FIG.
 実施の形態1、2では、上記したように、複数の発光層を積層して発光色を重ね合わせることにより、W発光を得る場合を例に挙げて説明した。 In the first and second embodiments, as described above, the case where W light emission is obtained by stacking a plurality of light emitting layers and superimposing emission colors has been described as an example.
 しかしながら、実施の形態1、2に示す第1電極21の形成方法は、発光層の色毎に蒸着を行う塗り分け方式を用いることで、同一平面内に、発光色が異なる複数の発光層を形成する場合にも、同様に適用することができる。 However, the method for forming the first electrode 21 shown in Embodiments 1 and 2 uses a separate coating method in which vapor deposition is performed for each color of the light emitting layer, so that a plurality of light emitting layers having different light emitting colors can be formed in the same plane. The same applies to the formation.
 塗り分け方式を用いたフルカラーの有機EL表示装置100では、図11に示すように、例えば、RGBの各色の発光層82R・82G・82Bを備えた有機EL素子20が、サブ画素71R・71G・71Bとして支持基板10上に配列形成される。このような有機EL表示装置100では、TFT12を用いて、これら有機EL素子20を選択的に所望の輝度で発光させることによりカラー画像表示を行う。 In the full-color organic EL display device 100 using the separate coloring method, as shown in FIG. 11, for example, the organic EL element 20 including the light emitting layers 82R, 82G, and 82B for each color of RGB includes sub-pixels 71R, 71G, and 71B is arranged on the support substrate 10. In such an organic EL display device 100, the TFT 12 is used to perform color image display by selectively causing the organic EL elements 20 to emit light with a desired luminance.
 本実施の形態では、このように、同一平面内に、発光色が異なる複数の発光層82R・82G・82Bを形成するとともに、発光色が異なる各サブ画素71R・71G・71Bにマイクロキャビティ構造を導入することで、上記したようにフルカラーの画像表示を行っている。 In the present embodiment, a plurality of light emitting layers 82R, 82G, and 82B having different emission colors are formed in the same plane as described above, and a microcavity structure is formed in each of the sub-pixels 71R, 71G, and 71B having different emission colors. By introducing this, full-color image display is performed as described above.
 また、本実施の形態でも、図11に示すようにCF層52を併用することで、有機EL素子20から出射した光のスペクトルをCF層52によって調整することができる。 Also in the present embodiment, the CF layer 52 can be used to adjust the spectrum of light emitted from the organic EL element 20 as shown in FIG.
 本実施の形態にかかる有機EL表示装置100は、図11に示すように、有機EL素子20における有機EL層43の積層構造が異なることを除けば、図5に示す有機EL表示装置100と同じ構成を有している。 The organic EL display device 100 according to the present embodiment is the same as the organic EL display device 100 shown in FIG. 5 except that the stacked structure of the organic EL layer 43 in the organic EL element 20 is different as shown in FIG. It has a configuration.
 以下に、本実施の形態にかかる有機EL素子20の構成について説明する。 Hereinafter, the configuration of the organic EL element 20 according to the present embodiment will be described.
 <有機EL素子20の構成>
 図11に示す有機EL表示装置100において、第1電極21と第2電極31との間には、有機EL層43として、第1電極21側から、例えば、正孔注入層兼正孔輸送層81、発光層82R・82G・82B、電子輸送層兼電子注入層83が、この順に形成された構成を有している。
<Configuration of Organic EL Element 20>
In the organic EL display device 100 shown in FIG. 11, between the first electrode 21 and the second electrode 31, as the organic EL layer 43, for example, from the first electrode 21 side, for example, a hole injection layer / hole transport layer 81. The light emitting layers 82R, 82G, and 82B and the electron transport layer / electron injection layer 83 are configured in this order.
 なお、正孔注入層兼正孔輸送層および電子輸送層兼電子注入層については、実施の形態1で説明した通りであり、ここでは、正孔注入層兼正孔輸送層81および電子輸送層兼電子注入層83の説明は省略する。 The hole injection layer / hole transport layer and the electron transport layer / electron injection layer are as described in the first embodiment. Here, the hole injection layer / hole transport layer 81 and the electron transport layer / electron Description of the injection layer 83 is omitted.
 図11に示すように、正孔注入層兼正孔輸送層81は、第1電極21およびエッジカバー15を覆うように、支持基板10における表示領域R1の全面に渡って一様に形成されている。 As shown in FIG. 11, the hole injection layer / hole transport layer 81 is uniformly formed over the entire surface of the display region R <b> 1 on the support substrate 10 so as to cover the first electrode 21 and the edge cover 15. .
 正孔注入層兼正孔輸送層81上には、発光層82R・82G・82Bが、それぞれ、サブ画素71R・71G・71Bに対応して形成されている。 On the hole injection layer / hole transport layer 81, light emitting layers 82R, 82G, and 82B are formed corresponding to the sub-pixels 71R, 71G, and 71B, respectively.
 発光層82R・82G・82Bは、第1電極21側から注入された正孔と第2電極31側から注入された電子とを再結合させて光を出射する。本実施の形態でも、発光層82R・82G・82Bは、それぞれ、低分子蛍光色素、金属錯体等の、発光効率が高い材料で形成されている。 The light emitting layers 82R, 82G, and 82B emit light by recombining holes injected from the first electrode 21 side with electrons injected from the second electrode 31 side. Also in the present embodiment, the light emitting layers 82R, 82G, and 82B are each formed of a material having high luminous efficiency, such as a low molecular fluorescent dye or a metal complex.
 電子輸送層兼電子注入層83は、発光層82R・82G・82Bおよび正孔注入層兼正孔輸送層81を覆うように、これら発光層82R・82G・82Bおよび正孔注入層兼正孔輸送層81上に、支持基板10における表示領域R1の全面に渡って一様に形成されている。 The electron transport layer / electron injection layer 83 covers the light emitting layers 82R / 82G / 82B and the hole injection layer / hole transport layer 81 so as to cover the light emitting layers 82R / 82G / 82B and the hole injection layer / hole transport layer 81. On the upper surface, it is uniformly formed over the entire surface of the display region R1 in the support substrate 10.
 なお、本実施の形態では、上記したように、正孔注入層および正孔輸送層として、正孔注入層兼正孔輸送層81を設けた場合を例に挙げて図示するとともに、電子輸送層および電子注入層として、電子輸送層兼電子注入層83を設けた場合を例に挙げて図示している。しかしながら、本実施の形態はこれに限定されるものではなく、正孔注入層と正孔輸送層とは互いに独立した層として形成されていてもよい。同様に、電子輸送層と電子注入層とは互いに独立した層として形成されていてもよい。 In the present embodiment, as described above, a case where the hole injection layer / hole transport layer 81 is provided as the hole injection layer and the hole transport layer is illustrated as an example, and the electron transport layer and As an electron injection layer, the case where an electron transport layer / electron injection layer 83 is provided is shown as an example. However, this embodiment is not limited to this, and the hole injection layer and the hole transport layer may be formed as independent layers. Similarly, the electron transport layer and the electron injection layer may be formed as independent layers.
 なお、発光層82R・82G・82B以外の有機層は有機EL層43として必須の層ではなく、要求される有機EL素子20の特性に応じて適宜形成すればよい。 The organic layers other than the light emitting layers 82R, 82G, and 82B are not essential layers as the organic EL layer 43, and may be appropriately formed according to the required characteristics of the organic EL element 20.
 また、正孔注入層兼正孔輸送層81および電子輸送層兼電子注入層83のように、一つの層は、複数の機能を有していてもよい。 Further, like the hole injection layer / hole transport layer 81 and the electron transport layer / electron injection layer 83, one layer may have a plurality of functions.
 また、有機EL層43には、必要に応じ、キャリアブロッキング層を追加することもできる。例えば、発光層82R・82G・82Bと電子輸送層兼電子注入層83との間にキャリアブロッキング層として正孔ブロッキング層を追加することで、正孔が電子輸送層兼電子注入層83に抜けるのを阻止し、発光効率を向上することができる。 In addition, a carrier blocking layer can be added to the organic EL layer 43 as necessary. For example, by adding a hole blocking layer as a carrier blocking layer between the light emitting layers 82R, 82G, and 82B and the electron transport layer / electron injection layer 83, holes escape to the electron transport layer / electron injection layer 83. Can be prevented and the luminous efficiency can be improved.
 本実施の形態でも、第1電極21(陽極)、第2電極31(陰極)、および発光層82R・82G・82B以外の層は、適宜挿入すればよい。 Also in this embodiment, layers other than the first electrode 21 (anode), the second electrode 31 (cathode), and the light emitting layers 82R, 82G, and 82B may be inserted as appropriate.
 上記有機EL素子20の構成としては、例えば、下記(1)~(8)に示すような層構成を採用することができる。
(1)第1電極/発光層/第2電極
(2)第1電極/正孔輸送層/発光層/電子輸送層/第2電極
(3)第1電極/正孔輸送層/発光層/正孔ブロッキング層/電子輸送層/第2電極
(4)第1電極/正孔輸送層/発光層/正孔ブロッキング層/電子輸送層/電子注入層/第2電極
(5)第1電極/正孔注入層/正孔輸送層/発光層/電子輸送層/電子注入層/第2電極
(6)第1電極/正孔注入層/正孔輸送層/発光層/正孔ブロッキング層/電子輸送層/第2電極
(7)第1電極/正孔注入層/正孔輸送層/発光層/正孔ブロッキング層/電子輸送層/電子注入層/第2電極
(8)第1電極/正孔注入層/正孔輸送層/電子ブロッキング層/発光層/正孔ブロッキング層/電子輸送層/電子注入層/第2電極
 なお、本実施の形態でも、上記積層順は、第1電極21を陽極とし、第2電極31を陰極としたものである。本実施の形態でも、第1電極21を陰極とし、第2電極31を陽極とする場合には、有機EL層43の積層順が反転する。
As the configuration of the organic EL element 20, for example, a layer configuration as shown in the following (1) to (8) can be adopted.
(1) First electrode / light emitting layer / second electrode (2) First electrode / hole transport layer / light emitting layer / electron transport layer / second electrode (3) First electrode / hole transport layer / light emitting layer / Hole blocking layer / electron transport layer / second electrode (4) first electrode / hole transport layer / light emitting layer / hole blocking layer / electron transport layer / electron injection layer / second electrode (5) first electrode / Hole injection layer / hole transport layer / light emitting layer / electron transport layer / electron injection layer / second electrode (6) first electrode / hole injection layer / hole transport layer / light emitting layer / hole blocking layer / electron Transport layer / second electrode (7) first electrode / hole injection layer / hole transport layer / light emitting layer / hole blocking layer / electron transport layer / electron injection layer / second electrode (8) first electrode / positive Hole injection layer / hole transport layer / electron blocking layer / light emitting layer / hole blocking layer / electron transport layer / electron injection layer / second electrode The order of lamination is such that the first electrode 21 is an anode and the second electrode 31 is a cathode. Also in this embodiment, when the first electrode 21 is used as a cathode and the second electrode 31 is used as an anode, the stacking order of the organic EL layers 43 is reversed.
 <有機EL表示装置100の製造方法>
 次に、本実施の形態にかかる有機EL表示装置100の製造方法について説明する。
<Method for Manufacturing Organic EL Display Device 100>
Next, a method for manufacturing the organic EL display device 100 according to the present embodiment will be described.
 本実施の形態でも、有機EL表示装置100の製造工程の流れの概要は、図7を用いて説明した通りである。なお、本実施の形態でも、第1電極21を陰極とし、第2電極31を陽極とする場合には、第1電極21と第2電極31とで、その材料並びに厚みが反転する。 Also in the present embodiment, the outline of the manufacturing process flow of the organic EL display device 100 is as described with reference to FIG. Even in the present embodiment, when the first electrode 21 is a cathode and the second electrode 31 is an anode, the material and thickness of the first electrode 21 and the second electrode 31 are reversed.
 以下では、図11に示す構成を有する有機EL表示装置100を例に挙げて、ステップS4における図7に示す有機EL層43の作製工程の流れの概要について説明する。 Hereinafter, an example of the organic EL display device 100 having the configuration shown in FIG. 11 will be described as an example, and an outline of the flow of the manufacturing process of the organic EL layer 43 shown in FIG.
 <有機EL層43の作製工程の流れ>
 図12は、図11に示す有機EL層43の作製工程の一例を工程順に示すフローチャートである。
<Flow of manufacturing process of organic EL layer 43>
FIG. 12 is a flowchart illustrating an example of a manufacturing process of the organic EL layer 43 illustrated in FIG. 11 in the order of processes.
 本実施の形態では、まず、図7に示すステップS4で、脱水のための減圧ベークおよび第1電極21の表面洗浄として酸素プラズマ処理が施された支持基板10に対し、図12に示すように、まず、正孔注入層兼正孔輸送層81(正孔注入層・正孔輸送層)を、第1電極21およびエッジカバー15を被覆するように、支持基板10の表示領域R1の全面に、真空蒸着法によりパターン形成する(ステップS31)。 In the present embodiment, first, as shown in FIG. 12, the support substrate 10 that has been subjected to oxygen plasma treatment as a vacuum bake for dehydration and surface cleaning of the first electrode 21 in step S4 shown in FIG. First, the hole injection layer / hole transport layer 81 (hole injection layer / hole transport layer) is applied to the entire surface of the display region R1 of the support substrate 10 so as to cover the first electrode 21 and the edge cover 15. A pattern is formed by a vacuum deposition method (step S31).
 なお、前記したように、正孔注入層兼正孔輸送層81は、支持基板10における表示領域R1の全面に渡って一様に形成される。このため、実施の形態1における正孔注入層22および正孔輸送層23同様、表示領域R1の全面が開口したオープンマスクを蒸着用のマスクとして用いて成膜を行う。 As described above, the hole injection / hole transport layer 81 is uniformly formed over the entire surface of the display region R1 in the support substrate 10. Therefore, like the hole injection layer 22 and the hole transport layer 23 in the first embodiment, film formation is performed using an open mask in which the entire surface of the display region R1 is opened as a mask for vapor deposition.
 一方、本実施の形態のように塗り分け方式を用いたフルカラーの有機EL表示装置100では、上記したように、TFT12を用いて有機EL素子20を選択的に所望の輝度で発光させることによりカラー画像表示を行う。 On the other hand, as described above, in the full-color organic EL display device 100 using the separate coloring method as in the present embodiment, the organic EL element 20 is selectively made to emit light with a desired luminance by using the TFT 12. Display an image.
 このため、上記有機EL表示装置100を製造するためには、各色に発光する有機発光材料からなる発光層82R・82G・82Bを、有機EL素子20毎に所定のパターンで成膜する必要がある。 Therefore, in order to manufacture the organic EL display device 100, it is necessary to form the light emitting layers 82R, 82G, and 82B made of organic light emitting materials that emit light of each color in a predetermined pattern for each organic EL element 20. .
 そこで、発光層82R・82G・82Bの成膜には、所望の表示色の発光材料を蒸着させる領域のみが開口したファインマスクを蒸着用のマスクとして用いて、真空蒸着法により塗り分け蒸着する(ステップS32)。これにより、各サブ画素71R・71G・71Bに応じたパターン膜を形成する。 Therefore, the light-emitting layers 82R, 82G, and 82B are formed by separate vapor deposition by a vacuum vapor deposition method using a fine mask having an opening only in a region where a light emitting material of a desired display color is vapor-deposited as a vapor deposition mask ( Step S32). Thereby, a pattern film corresponding to each of the sub-pixels 71R, 71G, and 71B is formed.
 その後、発光層82R・82G・82Bが形成された支持基板10上に、表示領域R1の全面が開口したオープンマスクを蒸着用のマスクとして用いて、真空蒸着法により、電子輸送層兼電子注入層83(電子輸送層・電子注入層)(ステップS33)、第2電極31(ステップS5)を、順に、画素領域全面に形成する。 Thereafter, an electron transport layer / electron injection layer is formed on the support substrate 10 on which the light emitting layers 82R, 82G, and 82B are formed, using an open mask having the entire display region R1 opened as a mask for vapor deposition, by a vacuum vapor deposition method. 83 (electron transport layer / electron injection layer) (step S33) and the second electrode 31 (step S5) are sequentially formed on the entire surface of the pixel region.
 なお、本実施の形態でも、上記蒸着には、従来と同様の真空蒸着装置を用いることができる。なお、好適な真空到達率等の条件については、実施の形態1で説明した通りである。したがって、真空蒸着装置並びに蒸着方法の詳細については、その説明並びに図示を省略する。 In the present embodiment, a vacuum deposition apparatus similar to the conventional one can be used for the vapor deposition. Note that conditions such as a preferable vacuum arrival rate are as described in the first embodiment. Therefore, the details and illustration of the vacuum vapor deposition apparatus and the vapor deposition method are omitted.
 また、本実施の形態でも、正孔注入層兼正孔輸送層81および電子輸送層兼電子注入層83として用いられる正孔注入層兼正孔輸送層および電子輸送層兼電子注入層の材料並びに膜厚としては、実施の形態1で説明した通りである。 Also in this embodiment, the material and film thickness of the hole injection layer / hole transport layer and electron transport layer / electron injection layer used as the hole injection layer / hole transport layer 81 and the electron transport layer / electron injection layer 83 Is as described in the first embodiment.
 また、発光層82R・82G・82Bとして用いられる発光層の材料については、実施の形態1で説明した通りである。なお、発光層82R・82G・82Bには、それぞれ、発光色が異なる単一の材料を用いてもよく、ある材料をホスト材料とし、他の材料をゲスト材料またはドーパントとして混ぜ込んだ混合材料を用いてもよい。 Further, the materials of the light emitting layers used as the light emitting layers 82R, 82G, and 82B are as described in the first embodiment. Each of the light emitting layers 82R, 82G, and 82B may be made of a single material having a different emission color. A mixed material in which a certain material is used as a host material and another material is mixed as a guest material or a dopant. It may be used.
 なお、この場合の発光層82R・82G・82Bの膜厚としては、例えば、10~100nmである。 In this case, the film thickness of the light emitting layers 82R, 82G, and 82B is, for example, 10 to 100 nm.
 本実施の形態では、図11に示すように、実施の形態1同様、第1電極21を、反射電極層111と透明電極層121との積層構造とすることで、有機EL素子20にマイクロキャビティ構造を導入している。 In the present embodiment, as shown in FIG. 11, the first electrode 21 has a laminated structure of the reflective electrode layer 111 and the transparent electrode layer 121 as in the first embodiment, so that the organic EL element 20 has a microcavity. The structure is introduced.
 このため、本実施の形態では、各発光層82R・82G・82Bの膜厚を同一の膜厚に設定している。このため、実施の形態1、2と同様にして光路長73R・73G・73Bが設定される。 For this reason, in the present embodiment, the thicknesses of the light emitting layers 82R, 82G, and 82B are set to the same thickness. For this reason, the optical path lengths 73R, 73G, and 73B are set as in the first and second embodiments.
 したがって、正孔注入層兼正孔輸送層81、電子輸送層兼電子注入層83、発光層82R・82G・82Bの材料および膜厚は、従来と同様に設定することができる。このため、本実施の形態では、これら正孔注入層兼正孔輸送層81、電子輸送層兼電子注入層83、発光層82R・82G・82Bの具体的な材料並びに膜厚についての説明は省略する。 Therefore, the materials and film thicknesses of the hole injection / hole transport layer 81, the electron transport / electron injection layer 83, and the light-emitting layers 82R, 82G, and 82B can be set in the same manner as in the past. For this reason, in the present embodiment, description of specific materials and film thicknesses of the hole injection layer / hole transport layer 81, the electron transport layer / electron injection layer 83, and the light emitting layers 82R, 82G, and 82B is omitted. .
 <効果>
 上記したように、本実施の形態では、実施の形態1同様、第1電極21を、反射電極層111と透明電極層121との積層構造とすることで、有機EL素子20にマイクロキャビティ構造を導入している。
<Effect>
As described above, in the present embodiment, as in the first embodiment, the first electrode 21 has a laminated structure of the reflective electrode layer 111 and the transparent electrode layer 121, so that the organic EL element 20 has a microcavity structure. It has been introduced.
 このため、本実施の形態では、有機EL素子20にマイクロキャビティ構造を導入するために、各発光層82R・82G・82Bの膜厚を、発光色毎に変更する必要はない。 Therefore, in the present embodiment, in order to introduce the microcavity structure into the organic EL element 20, it is not necessary to change the film thickness of each of the light emitting layers 82R, 82G, and 82B for each light emission color.
 このため、本実施の形態でも、実施の形態1~7のようにW発光の発光層を用いる場合と同様に、各発光層82R・82G・82Bの膜厚を等しく薄く成膜することができるので、処理タクトを短くすることができる。 Therefore, also in this embodiment, the light emitting layers 82R, 82G, and 82B can be formed to have the same thin film thickness as in the case of using the W light emitting layer as in the first to seventh embodiments. Therefore, the processing tact can be shortened.
 また、本実施の形態でも、各発光層82R・82G・82Bから出射された光の混合に対してマイクロキャビティ効果が加味された光が有機EL素子20により得られる。またその光を、封止基板50に設けられたCF層52によって調整することで、所望のスペクトルを有する光を外部に取り出すことができる。したがって、本実施の形態でも、このように塗り分け方式を用いた発光層82R・82G・82Bとマイクロキャビティ効果とCF層52とを組み合わせることで、色純度を高めることができる。 Also in the present embodiment, the organic EL element 20 can obtain light in which the microcavity effect is added to the mixture of the light emitted from the light emitting layers 82R, 82G, and 82B. Further, by adjusting the light by the CF layer 52 provided on the sealing substrate 50, light having a desired spectrum can be extracted to the outside. Therefore, also in this embodiment, color purity can be improved by combining the light emitting layers 82R, 82G, and 82B, the microcavity effect, and the CF layer 52 using the separate coating method.
 また、本実施の形態でも、実施の形態1、2と同様にして第1電極21における透明電極層121の膜厚をサブ画素71R・71G・71B毎に変更することで、実施の形態1、2と同様の効果が得られることは、言うまでもない。 Also in the present embodiment, the thickness of the transparent electrode layer 121 in the first electrode 21 is changed for each of the sub-pixels 71R, 71G, and 71B in the same manner as in the first and second embodiments. Needless to say, the same effect as 2 can be obtained.
 <要点概要>
 以上のように、本発明の一態様にかかる表示装置の製造方法は、反射電極層よりも上層に非晶質の透明電極材料からなる第1の透明電極層を成膜して一括してエッチングした後、非晶質の透明電極材料からなる第1の透明電極層を多結晶の透明電極材料からなる第1の透明電極層に転化させ、その上に成膜される第2の透明電極層とのエッチング耐性の違いを利用して透明電極層を積層することにより、サブ画素間で上記透明電極層の合計の膜厚を変更する方法である。
<Summary>
As described above, in the method for manufacturing a display device according to one embodiment of the present invention, the first transparent electrode layer made of an amorphous transparent electrode material is formed over the reflective electrode layer and etched together. After that, the first transparent electrode layer made of the amorphous transparent electrode material is converted into the first transparent electrode layer made of the polycrystalline transparent electrode material, and the second transparent electrode layer formed thereon is formed. This is a method of changing the total film thickness of the transparent electrode layer between the sub-pixels by laminating the transparent electrode layer using the difference in etching resistance.
 このため、本発明の一態様にかかる表示装置の製造方法は、各サブ画素における、電界を形成する対の電極のうち、一方の電極が、反射電極層と、該反射電極層上に形成された少なくとも一層の透明電極層とを備えるとともに、少なくとも1つのサブ画素における反射電極層上に、上記透明電極層が複数形成されており、表示色が異なるサブ画素間で上記透明電極層の全体の膜厚が異なる表示装置の製造方法であって、反射電極層を成膜する工程と、上記反射電極層よりも上層に、非晶質の透明電極材料からなる第1の透明電極層を成膜する第1の透明電極層成膜工程と、上記非晶質の透明電極材料からなる第1の透明電極層および上記反射電極層を一括してフォトリソグラフィによりエッチングしてパターニングするパターニング工程と、上記パターニング工程でパターニングした上記非晶質の透明電極材料からなる第1の透明電極層を結晶化して多結晶の透明電極材料からなる第1の透明電極層に転化させる第1の透明電極層結晶化工程と、上記多結晶の透明電極材料からなる第1の透明電極層上に、上記多結晶の透明電極材料からなる第1の透明電極層よりもエッチング耐性が低い透明電極材料からなる第2の透明電極層を成膜し、フォトリソグラフィにより上記第2の透明電極層を選択的にエッチングしてパターニングする第2の透明電極層積層工程とを含んでいる。 Therefore, in the method for manufacturing a display device according to one embodiment of the present invention, one electrode of the pair of electrodes that form an electric field in each subpixel is formed on the reflective electrode layer and the reflective electrode layer. At least one transparent electrode layer, and a plurality of the transparent electrode layers are formed on the reflective electrode layer in at least one sub-pixel, and the entire transparent electrode layer is arranged between sub-pixels having different display colors. A method of manufacturing a display device having different film thicknesses, the step of forming a reflective electrode layer, and the formation of a first transparent electrode layer made of an amorphous transparent electrode material above the reflective electrode layer A first transparent electrode layer forming step, and a patterning step of patterning the first transparent electrode layer made of the amorphous transparent electrode material and the reflective electrode layer together by photolithography. A first transparent electrode layer crystal that crystallizes the first transparent electrode layer made of the amorphous transparent electrode material patterned in the patterning step and converts it into a first transparent electrode layer made of a polycrystalline transparent electrode material. And a second electrode made of a transparent electrode material having lower etching resistance than the first transparent electrode layer made of the polycrystalline transparent electrode material on the first transparent electrode layer made of the polycrystalline transparent electrode material. And a second transparent electrode layer stacking step of selectively etching and patterning the second transparent electrode layer by photolithography.
 上記の方法によれば、各サブ画素における反射電極層上に透明電極層が積層されているとともに、表示色が異なるサブ画素間で反射電極層上の透明電極層の膜厚を任意に変更することができる実用的な表示装置の製造方法を提供するとともに、フォトリソグラフィの回数を削減することができる。 According to the above method, the transparent electrode layer is laminated on the reflective electrode layer in each subpixel, and the film thickness of the transparent electrode layer on the reflective electrode layer is arbitrarily changed between the subpixels having different display colors. In addition to providing a practical method for manufacturing a display device, the number of times of photolithography can be reduced.
 また、上記表示装置の製造方法において、上記第2の透明電極層積層工程は、レジストパターンを形成するサブ画素を変更して複数回行われるとともに、フォトリソグラフィにより上記第2の透明電極層を選択的にエッチングしてパターニングするときに、1つのサブ画素にのみレジストパターンを形成し、該レジストパターンをマスクとして上記第2の透明電極層をエッチングすることにより、上記1つのサブ画素にのみ上記第2の透明電極層のパターンを形成する工程を含むことが好ましい。 Further, in the display device manufacturing method, the second transparent electrode layer stacking step is performed a plurality of times by changing subpixels forming the resist pattern, and the second transparent electrode layer is selected by photolithography. When patterning is performed by etching, a resist pattern is formed only on one subpixel, and the second transparent electrode layer is etched using the resist pattern as a mask. It is preferable to include the process of forming the pattern of 2 transparent electrode layers.
 上記の方法によれば、上記したように、透明電極層の合計の膜厚を変更するために必要なフォトリソグラフィの回数としては2回のフォトリソグラフィで、上記透明電極層の合計の膜厚を、サブ画素毎に任意に変更することができ、任意のサブ画素における第2の透明電極層の膜厚を、他のサブ画素における第2の透明電極層の膜厚とは独立して設定することが可能となる。 According to the above method, as described above, the number of photolithography required to change the total film thickness of the transparent electrode layer is two photolithography, and the total film thickness of the transparent electrode layer is The thickness of the second transparent electrode layer in any sub-pixel can be set independently of the thickness of the second transparent electrode layer in other sub-pixels. It becomes possible.
 上記の方法によれば、上記したように、上記1つのサブ画素にのみ上記第2の透明電極層のパターンを形成する工程を含むことで、特許文献3のように光路長の制約を受けることなく、各サブ画素における光路長を、任意かつ容易に調整することができる。 According to the above method, as described above, by including the step of forming the pattern of the second transparent electrode layer only on the one sub-pixel, the optical path length is restricted as in Patent Document 3. In addition, the optical path length in each sub-pixel can be adjusted arbitrarily and easily.
 また、上記表示装置の製造方法は、上記第2の透明電極層が、非晶質の透明電極材料からなる透明電極層であり、上記第2の透明電極層積層工程は、上記非晶質の透明電極材料からなる第2の透明電極層を成膜する第2の透明電極層成膜工程と、上記非晶質の透明電極材料からなる第2の透明電極層をフォトリソグラフィによりエッチングしてパターニングする第2の透明電極層パターニング工程と、パターニングした上記非晶質の透明電極材料からなる第2の透明電極層を結晶化して多結晶の透明電極材料からなる第2の透明電極層に転化させる第2の透明電極層結晶化工程とを備え、上記第2の透明電極層積層工程では、上記第2の透明電極層成膜工程と、第2の透明電極層パターニング工程と、第2の透明電極層結晶化工程とを繰り返すことで、任意のサブ画素に、多結晶の透明電極材料からなる透明電極層を任意の数積層することが好ましい。 In the method for manufacturing the display device, the second transparent electrode layer is a transparent electrode layer made of an amorphous transparent electrode material, and the second transparent electrode layer laminating step includes the amorphous electrode layer. A second transparent electrode layer forming step for forming a second transparent electrode layer made of a transparent electrode material, and patterning by etching the second transparent electrode layer made of the amorphous transparent electrode material by photolithography The second transparent electrode layer patterning step and the patterned second transparent electrode layer made of the amorphous transparent electrode material are crystallized to be converted into a second transparent electrode layer made of a polycrystalline transparent electrode material. A second transparent electrode layer crystallization step, and in the second transparent electrode layer laminating step, the second transparent electrode layer forming step, the second transparent electrode layer patterning step, and a second transparent Repeat the electrode layer crystallization process. In Succoth, to any sub-pixel, it is preferable that the transparent electrode layer made of a transparent electrode material polycrystalline be any number lamination.
 上記の方法によれば、上記したように、非晶質の透明電極材料からなる透明電極層と多結晶の透明電極材料からなる透明電極層とのエッチング選択性の違いを利用した透明電極層の積み上げを行う。 According to the above method, as described above, the transparent electrode layer using the difference in etching selectivity between the transparent electrode layer made of an amorphous transparent electrode material and the transparent electrode layer made of a polycrystalline transparent electrode material is used. Stack up.
 上記の方法によれば、各透明電極層の膜厚を、他のサブ画素における透明電極層の膜厚とは独立して設定することが可能であり、各サブ画素における光路長を、任意かつ容易に調整することができる。 According to the above method, the film thickness of each transparent electrode layer can be set independently of the film thickness of the transparent electrode layer in other subpixels, and the optical path length in each subpixel can be set arbitrarily and It can be adjusted easily.
 また、上記表示装置の製造方法において、上記第1および第2の透明電極層はインジウム錫酸化物であることが好ましい。 In the display device manufacturing method, the first and second transparent electrode layers are preferably indium tin oxide.
 非晶質のインジウム錫酸化物は、熱処理により容易に多結晶のインジウム錫酸化物に転化させることができる。多結晶のインジウム錫酸化物は、非結晶のインジウム錫酸化物よりもエッチング耐性が高く、非結晶のインジウム錫酸化物のエッチング工程(第2の透明電極層パターニング工程、第2の透明電極層積層工程)において、エッチングされないか、あるいは、エッチング速度が著しく遅い。このため、非結晶のインジウム錫酸化物のエッチング工程では、非結晶のインジウム錫酸化物のみを選択的にエッチングすることができる。 Amorphous indium tin oxide can be easily converted to polycrystalline indium tin oxide by heat treatment. The polycrystalline indium tin oxide has higher etching resistance than the amorphous indium tin oxide, and the amorphous indium tin oxide etching step (second transparent electrode layer patterning step, second transparent electrode layer lamination) In step (5), etching is not performed or the etching rate is extremely low. For this reason, only the amorphous indium tin oxide can be selectively etched in the etching process of amorphous indium tin oxide.
 また、上記第2の透明電極層パターニング工程では、上記非晶質の透明電極材料からなる第2の透明電極層上に、平面視で、上記反射電極層および上記多結晶の透明電極材料からなる第1の透明電極層と重畳し、かつ、平面視で上記反射電極層および上記多結晶の透明電極材料からなる第1の透明電極層よりも大きく形成されたレジストパターンを形成し、該レジストパターンをマスクとして上記第2の透明電極層をエッチングしてパターニングすることが好ましい。 In the second transparent electrode layer patterning step, the reflective electrode layer and the polycrystalline transparent electrode material are formed on the second transparent electrode layer made of the amorphous transparent electrode material in a plan view. A resist pattern is formed which overlaps with the first transparent electrode layer and is larger than the first transparent electrode layer made of the reflective electrode layer and the polycrystalline transparent electrode material in plan view, the resist pattern It is preferable that the second transparent electrode layer is etched and patterned using as a mask.
 反射電極材料の種類によっては、上記反射電極層が剥き出しの状態(つまり、露出状態)にあると、例えばレジストのぬれ性を高めるために紫外線照射を行うと酸化して反射特定が低下したり、溶剤耐性が低く、溶剤が染み込んだりする可能性がある。このため、このような反射電極層が、このような反射電極材料からなる場合、反射電極層が剥き出しの状態となることは望ましくない。 Depending on the type of the reflective electrode material, if the reflective electrode layer is in an exposed state (that is, an exposed state), for example, when ultraviolet irradiation is performed to increase the wettability of the resist, it is oxidized and the reflection specification is reduced. The solvent resistance is low, and there is a possibility that the solvent may penetrate. For this reason, when such a reflective electrode layer consists of such a reflective electrode material, it is not desirable that the reflective electrode layer is exposed.
 しかしながら、上記の構成によれば、上記反射電極層を、多結晶の透明電極材料からなる第1の透明電極層および第2の透明電極層で囲むことができるので、上記表示装置の製造時に、上記反射電極層を、該反射電極層の品質を損なうおそれがある上記要因から保護することができる。 However, according to the above configuration, since the reflective electrode layer can be surrounded by the first transparent electrode layer and the second transparent electrode layer made of a polycrystalline transparent electrode material, at the time of manufacturing the display device, The reflective electrode layer can be protected from the above factors that may impair the quality of the reflective electrode layer.
 また、上記表示装置の製造方法において、上記第2の透明電極層は、上記第1の透明電極層とは組成が異なる透明電極材料からなる層であることが好ましい。 In the display device manufacturing method, the second transparent electrode layer is preferably a layer made of a transparent electrode material having a composition different from that of the first transparent electrode layer.
 上記の方法によれば、非結晶の透明電極材料からなる透明電極層を多結晶の透明電極材料からなる透明電極層に転化させることなく、多結晶の透明電極材料からなる第1の透明電極層と上記第2の透明電極層とのエッチング耐性の違いによるエッチング選択性の違いを利用して、透明電極層の積み上げを行うことができる。 According to said method, the 1st transparent electrode layer which consists of a polycrystalline transparent electrode material, without converting the transparent electrode layer which consists of an amorphous transparent electrode material into the transparent electrode layer which consists of a polycrystalline transparent electrode material The transparent electrode layers can be stacked using the difference in etching selectivity due to the difference in etching resistance between the second transparent electrode layer and the second transparent electrode layer.
 この場合、上記第1の透明電極層はインジウム錫酸化物であり、上記第2の透明電極層はインジウム亜鉛酸化物であることが好ましい。 In this case, it is preferable that the first transparent electrode layer is indium tin oxide and the second transparent electrode layer is indium zinc oxide.
 非晶質のインジウム錫酸化物は、熱処理により容易に多結晶のインジウム錫酸化物に転化させることができる。多結晶のインジウム錫酸化物は、インジウム亜鉛酸化物よりもエッチング耐性が高く、第2の透明電極層のエッチング工程(第2の透明電極層積層工程)でインジウム亜鉛酸化物をエッチングするときに、エッチングされないか、あるいは、エッチング速度が著しく遅い。このため、第2の透明電極層のエッチング工程では、インジウム亜鉛酸化物からなる第2の透明電極層のみが選択的にエッチングされる。 Amorphous indium tin oxide can be easily converted to polycrystalline indium tin oxide by heat treatment. Polycrystalline indium tin oxide has higher etching resistance than indium zinc oxide, and when etching indium zinc oxide in the second transparent electrode layer etching step (second transparent electrode layer stacking step), It is not etched or the etching rate is extremely slow. For this reason, in the etching process of the second transparent electrode layer, only the second transparent electrode layer made of indium zinc oxide is selectively etched.
 また、上記第2の透明電極層積層工程では、平面視で、上記反射電極層および上記多結晶の透明電極材料からなる第1の透明電極層と重畳し、かつ、平面視で上記反射電極層および上記多結晶の透明電極材料からなる第1の透明電極層よりも大きく形成されたレジストパターンをマスクとして用いて上記第2の透明電極層をエッチングすることが好ましい。 In the second transparent electrode layer laminating step, the reflective electrode layer and the first transparent electrode layer made of the polycrystalline transparent electrode material are overlapped with each other in a plan view, and the reflective electrode layer is seen in a plan view. The second transparent electrode layer is preferably etched using a resist pattern formed larger than the first transparent electrode layer made of the polycrystalline transparent electrode material as a mask.
 この場合にも、上記反射電極層を、多結晶の透明電極材料からなる第1の透明電極層および第2の透明電極層で囲むことができる。 Also in this case, the reflective electrode layer can be surrounded by a first transparent electrode layer and a second transparent electrode layer made of a polycrystalline transparent electrode material.
 また、上記表示装置の製造方法において、上記反射電極層は、銀、銀合金、およびアルミニウム合金からなる群より選ばれる何れか1種からなることが好ましい。 In the display device manufacturing method, the reflective electrode layer is preferably made of any one selected from the group consisting of silver, a silver alloy, and an aluminum alloy.
 これらの材料は、非晶質の透明電極層との間で電食反応が生じない。このため、上記反射電極層における反射電極材料に適している。 These materials do not cause an electrolytic corrosion reaction with the amorphous transparent electrode layer. For this reason, it is suitable for the reflective electrode material in the reflective electrode layer.
 また、上記表示装置の製造方法では、上記対の電極が陽極および陰極であり、上記一方の電極が陽極であるとともに、上記陽極と陰極とで有機エレクトロルミネッセンス層を挟むように上記陽極、陰極、および有機エレクトロルミネッセンス層を形成することが好ましい。 In the method for manufacturing the display device, the pair of electrodes is an anode and a cathode, the one electrode is an anode, and the anode, the cathode, and the anode, the cathode, and the organic electroluminescence layer are sandwiched between the anode and the cathode. It is preferable to form an organic electroluminescence layer.
 上記の方法によれば、上記陽極と陰極とで有機エレクトロルミネッセンス層が挟持されてなる有機エレクトロルミネッセンス素子の光路長を、発光色が異なるサブ画素毎に容易に変更することができる。 According to the above method, the optical path length of the organic electroluminescence element in which the organic electroluminescence layer is sandwiched between the anode and the cathode can be easily changed for each sub-pixel having a different emission color.
 したがって、上記の方法によれば、マイクロキャビティ構造を有する有機エレクトロルミネッセンス素子を得ることができる。このため、マイクロキャビティ効果により、上記有機エレクトロルミネッセンス素子を用いた表示装置における色純度、発光の色度、発光効率等を向上させることができる。 Therefore, according to the above method, an organic electroluminescence element having a microcavity structure can be obtained. Therefore, due to the microcavity effect, color purity, light emission chromaticity, light emission efficiency, and the like in a display device using the organic electroluminescence element can be improved.
 また、以上のように、本発明の一態様にかかる表示装置は、各サブ画素における、電界を形成する対の電極のうち、一方の電極が、反射電極層と、該反射電極層上に形成された少なくとも一層の透明電極層とを備えるとともに、少なくとも1つのサブ画素における反射電極層上に、上記透明電極層が複数形成されており、表示色が異なるサブ画素間で上記透明電極層の全体の膜厚が異なる表示装置であって、上記複数の透明電極層は、互いに異なる組成を有し、下層の透明電極層のエッチング耐性が、上層の透明電極層のエッチング耐性よりも高い。 As described above, in the display device according to one embodiment of the present invention, one electrode of the pair of electrodes forming an electric field in each subpixel is formed on the reflective electrode layer and the reflective electrode layer. A plurality of transparent electrode layers are formed on the reflective electrode layer in at least one subpixel, and the entire transparent electrode layer is arranged between subpixels having different display colors. The plurality of transparent electrode layers have different compositions, and the etching resistance of the lower transparent electrode layer is higher than the etching resistance of the upper transparent electrode layer.
 上記の構成によれば、表示色が異なるサブ画素毎に透明電極層の膜厚が異なるとともに実用的な方法で製造が可能な表示装置を提供することができる。 According to the above configuration, it is possible to provide a display device that can be manufactured by a practical method while the film thickness of the transparent electrode layer is different for each sub-pixel having a different display color.
 また、上記表示装置は、上記下層の透明電極層が多結晶のインジウム錫酸化物からなり、上記上層の透明電極層がインジウム亜鉛酸化物からなることが好ましい。 In the display device, the lower transparent electrode layer is preferably made of polycrystalline indium tin oxide, and the upper transparent electrode layer is preferably made of indium zinc oxide.
 非晶質のインジウム錫酸化物は、熱処理により容易に多結晶のインジウム錫酸化物に転化させることができる。多結晶のインジウム錫酸化物は、インジウム亜鉛酸化物よりもエッチング耐性が高く、インジウム亜鉛酸化物をエッチングするときに、エッチングされないか、あるいは、エッチング速度が著しく遅い。このため、インジウム亜鉛酸化物からなる透明電極層のみを選択的にエッチングすることができる。 Amorphous indium tin oxide can be easily converted to polycrystalline indium tin oxide by heat treatment. Polycrystalline indium tin oxide has higher etching resistance than indium zinc oxide, and is not etched or has a significantly slower etching rate when etching indium zinc oxide. For this reason, only the transparent electrode layer made of indium zinc oxide can be selectively etched.
 したがって、上記の構成によれば、表示色が異なるサブ画素毎に透明電極層の膜厚が異なるとともに実用的な方法で製造が可能な表示装置を提供することができる。 Therefore, according to the above configuration, it is possible to provide a display device that can be manufactured by a practical method while the film thickness of the transparent electrode layer is different for each sub-pixel having a different display color.
 また、上記表示装置において、上記反射電極層は、銀、銀合金、およびアルミニウム合金からなる群より選ばれる何れか1種からなることが好ましい。 In the display device, the reflective electrode layer is preferably made of any one selected from the group consisting of silver, a silver alloy, and an aluminum alloy.
 上記したように下層の透明電極層と上層の透明電極層とに、互いに異なる組成を有し、エッチング耐性が異なる透明電極材料を使用した場合、上記透明電極材料と反射電極材料との組み合わせによっては、電食反応が生じるおそれがある。 As described above, when transparent electrode materials having different compositions and different etching resistance are used for the lower transparent electrode layer and the upper transparent electrode layer, depending on the combination of the transparent electrode material and the reflective electrode material, There is a possibility that an electrolytic corrosion reaction may occur.
 しかしながら、上記反射電極層が上記反射電極材料からなる場合、そのようなおそれがない。このため、上記反射電極材料は、上記反射電極層における反射電極材料に適している。 However, when the reflective electrode layer is made of the reflective electrode material, there is no such fear. Therefore, the reflective electrode material is suitable for the reflective electrode material in the reflective electrode layer.
 また、上記表示装置において、上記上層の透明電極層は、上記下層の透明電極層の表面および上記反射電極層の側面を覆っていることが好ましい。 In the display device, it is preferable that the upper transparent electrode layer covers a surface of the lower transparent electrode layer and a side surface of the reflective electrode layer.
 反射電極材料の種類によっては、上記反射電極層が剥き出しの状態(つまり、露出状態)にあると、例えばレジストのぬれ性を高めるために紫外線照射を行うと酸化して反射特定が低下したり、溶剤耐性が低く、溶剤が染み込んだりする可能性がある。このため、このような反射電極層が、このような反射電極材料からなる場合、反射電極層が剥き出しの状態となることは望ましくない。 Depending on the type of the reflective electrode material, if the reflective electrode layer is in an exposed state (that is, an exposed state), for example, when ultraviolet irradiation is performed to increase the wettability of the resist, it is oxidized and the reflection specification is reduced. The solvent resistance is low, and there is a possibility that the solvent may penetrate. For this reason, when such a reflective electrode layer consists of such a reflective electrode material, it is not desirable that the reflective electrode layer is exposed.
 しかしながら、上記の構成によれば、上記表示装置の製造時に、上記反射電極層を、該反射電極層の品質を損なうおそれがある上記要因から保護することができる。 However, according to the above configuration, it is possible to protect the reflective electrode layer from the above factors that may impair the quality of the reflective electrode layer when the display device is manufactured.
 したがって、上記の構成によれば、反射特性に優れた反射電極層を有する表示装置を提供することができる。 Therefore, according to the above configuration, it is possible to provide a display device having a reflective electrode layer with excellent reflection characteristics.
 本発明は上述した各実施形態に限定されるものではなく、請求項に示した範囲で種々の変更が可能であり、異なる実施形態にそれぞれ開示された技術的手段を適宜組み合わせて得られる実施形態についても本発明の技術的範囲に含まれる。 The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention.
 本発明は、有機EL素子や無機EL素子のような微小共振器として構成することが可能な発光素子を用いた表示装置およびその製造方法に好適に利用することができる。 The present invention can be suitably used for a display device using a light emitting element that can be configured as a microresonator such as an organic EL element or an inorganic EL element, and a manufacturing method thereof.
  1   有機EL表示パネル
  2   電気配線端子
 10   支持基板
 11   絶縁基板
 12   TFT
 13   層間絶縁膜
 13a  コンタクトホール
 14   信号線
 15   エッジカバー
 15R・15G・15B 開口部
 20   有機EL素子
 21   第1電極
 22   正孔注入層
 23   正孔輸送層
 24   第1発光層
 25   電子輸送層
 26   キャリア発生層
 27   正孔輸送層
 28   第2発光層
 29   電子輸送層
 30   電子注入層
 31   第2電極
 41   封止樹脂層
 42   充填樹脂層
 43   有機EL層
 50   封止基板
 51   絶縁基板
 52   CF層
 53   BM
 60   接続部
 70   画素
 71   サブ画素
 71R・71G・71B サブ画素
 72   発光領域
 73R・73G・73B 光路長
 81   正孔注入層兼正孔輸送層
 82R・82G・82B 発光層
 83   電子輸送層兼電子注入層
100   有機EL表示装置
101   画素部
102   回路部
103   接続端子
110   a-ITO層
111   反射電極層
112   a-ITO層
113   p-ITO層
114   p-ITO層
115   a-ITO層
116   p-ITO層
117   a-ITO層
118   p-ITO層
121   透明電極層
131   IZO層
132   IZO層
201R・201G・201B レジストパターン
211R・211G・211B レジストパターン
  L   封止領域
  R1  表示領域
  R2  第2電極接続領域
  R3  端子部領域
1 Organic EL Display Panel 2 Electrical Wiring Terminal 10 Support Substrate 11 Insulating Substrate 12 TFT
13 Interlayer Insulating Film 13a Contact Hole 14 Signal Line 15 Edge Cover 15R / 15G / 15B Opening 20 Organic EL Element 21 First Electrode 22 Hole Injection Layer 23 Hole Transport Layer 24 First Light-Emitting Layer 25 Electron Transport Layer 26 Carrier Generation Layer 27 hole transport layer 28 second light emitting layer 29 electron transport layer 30 electron injection layer 31 second electrode 41 sealing resin layer 42 filling resin layer 43 organic EL layer 50 sealing substrate 51 insulating substrate 52 CF layer 53 BM
60 connection portion 70 pixel 71 sub pixel 71R / 71G / 71B sub pixel 72 light emitting region 73R / 73G / 73B optical path length 81 hole injection layer / hole transport layer 82R / 82G / 82B light emission layer 83 electron transport layer / electron injection layer 100 Organic EL display device 101 Pixel unit 102 Circuit unit 103 Connection terminal 110 a-ITO layer 111 Reflective electrode layer 112 a-ITO layer 113 p-ITO layer 114 p-ITO layer 115 a-ITO layer 116 p-ITO layer 117 a- ITO layer 118 p-ITO layer 121 Transparent electrode layer 131 IZO layer 132 IZO layer 201R / 201G / 201B Resist pattern 211R / 211G / 211B Resist pattern L Sealing area R1 Display area R2 Second electrode connection area R3 Terminal area

Claims (14)

  1.  各サブ画素における、電界を形成する対の電極のうち、一方の電極が、反射電極層と、該反射電極層上に形成された少なくとも一層の透明電極層とを備えるとともに、少なくとも1つのサブ画素における反射電極層上に、上記透明電極層が複数形成されており、表示色が異なるサブ画素間で上記透明電極層の全体の膜厚が異なる表示装置の製造方法であって、
     反射電極層を成膜する工程と、
     上記反射電極層よりも上層に、非晶質の透明電極材料からなる第1の透明電極層を成膜する第1の透明電極層成膜工程と、
     上記非晶質の透明電極材料からなる第1の透明電極層および上記反射電極層を一括してフォトリソグラフィによりエッチングしてパターニングするパターニング工程と、
     上記パターニング工程でパターニングした上記非晶質の透明電極材料からなる第1の透明電極層を結晶化して多結晶の透明電極材料からなる第1の透明電極層に転化させる第1の透明電極層結晶化工程と、
     上記多結晶の透明電極材料からなる第1の透明電極層上に、上記多結晶の透明電極材料からなる第1の透明電極層よりもエッチング耐性が低い透明電極材料からなる第2の透明電極層を成膜し、フォトリソグラフィにより上記第2の透明電極層を選択的にエッチングしてパターニングする第2の透明電極層積層工程とを含むことを特徴とする表示装置の製造方法。
    In each subpixel, one of the pair of electrodes forming an electric field includes a reflective electrode layer and at least one transparent electrode layer formed on the reflective electrode layer, and at least one subpixel. A plurality of the transparent electrode layers are formed on the reflective electrode layer, and a method of manufacturing a display device in which the entire film thickness of the transparent electrode layer is different between sub-pixels having different display colors,
    Forming a reflective electrode layer;
    A first transparent electrode layer forming step of forming a first transparent electrode layer made of an amorphous transparent electrode material above the reflective electrode layer;
    A patterning step of patterning the first transparent electrode layer made of the amorphous transparent electrode material and the reflective electrode layer by etching together by photolithography;
    A first transparent electrode layer crystal that crystallizes the first transparent electrode layer made of the amorphous transparent electrode material patterned in the patterning step and converts it into a first transparent electrode layer made of a polycrystalline transparent electrode material. Conversion process,
    A second transparent electrode layer made of a transparent electrode material having lower etching resistance than the first transparent electrode layer made of the polycrystalline transparent electrode material on the first transparent electrode layer made of the polycrystalline transparent electrode material. And a second transparent electrode layer stacking step of selectively etching and patterning the second transparent electrode layer by photolithography.
  2.  上記第2の透明電極層積層工程は、レジストパターンを形成するサブ画素を変更して複数回行われるとともに、フォトリソグラフィにより上記第2の透明電極層を選択的にエッチングしてパターニングするときに、1つのサブ画素にのみレジストパターンを形成し、該レジストパターンをマスクとして上記第2の透明電極層をエッチングすることにより、上記1つのサブ画素にのみ上記第2の透明電極層のパターンを形成する工程を含むことを特徴とする請求項1に記載の表示装置の製造方法。 The second transparent electrode layer laminating step is performed a plurality of times by changing subpixels for forming a resist pattern, and when the second transparent electrode layer is selectively etched and patterned by photolithography, A resist pattern is formed only on one subpixel, and the second transparent electrode layer is etched using the resist pattern as a mask, thereby forming the pattern of the second transparent electrode layer only on the one subpixel. The method for manufacturing a display device according to claim 1, further comprising a step.
  3.  上記第2の透明電極層が、非晶質の透明電極材料からなる透明電極層であり、
     上記第2の透明電極層積層工程は、
     上記非晶質の透明電極材料からなる第2の透明電極層を成膜する第2の透明電極層成膜工程と、
     上記非晶質の透明電極材料からなる第2の透明電極層をフォトリソグラフィによりエッチングしてパターニングする第2の透明電極層パターニング工程と、
     パターニングした上記非晶質の透明電極材料からなる第2の透明電極層を結晶化して多結晶の透明電極材料からなる第2の透明電極層に転化させる第2の透明電極層結晶化工程とを備え、
     上記第2の透明電極層積層工程では、上記第2の透明電極層成膜工程と、第2の透明電極層パターニング工程と、第2の透明電極層結晶化工程とを繰り返すことで、任意のサブ画素に、多結晶の透明電極材料からなる透明電極層を任意の数積層することを特徴とする請求項1または2に記載の表示装置の製造方法。
    The second transparent electrode layer is a transparent electrode layer made of an amorphous transparent electrode material,
    The second transparent electrode layer lamination step includes
    A second transparent electrode layer film forming step of forming a second transparent electrode layer made of the amorphous transparent electrode material;
    A second transparent electrode layer patterning step of patterning the second transparent electrode layer made of the amorphous transparent electrode material by etching by photolithography;
    A second transparent electrode layer crystallization step of crystallizing the patterned second transparent electrode layer made of the amorphous transparent electrode material into a second transparent electrode layer made of a polycrystalline transparent electrode material; Prepared,
    In the second transparent electrode layer laminating step, the second transparent electrode layer forming step, the second transparent electrode layer patterning step, and the second transparent electrode layer crystallization step are repeated, so that an arbitrary 3. The method for manufacturing a display device according to claim 1, wherein an arbitrary number of transparent electrode layers made of a polycrystalline transparent electrode material are laminated on the sub-pixel.
  4.  上記第1および第2の透明電極層がインジウム錫酸化物であることを特徴とする請求項3に記載の表示装置の製造方法。 4. The method for manufacturing a display device according to claim 3, wherein the first and second transparent electrode layers are indium tin oxide.
  5.  上記第2の透明電極層パターニング工程では、上記非晶質の透明電極材料からなる第2の透明電極層上に、平面視で、上記反射電極層および上記多結晶の透明電極材料からなる第1の透明電極層と重畳し、かつ、平面視で上記反射電極層および上記多結晶の透明電極材料からなる第1の透明電極層よりも大きく形成されたレジストパターンを形成し、該レジストパターンをマスクとして上記第2の透明電極層をエッチングしてパターニングすることを特徴とする請求項3または4に記載の表示装置の製造方法。 In the second transparent electrode layer patterning step, the first electrode made of the reflective electrode layer and the polycrystalline transparent electrode material in a plan view on the second transparent electrode layer made of the amorphous transparent electrode material. And forming a resist pattern which is larger than the reflective electrode layer and the first transparent electrode layer made of the polycrystalline transparent electrode material in a plan view, and masks the resist pattern. 5. The method of manufacturing a display device according to claim 3, wherein the second transparent electrode layer is patterned by etching.
  6.  上記第2の透明電極層が、上記第1の透明電極層とは組成が異なる透明電極材料からなる層であることを特徴とする請求項1または2に記載の表示装置の製造方法。 3. The method for manufacturing a display device according to claim 1, wherein the second transparent electrode layer is a layer made of a transparent electrode material having a composition different from that of the first transparent electrode layer.
  7.  上記第1の透明電極層がインジウム錫酸化物であり、上記第2の透明電極層がインジウム亜鉛酸化物であることを特徴とする請求項6に記載の表示装置の製造方法。 The method for manufacturing a display device according to claim 6, wherein the first transparent electrode layer is indium tin oxide and the second transparent electrode layer is indium zinc oxide.
  8.  上記第2の透明電極層積層工程では、平面視で、上記反射電極層および上記多結晶の透明電極材料からなる第1の透明電極層と重畳し、かつ、平面視で上記反射電極層および上記多結晶の透明電極材料からなる第1の透明電極層よりも大きく形成されたレジストパターンをマスクとして用いて上記第2の透明電極層をエッチングすることを特徴とする請求項6または7に記載の表示装置の製造方法。 In the second transparent electrode layer stacking step, the reflective electrode layer and the first transparent electrode layer made of the polycrystalline transparent electrode material are overlapped with each other in a plan view, and the reflective electrode layer and the above in a plan view The second transparent electrode layer is etched using a resist pattern formed larger than the first transparent electrode layer made of a polycrystalline transparent electrode material as a mask. Manufacturing method of display device.
  9.  上記反射電極層が、銀、銀合金、およびアルミニウム合金からなる群より選ばれる何れか1種からなることを特徴とする請求項1~8の何れか1項に記載の表示装置の製造方法。 The method for manufacturing a display device according to any one of claims 1 to 8, wherein the reflective electrode layer is made of any one selected from the group consisting of silver, a silver alloy, and an aluminum alloy.
  10.  上記対の電極が陽極および陰極であり、上記一方の電極が陽極であるとともに、
     上記陽極と陰極とで有機エレクトロルミネッセンス層を挟むように上記陽極、陰極、および有機エレクトロルミネッセンス層を形成することを特徴とする請求項1~9の何れか1項に記載の表示装置の製造方法。
    The pair of electrodes is an anode and a cathode, and the one electrode is an anode,
    10. The method of manufacturing a display device according to claim 1, wherein the anode, the cathode, and the organic electroluminescence layer are formed so that the organic electroluminescence layer is sandwiched between the anode and the cathode. .
  11.  各サブ画素における、電界を形成する対の電極のうち、一方の電極が、反射電極層と、該反射電極層上に形成された少なくとも一層の透明電極層とを備えるとともに、少なくとも1つのサブ画素における反射電極層上に、上記透明電極層が複数形成されており、表示色が異なるサブ画素間で上記透明電極層の全体の膜厚が異なる表示装置であって、
     上記複数の透明電極層は、互いに異なる組成を有し、下層の透明電極層のエッチング耐性が、上層の透明電極層のエッチング耐性よりも高いことを特徴とする表示装置。
    In each subpixel, one of the pair of electrodes forming an electric field includes a reflective electrode layer and at least one transparent electrode layer formed on the reflective electrode layer, and at least one subpixel. A plurality of the transparent electrode layers are formed on the reflective electrode layer in the display device, and the overall film thickness of the transparent electrode layer is different between sub-pixels having different display colors,
    The plurality of transparent electrode layers have different compositions, and the etching resistance of the lower transparent electrode layer is higher than the etching resistance of the upper transparent electrode layer.
  12.  上記下層の透明電極層が多結晶のインジウム錫酸化物からなり、上記上層の透明電極層がインジウム亜鉛酸化物からなることを特徴とする請求項11に記載の表示装置。 12. The display device according to claim 11, wherein the lower transparent electrode layer is made of polycrystalline indium tin oxide, and the upper transparent electrode layer is made of indium zinc oxide.
  13.  上記反射電極層が、銀、銀合金、およびアルミニウム合金からなる群より選ばれる何れか1種からなることを特徴とする請求項11または12に記載の表示装置。 The display device according to claim 11 or 12, wherein the reflective electrode layer is made of any one selected from the group consisting of silver, a silver alloy, and an aluminum alloy.
  14.  上記上層の透明電極層が、上記下層の透明電極層の表面および上記反射電極層の側面を覆っていることを特徴とする請求項11~13の何れか1項に記載の表示装置。 14. The display device according to claim 11, wherein the upper transparent electrode layer covers a surface of the lower transparent electrode layer and a side surface of the reflective electrode layer.
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015132693A1 (en) * 2014-03-07 2015-09-11 Semiconductor Energy Laboratory Co., Ltd. Light-emitting element, light-emitting device, electronic device, and lighting device
JP2015187982A (en) * 2014-03-13 2015-10-29 株式会社半導体エネルギー研究所 Light-emitting element, light-emitting device, electronic apparatus, and lighting system
JP2018142535A (en) * 2017-02-28 2018-09-13 株式会社半導体エネルギー研究所 Display device, display module, and electronic apparatus
CN112599703A (en) * 2020-12-14 2021-04-02 深圳市华星光电半导体显示技术有限公司 Display substrate, preparation method thereof and display panel

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005093401A (en) * 2003-09-19 2005-04-07 Sony Corp Organic light emitting device, its manufacturing method, and display device
JP2005197011A (en) * 2003-12-26 2005-07-21 Sanyo Electric Co Ltd Display device and manufacturing method of the same
JP2005197010A (en) * 2003-12-26 2005-07-21 Sanyo Electric Co Ltd Manufacturing method of display device
WO2005086539A1 (en) * 2004-03-05 2005-09-15 Idemitsu Kosan Co., Ltd. Organic electroluminescence display device
JP2007026852A (en) * 2005-07-15 2007-02-01 Seiko Epson Corp Organic electroluminescent device, manufacturing method of organic electroluminescent device, and electronic equipment
JP2009289740A (en) * 2008-05-28 2009-12-10 Samsung Mobile Display Co Ltd Organic light-emitting display

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005093401A (en) * 2003-09-19 2005-04-07 Sony Corp Organic light emitting device, its manufacturing method, and display device
JP2005197011A (en) * 2003-12-26 2005-07-21 Sanyo Electric Co Ltd Display device and manufacturing method of the same
JP2005197010A (en) * 2003-12-26 2005-07-21 Sanyo Electric Co Ltd Manufacturing method of display device
WO2005086539A1 (en) * 2004-03-05 2005-09-15 Idemitsu Kosan Co., Ltd. Organic electroluminescence display device
JP2007026852A (en) * 2005-07-15 2007-02-01 Seiko Epson Corp Organic electroluminescent device, manufacturing method of organic electroluminescent device, and electronic equipment
JP2009289740A (en) * 2008-05-28 2009-12-10 Samsung Mobile Display Co Ltd Organic light-emitting display

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015132693A1 (en) * 2014-03-07 2015-09-11 Semiconductor Energy Laboratory Co., Ltd. Light-emitting element, light-emitting device, electronic device, and lighting device
JP2015181103A (en) * 2014-03-07 2015-10-15 株式会社半導体エネルギー研究所 Light emitting element, light emitting device, electronic apparatus and light device
US9412793B2 (en) 2014-03-07 2016-08-09 Semiconductor Energy Laboratory Co., Ltd. Light-emitting element, light-emitting device, electronic device, and lighting device
US10033016B2 (en) 2014-03-07 2018-07-24 Semiconductor Energy Laboratory Co., Ltd. Light-emitting element, light-emitting device, electronic device, and lighting device
TWI668853B (en) * 2014-03-07 2019-08-11 日商半導體能源研究所股份有限公司 Light-emitting element, light-emitting device, electronic device, and lighting device
US10418594B2 (en) 2014-03-07 2019-09-17 Semiconductor Energy Laboratory Co., Ltd. Light-emitting element, light-emitting device, electronic device, and lighting device
JP2015187982A (en) * 2014-03-13 2015-10-29 株式会社半導体エネルギー研究所 Light-emitting element, light-emitting device, electronic apparatus, and lighting system
JP2020188025A (en) * 2014-03-13 2020-11-19 株式会社半導体エネルギー研究所 Light emitting device
JP2018142535A (en) * 2017-02-28 2018-09-13 株式会社半導体エネルギー研究所 Display device, display module, and electronic apparatus
JP7134642B2 (en) 2017-02-28 2022-09-12 株式会社半導体エネルギー研究所 Display device
CN112599703A (en) * 2020-12-14 2021-04-02 深圳市华星光电半导体显示技术有限公司 Display substrate, preparation method thereof and display panel
CN112599703B (en) * 2020-12-14 2022-08-23 深圳市华星光电半导体显示技术有限公司 Display substrate, preparation method thereof and display panel

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