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WO2012132064A1 - Photovoltaic element - Google Patents

Photovoltaic element Download PDF

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Publication number
WO2012132064A1
WO2012132064A1 PCT/JP2011/072452 JP2011072452W WO2012132064A1 WO 2012132064 A1 WO2012132064 A1 WO 2012132064A1 JP 2011072452 W JP2011072452 W JP 2011072452W WO 2012132064 A1 WO2012132064 A1 WO 2012132064A1
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Prior art keywords
layer
amorphous silicon
type amorphous
transparent conductive
silicon layer
Prior art date
Application number
PCT/JP2011/072452
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French (fr)
Japanese (ja)
Inventor
豊 桐畑
藤田　和範
嶋田　聡
三島　孝博
仁 坂田
Original Assignee
三洋電機株式会社
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Publication of WO2012132064A1 publication Critical patent/WO2012132064A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Definitions

  • the present invention relates to a photovoltaic device.
  • Patent Document 1 discloses a semiconductor substrate having a light receiving surface and a back surface provided on the opposite side of the light receiving surface, a first semiconductor layer formed along a predetermined direction on the back surface, and a back surface.
  • a pair of second semiconductor layers formed along a predetermined direction and disposed on both sides of the first semiconductor layer, and from one second semiconductor layer to the first semiconductor layer of the pair of second semiconductor layers
  • a photovoltaic device comprising a transparent electrode layer covering a second semiconductor layer and a collecting electrode layer formed on the transparent electrode layer is disclosed.
  • an insulating layer or the like may be stacked on a semiconductor layer formed on a semiconductor substrate.
  • residues such as the insulating layer may adhere to the semiconductor layer.
  • the residue of the insulating layer may increase the series resistance between the semiconductor layer and the collecting electrode portion.
  • a photovoltaic element includes a crystalline semiconductor substrate and a first conductivity type layer, and is laminated on the surface in a first region of one surface of the crystalline semiconductor substrate.
  • a second amorphous semiconductor layer that includes a semiconductor layer portion and a second conductivity type layer and is stacked over the second region on one surface and a part of the first amorphous semiconductor layer portion And a conductive layer disposed between a part of the first amorphous semiconductor layer portion and the second amorphous semiconductor layer portion.
  • the power generation characteristics of the photovoltaic element can be improved.
  • 1st Embodiment of this invention it is sectional drawing of a photovoltaic device.
  • 1st Embodiment of this invention it is a flowchart which shows the procedure of the manufacturing method of a photovoltaic device.
  • 1st Embodiment of this invention it is sectional drawing for demonstrating the procedure of the manufacturing method of a photovoltaic device.
  • 1st Embodiment of this invention it is sectional drawing for demonstrating the procedure of the manufacturing method of a photovoltaic device.
  • 1st Embodiment of this invention it is sectional drawing for demonstrating the procedure of the manufacturing method of a photovoltaic device. In 1st Embodiment of this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photovoltaic device. In 1st Embodiment of this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photovoltaic device. In 1st Embodiment of this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photovoltaic device. In 1st Embodiment of this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photovoltaic device.
  • 2nd Embodiment of this invention it is sectional drawing of a photovoltaic device.
  • 2nd Embodiment of this invention it is a flowchart which shows the procedure of the manufacturing method of a photovoltaic device.
  • 2nd Embodiment of this invention it is sectional drawing for demonstrating the procedure of the manufacturing method of a photovoltaic device.
  • 2nd Embodiment of this invention it is sectional drawing for demonstrating the procedure of the manufacturing method of a photovoltaic device.
  • 2nd Embodiment of this invention it is sectional drawing for demonstrating the procedure of the manufacturing method of a photovoltaic device. In 2nd Embodiment of this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photovoltaic device. In 2nd Embodiment of this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photovoltaic device. In 2nd Embodiment of this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photovoltaic device. In 2nd Embodiment of this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photovoltaic device.
  • FIG. 1 is a cross-sectional view of the photovoltaic element 10.
  • the photovoltaic device 10 includes an antireflection layer 12, an n-type amorphous silicon layer 14, an i-type amorphous silicon layer 16, an n-type single crystal silicon substrate 18, an in-layer stack portion 21, An ip laminated portion 31, a transparent conductive layer 20, an n-side electrode portion 25, and a p-side electrode portion 35 are provided.
  • an arrow A shown in FIG. 1 indicates a direction in which light such as sunlight is incident on the photovoltaic element 10.
  • the “light receiving surface” means a surface on which light such as sunlight is mainly incident.
  • the “back surface” means a surface opposite to the light receiving surface.
  • the n-type single crystal silicon substrate 18 is a power generation layer that receives light incident from the light receiving surface side and generates carriers.
  • the n-type single crystal silicon substrate 18 is used.
  • the present invention is not limited to this, and a wafer-like semiconductor substrate made of a crystalline semiconductor material of n-type or p-type conductivity is used. be able to.
  • a polycrystalline silicon substrate, a gallium arsenide substrate (GaAs), an indium phosphorus substrate (InP), or the like can be used.
  • the i-type amorphous silicon layer 16 is formed on the light-receiving surface of the n-type single crystal silicon substrate 18.
  • the i-type amorphous silicon layer 16 is a passivation layer containing hydrogen.
  • the n-type amorphous silicon layer 14 is formed on the i-type amorphous silicon layer 16.
  • the i-type amorphous silicon layer 16 and the n-type amorphous silicon layer 14 constitute an amorphous semiconductor layer portion formed on the light receiving surface.
  • the i-type amorphous silicon layer 16 is a layer made of an intrinsic amorphous semiconductor film.
  • the i-type amorphous silicon layer 16 has a lower dopant concentration in the film than the n-type amorphous silicon layer 14.
  • the i-type amorphous silicon layer 16 preferably has a low n-type or p-type dopant concentration and a dark conductivity of 10 ⁇ 9 S / cm or less.
  • the n-type amorphous silicon layer 14 is a layer made of an amorphous semiconductor film containing an n-type conductive dopant.
  • the n-type amorphous silicon layer 14 has a higher n-type dopant concentration in the film than the i-type amorphous silicon layer 16.
  • the n-type amorphous silicon layer 14 preferably has a dark conductivity of 10 ⁇ 5 S / cm or more.
  • the amorphous silicon layer may include a microcrystalline structure.
  • the microcrystalline structure is a structure in which crystal grains are precipitated in an amorphous semiconductor.
  • the average grain size of the crystal grains is not limited to this, but is estimated to be about 1 nm to 80 nm.
  • the antireflection layer 12 is formed on the n-type amorphous silicon layer 14 and reduces reflection of light incident from the light receiving surface side of the photovoltaic element 10.
  • the antireflection layer 12 also functions as a protective layer that protects the surface of the n-type amorphous silicon layer 14.
  • the antireflection layer 12 is made of a material having translucency for light in a wavelength range that can be absorbed by the n-type single crystal silicon substrate 18. Further, it is preferable to use a material having a refractive index and a film thickness that reduce reflection of light incident from the light receiving surface of the photovoltaic element 10 in relation to the refractive index of the layer covered by the antireflection layer 12. .
  • the antireflection layer 12 includes, for example, aluminum nitride, silicon nitride, silicon oxide, silicon oxynitride, and the like.
  • the photovoltaic element 10 can receive light over substantially the entire light receiving surface of the n-type single crystal silicon substrate 18.
  • the i-n laminated portion 21 is formed on the back surface of the n-type single crystal silicon substrate 18. It is preferable that the i-n laminated portion 21 is arranged so that current can be collected evenly from the surface of the photovoltaic element 10 in an n-side electrode portion 25 described later.
  • the i-n stacked portion 21 preferably has a comb-teeth shape in which a plurality of finger portions extend in parallel.
  • the i-n stacked unit 21 includes an i-type amorphous silicon layer 22 and an n-type amorphous silicon layer 23.
  • the i-type amorphous silicon layer 22 is a passivation layer formed on the back surface of the n-type single crystal silicon substrate 18.
  • the n-type amorphous silicon layer 23 is formed on the i-type amorphous silicon layer 22.
  • the i-n stacked portion 21 constitutes a first amorphous semiconductor layer portion formed on the back surface.
  • the i-type amorphous silicon layer 22 is a layer made of an intrinsic amorphous semiconductor film.
  • the i-type amorphous silicon layer 22 has a lower dopant concentration in the film than the n-type amorphous silicon layer 23.
  • the i-type amorphous silicon layer 22 preferably has a low n-type or p-type dopant concentration and a dark conductivity of 10 ⁇ 9 S / cm or less.
  • the n-type amorphous silicon layer 23 is a layer made of an amorphous semiconductor film containing an n-type conductive dopant.
  • the n-type amorphous silicon layer 23 has a higher n-type dopant concentration in the film than the i-type amorphous silicon layer 22.
  • the n-type amorphous silicon layer 23 preferably has a dark conductivity of 10 ⁇ 5 S / cm or more.
  • the transparent conductive layer 20 is formed on the n-type amorphous silicon layer 23.
  • the transparent conductive layer 20 includes at least one of metal oxides such as indium oxide (In 2 O 3 ), zinc oxide (ZnO), tin oxide (SnO 2 ), and titanium oxide (TiO 2 ).
  • ITO indium tin oxide
  • the n-side electrode part 25 is an electrode part provided for collecting and taking out the electricity generated in the photovoltaic element 10.
  • the n-side electrode unit 25 includes a transparent conductive layer 26, a metal layer 27, a first electrode unit 28, and a second electrode unit 29.
  • the transparent conductive layer 26 is formed on the transparent conductive layer 20.
  • the transparent conductive layer 26 includes at least one of metal oxides such as indium oxide (In 2 O 3 ), zinc oxide (ZnO), tin oxide (SnO 2 ), and titanium oxide (TiO 2 ).
  • ITO indium tin oxide
  • the metal layer 27 is formed on the transparent conductive layer 26.
  • the metal layer 27 is a seed layer including a metal such as copper (Cu) or an alloy, for example.
  • the “seed layer” refers to a layer that is a starting point for plating growth.
  • the first electrode portion 28 is an electrode formed on the metal layer 27 by plating growth.
  • the first electrode unit 28 includes, for example, copper (Cu).
  • the second electrode part 29 is an electrode formed on the first electrode part 28 by plating growth.
  • the second electrode unit 29 includes tin (Sn).
  • the i-p stacked portion 31 is formed on the back surface of the n-type single crystal silicon substrate 18 so as to be inserted into the i-n stacked portion 21.
  • the ip laminated portion 31 is formed from the back surface of the n-type single crystal silicon substrate 18 to the edge of the i-n laminated portion 21. That is, in the photovoltaic element 10, a part of the laminated structure of the ip laminated part 31 and the in laminated part 21 exists.
  • the ip stacked portion 31 is arranged so that current can be collected evenly from within the surface of the photovoltaic element 10.
  • the ip laminated portion 31 is preferably, for example, in a comb-teeth shape in which a plurality of finger portions extend in parallel.
  • the ip laminated portion 31 includes an i-type amorphous silicon layer 32 and a p-type amorphous silicon layer 33.
  • the i-type amorphous silicon layer 32 is a passivation layer formed on the back surface of the n-type single crystal silicon substrate 18.
  • the p-type amorphous silicon layer 33 is formed on the i-type amorphous silicon layer 32.
  • the ip stacked portion 31 constitutes a second amorphous semiconductor layer portion formed on the back surface.
  • the i-type amorphous silicon layer 32 is a layer made of an intrinsic amorphous semiconductor film.
  • the i-type amorphous silicon layer 32 has a lower dopant concentration in the film than the p-type amorphous silicon layer 33.
  • the i-type amorphous silicon layer 32 preferably has a low n-type or p-type dopant concentration and a dark conductivity of 10 ⁇ 9 S / cm or less.
  • the p-type amorphous silicon layer 33 is a layer made of an amorphous semiconductor film containing a p-type conductive dopant.
  • the p-type amorphous silicon layer 33 has a higher p-type dopant concentration in the film than the i-type amorphous silicon layer 32.
  • the p-type amorphous silicon layer 33 preferably has a dark conductivity of 10 ⁇ 8 s / cm or more.
  • the p-side electrode part 35 is an electrode part provided for collecting and taking out the electricity generated in the photovoltaic element 10.
  • the p-side electrode part 35 includes a transparent conductive layer 36, a metal layer 37, a first electrode part 38, and a second electrode part 39.
  • the transparent conductive layer 36 is formed on the p-type amorphous silicon layer 33.
  • the metal layer 37 is formed on the transparent conductive layer 36.
  • the first electrode portion 38 is formed on the metal layer 37 by plating growth.
  • the second electrode portion 39 is formed on the first electrode portion 38 by plating growth.
  • the material and the like of the second electrode portion 39 are the same as those of the second electrode portion 29, detailed description thereof is omitted.
  • FIG. 2 is a flowchart showing the procedure of the method for manufacturing the photovoltaic element 10.
  • the manufacturing method of the photovoltaic element 10 is not limited to the manufacturing method shown in each process. In each step, for example, a sputtering method, a plasma CVD method, a screen printing method, or a plating method can be appropriately used for forming each layer.
  • an n-type single crystal silicon substrate 18 is prepared, and the light receiving surface and the back surface of the n-type single crystal silicon substrate 18 are cleaned (S2).
  • the n-type single crystal silicon substrate 18 can be cleaned using, for example, an HF aqueous solution.
  • a texture structure is formed on the light receiving surface of the n-type single crystal silicon substrate 18 (S4).
  • the texture structure can be performed using anisotropic etching or isotropic etching.
  • an i-type amorphous silicon layer 22a and an n-type amorphous silicon layer 23a are formed on the back surface of the n-type single crystal silicon substrate 18, and thereafter, an n-type single crystal silicon layer 23a is formed.
  • the i-type amorphous silicon layer 16 and the n-type amorphous silicon layer 14 are formed on the light receiving surface of the crystalline silicon substrate 18 (S6).
  • a transparent conductive layer 20a is formed on the n-type amorphous silicon layer 23a (S8).
  • the antireflection layer 12 is formed on the n-type amorphous silicon layer 14 (S10).
  • a part of the transparent conductive layer 20a is etched (S12). Specifically, the transparent conductive layer 20 is formed by removing a portion of the transparent conductive layer 20a located on a region where the ip stacked portion 31 is bonded to the n-type single crystal silicon substrate 18 in a later step.
  • the etching of the transparent conductive layer 20a uses, for example, an acidic etching solution such as hydrochloric acid (HCl).
  • the i-type amorphous silicon layer 22a and the n-type amorphous silicon layer 23a are etched (S14). Specifically, portions of the i-type amorphous silicon layer 22a and the n-type amorphous silicon layer 23a other than the portion covered with the transparent conductive layer 20 are removed. As a result, the portion of the back surface of the n-type single crystal silicon substrate 18 where the transparent conductive layer 20 is not located is exposed, and the i-type amorphous silicon layer 22 and the n-type amorphous silicon layer 23 are formed. Form.
  • an alkaline etching solution such as an aqueous solution containing sodium hydroxide (NaOH) is used.
  • the transparent conductive layer 20, the i-type amorphous silicon layer 22, the n-type amorphous silicon layer 23 and the exposed back surface of the n-type single crystal silicon substrate 18 are covered.
  • the i-type amorphous silicon layer 32a and the p-type amorphous silicon layer 33a are formed (S16).
  • a portion of the i-type amorphous silicon layer 32a and the p-type amorphous silicon layer 33a located on the transparent conductive layer 20 is etched (S18). . Thereby, the i-type amorphous silicon layer 32 and the p-type amorphous silicon layer 33 are formed.
  • the transparent conductive layer 26a and the metal layer 27a are formed (S20).
  • the transparent conductive layers 26 and 36 and the metal layers 27 and 37 are separated by dividing a portion of the transparent conductive layer 26 a and the metal layer 27 a located on the transparent conductive layer 20. Is formed (S22).
  • the transparent conductive layer 26a and the metal layer 27a are divided by, for example, a lithography method.
  • the first electrode portion 28 and the second electrode portion 29 are sequentially formed on the metal layer 27 by electrolytic plating, and the first electrode portion 38 and the second electrode portion 29 are formed on the metal layer 37.
  • the electrode portions 39 are sequentially formed (S24). Thereby, the n-side electrode part 25 and the p-side electrode part 35 are formed.
  • the carrier mobility is low in the i-type amorphous silicon layer 22 and the n-type amorphous silicon layer 23.
  • the carrier mobility is higher in the transparent conductive layer 20 than in the i-type amorphous silicon layer 22 and the n-type amorphous silicon layer 23.
  • carriers are preferably discharged from the n-side electrode portion 25 by compensating for the low carrier mobility in the i-type amorphous silicon layer 22 and the n-type amorphous silicon layer 23. It can be taken out.
  • the i-type amorphous silicon layer 22 and the n-type amorphous silicon layer 23, and the i-type amorphous silicon layer 32 and the p-type amorphous silicon layer 33 are electrically connected via the transparent conductive layer 20.
  • the n-side electrode since the carrier mobility is low in the i-type amorphous silicon layer 32 and the p-type amorphous silicon layer 33, the n-side electrode has a high carrier mobility. Since the carrier can be suitably taken out from the portion 25, the electrical connection as described above does not cause a significant problem.
  • an insulating layer is not formed on the in laminated portion 21 on the back surface side. Therefore, there is no step of etching the insulating layer, and the residue of the insulating layer does not adhere to the transparent conductive layer 20, the i-type amorphous silicon layer 22, or the n-type amorphous silicon layer 23. Thereby, it is possible to prevent the series resistance between the in-stacked portion 21 and the n-side electrode portion 25 of the photovoltaic element 10 from increasing due to the presence of the insulating layer residue. Therefore, the power generation characteristics of the photovoltaic element 10 can be improved.
  • FIG. 11 is a cross-sectional view of a photovoltaic element 11 according to the second embodiment of the present invention.
  • the photovoltaic device 11 includes an antireflection layer 12, an n-type amorphous silicon layer 14, an i-type amorphous silicon layer 16, an n-type single crystal silicon substrate 18, an in-layer stack portion 21, It includes an ip laminated portion 31, a transparent conductive layer 20, an insulating layer 24, an n-side electrode portion 25, and a p-side electrode portion 35.
  • an arrow A shown in FIG. 11 indicates a direction in which light such as sunlight is incident on the photovoltaic element 11.
  • the insulating layer 24 is formed to electrically insulate the i-n laminated portion 21 and the ip laminated portion 31.
  • the insulating layer 24 also functions as a protective layer formed on the transparent conductive layer 20.
  • the insulating layer 24 may be any material having electrical insulation properties, and preferably includes, for example, aluminum nitride, silicon nitride, silicon oxide, silicon oxynitride, and the like.
  • FIG. 12 is a flowchart showing the procedure of the method for manufacturing the photovoltaic element 11.
  • the manufacturing method of the photovoltaic element 11 is not limited to the manufacturing method shown in each process. In each step, for example, a sputtering method, a plasma CVD method, a screen printing method, a plating method, or the like can be used as appropriate.
  • the manufacturing method of the photovoltaic element 11 and the manufacturing method of the photovoltaic element 10 are the same in the steps S2 to S8. And since the difference between the manufacturing method of the photovoltaic element 11 and the manufacturing method of the photovoltaic element 10 is a process after S8, it demonstrates centering on the difference.
  • steps S2 to S8 are performed.
  • the insulating layer 24a is formed on the transparent conductive layer 20a, and the antireflection layer 12 is formed on the n-type amorphous silicon layer 14 (S30).
  • the insulating layer 24a is etched to remove a part of the insulating layer 24a (S32). Specifically, the insulating layer 24b is formed by removing a portion of the insulating layer 24a located above a region for bonding the ip stacked portion 31 to the n-type single crystal silicon substrate 18 in a later step.
  • an acidic etching solution such as an HF aqueous solution is used for the etching of the insulating layer 24a.
  • the transparent conductive layer 20a is etched using the insulating layer 24b patterned in S32 as a mask (S34). Thereby, the patterned transparent conductive layer 20 is formed.
  • the same steps as S14, S16, and S18 of the first embodiment are performed except that the insulating layer 24b is present on the transparent conductive layer 20.
  • the transparent conductive layer 20 patterned in S34 as a mask
  • the i-type amorphous silicon layer 22a and the n-type amorphous silicon layer 23a are used. Is etched (S36).
  • An i-type amorphous silicon layer 32a and a p-type amorphous silicon layer 33a are formed so as to cover the back surface of the silicon substrate 18 (S38). Thereafter, as shown in FIG. 18, as in S18, a part of the portion of the i-type amorphous silicon layer 32a and the p-type amorphous silicon layer 33a located on the insulating layer 24b is etched. (S40).
  • a part of the insulating layer 24b is further removed by etching the insulating layer 24b (S42).
  • the insulating layer 24 is formed by removing the exposed portion of the insulating layer 24b by etching using the i-type amorphous silicon layer 32 and the p-type amorphous silicon layer 33 as a mask.
  • the exposed surface of the transparent conductive layer 20 is cleaned (S44). Thereby, even if it is a case where the residue of the insulating layer 24a has adhered to the transparent conductive layer 20, in S42, it can remove suitably.
  • the cleaning of the exposed surface of the transparent conductive layer 20 can be performed using, for example, an HF aqueous solution.
  • the transparent conductive layer 26a and the metal layer 27a are formed (S46). Subsequently, as shown in FIG. 20, similarly to S22, the transparent conductive layers 26 and 36 and the metal layer 27a and the metal layer 27a are separated from each other by dividing a part located on the insulating layer 24. Layers 27 and 37 are formed (S48). After that, as shown in FIG. 21, the first electrode portion 28 and the second electrode portion 29 are sequentially formed on the metal layer 27 by electrolytic plating as in S24, and the first electrode is formed on the metal layer 37. The part 38 and the second electrode part 39 are formed (S50). Thereby, the n-side electrode part 25 and the p-side electrode part 35 are formed.
  • the carrier mobility is low in the i-type amorphous silicon layer 22 and the n-type amorphous silicon layer 23.
  • the carrier mobility is higher in the transparent conductive layer 20 than in the i-type amorphous silicon layer 22 and the n-type amorphous silicon layer 23.
  • carriers are preferably discharged from the n-side electrode portion 25 by compensating for the low carrier mobility in the i-type amorphous silicon layer 22 and the n-type amorphous silicon layer 23. It can be taken out.
  • the i-type amorphous silicon layer 22 and the n-type amorphous silicon layer 23, and the i-type amorphous silicon layer 32 and the p-type amorphous silicon layer 33 are electrically connected via the transparent conductive layer 20.
  • the n-side electrode since the carrier mobility is low in the i-type amorphous silicon layer 32 and the p-type amorphous silicon layer 33, the n-side electrode has a high carrier mobility. Since the carrier can be suitably taken out from the portion 25, the electrical connection as described above is not particularly problematic.
  • an insulating layer 24 is formed on the transparent conductive layer 20 on the back side of the photovoltaic element 11. That is, the transparent conductive layer 20 is interposed between the n-type amorphous silicon layer 23 and the insulating layer 24.
  • the transparent conductive layer 20 has higher HF resistance than the i-type amorphous silicon layer 22 and the n-type amorphous silicon layer 23. For this reason, even if the residue of the insulating layer 24 remains on the transparent conductive layer 20 by etching the insulating layer 24, the residue is removed by the process of S44. Further, even when the transparent conductive layer 20 is washed using an HF aqueous solution, the transparent conductive layer 20 is hardly damaged by the HF aqueous solution.
  • the residue can be eliminated by appropriately selecting a cleaning solution that can remove the residue of the insulating layer 24.
  • a cleaning solution that can remove the residue of the insulating layer 24.
  • the insulating layer 24 is formed on the transparent conductive layer 20 on the back surface side of the photovoltaic element 11, the insulating performance between the in laminated portion 21 and the ip laminated portion 31 is improved. be able to.
  • FIG. 22 is a cross-sectional view of a photovoltaic element 11a according to the third embodiment of the present invention.
  • the photovoltaic element 11a includes an antireflection layer 12, an n-type amorphous silicon layer 14, an i-type amorphous silicon layer 16, an n-type single crystal silicon substrate 18, an i-n stacked portion 21, It includes an ip laminated portion 31, a transparent conductive layer 20, an insulating layer 40, an n-side electrode portion 25 and a p-side electrode portion 35.
  • an arrow A shown in FIG. 22 indicates a direction in which light such as sunlight is incident on the photovoltaic element 11a.
  • the insulating layer 40 is formed to electrically insulate the i-n laminated portion 21 and the i-p laminated portion 31.
  • the insulating layer 40 also functions as a protective layer formed on the transparent conductive layer 20.
  • the insulating layer 40 is formed so that the back surface and side surface of the transparent conductive layer 20 may be covered so that the back surface and side surface of the transparent conductive layer 20 may not be exposed, as FIG. 22 shows.
  • the “side surface” means a surface along the thickness direction of the transparent conductive layer 20.
  • the insulating layer 40 may be any material having electrical insulating properties, but preferably includes, for example, aluminum nitride, silicon nitride, silicon oxide, silicon oxynitride, and the like.
  • FIG. 23 is a flowchart showing a procedure of a manufacturing method of the photovoltaic element 11a.
  • the manufacturing method of the photovoltaic element 11a is not limited to the manufacturing method shown in each process. In each step, for example, a sputtering method, a plasma CVD method, a screen printing method, or a plating method can be appropriately used for forming each layer.
  • the manufacturing method of the photovoltaic element 11a and the manufacturing method of the photovoltaic element 11 are the same in the steps S2 to S8. And since the difference between the manufacturing method of the photovoltaic element 11a and the manufacturing method of the photovoltaic element 11 is the process after S8, it demonstrates centering on the difference.
  • steps S2 to S8 are performed.
  • the transparent conductive layer 20a is etched using a patterning mask as shown in FIG. 24 (S30a).
  • the insulating layer 40a is formed on the transparent conductive layer 20, and the antireflection layer 12 is formed on the n-type amorphous silicon layer 14 (S32a).
  • the insulating layer 40a is etched by using a patterning mask designed in advance so as to leave a portion where the side surface of the transparent conductive layer 20 is covered with the insulating layer 40a. Is removed (S34a).
  • the insulating layer 40b is formed by removing a portion of the insulating layer 40a located on a region where the ip stacked portion 31 is bonded to the n-type single crystal silicon substrate 18 in a later step.
  • step S34a since the mask used in step S34a is designed in advance so that the width of the insulating layer 40b is larger than the width of the transparent conductive layer 20, the insulating layer 40b is transparent conductive as shown in FIG. The back surface and side surface of the transparent conductive layer 20 are covered so that the back surface and side surface of the layer 20 are not exposed.
  • an acidic etching solution such as an HF aqueous solution is used for the etching of the insulating layer 40a.
  • the i-type amorphous silicon layer 22a and the n-type amorphous silicon layer 23a are etched (S36a). Specifically, portions of the i-type amorphous silicon layer 22a and the n-type amorphous silicon layer 23a other than the portions covered by the transparent conductive layer 20 and the insulating layer 40b are removed. As a result, the portion of the back surface of the n-type single crystal silicon substrate 18 where the transparent conductive layer 20 and the insulating layer 40b are not located is exposed, so that the i-type amorphous silicon layer 22 and the n-type amorphous silicon layer are exposed. A silicon layer 23 is formed.
  • steps S38 to S40 are performed in the same manner as in the method of manufacturing the photovoltaic element 11.
  • the insulating layer 40b is etched to further remove a part of the insulating layer 40b (S42a).
  • steps S44 to S50 are performed in the same manner as in the method of manufacturing the photovoltaic element 11.
  • the photovoltaic element 11a shown in FIG. 27 is formed.
  • the photovoltaic element 11a has the transparent conductive layer 20 with high carrier mobility, it is possible to suitably take out carriers from the n-side electrode portion 25 as in the photovoltaic elements 10 and 11.
  • the residue of the insulating layer 40 can be removed using an HF aqueous solution in the same manner as the photovoltaic element 11. Thereby, it is possible to prevent an increase in series resistance between the i-n stacked portion 21 and the n-side electrode portion 25 of the photovoltaic element 11a.
  • the photovoltaic element 11a not only the back surface of the transparent conductive layer 20 but also the side surfaces thereof are covered with the insulating layer 40, so that the insulating performance between the in laminated portion 21 and the ip laminated portion 31 is improved. Further improvement can be achieved.
  • the ip stack part 31 is stacked on a part of the in stack part 21, but the present invention is not limited to this.
  • the i-n laminated part 21 may be laminated on a part of the ip laminated part 31 by forming the ip laminated part 31 first and then forming the i-n laminated part 21.
  • the i-n laminated portion 21 may be formed of only an n-type amorphous layer. May be composed of only a p-type amorphous layer.
  • the transparent conductive layer 20 instead of the transparent conductive layer 20, using a metal layer with high electroconductivity and high HF resistance, for example, copper (Cu), silver (Ag), etc. Also good.
  • a metal layer with high electroconductivity and high HF resistance for example, copper (Cu), silver (Ag), etc. Also good.
  • n-type amorphous silicon layer 16 i-type amorphous silicon layer, 18 n-type single crystal silicon substrate, 20, 20a transparent conductive layer, 21 i -N stacked portion, 22, 22a i-type amorphous silicon layer, 23, 23a n-type amorphous silicon layer, 24, 24a, 24b insulating layer, 25 n-side electrode portion, 26, 26a, 36 transparent conductive layer, 27, 27a, 37 metal layer, 28, 38 first electrode part, 29, 39 second electrode part, 31 ip stacked part, 32, 32a i-type amorphous silicon layer, 33, 33a p-type amorphous Silicon layer, 35 p-side electrode part, 40a, 40b insulating layer.

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Abstract

A photovoltaic element (10) is provided with: an i-n laminate (21) laminated on the surface at a first region of one surface of an n-type monocrystalline silicon substrate (18); an i-p laminate (31) laminated straddling a second region of the one surface and a portion of the i-n laminate (21); and a transparent conductive layer (20) disposed between a portion of the i-n laminate (21) and the in-n laminate (21).

Description

光起電力素子Photovoltaic element
　本発明は、光起電力素子に関する。 The present invention relates to a photovoltaic device.
　単結晶シリコン、多結晶シリコンまたはアモルファスシリコンを用いた様々な光起電力素子が開発されている。その一例として、特許文献１には、受光面と、受光面の反対側に設けられる裏面とを有する半導体基板と、裏面上において所定の方向に沿って形成される第１半導体層と、裏面上において所定の方向に沿って形成され、第１半導体層の両隣に配設される一対の第２半導体層と、一対の第２半導体層のうち一方の第２半導体層上から第１半導体層上まで跨って形成される第１絶縁層と、一対の第２半導体層のうち他方の第２半導体層上から第１半導体層上まで跨って形成される第２絶縁層と、第１半導体層及び第２半導体層を覆う透明電極層と、透明電極層上に形成される収集電極層と、を備える光起電力素子が開示されている。 Various photovoltaic devices using single crystal silicon, polycrystalline silicon, or amorphous silicon have been developed. As an example, Patent Document 1 discloses a semiconductor substrate having a light receiving surface and a back surface provided on the opposite side of the light receiving surface, a first semiconductor layer formed along a predetermined direction on the back surface, and a back surface. A pair of second semiconductor layers formed along a predetermined direction and disposed on both sides of the first semiconductor layer, and from one second semiconductor layer to the first semiconductor layer of the pair of second semiconductor layers A first insulating layer formed over the first semiconductor layer, a second insulating layer formed over the first semiconductor layer from the other second semiconductor layer of the pair of second semiconductor layers, a first semiconductor layer, A photovoltaic device comprising a transparent electrode layer covering a second semiconductor layer and a collecting electrode layer formed on the transparent electrode layer is disclosed.
特開２００９－２００２６７号公報JP 2009-200277 A
　ところで、半導体基板上に形成される半導体層上に絶縁層等が積層されることがある。当該絶縁層等のパターンニング処理を行う際に、半導体層上に当該絶縁層等の残渣が付着することがある。この絶縁層の残渣により、半導体層と集電電極部との間のシリーズ抵抗が増大する可能性がある。 By the way, an insulating layer or the like may be stacked on a semiconductor layer formed on a semiconductor substrate. When patterning the insulating layer or the like, residues such as the insulating layer may adhere to the semiconductor layer. The residue of the insulating layer may increase the series resistance between the semiconductor layer and the collecting electrode portion.
　本発明に係る光起電力素子は、結晶系半導体基板と、第１導電型の層を含み、結晶系半導体基板の一方の表面の第１領域において表面上に積層された第１非晶質系半導体層部と、第２導電型の層を含み、一方の表面の第２領域上及び第１非晶質系半導体層部の一部上に跨って積層された第２非晶質系半導体層部と、第１非晶質系半導体層部の一部と第２非晶質系半導体層部との間に配された導電層と、を備えることを特徴とする。 A photovoltaic element according to the present invention includes a crystalline semiconductor substrate and a first conductivity type layer, and is laminated on the surface in a first region of one surface of the crystalline semiconductor substrate. A second amorphous semiconductor layer that includes a semiconductor layer portion and a second conductivity type layer and is stacked over the second region on one surface and a part of the first amorphous semiconductor layer portion And a conductive layer disposed between a part of the first amorphous semiconductor layer portion and the second amorphous semiconductor layer portion.
　本発明によれば、光起電力素子の発電特性を向上させることができる。 According to the present invention, the power generation characteristics of the photovoltaic element can be improved.
本発明の第１実施形態において、光起電力素子の断面図である。In 1st Embodiment of this invention, it is sectional drawing of a photovoltaic device. 本発明の第１実施形態において、光起電力素子の製造方法の手順を示すフローチャートである。In 1st Embodiment of this invention, it is a flowchart which shows the procedure of the manufacturing method of a photovoltaic device. 本発明の第１実施形態において、光起電力素子の製造方法の手順を説明するための断面図である。In 1st Embodiment of this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photovoltaic device. 本発明の第１実施形態において、光起電力素子の製造方法の手順を説明するための断面図である。In 1st Embodiment of this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photovoltaic device. 本発明の第１実施形態において、光起電力素子の製造方法の手順を説明するための断面図である。In 1st Embodiment of this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photovoltaic device. 本発明の第１実施形態において、光起電力素子の製造方法の手順を説明するための断面図である。In 1st Embodiment of this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photovoltaic device. 本発明の第１実施形態において、光起電力素子の製造方法の手順を説明するための断面図である。In 1st Embodiment of this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photovoltaic device. 本発明の第１実施形態において、光起電力素子の製造方法の手順を説明するための断面図である。In 1st Embodiment of this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photovoltaic device. 本発明の第１実施形態において、光起電力素子の製造方法の手順を説明するための断面図である。In 1st Embodiment of this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photovoltaic device. 本発明の第１実施形態において、光起電力素子の製造方法の手順を説明するための断面図である。In 1st Embodiment of this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photovoltaic device. 本発明の第２実施形態において、光起電力素子の断面図である。In 2nd Embodiment of this invention, it is sectional drawing of a photovoltaic device. 本発明の第２実施形態において、光起電力素子の製造方法の手順を示すフローチャートである。In 2nd Embodiment of this invention, it is a flowchart which shows the procedure of the manufacturing method of a photovoltaic device. 本発明の第２実施形態において、光起電力素子の製造方法の手順を説明するための断面図である。In 2nd Embodiment of this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photovoltaic device. 本発明の第２実施形態において、光起電力素子の製造方法の手順を説明するための断面図である。In 2nd Embodiment of this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photovoltaic device. 本発明の第２実施形態において、光起電力素子の製造方法の手順を説明するための断面図である。In 2nd Embodiment of this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photovoltaic device. 本発明の第２実施形態において、光起電力素子の製造方法の手順を説明するための断面図である。In 2nd Embodiment of this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photovoltaic device. 本発明の第２実施形態において、光起電力素子の製造方法の手順を説明するための断面図である。In 2nd Embodiment of this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photovoltaic device. 本発明の第２実施形態において、光起電力素子の製造方法の手順を説明するための断面図である。In 2nd Embodiment of this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photovoltaic device. 本発明の第２実施形態において、光起電力素子の製造方法の手順を説明するための断面図である。In 2nd Embodiment of this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photovoltaic device. 本発明の第２実施形態において、光起電力素子の製造方法の手順を説明するための断面図である。In 2nd Embodiment of this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photovoltaic device. 本発明の第２実施形態において、光起電力素子の製造方法の手順を説明するための断面図である。In 2nd Embodiment of this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photovoltaic device. 本発明の第３実施形態において、光起電力素子の断面図である。In 3rd Embodiment of this invention, it is sectional drawing of a photovoltaic device. 本発明の第３実施形態において、光起電力素子の製造方法の手順を示すフローチャートである。In 3rd Embodiment of this invention, it is a flowchart which shows the procedure of the manufacturing method of a photovoltaic device. 本発明の第３実施形態において、光起電力素子の製造方法の手順を説明するための断面図である。In 3rd Embodiment of this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photovoltaic device. 本発明の第３実施形態において、光起電力素子の製造方法の手順を説明するための断面図である。In 3rd Embodiment of this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photovoltaic device. 本発明の第３実施形態において、光起電力素子の製造方法の手順を説明するための断面図である。In 3rd Embodiment of this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photovoltaic device. 本発明の第３実施形態において、光起電力素子の製造方法の手順を説明するための断面図である。In 3rd Embodiment of this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photovoltaic device.
　以下に図面を用いて、本発明に係る実施の形態を詳細に説明する。また、以下では、全ての図面において、同様の要素には同一の符号を付し、重複する説明を省略する。また、本文中の説明においては、必要に応じそれ以前に述べた符号を用いるものとする。 Embodiments according to the present invention will be described below in detail with reference to the drawings. Also, in the following, in all the drawings, the same symbols are attached to the same elements, and the duplicate description is omitted. In the description in the text, the symbols described before are used as necessary.
（第１実施形態）
　図１は、光起電力素子１０の断面図である。光起電力素子１０は、反射防止層１２と、ｎ型非晶質シリコン層１４と、ｉ型非晶質シリコン層１６と、ｎ型単結晶シリコン基板１８と、ｉ－ｎ積層部２１と、ｉ－ｐ積層部３１と、透明導電層２０と、ｎ側電極部２５と、ｐ側電極部３５とを備える。ここで、図１に示される矢印Ａは、光起電力素子１０に対して太陽光等の光が入射される方向を示している。なお、本明細書では、「受光面」とは、太陽光等の光が主に入射される面を意味する。また、「裏面」とは、受光面と反対側の面を意味する。 (First embodiment)
FIG. 1 is a cross-sectional view of the photovoltaic element 10. The photovoltaic device 10 includes an antireflection layer 12, an n-type amorphous silicon layer 14, an i-type amorphous silicon layer 16, an n-type single crystal silicon substrate 18, an in-layer stack portion 21, An ip laminated portion 31, a transparent conductive layer 20, an n-side electrode portion 25, and a p-side electrode portion 35 are provided. Here, an arrow A shown in FIG. 1 indicates a direction in which light such as sunlight is incident on the photovoltaic element 10. In the present specification, the “light receiving surface” means a surface on which light such as sunlight is mainly incident. The “back surface” means a surface opposite to the light receiving surface.
　ｎ型単結晶シリコン基板１８は、受光面側から入射された光を受けてキャリアを生成する発電層である。なお、本実施の形態では、ｎ型単結晶シリコン基板１８としたが、これに限定されるものではなく、ｎ型又はｐ型の導電型の結晶系半導体材料からなるウエハ状の半導体基板とすることができる。単結晶シリコン基板の他にも、例えば、多結晶シリコン基板、砒化ガリウム基板（ＧａＡｓ）、インジウム燐基板（ＩｎＰ）等を適用することができる。 The n-type single crystal silicon substrate 18 is a power generation layer that receives light incident from the light receiving surface side and generates carriers. In the present embodiment, the n-type single crystal silicon substrate 18 is used. However, the present invention is not limited to this, and a wafer-like semiconductor substrate made of a crystalline semiconductor material of n-type or p-type conductivity is used. be able to. In addition to the single crystal silicon substrate, for example, a polycrystalline silicon substrate, a gallium arsenide substrate (GaAs), an indium phosphorus substrate (InP), or the like can be used.
　ｉ型非晶質シリコン層１６は、ｎ型単結晶シリコン基板１８の受光面上に形成される。ｉ型非晶質シリコン層１６は、水素を含むパッシベーション層である。ｎ型非晶質シリコン層１４は、ｉ型非晶質シリコン層１６上に形成される。ｉ型非晶質シリコン層１６及びｎ型非晶質シリコン層１４は、受光面に形成される非晶質系半導体層部を構成する。ｉ型非晶質シリコン層１６は、真性な非晶質半導体膜からなる層である。ｉ型非晶質シリコン層１６は、ｎ型非晶質シリコン層１４よりも膜中のドーパント濃度が低くされる。例えば、ｉ型非晶質シリコン層１６は、ｎ型又はｐ型のドーパント濃度を低くし、暗導電率を１０-9Ｓ／ｃｍ以下とすることが好適である。ｎ型非晶質シリコン層１４は、ｎ型の導電型のドーパントを含む非晶質半導体膜からなる層である。ｎ型非晶質シリコン層１４は、ｉ型非晶質シリコン層１６よりも膜中のｎ型ドーパント濃度が高くされる。例えば、ｎ型非晶質シリコン層１４は、暗導電率を１０-5Ｓ／ｃｍ以上とすることが好適である。 The i-type amorphous silicon layer 16 is formed on the light-receiving surface of the n-type single crystal silicon substrate 18. The i-type amorphous silicon layer 16 is a passivation layer containing hydrogen. The n-type amorphous silicon layer 14 is formed on the i-type amorphous silicon layer 16. The i-type amorphous silicon layer 16 and the n-type amorphous silicon layer 14 constitute an amorphous semiconductor layer portion formed on the light receiving surface. The i-type amorphous silicon layer 16 is a layer made of an intrinsic amorphous semiconductor film. The i-type amorphous silicon layer 16 has a lower dopant concentration in the film than the n-type amorphous silicon layer 14. For example, the i-type amorphous silicon layer 16 preferably has a low n-type or p-type dopant concentration and a dark conductivity of 10 −9 S / cm or less. The n-type amorphous silicon layer 14 is a layer made of an amorphous semiconductor film containing an n-type conductive dopant. The n-type amorphous silicon layer 14 has a higher n-type dopant concentration in the film than the i-type amorphous silicon layer 16. For example, the n-type amorphous silicon layer 14 preferably has a dark conductivity of 10 −5 S / cm or more.
　なお、本実施の形態において非晶質シリコン層は、微結晶構造を含んでも良い。微結晶構造は、非晶質半導体中に結晶粒が析出している構造である。結晶粒の平均粒径は、これに限定されるものではないが、１ｎｍ以上８０ｎｍ以下程度であると推定されている。 Note that in this embodiment mode, the amorphous silicon layer may include a microcrystalline structure. The microcrystalline structure is a structure in which crystal grains are precipitated in an amorphous semiconductor. The average grain size of the crystal grains is not limited to this, but is estimated to be about 1 nm to 80 nm.
　反射防止層１２は、ｎ型非晶質シリコン層１４上に形成され、光起電力素子１０の受光面側から入射される光の反射を低減させる。また、反射防止層１２は、ｎ型非晶質シリコン層１４の表面を保護する保護層としても機能する。反射防止層１２は、ｎ型単結晶シリコン基板１８により吸収可能な波長範囲の光に対し、透光性を有する材料で構成される。また、反射防止層１２によって覆われる層の屈折率との関係で光起電力素子１０の受光面から入射される光の反射を低減させる屈折率を有する材料及び膜厚とすることが好適である。反射防止層１２は、例えば、窒化アルミニウム、窒化ケイ素及び酸化ケイ素、酸窒化ケイ素等を含んで構成される。 The antireflection layer 12 is formed on the n-type amorphous silicon layer 14 and reduces reflection of light incident from the light receiving surface side of the photovoltaic element 10. The antireflection layer 12 also functions as a protective layer that protects the surface of the n-type amorphous silicon layer 14. The antireflection layer 12 is made of a material having translucency for light in a wavelength range that can be absorbed by the n-type single crystal silicon substrate 18. Further, it is preferable to use a material having a refractive index and a film thickness that reduce reflection of light incident from the light receiving surface of the photovoltaic element 10 in relation to the refractive index of the layer covered by the antireflection layer 12. . The antireflection layer 12 includes, for example, aluminum nitride, silicon nitride, silicon oxide, silicon oxynitride, and the like.
　上述の通り、ｎ型単結晶シリコン基板１８の受光面上には、厚い金属層等の、ｎ型単結晶シリコン基板１８により吸収可能な波長範囲の光に対し遮光性を有する構造が設けられていない。従って、光起電力素子１０は、ｎ型単結晶シリコン基板１８の受光面の略全面で受光することができる。 As described above, on the light-receiving surface of the n-type single crystal silicon substrate 18, a structure having a light shielding property against light in a wavelength range that can be absorbed by the n-type single crystal silicon substrate 18, such as a thick metal layer, is provided. Absent. Therefore, the photovoltaic element 10 can receive light over substantially the entire light receiving surface of the n-type single crystal silicon substrate 18.
　ｉ－ｎ積層部２１は、ｎ型単結晶シリコン基板１８の裏面上に形成される。ｉ－ｎ積層部２１は、後述するｎ側電極部２５において、光起電力素子１０の面内からまんべんなく集電可能なように配置することが好適である。ｉ－ｎ積層部２１は、例えば、複数のフィンガー部が平行に延伸する櫛歯形状とすることが好適である。ｉ－ｎ積層部２１は、ｉ型非晶質シリコン層２２と、ｎ型非晶質シリコン層２３と、を備える。 The i-n laminated portion 21 is formed on the back surface of the n-type single crystal silicon substrate 18. It is preferable that the i-n laminated portion 21 is arranged so that current can be collected evenly from the surface of the photovoltaic element 10 in an n-side electrode portion 25 described later. For example, the i-n stacked portion 21 preferably has a comb-teeth shape in which a plurality of finger portions extend in parallel. The i-n stacked unit 21 includes an i-type amorphous silicon layer 22 and an n-type amorphous silicon layer 23.
　ｉ型非晶質シリコン層２２は、ｎ型単結晶シリコン基板１８の裏面上に形成されるパッシベーション層である。ｎ型非晶質シリコン層２３は、ｉ型非晶質シリコン層２２上に形成される。ｉ－ｎ積層部２１は、裏面に形成される第１の非晶質系半導体層部を構成する。ｉ型非晶質シリコン層２２は、真性な非晶質半導体膜からなる層である。ｉ型非晶質シリコン層２２は、ｎ型非晶質シリコン層２３よりも膜中のドーパント濃度が低くされる。例えば、ｉ型非晶質シリコン層２２は、ｎ型又はｐ型のドーパント濃度を低くし、暗導電率を１０-9Ｓ／ｃｍ以下とすることが好適である。ｎ型非晶質シリコン層２３は、ｎ型の導電型のドーパントを含む非晶質半導体膜からなる層である。ｎ型非晶質シリコン層２３は、ｉ型非晶質シリコン層２２よりも膜中のｎ型のドーパント濃度が高くされる。例えば、ｎ型非晶質シリコン層２３は、暗導電率を１０-5Ｓ／ｃｍ以上とすることが好適である。 The i-type amorphous silicon layer 22 is a passivation layer formed on the back surface of the n-type single crystal silicon substrate 18. The n-type amorphous silicon layer 23 is formed on the i-type amorphous silicon layer 22. The i-n stacked portion 21 constitutes a first amorphous semiconductor layer portion formed on the back surface. The i-type amorphous silicon layer 22 is a layer made of an intrinsic amorphous semiconductor film. The i-type amorphous silicon layer 22 has a lower dopant concentration in the film than the n-type amorphous silicon layer 23. For example, the i-type amorphous silicon layer 22 preferably has a low n-type or p-type dopant concentration and a dark conductivity of 10 −9 S / cm or less. The n-type amorphous silicon layer 23 is a layer made of an amorphous semiconductor film containing an n-type conductive dopant. The n-type amorphous silicon layer 23 has a higher n-type dopant concentration in the film than the i-type amorphous silicon layer 22. For example, the n-type amorphous silicon layer 23 preferably has a dark conductivity of 10 −5 S / cm or more.
　透明導電層２０は、ｎ型非晶質シリコン層２３上に形成される。透明導電層２０は、酸化インジウム（Ｉｎ2Ｏ3）、酸化亜鉛（ＺｎＯ）、酸化錫（ＳｎＯ2）及び酸化チタン（ＴｉＯ2）等の金属酸化物のうちの少なくとも１つを含んで構成される。ここでは、透明導電層２０はインジウム錫酸化物（ＩＴＯ）を用いて形成されているものとして説明する。 The transparent conductive layer 20 is formed on the n-type amorphous silicon layer 23. The transparent conductive layer 20 includes at least one of metal oxides such as indium oxide (In 2 O 3 ), zinc oxide (ZnO), tin oxide (SnO 2 ), and titanium oxide (TiO 2 ). The Here, the transparent conductive layer 20 is described as being formed using indium tin oxide (ITO).
　ｎ側電極部２５は、光起電力素子１０において発電された電気を集電して取り出すために設けられる電極部である。ｎ側電極部２５は、透明導電層２６と、金属層２７と、第１電極部２８と、第２電極部２９とを備える。 The n-side electrode part 25 is an electrode part provided for collecting and taking out the electricity generated in the photovoltaic element 10. The n-side electrode unit 25 includes a transparent conductive layer 26, a metal layer 27, a first electrode unit 28, and a second electrode unit 29.
　透明導電層２６は、透明導電層２０上に形成される。透明導電層２６は、酸化インジウム（Ｉｎ2Ｏ3）、酸化亜鉛（ＺｎＯ）、酸化錫（ＳｎＯ2）及び酸化チタン（ＴｉＯ2）等の金属酸化物のうちの少なくとも１つを含んで構成される。ここでは、透明導電層２６はインジウム錫酸化物（ＩＴＯ）を用いて形成されているものとして説明する。 The transparent conductive layer 26 is formed on the transparent conductive layer 20. The transparent conductive layer 26 includes at least one of metal oxides such as indium oxide (In 2 O 3 ), zinc oxide (ZnO), tin oxide (SnO 2 ), and titanium oxide (TiO 2 ). The Here, the transparent conductive layer 26 is described as being formed using indium tin oxide (ITO).
　金属層２７は、透明導電層２６上に形成される。金属層２７は、例えば、銅（Ｃｕ）等の金属や合金を含んで構成されるシード層である。ここで、「シード層」とは、めっき成長の起点となる層のことをいう。第１電極部２８は、めっき成長によって金属層２７上に形成される電極である。第１電極部２８は、例えば、銅（Ｃｕ）を含んで構成される。第２電極部２９は、めっき成長によって第１電極部２８上に形成される電極である。第２電極部２９は、例えば、錫（Ｓｎ）を含んで構成される。 The metal layer 27 is formed on the transparent conductive layer 26. The metal layer 27 is a seed layer including a metal such as copper (Cu) or an alloy, for example. Here, the “seed layer” refers to a layer that is a starting point for plating growth. The first electrode portion 28 is an electrode formed on the metal layer 27 by plating growth. The first electrode unit 28 includes, for example, copper (Cu). The second electrode part 29 is an electrode formed on the first electrode part 28 by plating growth. For example, the second electrode unit 29 includes tin (Sn).
　ｉ－ｐ積層部３１は、ｎ型単結晶シリコン基板１８の裏面上にｉ－ｎ積層部２１と間挿し合うように形成される。ｉ－ｐ積層部３１は、ｎ型単結晶シリコン基板１８の裏面上からｉ－ｎ積層部２１の縁部上に跨って形成される。即ち、光起電力素子１０においては、ｉ－ｐ積層部３１とｉ－ｎ積層部２１との積層構造が一部に存在する。 The i-p stacked portion 31 is formed on the back surface of the n-type single crystal silicon substrate 18 so as to be inserted into the i-n stacked portion 21. The ip laminated portion 31 is formed from the back surface of the n-type single crystal silicon substrate 18 to the edge of the i-n laminated portion 21. That is, in the photovoltaic element 10, a part of the laminated structure of the ip laminated part 31 and the in laminated part 21 exists.
　ｉ－ｐ積層部３１は、光起電力素子１０の面内からまんべんなく集電可能なように配置することが好適である。ｉ－ｐ積層部３１は、例えば、複数のフィンガー部が平行に延伸する櫛歯形状とすることが好適である。ｉ－ｐ積層部３１は、ｉ型非晶質シリコン層３２と、ｐ型非晶質シリコン層３３と、を備える。 It is preferable that the ip stacked portion 31 is arranged so that current can be collected evenly from within the surface of the photovoltaic element 10. The ip laminated portion 31 is preferably, for example, in a comb-teeth shape in which a plurality of finger portions extend in parallel. The ip laminated portion 31 includes an i-type amorphous silicon layer 32 and a p-type amorphous silicon layer 33.
　ｉ型非晶質シリコン層３２は、ｎ型単結晶シリコン基板１８の裏面上に形成されるパッシベーション層である。ｐ型非晶質シリコン層３３は、ｉ型非晶質シリコン層３２上に形成される。ｉ－ｐ積層部３１は、裏面に形成される第２の非晶質系半導体層部を構成する。ｉ型非晶質シリコン層３２は、真性な非晶質半導体膜からなる層である。ｉ型非晶質シリコン層３２は、ｐ型非晶質シリコン層３３よりも膜中のドーパント濃度が低くされる。例えば、ｉ型非晶質シリコン層３２は、ｎ型又はｐ型のドーパント濃度を低くし、暗導電率を１０-9Ｓ／ｃｍ以下とすることが好適である。ｐ型非晶質シリコン層３３は、ｐ型の導電型のドーパントを含む非晶質半導体膜からなる層である。ｐ型非晶質シリコン層３３は、ｉ型非晶質シリコン層３２よりも膜中のｐ型のドーパント濃度が高くされる。例えば、ｐ型非晶質シリコン層３３は、暗導電率を１０-8ｓ／ｃｍ以上とすることが好適である。 The i-type amorphous silicon layer 32 is a passivation layer formed on the back surface of the n-type single crystal silicon substrate 18. The p-type amorphous silicon layer 33 is formed on the i-type amorphous silicon layer 32. The ip stacked portion 31 constitutes a second amorphous semiconductor layer portion formed on the back surface. The i-type amorphous silicon layer 32 is a layer made of an intrinsic amorphous semiconductor film. The i-type amorphous silicon layer 32 has a lower dopant concentration in the film than the p-type amorphous silicon layer 33. For example, the i-type amorphous silicon layer 32 preferably has a low n-type or p-type dopant concentration and a dark conductivity of 10 −9 S / cm or less. The p-type amorphous silicon layer 33 is a layer made of an amorphous semiconductor film containing a p-type conductive dopant. The p-type amorphous silicon layer 33 has a higher p-type dopant concentration in the film than the i-type amorphous silicon layer 32. For example, the p-type amorphous silicon layer 33 preferably has a dark conductivity of 10 −8 s / cm or more.
　ｐ側電極部３５は、光起電力素子１０において発電された電気を集電して取り出すために設けられる電極部である。ｐ側電極部３５は、透明導電層３６と、金属層３７と、第１電極部３８と、第２電極部３９とを備える。透明導電層３６は、ｐ型非晶質シリコン層３３上に形成される。ここで、透明導電層３６の材料等は、透明導電層２６と同じであるため、詳細な説明は省略する。金属層３７は、透明導電層３６上に形成される。ここで、金属層３７の材料等は、金属層２７と同じであるため、詳細な説明は省略する。第１電極部３８は、めっき成長によって金属層３７上に形成される。ここで、第１電極部３８の材料等は、第１電極部２８と同じであるため、詳細な説明は省略する。第２電極部３９は、めっき成長によって第１電極部３８上に形成される。ここで、第２電極部３９の材料等は、第２電極部２９と同じであるため、詳細な説明は省略する。 The p-side electrode part 35 is an electrode part provided for collecting and taking out the electricity generated in the photovoltaic element 10. The p-side electrode part 35 includes a transparent conductive layer 36, a metal layer 37, a first electrode part 38, and a second electrode part 39. The transparent conductive layer 36 is formed on the p-type amorphous silicon layer 33. Here, since the material and the like of the transparent conductive layer 36 are the same as those of the transparent conductive layer 26, detailed description thereof is omitted. The metal layer 37 is formed on the transparent conductive layer 36. Here, since the material and the like of the metal layer 37 are the same as those of the metal layer 27, detailed description thereof is omitted. The first electrode portion 38 is formed on the metal layer 37 by plating growth. Here, since the material and the like of the first electrode portion 38 are the same as those of the first electrode portion 28, detailed description thereof is omitted. The second electrode portion 39 is formed on the first electrode portion 38 by plating growth. Here, since the material and the like of the second electrode portion 39 are the same as those of the second electrode portion 29, detailed description thereof is omitted.
　次に、光起電力素子１０の製造方法の一例を説明する。図２は、光起電力素子１０の製造方法の手順を示すフローチャートである。なお、光起電力素子１０の製造方法は、各工程において示す製造方法に限定されない。各工程において、各層の形成は、例えば、スパッタリング法、プラズマＣＶＤ法、スクリーン印刷法或いはめっき法等を適宜用いることができる。 Next, an example of a method for manufacturing the photovoltaic element 10 will be described. FIG. 2 is a flowchart showing the procedure of the method for manufacturing the photovoltaic element 10. In addition, the manufacturing method of the photovoltaic element 10 is not limited to the manufacturing method shown in each process. In each step, for example, a sputtering method, a plasma CVD method, a screen printing method, or a plating method can be appropriately used for forming each layer.
　まず、ｎ型単結晶シリコン基板１８を用意して、ｎ型単結晶シリコン基板１８の受光面及び裏面の洗浄を行う（Ｓ２）。ここで、ｎ型単結晶シリコン基板１８の洗浄は、例えば、ＨＦ水溶液等を用いて行うことができる。 First, an n-type single crystal silicon substrate 18 is prepared, and the light receiving surface and the back surface of the n-type single crystal silicon substrate 18 are cleaned (S2). Here, the n-type single crystal silicon substrate 18 can be cleaned using, for example, an HF aqueous solution.
　次に、ｎ型単結晶シリコン基板１８の受光面上にテクスチャ構造を形成する（Ｓ４）。テクスチャ構造は、異方性エッチングまたは等方性エッチングを用いて行うことができる。そして、図３に示されるように、ｎ型単結晶シリコン基板１８の裏面上に、ｉ型非晶質シリコン層２２ａとｎ型非晶質シリコン層２３ａを形成して、その後に、ｎ型単結晶シリコン基板１８の受光面上に、ｉ型非晶質シリコン層１６とｎ型非晶質シリコン層１４を形成する（Ｓ６）。 Next, a texture structure is formed on the light receiving surface of the n-type single crystal silicon substrate 18 (S4). The texture structure can be performed using anisotropic etching or isotropic etching. Then, as shown in FIG. 3, an i-type amorphous silicon layer 22a and an n-type amorphous silicon layer 23a are formed on the back surface of the n-type single crystal silicon substrate 18, and thereafter, an n-type single crystal silicon layer 23a is formed. The i-type amorphous silicon layer 16 and the n-type amorphous silicon layer 14 are formed on the light receiving surface of the crystalline silicon substrate 18 (S6).
　続いて、図４に示されるように、ｎ型非晶質シリコン層２３ａ上に透明導電層２０ａを形成する（Ｓ８）。 Subsequently, as shown in FIG. 4, a transparent conductive layer 20a is formed on the n-type amorphous silicon layer 23a (S8).
　その後、ｎ型非晶質シリコン層１４上に反射防止層１２を形成する（Ｓ１０）。 Thereafter, the antireflection layer 12 is formed on the n-type amorphous silicon layer 14 (S10).
　次に、図５に示されるように、透明導電層２０ａの一部分をエッチングする（Ｓ１２）。具体的には、透明導電層２０ａのうち、後工程でｎ型単結晶シリコン基板１８にｉ－ｐ積層部３１を接合させる領域の上に位置する部分を除去して透明導電層２０を形成する。ここで、透明導電層２０ａのエッチングは、例えば、塩酸（ＨＣｌ）等の酸性のエッチング液を用いる。 Next, as shown in FIG. 5, a part of the transparent conductive layer 20a is etched (S12). Specifically, the transparent conductive layer 20 is formed by removing a portion of the transparent conductive layer 20a located on a region where the ip stacked portion 31 is bonded to the n-type single crystal silicon substrate 18 in a later step. . Here, the etching of the transparent conductive layer 20a uses, for example, an acidic etching solution such as hydrochloric acid (HCl).
　そして、図６に示されるように、Ｓ１２においてパターンニングされた透明導電層２０をマスクとして用い、ｉ型非晶質シリコン層２２ａとｎ型非晶質シリコン層２３ａをエッチングする（Ｓ１４）。具体的には、ｉ型非晶質シリコン層２２ａとｎ型非晶質シリコン層２３ａのうち、透明導電層２０によって覆われている部分以外の部分を除去する。これにより、ｎ型単結晶シリコン基板１８の裏面のうち、上方に透明導電層２０が位置していない部分を露出させて、ｉ型非晶質シリコン層２２とｎ型非晶質シリコン層２３を形成する。ここで、ｉ型非晶質シリコン層２２ａとｎ型非晶質シリコン層２３ａのエッチングは、例えば、水酸化ナトリウム（ＮａＯＨ）を含む水溶液等のアルカリ性のエッチング液を用いる。 Then, as shown in FIG. 6, using the transparent conductive layer 20 patterned in S12 as a mask, the i-type amorphous silicon layer 22a and the n-type amorphous silicon layer 23a are etched (S14). Specifically, portions of the i-type amorphous silicon layer 22a and the n-type amorphous silicon layer 23a other than the portion covered with the transparent conductive layer 20 are removed. As a result, the portion of the back surface of the n-type single crystal silicon substrate 18 where the transparent conductive layer 20 is not located is exposed, and the i-type amorphous silicon layer 22 and the n-type amorphous silicon layer 23 are formed. Form. Here, for etching the i-type amorphous silicon layer 22a and the n-type amorphous silicon layer 23a, for example, an alkaline etching solution such as an aqueous solution containing sodium hydroxide (NaOH) is used.
　続いて、図７に示されるように、透明導電層２０、ｉ型非晶質シリコン層２２、ｎ型非晶質シリコン層２３及び露出されたｎ型単結晶シリコン基板１８の裏面を覆うように、ｉ型非晶質シリコン層３２ａとｐ型非晶質シリコン層３３ａを形成する（Ｓ１６）。 Subsequently, as shown in FIG. 7, the transparent conductive layer 20, the i-type amorphous silicon layer 22, the n-type amorphous silicon layer 23 and the exposed back surface of the n-type single crystal silicon substrate 18 are covered. Then, the i-type amorphous silicon layer 32a and the p-type amorphous silicon layer 33a are formed (S16).
　その後、図８に示されるように、ｉ型非晶質シリコン層３２ａ及びｐ型非晶質シリコン層３３ａのうち、透明導電層２０の上に位置している部分の一部分をエッチングする（Ｓ１８）。これにより、ｉ型非晶質シリコン層３２及びｐ型非晶質シリコン層３３を形成する。 Thereafter, as shown in FIG. 8, a portion of the i-type amorphous silicon layer 32a and the p-type amorphous silicon layer 33a located on the transparent conductive layer 20 is etched (S18). . Thereby, the i-type amorphous silicon layer 32 and the p-type amorphous silicon layer 33 are formed.
　次に、透明導電層２６ａ、金属層２７ａを形成する（Ｓ２０）。 Next, the transparent conductive layer 26a and the metal layer 27a are formed (S20).
　続いて、図９に示されるように、透明導電層２６ａ及び金属層２７ａのうち、透明導電層２０の上に位置する一部分を分断することにより、透明導電層２６，３６及び金属層２７，３７を形成する（Ｓ２２）。ここで、透明導電層２６ａ及び金属層２７ａは、例えば、リソグラフィー法等によって分断する。 Subsequently, as shown in FIG. 9, the transparent conductive layers 26 and 36 and the metal layers 27 and 37 are separated by dividing a portion of the transparent conductive layer 26 a and the metal layer 27 a located on the transparent conductive layer 20. Is formed (S22). Here, the transparent conductive layer 26a and the metal layer 27a are divided by, for example, a lithography method.
　その後、図１０に示されるように、電解めっきにより、金属層２７の上に第１電極部２８と第２電極部２９を順次形成し、金属層３７の上に第１電極部３８と第２電極部３９を順次形成する（Ｓ２４）。これにより、ｎ側電極部２５とｐ側電極部３５とが形成がされる。 Thereafter, as shown in FIG. 10, the first electrode portion 28 and the second electrode portion 29 are sequentially formed on the metal layer 27 by electrolytic plating, and the first electrode portion 38 and the second electrode portion 29 are formed on the metal layer 37. The electrode portions 39 are sequentially formed (S24). Thereby, the n-side electrode part 25 and the p-side electrode part 35 are formed.
　一般的に、光起電力素子１０において、ｉ型非晶質シリコン層２２、ｎ型非晶質シリコン層２３内では、キャリアの移動度が低い。一方、透明導電層２０内では、キャリアの移動度がｉ型非晶質シリコン層２２、ｎ型非晶質シリコン層２３内に比べて高い。これにより、透明導電層２０内において、ｉ型非晶質シリコン層２２、ｎ型非晶質シリコン層２３でのキャリアの移動度の低さを補うことでｎ側電極部２５から好適にキャリアを取り出すことができる。なお、透明導電層２０を介して、ｉ型非晶質シリコン層２２及びｎ型非晶質シリコン層２３と、ｉ型非晶質シリコン層３２及びｐ型非晶質シリコン層３３とが電気的に接続されることとなるが、一般的に、ｉ型非晶質シリコン層３２、ｐ型非晶質シリコン層３３においてもキャリアの移動度が低いことから、キャリアの移動度が高いｎ側電極部２５からキャリアを好適に取り出すことができるため、上記のように電気的に接続されていることは特に大きな問題とならない。 Generally, in the photovoltaic device 10, the carrier mobility is low in the i-type amorphous silicon layer 22 and the n-type amorphous silicon layer 23. On the other hand, the carrier mobility is higher in the transparent conductive layer 20 than in the i-type amorphous silicon layer 22 and the n-type amorphous silicon layer 23. As a result, in the transparent conductive layer 20, carriers are preferably discharged from the n-side electrode portion 25 by compensating for the low carrier mobility in the i-type amorphous silicon layer 22 and the n-type amorphous silicon layer 23. It can be taken out. Note that the i-type amorphous silicon layer 22 and the n-type amorphous silicon layer 23, and the i-type amorphous silicon layer 32 and the p-type amorphous silicon layer 33 are electrically connected via the transparent conductive layer 20. In general, since the carrier mobility is low in the i-type amorphous silicon layer 32 and the p-type amorphous silicon layer 33, the n-side electrode has a high carrier mobility. Since the carrier can be suitably taken out from the portion 25, the electrical connection as described above does not cause a significant problem.
　また、光起電力素子１０において、裏面側には、ｉ－ｎ積層部２１上に絶縁層が形成されない。このため、絶縁層をエッチングする工程も存在せず、絶縁層の残渣が透明導電層２０、ｉ型非晶質シリコン層２２又はｎ型非晶質シリコン層２３に付着することがない。これにより、絶縁層の残渣が存在することによって光起電力素子１０のｉ－ｎ積層部２１とｎ側電極部２５との間のシリーズ抵抗が増大してしまうことを防止することができる。したがって、光起電力素子１０の発電特性を向上させることができる。 Further, in the photovoltaic element 10, an insulating layer is not formed on the in laminated portion 21 on the back surface side. Therefore, there is no step of etching the insulating layer, and the residue of the insulating layer does not adhere to the transparent conductive layer 20, the i-type amorphous silicon layer 22, or the n-type amorphous silicon layer 23. Thereby, it is possible to prevent the series resistance between the in-stacked portion 21 and the n-side electrode portion 25 of the photovoltaic element 10 from increasing due to the presence of the insulating layer residue. Therefore, the power generation characteristics of the photovoltaic element 10 can be improved.
（第２実施形態）
　図１１は、本発明の第２実施形態である光起電力素子１１の断面図である。光起電力素子１１は、反射防止層１２と、ｎ型非晶質シリコン層１４と、ｉ型非晶質シリコン層１６と、ｎ型単結晶シリコン基板１８と、ｉ－ｎ積層部２１と、ｉ－ｐ積層部３１と、透明導電層２０と、絶縁層２４と、ｎ側電極部２５と、ｐ側電極部３５とを含む。ここで、光起電力素子１１と、上記第１実施形態である光起電力素子１０の相違点は、絶縁層２４のみであるため、その相違点を中心に説明する。ここで、図１１に示される矢印Ａは、光起電力素子１１に対して太陽光等の光が入射される方向を示している。 (Second Embodiment)
FIG. 11 is a cross-sectional view of a photovoltaic element 11 according to the second embodiment of the present invention. The photovoltaic device 11 includes an antireflection layer 12, an n-type amorphous silicon layer 14, an i-type amorphous silicon layer 16, an n-type single crystal silicon substrate 18, an in-layer stack portion 21, It includes an ip laminated portion 31, a transparent conductive layer 20, an insulating layer 24, an n-side electrode portion 25, and a p-side electrode portion 35. Here, since the difference between the photovoltaic element 11 and the photovoltaic element 10 according to the first embodiment is only the insulating layer 24, the difference will be mainly described. Here, an arrow A shown in FIG. 11 indicates a direction in which light such as sunlight is incident on the photovoltaic element 11.
　絶縁層２４は、ｉ－ｎ積層部２１とｉ－ｐ積層部３１とを電気的に絶縁するために形成される。また、絶縁層２４は、透明導電層２０上に形成される保護層としても機能する。絶縁層２４は、電気的な絶縁性を有する材料であればよく、例えば、窒化アルミニウム、窒化ケイ素、酸化ケイ素及び酸窒化ケイ素等を含んで構成することが好適である。 The insulating layer 24 is formed to electrically insulate the i-n laminated portion 21 and the ip laminated portion 31. The insulating layer 24 also functions as a protective layer formed on the transparent conductive layer 20. The insulating layer 24 may be any material having electrical insulation properties, and preferably includes, for example, aluminum nitride, silicon nitride, silicon oxide, silicon oxynitride, and the like.
　次に、光起電力素子１１の製造方法の一例を説明する。図１２は、光起電力素子１１の製造方法の手順を示すフローチャートである。なお、光起電力素子１１の製造方法は、各工程において示す製造方法に限定されない。各工程において、例えば、スパッタリング法、プラズマＣＶＤ法、スクリーン印刷法或いはめっき法等を適宜用いることができる。 Next, an example of a method for manufacturing the photovoltaic element 11 will be described. FIG. 12 is a flowchart showing the procedure of the method for manufacturing the photovoltaic element 11. In addition, the manufacturing method of the photovoltaic element 11 is not limited to the manufacturing method shown in each process. In each step, for example, a sputtering method, a plasma CVD method, a screen printing method, a plating method, or the like can be used as appropriate.
　光起電力素子１１の製造方法と光起電力素子１０の製造方法は、Ｓ２～Ｓ８の各工程において同じである。そして、光起電力素子１１の製造方法と光起電力素子１０の製造方法の相違は、Ｓ８以降の工程であるため、その相違点を中心に説明する。 The manufacturing method of the photovoltaic element 11 and the manufacturing method of the photovoltaic element 10 are the same in the steps S2 to S8. And since the difference between the manufacturing method of the photovoltaic element 11 and the manufacturing method of the photovoltaic element 10 is a process after S8, it demonstrates centering on the difference.
　まず、Ｓ２～Ｓ８の工程を行う。Ｓ８の後は、図１３に示されるように、透明導電層２０ａ上に絶縁層２４ａを形成するとともに、ｎ型非晶質シリコン層１４上に反射防止層１２を形成する（Ｓ３０）。 First, steps S2 to S8 are performed. After S8, as shown in FIG. 13, the insulating layer 24a is formed on the transparent conductive layer 20a, and the antireflection layer 12 is formed on the n-type amorphous silicon layer 14 (S30).
　次に、図１４に示されるように、絶縁層２４ａをエッチングすることにより、絶縁層２４ａの一部分を除去する（Ｓ３２）。具体的には、絶縁層２４ａのうち、後工程でｎ型単結晶シリコン基板１８にｉ－ｐ積層部３１を接合させるための領域の上に位置する部分を除去して絶縁層２４ｂを形成する。ここで、絶縁層２４ａのエッチングには、例えば、ＨＦ水溶液等の酸性のエッチング液を用いる。 Next, as shown in FIG. 14, the insulating layer 24a is etched to remove a part of the insulating layer 24a (S32). Specifically, the insulating layer 24b is formed by removing a portion of the insulating layer 24a located above a region for bonding the ip stacked portion 31 to the n-type single crystal silicon substrate 18 in a later step. . Here, for the etching of the insulating layer 24a, for example, an acidic etching solution such as an HF aqueous solution is used.
　そして、図１５に示されるように、Ｓ３２においてパターンニングされた絶縁層２４ｂをマスクとして用い、透明導電層２０ａをエッチングする（Ｓ３４）。これにより、パターンニングされた透明導電層２０が形成される。 Then, as shown in FIG. 15, the transparent conductive layer 20a is etched using the insulating layer 24b patterned in S32 as a mask (S34). Thereby, the patterned transparent conductive layer 20 is formed.
　以下、透明導電層２０上に絶縁層２４ｂがあることを除けば、第１実施形態のＳ１４，Ｓ１６,Ｓ１８と同様の工程を行う。具体的には、図１６に示されるように、Ｓ１４と同様に、Ｓ３４においてパターンニングされた透明導電層２０をマスクとして用い、ｉ型非晶質シリコン層２２ａとｎ型非晶質シリコン層２３ａをエッチングする（Ｓ３６）。続いて、図１７に示されるように、Ｓ１６と同様に、絶縁層２４ｂ、透明導電層２０、ｉ型非晶質シリコン層２２、ｎ型非晶質シリコン層２３及び露出されたｎ型単結晶シリコン基板１８の裏面を覆うように、ｉ型非晶質シリコン層３２ａとｐ型非晶質シリコン層３３ａを形成する（Ｓ３８）。その後、図１８に示されるように、Ｓ１８と同様に、ｉ型非晶質シリコン層３２ａ及びｐ型非晶質シリコン層３３ａのうち、絶縁層２４ｂの上に位置している部分の一部分をエッチングする（Ｓ４０）。 Hereinafter, the same steps as S14, S16, and S18 of the first embodiment are performed except that the insulating layer 24b is present on the transparent conductive layer 20. Specifically, as shown in FIG. 16, similarly to S14, using the transparent conductive layer 20 patterned in S34 as a mask, the i-type amorphous silicon layer 22a and the n-type amorphous silicon layer 23a are used. Is etched (S36). Subsequently, as shown in FIG. 17, as in S16, the insulating layer 24b, the transparent conductive layer 20, the i-type amorphous silicon layer 22, the n-type amorphous silicon layer 23, and the exposed n-type single crystal. An i-type amorphous silicon layer 32a and a p-type amorphous silicon layer 33a are formed so as to cover the back surface of the silicon substrate 18 (S38). Thereafter, as shown in FIG. 18, as in S18, a part of the portion of the i-type amorphous silicon layer 32a and the p-type amorphous silicon layer 33a located on the insulating layer 24b is etched. (S40).
　次に、図１９に示されるように、絶縁層２４ｂをエッチングすることにより、絶縁層２４ｂの一部分をさらに除去する（Ｓ４２）。具体的には、ｉ型非晶質シリコン層３２及びｐ型非晶質シリコン層３３をマスクとして用い、絶縁層２４ｂの露出部分をエッチングにより除去することで絶縁層２４を形成する。 Next, as shown in FIG. 19, a part of the insulating layer 24b is further removed by etching the insulating layer 24b (S42). Specifically, the insulating layer 24 is formed by removing the exposed portion of the insulating layer 24b by etching using the i-type amorphous silicon layer 32 and the p-type amorphous silicon layer 33 as a mask.
　その後、露出した透明導電層２０の表面の洗浄を行う（Ｓ４４）。これにより、Ｓ４２において、仮に絶縁層２４ａの残渣が透明導電層２０に付着している場合であっても好適に取り除くことができる。ここで、露出した透明導電層２０の表面の洗浄は、例えば、ＨＦ水溶液等を用いて行うことができる。 Thereafter, the exposed surface of the transparent conductive layer 20 is cleaned (S44). Thereby, even if it is a case where the residue of the insulating layer 24a has adhered to the transparent conductive layer 20, in S42, it can remove suitably. Here, the cleaning of the exposed surface of the transparent conductive layer 20 can be performed using, for example, an HF aqueous solution.
　そして、透明導電層２６ａ、金属層２７ａを形成する（Ｓ４６）。続いて、図２０に示されるように、Ｓ２２と同様に、透明導電層２６ａ及び金属層２７ａのうち、絶縁層２４の上に位置する一部分を分断することにより、透明導電層２６，３６及び金属層２７，３７を形成する（Ｓ４８）。その後、図２１に示されるように、Ｓ２４と同様に、電解めっきにより、金属層２７の上に第１電極部２８と第２電極部２９を順次形成し、金属層３７の上に第１電極部３８と第２電極部３９を形成する（Ｓ５０）。これにより、ｎ側電極部２５とｐ側電極部３５とが形成がされる。 Then, the transparent conductive layer 26a and the metal layer 27a are formed (S46). Subsequently, as shown in FIG. 20, similarly to S22, the transparent conductive layers 26 and 36 and the metal layer 27a and the metal layer 27a are separated from each other by dividing a part located on the insulating layer 24. Layers 27 and 37 are formed (S48). After that, as shown in FIG. 21, the first electrode portion 28 and the second electrode portion 29 are sequentially formed on the metal layer 27 by electrolytic plating as in S24, and the first electrode is formed on the metal layer 37. The part 38 and the second electrode part 39 are formed (S50). Thereby, the n-side electrode part 25 and the p-side electrode part 35 are formed.
　一般的に、光起電力素子１１において、ｉ型非晶質シリコン層２２、ｎ型非晶質シリコン層２３内では、キャリアの移動度が低い。一方、透明導電層２０内では、キャリアの移動度がｉ型非晶質シリコン層２２、ｎ型非晶質シリコン層２３内に比べて高い。これにより、透明導電層２０内において、ｉ型非晶質シリコン層２２、ｎ型非晶質シリコン層２３でのキャリアの移動度の低さを補うことでｎ側電極部２５から好適にキャリアを取り出すことができる。なお、透明導電層２０を介して、ｉ型非晶質シリコン層２２及びｎ型非晶質シリコン層２３と、ｉ型非晶質シリコン層３２及びｐ型非晶質シリコン層３３とが電気的に接続されることとなるが、一般的に、ｉ型非晶質シリコン層３２、ｐ型非晶質シリコン層３３においてもキャリアの移動度が低いことから、キャリアの移動度が高いｎ側電極部２５からキャリアを好適に取り出すことができるため、上記のように電気的に接続されていることは特に問題とならない。 Generally, in the photovoltaic element 11, the carrier mobility is low in the i-type amorphous silicon layer 22 and the n-type amorphous silicon layer 23. On the other hand, the carrier mobility is higher in the transparent conductive layer 20 than in the i-type amorphous silicon layer 22 and the n-type amorphous silicon layer 23. As a result, in the transparent conductive layer 20, carriers are preferably discharged from the n-side electrode portion 25 by compensating for the low carrier mobility in the i-type amorphous silicon layer 22 and the n-type amorphous silicon layer 23. It can be taken out. Note that the i-type amorphous silicon layer 22 and the n-type amorphous silicon layer 23, and the i-type amorphous silicon layer 32 and the p-type amorphous silicon layer 33 are electrically connected via the transparent conductive layer 20. In general, since the carrier mobility is low in the i-type amorphous silicon layer 32 and the p-type amorphous silicon layer 33, the n-side electrode has a high carrier mobility. Since the carrier can be suitably taken out from the portion 25, the electrical connection as described above is not particularly problematic.
　また、光起電力素子１１の裏面側において、透明導電層２０上に絶縁層２４が形成されている。すなわち、ｎ型非晶質シリコン層２３と絶縁層２４との間には、透明導電層２０が介在している。ここで、一般的に、透明導電層２０は、ｉ型非晶質シリコン層２２及びｎ型非晶質シリコン層２３に比べて耐ＨＦ性が高い。このため、絶縁層２４をエッチングすることで、仮に絶縁層２４の残渣が透明導電層２０上に残った場合であっても、Ｓ４４の工程によって当該残渣は除去される。また、ＨＦ水溶液を用いて透明導電層２０を洗浄した場合であってもＨＦ水溶液による透明導電層２０の損傷は極めて小さい。このように、透明導電層２０の洗浄の際に、絶縁層２４の残渣を除去できる洗浄液を適宜選択することで残渣を無くすことができる。これにより、絶縁層２４の残渣が存在することによって光起電力素子１１のｉ－ｎ積層部２１とｎ側電極部２５との間のシリーズ抵抗が増大してしまうことを防止することができる。したがって、光起電力素子１１の発電特性を向上させることができる。 Further, an insulating layer 24 is formed on the transparent conductive layer 20 on the back side of the photovoltaic element 11. That is, the transparent conductive layer 20 is interposed between the n-type amorphous silicon layer 23 and the insulating layer 24. In general, the transparent conductive layer 20 has higher HF resistance than the i-type amorphous silicon layer 22 and the n-type amorphous silicon layer 23. For this reason, even if the residue of the insulating layer 24 remains on the transparent conductive layer 20 by etching the insulating layer 24, the residue is removed by the process of S44. Further, even when the transparent conductive layer 20 is washed using an HF aqueous solution, the transparent conductive layer 20 is hardly damaged by the HF aqueous solution. As described above, when the transparent conductive layer 20 is cleaned, the residue can be eliminated by appropriately selecting a cleaning solution that can remove the residue of the insulating layer 24. Thereby, it is possible to prevent the series resistance between the in-stacked portion 21 and the n-side electrode portion 25 of the photovoltaic element 11 from increasing due to the presence of the residue of the insulating layer 24. Therefore, the power generation characteristics of the photovoltaic element 11 can be improved.
　さらに、光起電力素子１１の裏面側において、透明導電層２０上に絶縁層２４が形成されているため、ｉ－ｎ積層部２１とｉ－ｐ積層部３１との間おける絶縁性能を向上させることができる。 Further, since the insulating layer 24 is formed on the transparent conductive layer 20 on the back surface side of the photovoltaic element 11, the insulating performance between the in laminated portion 21 and the ip laminated portion 31 is improved. be able to.
（第３実施形態）
　図２２は、本発明の第３実施形態である光起電力素子１１ａの断面図である。光起電力素子１１ａは、反射防止層１２と、ｎ型非晶質シリコン層１４と、ｉ型非晶質シリコン層１６と、ｎ型単結晶シリコン基板１８と、ｉ－ｎ積層部２１と、ｉ－ｐ積層部３１と、透明導電層２０と、絶縁層４０と、ｎ側電極部２５と、ｐ側電極部３５とを含む。ここで、光起電力素子１１ａと、上記第２実施形態である光起電力素子１１の相違点は、絶縁層４０のみであるため、その相違点を中心に説明する。ここで、図２２に示される矢印Ａは、光起電力素子１１ａに対して太陽光等の光が入射される方向を示している。 (Third embodiment)
FIG. 22 is a cross-sectional view of a photovoltaic element 11a according to the third embodiment of the present invention. The photovoltaic element 11a includes an antireflection layer 12, an n-type amorphous silicon layer 14, an i-type amorphous silicon layer 16, an n-type single crystal silicon substrate 18, an i-n stacked portion 21, It includes an ip laminated portion 31, a transparent conductive layer 20, an insulating layer 40, an n-side electrode portion 25 and a p-side electrode portion 35. Here, since the difference between the photovoltaic element 11a and the photovoltaic element 11 according to the second embodiment is only the insulating layer 40, the difference will be mainly described. Here, an arrow A shown in FIG. 22 indicates a direction in which light such as sunlight is incident on the photovoltaic element 11a.
　絶縁層４０は、ｉ－ｎ積層部２１とｉ－ｐ積層部３１とを電気的に絶縁するために形成される。また、絶縁層４０は、透明導電層２０上に形成される保護層としても機能する。そして、絶縁層４０は、図２２に示されるように、透明導電層２０の裏面及び側面が露出することがないように、透明導電層２０の裏面及び側面を覆うように形成されている。「側面」とは、透明導電層２０の厚み方向に沿った面を意味する。また、絶縁層４０は、電気的な絶縁性を有する材料であればよいが、例えば、窒化アルミニウム、窒化ケイ素、酸化ケイ素及び酸窒化ケイ素等を含んで構成することが好適である。 The insulating layer 40 is formed to electrically insulate the i-n laminated portion 21 and the i-p laminated portion 31. The insulating layer 40 also functions as a protective layer formed on the transparent conductive layer 20. And the insulating layer 40 is formed so that the back surface and side surface of the transparent conductive layer 20 may be covered so that the back surface and side surface of the transparent conductive layer 20 may not be exposed, as FIG. 22 shows. The “side surface” means a surface along the thickness direction of the transparent conductive layer 20. The insulating layer 40 may be any material having electrical insulating properties, but preferably includes, for example, aluminum nitride, silicon nitride, silicon oxide, silicon oxynitride, and the like.
　次に、光起電力素子１１ａの製造方法の一例を説明する。図２３は、光起電力素子１１ａの製造方法の手順を示すフローチャートである。なお、光起電力素子１１ａの製造方法は、各工程において示す製造方法に限定されない。各工程において、各層の形成は、例えば、スパッタリング法、プラズマＣＶＤ法、スクリーン印刷法或いはめっき法等を適宜用いることができる。 Next, an example of a method for manufacturing the photovoltaic element 11a will be described. FIG. 23 is a flowchart showing a procedure of a manufacturing method of the photovoltaic element 11a. In addition, the manufacturing method of the photovoltaic element 11a is not limited to the manufacturing method shown in each process. In each step, for example, a sputtering method, a plasma CVD method, a screen printing method, or a plating method can be appropriately used for forming each layer.
　光起電力素子１１ａの製造方法と光起電力素子１１の製造方法は、Ｓ２～Ｓ８の各工程において同じである。そして、光起電力素子１１ａの製造方法と光起電力素子１１の製造方法の相違は、Ｓ８以降の工程であるため、その相違点を中心に説明する。 The manufacturing method of the photovoltaic element 11a and the manufacturing method of the photovoltaic element 11 are the same in the steps S2 to S8. And since the difference between the manufacturing method of the photovoltaic element 11a and the manufacturing method of the photovoltaic element 11 is the process after S8, it demonstrates centering on the difference.
　まず、Ｓ２～Ｓ８の工程を行う。Ｓ８の後は、パターンニング用のマスクを用い、図２４に示されるように、透明導電層２０ａをエッチングする（Ｓ３０ａ）。 First, steps S2 to S8 are performed. After S8, the transparent conductive layer 20a is etched using a patterning mask as shown in FIG. 24 (S30a).
　そして、図２５に示されるように、透明導電層２０上に絶縁層４０ａを形成するとともに、ｎ型非晶質シリコン層１４上に反射防止層１２を形成する（Ｓ３２ａ）。次に、絶縁層４０ａによって透明導電層２０の側面が覆われた部分が残るように予め設計されたパターンニング用のマスクを用い、エッチングすることにより、図２６に示されるように、絶縁層４０ａの一部分を除去する（Ｓ３４ａ）。具体的には、絶縁層４０ａのうち、後工程でｎ型単結晶シリコン基板１８にｉ－ｐ積層部３１を接合させる領域の上に位置する部分を除去して絶縁層４０ｂを形成する。また、Ｓ３４ａの工程において用いられるマスクは、透明導電層２０の幅よりも絶縁層４０ｂの幅が大きくなるように予め設計されているため、図２６に示されるように、絶縁層４０ｂが透明導電層２０の裏面及び側面が露出することがないように、透明導電層２０の裏面及び側面を覆っている。ここで、絶縁層４０ａのエッチングには、例えば、ＨＦ水溶液等の酸性のエッチング液を用いる。 Then, as shown in FIG. 25, the insulating layer 40a is formed on the transparent conductive layer 20, and the antireflection layer 12 is formed on the n-type amorphous silicon layer 14 (S32a). Next, as shown in FIG. 26, the insulating layer 40a is etched by using a patterning mask designed in advance so as to leave a portion where the side surface of the transparent conductive layer 20 is covered with the insulating layer 40a. Is removed (S34a). Specifically, the insulating layer 40b is formed by removing a portion of the insulating layer 40a located on a region where the ip stacked portion 31 is bonded to the n-type single crystal silicon substrate 18 in a later step. In addition, since the mask used in step S34a is designed in advance so that the width of the insulating layer 40b is larger than the width of the transparent conductive layer 20, the insulating layer 40b is transparent conductive as shown in FIG. The back surface and side surface of the transparent conductive layer 20 are covered so that the back surface and side surface of the layer 20 are not exposed. Here, for the etching of the insulating layer 40a, for example, an acidic etching solution such as an HF aqueous solution is used.
　そして、Ｓ３４ａにおいてパターンニングされた絶縁層４０ｂをマスクとして用い、ｉ型非晶質シリコン層２２ａとｎ型非晶質シリコン層２３ａをエッチングする（Ｓ３６ａ）。具体的には、ｉ型非晶質シリコン層２２ａとｎ型非晶質シリコン層２３ａのうち、透明導電層２０及び絶縁層４０ｂによって覆われている部分以外の部分を除去する。これにより、ｎ型単結晶シリコン基板１８の裏面のうち、上方に透明導電層２０及び絶縁層４０ｂが位置していない部分を露出させて、ｉ型非晶質シリコン層２２とｎ型非晶質シリコン層２３を形成する。 Then, using the insulating layer 40b patterned in S34a as a mask, the i-type amorphous silicon layer 22a and the n-type amorphous silicon layer 23a are etched (S36a). Specifically, portions of the i-type amorphous silicon layer 22a and the n-type amorphous silicon layer 23a other than the portions covered by the transparent conductive layer 20 and the insulating layer 40b are removed. As a result, the portion of the back surface of the n-type single crystal silicon substrate 18 where the transparent conductive layer 20 and the insulating layer 40b are not located is exposed, so that the i-type amorphous silicon layer 22 and the n-type amorphous silicon layer are exposed. A silicon layer 23 is formed.
　続いて、光起電力素子１１の製造方法と同様にＳ３８～Ｓ４０の工程を行う。そして、Ｓ４２と同様に、絶縁層４０ｂをエッチングすることにより、絶縁層４０ｂの一部分をさらに除去する（Ｓ４２ａ）。その後、光起電力素子１１の製造方法と同様にＳ４４～Ｓ５０の工程を行う。これにより、図２７に示される光起電力素子１１ａが形成される。 Subsequently, steps S38 to S40 are performed in the same manner as in the method of manufacturing the photovoltaic element 11. Then, as in S42, the insulating layer 40b is etched to further remove a part of the insulating layer 40b (S42a). Thereafter, steps S44 to S50 are performed in the same manner as in the method of manufacturing the photovoltaic element 11. Thereby, the photovoltaic element 11a shown in FIG. 27 is formed.
　ここで、光起電力素子１１ａは、キャリアの移動度の高い透明導電層２０を有する限りにおいて、光起電力素子１０，１１と同様にｎ側電極部２５から好適にキャリアを取り出すことができる。 Here, as long as the photovoltaic element 11a has the transparent conductive layer 20 with high carrier mobility, it is possible to suitably take out carriers from the n-side electrode portion 25 as in the photovoltaic elements 10 and 11.
　また、光起電力素子１１ａは、耐ＨＦ性の高い透明導電層２０を有する限りにおいて、光起電力素子１１と同様にＨＦ水溶液を用いて絶縁層４０の残渣を除去することができる。これにより、光起電力素子１１ａのｉ－ｎ積層部２１とｎ側電極部２５との間のシリーズ抵抗が増大してしまうことを防止することができる。 Further, as long as the photovoltaic element 11a has the transparent conductive layer 20 with high HF resistance, the residue of the insulating layer 40 can be removed using an HF aqueous solution in the same manner as the photovoltaic element 11. Thereby, it is possible to prevent an increase in series resistance between the i-n stacked portion 21 and the n-side electrode portion 25 of the photovoltaic element 11a.
　さらに、光起電力素子１１ａでは、透明導電層２０の裏面だけでなく側面も絶縁層４０によって覆われているため、ｉ－ｎ積層部２１とｉ－ｐ積層部３１との間における絶縁性能をさらに向上させることができる。 Further, in the photovoltaic element 11a, not only the back surface of the transparent conductive layer 20 but also the side surfaces thereof are covered with the insulating layer 40, so that the insulating performance between the in laminated portion 21 and the ip laminated portion 31 is improved. Further improvement can be achieved.
　なお、上記第１～３実施形態において、ｉ－ｎ積層部２１上の一部にｉ－ｐ積層部３１が積層されているが、これに限らない。ｉ－ｐ積層部３１を先に形成し、その後ｉ－ｎ積層部２１を形成することにより、ｉ－ｐ積層部３１上の一部にｉ－ｎ積層部２１が積層されていても良い。 In the first to third embodiments, the ip stack part 31 is stacked on a part of the in stack part 21, but the present invention is not limited to this. The i-n laminated part 21 may be laminated on a part of the ip laminated part 31 by forming the ip laminated part 31 first and then forming the i-n laminated part 21.
　また、ｉ－ｎ積層部２１とｉ－ｐ積層部３１を有するものとして説明したが、ｉ－ｎ積層部２１をｎ型非晶質層のみで構成してもよく、ｉ－ｐ積層部３１をｐ型非晶質層のみで構成してもよい。 Further, although the description has been made on the assumption that the i-n laminated portion 21 and the i-p laminated portion 31 are provided, the i-n laminated portion 21 may be formed of only an n-type amorphous layer. May be composed of only a p-type amorphous layer.
　また、透明導電層２０を有するものとして説明したが、透明導電層２０の代わりに、導電性が高く、耐ＨＦ性の高い金属層、例えば、銅（Ｃｕ）、銀（Ａｇ）等を用いてもよい。 Moreover, although demonstrated as what has the transparent conductive layer 20, instead of the transparent conductive layer 20, using a metal layer with high electroconductivity and high HF resistance, for example, copper (Cu), silver (Ag), etc. Also good.
　１０，１１，１１ａ　光起電力素子、１２　反射防止層、１４　ｎ型非晶質シリコン層、１６　ｉ型非晶質シリコン層、１８　ｎ型単結晶シリコン基板、２０，２０ａ　透明導電層、２１　ｉ－ｎ積層部、２２，２２ａ　ｉ型非晶質シリコン層、２３，２３ａ　ｎ型非晶質シリコン層、２４，２４ａ，２４ｂ　絶縁層、２５　ｎ側電極部、２６，２６ａ，３６　透明導電層、２７，２７ａ，３７　金属層、２８，３８　第１電極部、２９，３９　第２電極部、３１　ｉ－ｐ積層部、３２，３２ａ　ｉ型非晶質シリコン層、３３，３３ａ　ｐ型非晶質シリコン層、３５　ｐ側電極部、４０ａ，４０ｂ　絶縁層。 10, 11, 11a Photovoltaic element, 12 Antireflection layer, 14 n-type amorphous silicon layer, 16 i-type amorphous silicon layer, 18 n-type single crystal silicon substrate, 20, 20a transparent conductive layer, 21 i -N stacked portion, 22, 22a i-type amorphous silicon layer, 23, 23a n-type amorphous silicon layer, 24, 24a, 24b insulating layer, 25 n-side electrode portion, 26, 26a, 36 transparent conductive layer, 27, 27a, 37 metal layer, 28, 38 first electrode part, 29, 39 second electrode part, 31 ip stacked part, 32, 32a i-type amorphous silicon layer, 33, 33a p-type amorphous Silicon layer, 35 p-side electrode part, 40a, 40b insulating layer.

Claims (11)

  1. 　結晶系半導体基板と、
    　第１導電型の層を含み、前記結晶系半導体基板の一方の表面の第１領域において前記表面上に積層された第１非晶質系半導体層部と、
    　第２導電型の層を含み、前記一方の表面の第２領域上及び前記第１非晶質系半導体層部の一部上に跨って積層された第２非晶質系半導体層部と、
    　前記第１非晶質系半導体層部の一部と前記第２非晶質系半導体層部との間に配された導電層と、
    　を備える、光起電力素子。     A crystalline semiconductor substrate;
    A first amorphous semiconductor layer portion including a layer of a first conductivity type and stacked on the surface in a first region of one surface of the crystalline semiconductor substrate;
    A second amorphous semiconductor layer portion including a layer of a second conductivity type and stacked over the second region of the one surface and a part of the first amorphous semiconductor layer portion;
    A conductive layer disposed between a part of the first amorphous semiconductor layer portion and the second amorphous semiconductor layer portion;
    A photovoltaic device comprising:
  2. 　請求項１に記載の光起電力素子において、
    　前記導電層と前記第２非晶質系半導体層部との間に配された絶縁層をさらに備える。     The photovoltaic device according to claim 1, wherein
    The semiconductor device further includes an insulating layer disposed between the conductive layer and the second amorphous semiconductor layer portion.
  3. 　請求項２に記載の光起電力素子において、
    　前記絶縁層は、前記導電層の前記第２領域側の側面を覆うように設けられる。     The photovoltaic device according to claim 2, wherein
    The insulating layer is provided so as to cover a side surface of the conductive layer on the second region side.
  4. 　請求項１から請求項３のいずれか１項に記載の光起電力素子において、
    　前記導電層は、酸化インジウム、酸化亜鉛、酸化錫及び酸化チタンのいずれか１つを含む。     In the photovoltaic device according to any one of claims 1 to 3,
    The conductive layer includes any one of indium oxide, zinc oxide, tin oxide, and titanium oxide.
  5. 　請求項２から請求項４のいずれか１項に記載の光起電力素子において、
    　前記絶縁層は、窒化アルミニウム、窒化ケイ素、酸化ケイ素及び酸窒化ケイ素のいずれか１つを含む。     In the photovoltaic device according to any one of claims 2 to 4,
    The insulating layer includes any one of aluminum nitride, silicon nitride, silicon oxide, and silicon oxynitride.
  6. 　請求項１から請求項５のいずれか１項に記載の光起電力素子において、
    　第１非晶質系半導体層部の表面上に、前記導電層に電気的に接続された電極を有する。     In the photovoltaic device according to any one of claims 1 to 5,
    An electrode electrically connected to the conductive layer is provided on the surface of the first amorphous semiconductor layer portion.
  7. 　請求項１から請求項６のいずれか１項に記載の光起電力素子において、
    　前記結晶系半導体基板は、前記第１導電型を有する。     In the photovoltaic device according to any one of claims 1 to 6,
    The crystalline semiconductor substrate has the first conductivity type.
  8. 　請求項１から請求項７のいずれか１項に記載の光起電力素子において、
    　前記結晶系半導体基板の他方の表面上に積層された、非晶質系半導体層部を備える。     In the photovoltaic device according to any one of claims 1 to 7,
    An amorphous semiconductor layer portion is provided on the other surface of the crystalline semiconductor substrate.
  9. 　請求項１から請求項８のいずれか１項に記載の光起電力素子において、
    　前記非晶質系半導体層部は、前記結晶系半導体基板と同導電型の層を含む。     In the photovoltaic device according to any one of claims 1 to 8,
    The amorphous semiconductor layer portion includes a layer having the same conductivity type as that of the crystalline semiconductor substrate.
  10. 　請求項１から９のいずれか１項に記載の光起電力素子において、
    　前記非晶質系半導体層部の表面上に積層された、反射防止層を備える。     In the photovoltaic device according to any one of claims 1 to 9,
    An antireflection layer is provided on the surface of the amorphous semiconductor layer.
  11. 　請求項１から１０のいずれか１項に記載の光起電力素子において、
    　前記結晶系半導体基板の他方の主面の全面に、光が入射する。     In the photovoltaic device according to any one of claims 1 to 10,
    Light is incident on the entire other main surface of the crystalline semiconductor substrate.
PCT/JP2011/072452 2011-03-25 2011-09-29 Photovoltaic element WO2012132064A1 (en)

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