WO2011021521A1

WO2011021521A1 - Magnetic sensor device and electronic equipment using same

Info

Publication number: WO2011021521A1
Application number: PCT/JP2010/063459
Authority: WO
Inventors: 哲也山崎
Original assignee: ローム株式会社
Priority date: 2009-08-19
Filing date: 2010-08-09
Publication date: 2011-02-24
Also published as: JP2011043331A

Abstract

Provided is a magnetic sensor device (1) comprising the following integrated on a single semiconductor chip: a plurality of electromagnetic transducers (10X, 10Y) separated by a prescribed inter-element distance d; and a first signal-processing circuit (20X-80X, 90) and second signal-processing circuit (20Y-80Y, 90) that generate, respectively, a plurality of output signals (OUTX, OUTY), the logic levels of which change, respectively, in accordance with magnetic field strengths or polarities detected by the plurality of electromagnetic transducers (10X, 10Y).

Description

Magnetic sensor device and electronic apparatus using the same

The present invention uses a magnetoelectric conversion element (such as a Hall element or a magnetoresistive element) to detect a magnetic field where it is installed, and outputs an output signal having a logic level corresponding to its strength or polarity (S pole / N pole). The present invention relates to a magnetic sensor device that generates a magnetic field, and an electronic device using the same.

FIG. 15 is a schematic diagram showing a conventional example of an electronic apparatus using a magnetic sensor device. The electronic apparatus according to the conventional example uses two magnetic sensor devices (Hall ICs) 100X and 100Y each having only one Hall element, and analyzes each output signal OUTX and OUTY with the analysis device 300, whereby a target is obtained. It was set as the structure which calculates the rotational speed V of (circular magnet) 200.

Note that the distance between the

magnetic sensor devices

100X and 100Y (that is, the distance between the Hall elements integrated in the

magnetic sensor devices

100X and 100Y) is d, and output after the logic level of the output signal OUTX changes. When the output time difference until the logic level of the signal OUTY changes is Δt, the rotation speed V of the target 200 can be calculated by the following equation (1).

V = d / Δt (1)

In addition, as an example of the related art related to the above, Patent Document 1 disclosed and proposed by the applicant of the present application can be cited.

JP 2009-28551 A

However, in the electronic apparatus having the above-described conventional configuration, it is necessary to use the two

magnetic sensor devices

100X and 100Y in order to detect the rotational speed V of the target 200. Therefore, the mounting area on the set substrate is increased and the number of handling (set) There has been a problem in that the number of steps related to mounting on the substrate is increased.

In addition, in the electronic apparatus having the above-described conventional configuration, due to variations in mounting positions of the

magnetic sensor devices

100X and 100Y (and, therefore, variations in distance between Hall elements integrated in the

magnetic sensor devices

100X and 100Y), There was also a problem that a detection error of the rotational speed V occurred.

Further, in the electronic apparatus having the above-described conventional configuration, there is a problem that a detection error of the rotation speed V occurs due to variations in detection sensitivity of each of the

magnetic sensor devices

100X and 100Y (manufacturing variations within a wafer surface or between wafer lots). .

In view of the above-mentioned problems found by the inventors of the present application, the present invention realizes reduction of the mounting area on the set substrate and reduction of the number of handling, and further improves the accuracy of target motion analysis based on the output signal. It is an object of the present invention to provide a magnetic sensor device that can be used and an electronic device using the same.

In order to achieve the above object, a magnetic sensor device according to the present invention includes a plurality of magnetoelectric transducers arranged at a predetermined inter-element distance; and the intensity of a magnetic field detected by each of the plurality of magnetoelectric transducers. Or a plurality of signal processing circuits that respectively generate a plurality of output signals whose logic levels change according to the polarity; and are integrated in a single semiconductor chip (first configuration). .

In the magnetic sensor device having the first configuration, each of the plurality of signal processing circuits is a changeover switch circuit that switches the detection state of the magnetoelectric conversion element to one of the first and second switching states; A comparison circuit that performs a predetermined comparison process using a detection voltage of the magnetoelectric conversion element and a predetermined reference voltage, and generates a comparison result signal according to the result; and based on the output signal and the comparison result signal, A logic circuit that generates a logic operation signal for maintaining or inverting the logic of the output signal; a D-type flip-flop that latches the logic operation signal and outputs it as the output signal; and based on the output signal, The switching control of the selector switch circuit is performed in the order from the first switching state to the second switching state, or the first switching state is switched from the second switching state to the first switching state. Better to configure comprising a (second configuration); in the order of state, and a control circuit for determining whether to perform switching control of the switching circuit.

Further, in the magnetic sensor device having the first configuration, the plurality of magnetoelectric transducers may be configured to be Hall elements (third configuration).

Further, in the magnetic sensor device having the third configuration, each of the plurality of signal processing circuits is a changeover switch circuit that switches the detection state of the magnetoelectric conversion element to one of the first and second switching states; A comparison circuit that performs a predetermined comparison process using a detection voltage of the magnetoelectric conversion element and a predetermined reference voltage, and generates a comparison result signal according to the result; and based on the output signal and the comparison result signal, A logic circuit that generates a logic operation signal for maintaining or inverting the logic of the output signal; a D-type flip-flop that latches the logic operation signal and outputs it as the output signal; and based on the output signal, The switching control of the selector switch circuit is performed in the order from the first switching state to the second switching state, or the first switching state is switched from the second switching state to the first switching state. Better to configure comprising a (fourth configuration); in the order of state, and a control circuit for determining whether to perform switching control of the switching circuit.

An electronic apparatus according to the present invention analyzes the movement of the target based on the magnetic sensor device having the first configuration, the target having a magnet, and the plurality of output signals output from the magnetic sensor device. And a analyzing device (fifth configuration).

In the electronic apparatus having the fifth configuration, the magnetic sensor device is arranged such that the plurality of magnetoelectric transducers integrated in the magnetic sensor device are arranged along the movement direction of the target. An apparatus detects an output time difference from a change in the logic level of the first output signal output from the magnetic sensor device to a change in the logic level of the second output signal, and the difference between the output time difference and the predetermined element A configuration (sixth configuration) for calculating the motion speed of the target from the distance may be used.

Further, in the electronic apparatus having the fifth configuration, the magnet includes a plurality of S-pole magnetic domains and N-pole magnetic domains alternately arranged along the movement direction of the target. The magnetic sensor device includes: A configuration in which an alternating magnetic field is applied in accordance with the movement of the target (seventh configuration) is preferable.

The magnetic sensor device having the second configuration further includes an oscillator that outputs a reference clock signal having a predetermined frequency, and the control circuit operates based on the reference clock signal output from the oscillator. (Eighth configuration) is preferable.

In the magnetic sensor device having the eighth configuration, the control circuit includes a start pulse signal generation circuit that generates a start pulse signal based on the reference clock signal, and the reference clock signal and the start pulse signal. A shift register that sequentially receives the start pulse signal based on the reference clock signal, and outputs a first switching signal, a second switching signal, and a third switching signal based on the output of the shift register and the output signal. A switching signal generation circuit to be generated (9th configuration) is preferable.

Also, in the magnetic sensor device having the ninth configuration, the output of the shift register may be configured to have a first timing signal and a second timing signal (tenth configuration).

Further, in the magnetic sensor device having the second configuration, each of the plurality of signal processing circuits includes a first operational amplifier having a non-inverting input terminal connected to a first output terminal of the changeover switch circuit, and a non-inverting terminal. A second operational amplifier having an input terminal connected to a second output terminal of the changeover switch circuit; a first feedback resistor connected between an inverting input terminal and an output terminal of the first operational amplifier; A second feedback resistor connected between the inverting input terminal of the operational amplifier and a predetermined reference voltage application terminal; and a third feedback resistor connected between the inverting input terminal and the output terminal of the second operational amplifier. And a fourth feedback resistor connected between the inverting input terminal of the second operational amplifier and a predetermined reference voltage application terminal (an eleventh structure).

Further, in the magnetic sensor device having the second configuration, each of the plurality of signal processing circuits includes a first operational amplifier having a non-inverting input terminal connected to a first output terminal of the changeover switch circuit, and a non-inverting terminal. A second operational amplifier having an input terminal connected to a second output terminal of the changeover switch circuit; a first feedback resistor connected between an inverting input terminal and an output terminal of the first operational amplifier; A second feedback resistor connected between the inverting input terminal and the output terminal of the operational amplifier, and a third feedback resistor connected between the inverting input terminal of the first operational amplifier and the inverting input terminal of the second operational amplifier. A configuration including a feedback resistor (a twelfth configuration) is preferable.

In the magnetic sensor device having the second configuration, the reference voltage generating circuit that generates the reference voltage includes a voltage dividing resistor that generates the reference voltage by dividing a power supply voltage, and the voltage dividing resistor. A first transistor connected to the power supply voltage side and turned on / off in response to a predetermined control signal; and a first transistor connected to the ground side of the voltage dividing resistor and turned on / off in response to the control signal. A configuration including two transistors (a thirteenth configuration) is preferable.

An electronic apparatus according to the present invention analyzes the movement of the target based on the magnetic sensor device having the second configuration described above, a target having a magnet, and the plurality of output signals output from the magnetic sensor device. And a analyzing device (fourteenth configuration).

An electronic apparatus according to the present invention analyzes the movement of the target based on the magnetic sensor device having the third configuration, a target having a magnet, and the plurality of output signals output from the magnetic sensor device. And a analyzing device (a fifteenth configuration).

An electronic apparatus according to the present invention analyzes the movement of the target based on the magnetic sensor device having the fourth configuration, a target having a magnet, and the plurality of output signals output from the magnetic sensor device. And an analyzing device (a sixteenth configuration).

Further, in the magnetic sensor device having the sixth configuration, the magnet includes a plurality of S-pole magnetic domains and N-pole magnetic domains alternately arranged along the movement direction of the target. Is preferably configured to apply an alternating magnetic field in accordance with the movement of the target (a seventeenth configuration).

In the magnetic sensor device having the fourth configuration, each of the plurality of signal processing circuits includes a first operational amplifier having a non-inverting input terminal connected to a first output terminal of the changeover switch circuit, and a non-inverting A second operational amplifier having an input terminal connected to a second output terminal of the changeover switch circuit; a first feedback resistor connected between an inverting input terminal and an output terminal of the first operational amplifier; A second feedback resistor connected between the inverting input terminal of the operational amplifier and a predetermined reference voltage application terminal; and a third feedback resistor connected between the inverting input terminal and the output terminal of the second operational amplifier. And a fourth feedback resistor connected between an inverting input terminal of the second operational amplifier and a predetermined reference voltage application terminal (an eighteenth structure).

In the magnetic sensor device having the fourth configuration, each of the plurality of signal processing circuits includes a first operational amplifier having a non-inverting input terminal connected to a first output terminal of the changeover switch circuit, and a non-inverting A second operational amplifier having an input terminal connected to a second output terminal of the changeover switch circuit; a first feedback resistor connected between an inverting input terminal and an output terminal of the first operational amplifier; A second feedback resistor connected between the inverting input terminal and the output terminal of the operational amplifier, and a third feedback resistor connected between the inverting input terminal of the first operational amplifier and the inverting input terminal of the second operational amplifier. A configuration including a feedback resistor (a nineteenth configuration) is preferable.

In the magnetic sensor device having the fourth configuration, the reference voltage generation circuit that generates the reference voltage includes a voltage dividing resistor that generates the reference voltage by dividing a power supply voltage, and the voltage dividing resistor. A first transistor connected to the power supply voltage side and turned on / off in response to a predetermined control signal; and a first transistor connected to the ground side of the voltage dividing resistor and turned on / off in response to the control signal. A configuration including the two transistors (a twentieth configuration) is preferable.

If the magnetic sensor circuit according to the present invention and an electronic device using the magnetic sensor circuit are realized, the mounting area on the set substrate can be reduced and the number of handling can be reduced, and the motion analysis accuracy of the target based on the output signal can be improved. Can be improved.

The schematic diagram which shows schematic structure of the magnetic sensor apparatus which concerns on this invention The block diagram which shows schematic structure of the internal circuit integrated in the magnetic sensor apparatus 1 The figure which shows the logic level change of the output signal with respect to the applied magnetic field (magnetic flux density) The schematic diagram which shows the 1st structural example of the electronic device using the magnetic sensor apparatus 1. FIG. The schematic diagram which shows the 2nd structural example of the electronic device using the magnetic sensor apparatus 1. FIG. Timing chart showing how the applied magnetic field and output signal change as the target 2 moves The figure which showed the specific structure of the internal circuit integrated in the magnetic sensor apparatus 1 The figure which shows the 1st structural example of the amplifier circuit 30X. The figure which shows the 2nd structural example of the amplifier circuit 30X. The figure which shows the example of 1 structure of the reference voltage generation circuit 100 The figure which shows the example of 1 structure of the logic circuit 61 Logic value table showing input / output logic of logic circuit 61 The figure which shows the example of 1 structure of the control circuit 80X Timing chart for explaining the operation of the magnetic sensor device 1 Flow chart for explaining the operation of the magnetic sensor device 1 Schematic diagram showing an example of a conventional electronic device using a magnetic sensor device

FIG. 1 is a schematic diagram showing a schematic configuration of a magnetic sensor device according to the present invention. The top view of FIG. 1 shows a plan view of the magnetic sensor device 1 seen through from the upper surface side, and the bottom row shows a longitudinal sectional view of the magnetic sensor device 1 cut along the α-α ′ line. Yes. As shown in the figure, the magnetic sensor device 1 according to the present invention is a semiconductor device (so-called Hall IC) having two

Hall elements

10X and 10Y arranged with a predetermined inter-element distance d. . The inter-element distance d may be appropriately designed so as to satisfy the specifications required for each application (for example, speed detection accuracy).

FIG. 2 is a block diagram showing a schematic configuration of an internal circuit integrated in the magnetic sensor device 1. As shown in the figure, in addition to the

hall elements

10X and 10Y, the magnetic sensor device 1 according to the present invention includes

changeover switch circuits

20X and 20Y,

amplifier circuits

30X and 30Y,

sample hold circuits

40X and 40Y, and a comparison circuit. 50X and 50Y,

latch circuits

60X and 60Y,

output circuits

70X and 70Y,

control circuits

80X and 80Y, and an oscillation circuit 90 are integrated in a single semiconductor chip.

Note that the changeover switch circuit 20X, the amplifier circuit 30X, the sample hold circuit 40X, the comparison circuit 50X, the latch circuit 60X, the output circuit 70X, the control circuit 80X, and the oscillation circuit 90 have the magnetic field intensity detected by the Hall element 10X. A first signal processing circuit that generates an output signal OUTX whose logic level changes according to the polarity is formed.

In addition, the changeover switch circuit 20Y, the amplifier circuit 30Y, the sample hold circuit 40Y, the comparison circuit 50Y, the latch circuit 60Y, the output circuit 70Y, the control circuit 80Y, and the oscillation circuit 90 are configured so that the intensity of the magnetic field detected by the Hall element 10Y or A second signal processing circuit for generating an output signal OUTY whose logic level changes according to the polarity is formed.

The oscillation circuit 90 is shared between the first signal processing circuit and the second signal processing circuit. With such a configuration, the circuit scale and power consumption can be reduced, and the generation timings of the output signals OUTX and OUTY can be synchronized with each other.

FIG. 3 is a diagram showing a change in logic level of the output signals OUTX and OUTY with respect to the applied magnetic field (magnetic flux density). As shown in the figure, when the magnetic field applied to the

Hall elements

10X and 10Y exceeds the detection magnetic field level Bop of the south pole, the output signals OUTX and OUTY are at a low level. On the other hand, when the magnetic field applied to the

Hall elements

10X and 10Y exceeds the detection magnetic field level Brp of the N pole, the output signals OUTX and OUTY are at a high level. In this way, the output signals OUTX and OUTY have a predetermined hysteresis width with respect to the applied magnetic field, and their logic levels change.

The magnetic sensor device 1 having the above-described configuration includes a magnetic sensor such as an open / close detection sensor of a foldable mobile phone terminal or a slide mobile phone terminal, a rotational position detection sensor or a rotational speed detection sensor of a motor, or a rotation operation detection sensor of a dial. As a sensor for detecting the state (magnetic field strength) and magnetic field polarity, it can be used in a wide range of applications.

The specific configuration of the internal circuit integrated in the magnetic sensor device 1 and the generation operation of the output signals OUTX and OUTY will be described in detail later.

FIG. 4A and FIG. 4B are schematic diagrams each showing an example of the configuration of an electronic device using the magnetic sensor device 1, and each of the electronic devices shown in each figure is a magnetic sensor device 1 according to the present invention. And a target 2A to 2B having magnets, and an analysis device 3 for analyzing the motion of the targets 2A to 2B based on two systems of output signals OUTX and OUTY output from the magnetic sensor device 1.

The target 2A is rotationally driven at a rotational speed V, and the target 2B is slide-driven at a slide speed V. In the following description, both are collectively referred to as target 2.

The magnet provided on the target 2 has a plurality of magnetic domains of S poles and N poles alternately arranged along the moving direction (rotating direction or sliding direction) of the target 2. Therefore, an alternating magnetic field in which the N pole and the S pole are alternately switched with the movement of the target 2 (rotation driving or sliding driving) is applied to the magnetic sensor device 1.

The magnetic sensor device 1 is arranged on a set substrate so as to face the target 2 so that two

Hall elements

10X and 10Y integrated with a predetermined inter-element distance d are aligned along the movement direction of the target 2. Arranged appropriately. 4A and 4B, the magnetic sensor device 1 is arranged so that the Hall element 10X is arranged on the upstream side and the Hall element 10Y is arranged on the downstream side with respect to the movement direction of the target 2.

FIG. 5 is a timing chart showing how the applied magnetic field and the output signal change as the target 2 moves. The upper solid line indicates the time change of the applied magnetic field for the Hall element 10X, and the broken line indicates the time change of the applied magnetic field for the Hall element 10Y. Also, the lower stage shows the time change of the output signals OUTX and OUTY. As shown in the figure, the Hall element 10X arranged on the upstream side with respect to the movement direction of the target 2 is applied from the target 2 before the Hall element 10Y arranged on the downstream side. A change in polarity of the alternating magnetic field is detected. Therefore, an output time difference Δt corresponding to the movement speed of the target 2 is generated from the change of the logic level of the output signal OUTX to the change of the logic level of the output signal OUTY.

The analysis device 3 detects an output time difference Δt from when the logic level of the output signal OUTX output from the magnetic sensor device 1 changes until the logic level of the output signal OUTY changes, and this output time difference Δt and a predetermined element Based on the distance d, the motion speed V (rotation speed or slide speed) of the target 2 is calculated based on the above equation (1).

As described above, in the case of an electronic apparatus using the magnetic sensor device 1 according to the present invention, it is sufficient to use only one magnetic sensor device 1 in order to detect the motion speed V of the target 2. The mounting area can be reduced and the number of handlings can be reduced, which can contribute to the cost reduction of the product. It is also possible to increase the degree of freedom of set design.

In the magnetic sensor device 1 according to the present invention, since the

Hall elements

10X and 10Y are integrated in the same chip, the error of the inter-element distance d is an error caused by the exposure accuracy of the mask (reticle). In addition, the detection sensitivity variation (relative error) for each of the

Hall elements

10X and 10Y hardly needs to be considered. Therefore, if the electronic device uses the magnetic sensor device 1 according to the present invention, it is possible to detect the motion speed V of the target 2 with higher accuracy than in the conventional configuration using a plurality of magnetic sensor devices. It becomes.

In addition, as the magnetic field detection speed (response speed) of the magnetic sensor device 1 is increased, the motion speed V of the target 2 can be detected widely from a low speed range to a high speed range.

Next, a specific configuration of the internal circuit integrated in the magnetic sensor device 1 according to the present invention and an operation for generating the output signals OUTX and OUTY will be described in detail. However, only the first signal processing circuit (20X to 80X, 90) that generates the output signal OUTX from the Hall element 10X and its detection signal will be described below, and the output signal is based on the Hall element 10Y and its detection signal. The second signal processing circuit (20Y to 80Y, 90) that generates OUTY will not be described repeatedly.

FIG. 6 is a diagram showing a specific configuration of an internal circuit integrated in the magnetic sensor device 1, and shows a Hall element 10X and a first signal processing circuit (20X) that generates an output signal OUTX from its detection signal. ˜80X, 90), and only the reference voltage generation circuit 100 is depicted. However, in the magnetic sensor device 1 of this configuration example, the output circuit 70X is omitted, unlike the example of FIG.

In FIG. 6, the Hall element 10X is formed in a plate shape having a geometrically equivalent shape with respect to the four terminals A, C, B, and D. When the power supply voltage VDD is applied to the first terminal pair AC of the Hall element 10X, the Hall voltage generated in the second terminal pair BD and the power supply voltage VDD are applied between the second terminal pair BD. When the Hall voltage generated at the first terminal pair CA is compared, the effective signal component corresponding to the strength of the magnetic field applied to the Hall element 10X is in phase, and the element offset component (element offset voltage) Is out of phase.

The changeover switch circuit 20X is a means for switching between a method for applying the power supply voltage VDD to the Hall element 10X and a method for extracting the Hall voltage from the Hall element 10X.

More specifically, the changeover switch circuit 20X is turned on according to the logic of the

switches

21, 23, 25, and 27 that are on / off controlled according to the logic of the first switching signal CTL1 and the second switching signal CTL2. The

switches

22, 24, 26, and 28 are controlled. In the magnetic sensor device 1 of the present embodiment, the

switches

21, 23, 25, and 27 are turned on when the first switching signal CTL1 is at a high level, and are turned off when the first switching signal CTL1 is at a low level. The

switches

22, 24, 25, and 27 are turned on when the second switching signal CTL2 is at a high level, and turned off when the second switching signal CTL2 is at a low level. However, the above signal logic is merely an example, and may be implemented with the reverse logic.

The first and second switching signals CTL1 and CTL2 are the first half of a period during which the power-on signal POW is at a high level (ie, corresponding to the sensing period of the magnetic sensor device 1) so that their logics do not match each other. The first switching signal CTL1 is set to the high level in the second half (or the second half), and the second switching signal CTL2 is set to the high level in the second half (or the first half). The power-on signal POW is intermittently set at a high level for a predetermined period, for example, at regular intervals. However, the signal logic described above is merely an example, and the reverse logic may be used.

In the first switching state in which the first switching signal CTL1 is set to the high level and the second switching signal CTL2 is set to the low level, the power supply voltage VDD is applied to the terminal A, and the terminal C is connected to the ground. A Hall voltage corresponding to the strength of the magnetic field is generated between B and the terminal D. At this time, the voltage generated between the terminal B and the terminal D varies depending on the polarity of the applied magnetic field (direction of the magnetic field). Here, the voltage Vb at the terminal B is low, and the voltage Vd at the terminal D is Assume a high case. Note that the voltage represents a potential with respect to the ground unless otherwise specified.

On the other hand, in the second switching state in which the first switching signal CTL1 is set to the low level and the second switching signal CTL2 is set to the high level, the power supply voltage VDD is applied to the terminal B and the terminal D is connected to the ground. A Hall voltage corresponding to the strength of the magnetic field is generated between the terminal C and the terminal A. Here, as a result of the state transition from the first switching state to the second switching state being performed at a high speed, a magnetic field having the same polarity (direction) as that in the first switching state is applied even in the second switching state. Assuming that the voltage generated between the terminal C and the terminal A is such that the voltage Vc at the terminal C is low and the voltage Va at the terminal A is high.

Therefore, the voltage at the first output terminal i of the changeover switch circuit 20X is the voltage Vb in the first switching state and the voltage Va in the second switching state. On the other hand, the voltage of the second output terminal ii of the changeover switch circuit 20X is the voltage Vd in the first switching state and the voltage Vc in the second switching state.

The amplifier circuit 30X includes a first amplifier circuit 31 connected to the first output terminal i of the changeover switch circuit 20X, and a second amplifier circuit 32 connected to the second output terminal ii of the changeover switch circuit 20X. Become.

The first amplifier circuit 31 is means for amplifying an input voltage (voltage Vb to voltage Va) from the first output terminal i with a predetermined amplification degree α and outputting the amplified voltage from the first amplification output terminal iii as the first amplified voltage AOUT1. is there. Since the first amplifier circuit 31 has an input offset voltage Voffa1, the first amplifier circuit 31 adds the input offset voltage Voffa1 to the input voltage (voltage Vb to voltage Va). Then, a predetermined amplification process is performed.

The second amplifier circuit 32 is means for amplifying the input voltage (voltage Vd to voltage Vc) from the second output terminal ii with a predetermined amplification degree α and outputting the amplified voltage as the second amplified voltage AOUT2 from the second amplified output terminal iv. is there. Since the input offset voltage Voffa2 also exists in the second amplifier circuit 32, the second amplifier circuit 32 adds the input offset voltage Voffa2 to the input voltage (voltage Vd to voltage Vc). Then, a predetermined amplification process is performed.

The power supply voltage VDD is applied to the first and

second amplifier circuits

31 and 32 constituting the amplifier circuit 30X via the switch circuit 34 and the switch circuit 35, respectively. Note that both the switch circuit 34 and the switch circuit 35 are on / off controlled according to the logic of the power-on signal POW. In this embodiment, the switch circuit 34 and the switch circuit 35 are turned on when the power-on signal POW is at a high level. It is turned off when it is at low level.

Therefore, the amplifying circuit 30X is driven only for a predetermined period, for example, every fixed period intermittently in response to the high level transition of the power-on signal POW. Further, when the first and

second amplifier circuits

31 and 32 are of the current drive type, a current source circuit with a switch function may be used as the switch circuit 34 and the switch circuit 35.

The sample and hold circuit 40X includes a first capacitor 41, a second capacitor 42, a first switch circuit 43, and a second switch circuit 44.

The first capacitor 41 is connected between the first amplification output terminal iii of the amplification circuit 30X and the first comparison input terminal v (non-inverting input terminal (+) of the comparator 51) of the comparison circuit 50X. The second capacitor 42 is connected between the second amplification output terminal iv of the amplification circuit 30X and the second comparison input terminal vi (the inverting input terminal (−) of the comparator 51) of the comparison circuit 50X.

A first reference voltage Vref1 is supplied to the first comparison input terminal v of the comparison circuit 50X via the first switch circuit 43, and the second comparison input terminal vi is supplied to the first comparison input terminal v via the second switch circuit 44. 2 Reference voltage Vref2 is supplied. Both the first and

second switch circuits

43 and 44 are on / off controlled in accordance with the logic of the third switching signal CTL3. In the present embodiment, when the third switching signal CTL3 is at a high level. On, and off when low. However, the above signal logic is merely an example, and may be implemented with the reverse logic.

The comparison circuit 50X compares the first comparison voltage INC1 input to the first comparison input terminal v with the second comparison voltage INC2 input to the second comparison input terminal vi, and the first comparison voltage INC1 is the second comparison voltage INC1. When the comparison voltage INC2 is higher, the logic of the comparison result signal COUT is set to the high level, and when the first comparison voltage INC1 is lower than the second comparison voltage INC2, the logic of the comparison result signal COUT is set to the low level. A comparator 51 and

switch circuits

52 and 53. The comparison circuit 50X is configured to have an extremely high input impedance. For example, the input stage of the comparator 51 is composed of a MOS transistor circuit. As described above, since the magnetic sensor device 1 of the present embodiment includes the comparison circuit 50X, the magnetic sensor device 1 is less susceptible to the ripple of the power supply voltage VDD and noise, and a stable sensing operation is possible.

The power supply voltage VDD is applied to the comparator 51 through the switch circuit 52. The switch circuit 52 is on / off controlled according to the logic of the power-on signal POW. In the present embodiment, the switch circuit 52 is turned on when the power-on signal POW is at a high level, and is switched on at a low level. Off.

Therefore, the comparator 51 is driven intermittently, for example, for a predetermined period every fixed period in accordance with the high level transition of the power-on signal POW (and hence the low-level transition of the inverted power-on signal (/ POW)). The When the comparator 51 is of a current drive type, a current source circuit with a switch function may be used as the switch circuit 52.

The output terminal of the comparison circuit 50X (the output terminal of the comparator 51) is connected to the ground terminal via the switch circuit 53. Note that the switch circuit 53 is ON / OFF controlled in accordance with the logic of the inverted power supply ON signal (/ POW), and in this embodiment, when the inverted power supply ON signal (/ POW) is at a high level. Turned on and turned off when low level. As a result, when the power supply to the comparator 51 is interrupted, the comparison result signal COUT is forcibly set to the low level, so that the logical operation signal LOUT (and thus the signal generated by the latch circuit 60X at the subsequent stage is extended). It is possible to prevent an unintended logic transition from occurring in the output signal OUT).

The latch circuit 60X includes a logic circuit 61 and a D-type flip-flop 62.

The logic circuit 61 is means for generating a logical operation signal LOUT based on the comparison result signal COUT and the output signal OUT. The specific configuration and operation of the logic circuit 61 will be described in detail later.

The D-type flip-flop 62 is means for latching the logical operation signal LOUT obtained by the logic circuit 61 at the edge timing of the clock signal CLK_SH and outputting it as an output signal OUT (and thus the first output signal OUTX). is there.

When the output circuit 70X is connected to the subsequent stage of the latch circuit 60X, an inverter stage or buffer is used as the output circuit 70X so that the strength or polarity of the magnetic field and the logic level of the output signal OUTX have a desired correlation. A step or the like may be used as appropriate (see FIG. 2).

The control circuit 80X generates a power-on signal POW, an inverted power-on signal (/ POW), a clock signal CLK_SH, and a third switching signal CTL3 based on the reference clock signal OSC, and further receives an output signal OUT. In response to this, the first switching signal CTL1 and the second switching signal CTL2 are generated. The specific configuration and operation of the control circuit 80X will be described in detail later.

The oscillation circuit 90 is means for generating a reference clock signal OSC having a predetermined frequency and supplying it to the control circuit 80X.

The reference voltage generation circuit 100 is means for generating a first reference voltage Vref1 and a second reference voltage Vref2 that is higher than the first reference voltage Vref1 by a predetermined value VREF. The specific configuration of the reference voltage generation circuit 100 will be described in detail later.

FIG. 7 is a diagram illustrating a first configuration example of the amplifier circuit 30X. The amplifier circuit 30X of this configuration example includes a first amplifier circuit 31A and a second amplifier circuit 32A.

In the first amplifier circuit 31A, the non-inverting input terminal (+) of the operational amplifier 31-1 is connected to the first output terminal i of the changeover switch circuit 20X. A feedback resistor 31-2 is connected between the inverting input terminal (−) of the operational amplifier 31-1 and the first amplification output terminal iii. A feedback resistor 31-3 is connected between the inverting input terminal (−) of the operational amplifier 31-1 and the application terminal of the reference voltage Vref0.

The first amplifying circuit 31A having the above configuration amplifies the voltage (voltage Vb to voltage Va) input from the first output terminal i of the changeover switch circuit 20X with a predetermined amplification degree α as a first amplified voltage AOUT1. Output from the first amplification output terminal iii.

On the other hand, in the second amplifier circuit 32A, the non-inverting input terminal (+) of the operational amplifier 32-1 is connected to the second output terminal ii of the changeover switch circuit 20X. A feedback resistor 32-2 is connected between the inverting input terminal (−) of the operational amplifier 32-1 and the second amplification output terminal iv. A feedback resistor 32-3 is connected between the inverting input terminal (−) of the operational amplifier 32-1 and the application terminal of the reference voltage Vref0.

The second amplifying circuit 32A having the above configuration amplifies the voltage (voltage Vd to voltage Vc) input from the second output terminal ii of the changeover switch circuit 20X with a predetermined amplification degree α to obtain a second amplified voltage AOUT2. Output from the second amplification output terminal iv.

In the amplifier circuit 30X of the first configuration example, when the resistance values of the feedback resistors 31-2 and 32-2 are R2, and the resistance values of the feedback resistors 31-3 and 32-3 are R1, the amplification factor α is about R2 / R1. However, R2 >> R1.

FIG. 8 is a diagram illustrating a second configuration example of the amplifier circuit 30X. The amplifier circuit 30X of this configuration example includes a first amplifier circuit 31B and a second amplifier circuit 32B.

In the first amplifier circuit 31B, the non-inverting input terminal (+) of the operational amplifier 31-1 is connected to the first output terminal i of the changeover switch circuit 20X. A first feedback resistor 31-2 is connected between the inverting input terminal (−) of the operational amplifier 31-1 and the first amplification output terminal iii.

On the other hand, in the second amplifier circuit 32B, the non-inverting input terminal (+) of the operational amplifier 32-1 is connected to the second output terminal ii of the changeover switch circuit 20X. A second feedback resistor 32-2 is connected between the inverting input terminal (−) of the operational amplifier 32-1 and the second amplification output terminal iv.

The third feedback resistor 33 is connected between the inverting input terminal (−) of the first operational amplifier 31-1 and the inverting input terminal (−) of the second operational amplifier 32-1.

As described above, the amplifier circuit 30X of the present configuration example is an amplifier circuit in which the first amplifier circuit 31B and the second amplifier circuit 32B share the third feedback resistor 33, that is, an amplifier circuit of a balanced input-balanced output format. . In the amplifier circuit 30X of the second configuration example, the number of feedback resistors can be reduced compared to the amplifier circuit 30X of the first configuration example, and the reference voltages of the first and

second amplifier circuits

31B and 32B are Since it is automatically set in the circuit, it is not necessary to set the reference voltage.

Further, in the amplifier circuit 30X of this configuration example, a voltage amplification gain can be greatly increased by adopting a balanced input-balanced output type using a specific configuration. That is, when the resistance value of the first and second feedback resistors 31-2 and 32-2 is R2, and the resistance value of the third feedback resistor 33 is R1, the amplification degree α is about 2 × R2 / R1. However, R2 >> R1. As described above, since the amplification degree α is doubled, the circuit design can be easily performed, and a Hall element having low sensitivity can be easily used. Although not explicitly shown in FIGS. 7 and 8, the power supply voltage VDD necessary for driving the

first amplifier circuits

31A and 31B may be supplied via the switch circuit 34 as in FIG. Further, the power supply voltage VDD necessary for driving the

second amplifier circuits

32A and 32B may be supplied via the switch circuit 35 as in FIG.

Next, the configuration and operation of the reference voltage generation circuit 100 will be described with reference to FIG.

FIG. 9 is a diagram illustrating a configuration example of the reference voltage generation circuit 100.

As shown in FIG. 9, the reference voltage generation circuit 100 generates the first reference voltage Vref1 and the second reference voltage Vref2 by dividing the power supply voltage VDD by the voltage dividing resistors 100-1 to 100-3. These reference voltages are such that the P-type MOS transistor 100-4 connected to the power supply voltage VDD side of the voltage dividing resistors 100-1 to 100-3 and the N-type MOS transistor 100-5 connected to the ground side are turned on. It is generated when it is said. The MOS transistors 100-4 and 100-5 are on / off controlled in accordance with the logic of the third switching signal CTL3 through the inverters 100-6 to 100-7. Instead of the third switching signal CTL3, on / off control of the MOS transistors 100-4 and 100-5 may be performed according to the logic of the power-on signal POW.

Next, the configuration and operation of the logic circuit 61 included in the latch circuit 60X will be described with reference to FIGS.

FIG. 10 is a diagram illustrating a configuration example of the logic circuit 61. FIG. 11 is a logic value table showing the input / output logic of the logic circuit 61.

As shown in FIG. 10, the logic circuit 61 includes inverters 61-1 and 61-2, AND operation units 61-3 and 61-4, and an OR operation unit 61-5.

The input terminal of the inverter 61-1 is connected to the application terminal of the output signal OUT. The input end of the inverter 61-2 is connected to the application end of the comparison result signal COUT. One input terminal of the AND operator 61-3 is connected to the output terminal of the inverter 61-1. The other input terminal of the AND operator 61-3 is connected to the application terminal of the comparison result signal COUT. One input terminal of the AND operator 61-4 is connected to the application terminal of the output signal OUT. The other input terminal of the AND operator 61-4 is connected to the output terminal of the inverter 61-2. One input terminal of the logical sum calculator 61-5 is connected to the output terminal of the logical product calculator 61-3. The other input terminal of the logical sum calculator 61-5 is connected to the output terminal of the logical product calculator 61-4. The output terminal of the logical sum calculator 61-5 is connected to the data input terminal (not shown in FIG. 10) of the D-type flip-flop 62 as a lead-out terminal for the logical operation signal LOUT.

In the logic circuit 61 having the above configuration, when both the output signal OUT and the comparison result signal COUT are at a low level, the logic operation signal LOUT is at a low level. When the output signal OUT is at a low level and the comparison result signal COUT is at a high level, the logic operation signal LOUT is set to a high level. When the output signal OUT is at a high level and the comparison result signal COUT is at a low level, the logical operation signal LOUT is set to a high level. When the output signal OUT and the comparison result signal are both at the high level, the logical operation signal LOUT is at the low level.

Next, the configuration and operation of the control circuit 80X will be described in detail with reference to FIGS.

FIG. 12 is a diagram illustrating a configuration example of the control circuit 80X. FIG. 13 is a timing chart for explaining the operation of the magnetic sensor device 1 according to the present invention.

As shown in FIG. 12, the control circuit 80X of this configuration example includes a start pulse signal generation circuit 81, a shift register 82, an OR calculator 83, inverters 84 and 85, and a switching signal generation circuit 86. Have.

The start pulse generation circuit 81 is means for generating one pulse every time the number of pulses of the reference clock signal OSC reaches a predetermined value (for example, 32) and outputting this as a start pulse signal SIG (see FIG. 13). .

The shift register 82 receives the input of the reference clock signal OSC and the start pulse signal SIG, and sequentially takes in the start pulse signal SIG while shifting the start pulse signal SIG for each pulse of the reference clock signal OSC. These register data are respectively output as a first timing signal S1 and a second timing signal S2. That is, as shown in FIG. 13, when a pulse is generated in the start pulse signal SIG, first, a pulse is generated in the first timing signal S1, and then a pulse is generated in the second timing signal S2, in synchronization with the reference clock signal OSC. .

The logical sum calculator 83 is means for performing a logical sum operation of the first timing signal S1 and the second timing signal S2 to generate a power-on signal POW (see FIG. 13).

The inverter 84 is a means for generating an inverted power-on signal (/ POW) (not shown in FIG. 13) by inverting the logic of the power-on signal POW.

The inverter 85 is means for generating the clock signal CLK_SH (see FIG. 13) by inverting the logic of the second timing signal S2.

The switching signal generation circuit 86 receives the first timing signal S1 and the second timing signal S2 and the output signal OUT, and generates the first switching signal CTL1, the second switching signal CTL2, and the third switching signal CTL3. And includes AND operation units 86-1 to 86-4, OR operation units 96-5 and 86-6, and an inverter 86-7.

One input terminal of the AND operator 86-1 is connected to the application terminal of the first timing signal S1. The other input terminal of the AND operator 86-1 is connected to the output terminal of the inverter 86-7. One input terminal of the AND operator 86-2 is connected to the application terminal of the second timing signal S2. The other input terminal of the AND operator 86-2 is connected to the application terminal of the output signal OUT. One input terminal of the AND operator 86-3 is connected to the application terminal of the second timing signal S2. The other input terminal of the AND operator 86-3 is connected to the output terminal of the inverter 86-7. One input terminal of the AND operator 86-4 is connected to the application terminal of the first timing signal S1. The other input terminal of the AND operator 86-4 is connected to the application terminal of the output signal OUT. One input terminal of the logical sum calculator 86-5 is connected to the output terminal of the logical product calculator 86-1. The other input terminal of the logical sum calculator 86-5 is connected to the output terminal of the logical product calculator 86-2. The output terminal of the logical sum calculator 86-5 is connected to the changeover switch circuit 20X (not shown in FIG. 12) as a lead-out terminal for the first switching signal CTL1. One input terminal of the logical sum calculator 86-6 is connected to the output terminal of the logical product calculator 86-3. The other input terminal of the logical sum calculator 86-6 is connected to the output terminal of the logical product calculator 86-4. The output terminal of the logical sum calculator 86-6 is connected to the changeover switch circuit 20X (not shown in FIG. 12) as a lead-out terminal for the second switching signal CTL2. The input end of the inverter 86-7 is connected to the application end of the output signal OUT.

The switching signal generation circuit 86 configured as described above outputs the logical sum operation signal obtained by the logical sum operation unit 86-5 as the first switching signal CTL1, and the logical sum operation signal obtained by the logical sum operation unit 86-6. Is output as the second switching signal CTL2.

Therefore, as shown in (1) and (4) of FIG. 13, when the output signal OUT is at a high level (that is, after the detection of the N pole signal, the S pole signal should be detected next), In order to amplify the S pole signal, first, a pulse is generated in the first switching signal CTL1, and then a pulse is generated in the second switching signal CTL2. In other words, when the output signal OUT is at the high level, the changeover switch 20X performs the switching control of the switches 21 to 28 in the order from the first switching state to the second switching state.

On the other hand, as shown in (2) and (3) of FIG. 13, when the output signal OUT is at a low level (that is, the state where the N pole signal should be detected next after the detection of the S pole signal), In order to amplify the N pole signal, first, a pulse is generated in the second switching signal CTL2, and then a pulse is generated in the first switching signal CTL1. In other words, when the output signal OUT is at the low level, the changeover switch circuit 20X performs the switching control of the switches 21 to 28 in the order from the second switching state to the first switching state.

Further, the switching signal generation circuit 86 is configured to output the first timing signal S1 as it is as the third switching signal CTL3, and the application terminal of the first timing signal S1 is used as the extraction terminal of the third switching signal CTL3. The switch circuit 43 and the second switch circuit 44 (both not shown in FIG. 12) are connected.

Next, the operation of the magnetic sensor device 1 configured as described above will be described in detail with reference to the timing chart of FIG.

First, since the power-on signal POW is intermittently set to the high level, the power supply voltage is intermittently applied to each part of the magnetic sensor device 1 (specifically, main units such as the amplifier circuit 30X and the comparison circuit 50X). The detection operation can be performed when VDD is supplied. By combining such intermittent power supply control and latch control of the output signal OUT, the detection operation of the magnetic sensor device 1 is not hindered, and an electronic device (for example, a battery-powered mobile phone) on which the magnetic sensor device 1 is mounted is used. Power consumption can be significantly reduced. Note that the period for setting the power-on signal POW to the high level and the high-level period of the power-on signal POW may be set to an appropriate time length according to the application to which the magnetic sensor device 1 is applied. The magnetic sensor device 1 may be configured to operate continuously rather than intermittently.

As shown in (1) and (4) of FIG. 13, when the output signal OUT is at a high level (that is, after the detection of the N pole signal, the S pole signal is to be detected next), the reference In synchronization with the rising edge of the clock signal OSC, first, the first switching signal CTL1 and the third switching signal CTL3 are set to the high level. When the first switching signal CTL1 is set to the high level, the changeover switch circuit 20X enters the first switching state. Further, since the third switching signal CTL3 is set to the high level, the first switch circuit 43 and the second switch circuit 44 are turned on.

In response to the high-level transition of the first switching signal CTL1, the changeover switch circuit 20X is set to the first switching state, so that the terminals A and C, which are the first terminal pair of the Hall element 10X, are respectively supplied with the power supply voltage VDD. And a ground voltage are applied, and a Hall voltage is generated at each of the terminals B and D as the second terminal pair. At this time, the voltage Vb is generated at the terminal B, and the voltage Vd is generated at the terminal D.

A first amplified voltage AOUT1 (= α (Vb−Voffa1)) obtained by amplifying the voltage Vb is generated at the first amplified output terminal iii of the amplifier circuit 30X, and the voltage Vd is amplified at the second amplified output terminal iv. The second amplified voltage AOUT2 (= α (Vd−Voffa2)) is generated. Α is the amplification degree of the amplifier circuit 30X, and Voffa1 and Voffa2 are input offset voltages of the first amplifier circuit 31 and the second amplifier circuit 32, respectively.

On the other hand, when both the first switch circuit 43 and the second switch circuit 44 are turned on in response to the high level transition of the third switching signal CTL3, the first reference input terminal v of the comparison circuit 50X has a first reference input v. The voltage Vref1 is applied, and the second reference voltage Vref2 is applied to the second comparison input terminal vi.

Thereby, the first capacitor 41 is charged with a voltage difference (Vref1-α (Vb-Voffa1)) between the first reference voltage Vref1 and the first amplified voltage AOUT1. On the other hand, the second capacitor 42 is charged with a difference voltage (Vref2-α (Vd−Voffa2)) between the second reference voltage Vref2 and the second amplified voltage AOUT2.

After the above-described charging operation is performed, the first switching signal CTL1 and the third switching signal CTL3 are set to the low level and the second switching signal CTL2 is set to the high level in synchronization with the rising edge of the next incoming reference clock signal OSC. Level. When the second switching signal CTL2 is set to the high level, the changeover switch circuit 20X enters the second switching state. Further, since the third switching signal CTL3 is set to the low level, both the first switch circuit 43 and the second switch circuit 44 are turned off.

In response to the high-level transition of the second switching signal CTL2, the changeover switch circuit 20X is set to the second switching state, so that the power supply voltage VDD is applied to the terminals B and D, which are the second terminal pair of the Hall element 10X, respectively. And a ground voltage are applied, and a Hall voltage is generated at each of the terminals C and A, which is the first terminal pair. At this time, the voltage Vc is generated at the terminal C, and the voltage Va is generated at the terminal A.

A first amplified voltage AOUT1 (= α (Va−Voffa1)) obtained by amplifying the voltage Va is generated at the first amplified output terminal iii of the amplifier circuit 30X, and the voltage Vc is amplified at the second amplified output terminal iv. The second amplified voltage AOUT2 (= α (Vc−Voffa2)) is generated.

On the other hand, according to the low-level transition of the third switching signal CTL3, both the first switch circuit 43 and the second switch circuit 44 are turned off, but the charges charged in the first capacitor 41 and the second capacitor 42 change. Therefore, the first comparison voltage INC1 at the first comparison input terminal v and the second comparison voltage INC2 at the second comparison input terminal vi of the comparison circuit 50X are respectively expressed by the following equations (2) and (3 )

INC1 = Vref1− [α (Vb−Voffa1) −α (Va−Voff
a1)]
= Vref1-α (Vb-Va) (2)
INC2 = Vref2- [α (Vd−Voffa2) −α (Vc−Voff
a2)]
= Vref2-α (Vd-Vc) (3)

As shown in the above equations (2) and (2), the first and second comparison voltages INC1 and INC2 do not include the input offset voltages Voffa1 and Voffa2. That is, the input offset voltages Voffa1 and Voffa2 are canceled through the operations in the first switching state and the second switching state.

In the comparison circuit 50X, a comparison process between the first comparison voltage INC1 and the second comparison voltage INC2 is performed. Here, as shown by (1) in FIG. 13, if the S pole signal is input to the magnetic sensor device 1 and the first comparison voltage INC1 is higher than the second comparison voltage INC2, the comparison result signal COUT is high. Level. On the other hand, as shown in (4) of FIG. 13, if the N-pole signal is input to the magnetic sensor device 1 and the first comparison voltage INC1 is lower than the second comparison voltage INC2, the comparison result signal COUT is at a low level. Maintained. The difference voltage between the first and second comparison voltages INC1 and INC2 to be compared in the comparison circuit 50X is expressed by the following equation (4).

INC1-INC2
= Vref1-Vref2-α (Vb−Va) + α (Vd−Vc)
... (4)

Incidentally, the Hall voltage generated from the Hall element 10X includes a signal component voltage and an element offset voltage proportional to the strength of the magnetic field. Note that the effective signal component corresponding to the strength of the magnetic field is in phase with the voltage generated between the terminals B and D in the first switching state of the Hall element 10X and the voltage generated between the terminals C and A in the second switching state. The element offset voltage is in reverse phase.

When the element offset voltages included in the voltages Vb, Vd, Va, and Vc are Vboffe, Vdoffe, Vaoffe, and Vcoffe, the relational expression Vboff−Vdoffe = Vaoffe−Vcoffe is established. When this relational expression is modified, the following expression (5) is obtained.

Vboffe-Vaoffe = Vdoffe-Vcoffe (5)

The above equation (5) indicates that the element offset voltage is canceled in the comparison between the first comparison voltage INC1 and the second comparison voltage INC2 according to the above equation (4).

Thus, both the element offset voltage of the Hall element 10X and the input offset voltage of the amplifier circuit 30X are canceled in the comparison operation in the comparison circuit 50X.

The logic circuit 61 generates a logical operation signal LOUT based on the comparison result signal COUT obtained above and the output signal OUT currently output.

More specifically, as shown in (1) of FIG. 13, when the comparison result signal COUT transitions to a high level when the output signal OUT is at a high level, the S pole signal is detected. In order to invert the logic of the output signal OUT, the logic operation signal LOUT is transited to a low level. On the other hand, as shown by (4) in FIG. 13, when the output signal OUT is at the high level and the comparison result signal COUT is maintained at the low level, it is determined that the S pole signal is not detected. The logic operation signal LOUT is maintained at a high level in order to maintain the logic of the output signal OUT at the current state.

The D-type flip-flop 62 latches the logical operation signal LOUT generated by the logic circuit 61 in synchronization with the rising edge of the clock signal CLK_SH, and outputs this as the output signal OUT. Accordingly, in (1) of FIG. 13, the output signal OUT is switched from the high level to the low level, and in (4) of FIG. 13, the output signal OUT is maintained at the high level.

On the other hand, as shown in (2) and (3) of FIG. 13, when the output signal OUT is at a low level (that is, after the detection of the S pole signal, the N pole signal should be detected next), In synchronization with the rising edge of the reference clock signal OSC, first, the second switching signal CTL2 and the third switching signal CTL3 are set to the high level. When the second switching signal CTL2 is set to the high level, the changeover switch circuit 20X enters the second switching state. Further, since the third switching signal CTL3 is set to the high level, the first switch circuit 43 and the second switch circuit 44 are turned on.

Thereby, the first capacitor 41 is charged with a voltage difference (Vref1-α (Va-Voffa1)) between the first reference voltage Vref1 and the first amplified voltage AOUT1. On the other hand, the second capacitor 42 is charged with a difference voltage (Vref2−α (Vc−Voffa2)) between the second reference voltage Vref2 and the second amplified voltage AOUT2.

After the above charging operation is performed, in synchronization with the rising edge of the next incoming reference clock signal OSC, the second switching signal CTL2 and the third switching signal CTL3 are set to the low level, and the first switching signal CTL1 is set to the high level. Level. When the first switch signal CTL1 is set to the high level, the switch circuit 20X enters the first switch state. Further, since the third switching signal CTL3 is set to the low level, both the first switch circuit 43 and the second switch circuit 44 are turned off.

A first amplified voltage AOUT1 (= α (Vb−Voffa1)) obtained by amplifying the voltage Vb is generated at the first amplified output terminal iii of the amplifier circuit 30X, and the voltage Vd is amplified at the second amplified output terminal iv. The second amplified voltage AOUT2 (= α (Vd−Voffa2)) is generated.

On the other hand, according to the low-level transition of the third switching signal CTL3, both the first switch circuit 43 and the second switch circuit 44 are turned off, but the charges charged in the first capacitor 41 and the second capacitor 42 change. Therefore, the first comparison voltage INC1 at the first comparison input terminal v and the second comparison voltage INC2 at the second comparison input terminal vi of the comparison circuit 50X are respectively expressed by the following equations (6) and (7 )

INC1 = Vref1− [α (Va−Voffa1) −α (Vb−Voff
a1)]
= Vref1-α (Va-Vb) (6)
INC2 = Vref2- [α (Vc−Voffa2) −α (Vd−Voff
a2)]
= Vref2-α (Vc-Vd) (7)

As shown in the above formulas (6) and (7), the first and second comparison voltages INC1 and INC2 do not include the input offset voltages Voffa1 and Voffa2. That is, the input offset voltages Voffa1 and Voffa2 are canceled through the operations in the second switching state and the first switching state.

In the comparison circuit 50X, a comparison process between the first comparison voltage INC1 and the second comparison voltage INC2 is performed. Here, as shown by (3) in FIG. 13, if the N-pole signal is input to the magnetic sensor device 1 and the first comparison voltage INC1 is higher than the second comparison voltage INC2, the comparison result signal COUT is high. Level. On the other hand, as shown in (2) of FIG. 13, if the S pole signal is input to the magnetic sensor device 1 and the first comparison voltage INC1 is lower than the second comparison voltage INC2, the comparison result signal COUT is at a low level. Maintained. The differential voltage between the first and second comparison voltages INC1 and INC2 to be compared in the comparison circuit 50X is expressed by the following equation (8).

INC1-INC2
= Vref1-Vref2-α (Va−Vb) + α (Vc−Vd)
... (8)

Incidentally, as described above, the Hall voltage generated from the Hall element 10X includes a signal component voltage and an element offset voltage proportional to the strength of the magnetic field. The effective signal component according to the strength of the magnetic field is in phase with the voltage generated between the terminals B and D in the first switching state of the Hall element 10X and the voltage generated between the terminals C and A in the second switching state. The element offset voltage is in reverse phase.

As described above, when the element offset voltage included in the voltages Vb, Vd, Va, and Vc is Vboff, Vdoffe, Vaoffe, and Vcoffe, a relational expression of Vboff−Vdoff = Vaoffe−Vcoffe is established. When this relational expression is transformed, the following expression (9) is obtained.

Vaoffe-Vboffe = Vcoffe-Vdoffe (9)

The above equation (9) indicates that the element offset voltage is canceled in the comparison between the first comparison voltage INC1 and the second comparison voltage INC2 according to the above equation (8).

More specifically, as shown in (3) of FIG. 13, when the output signal OUT is at a low level and the comparison result signal COUT transitions to a high level, an N pole signal is detected. The logic operation signal LOUT is transited to a high level to invert the logic of the output signal OUT. On the other hand, as shown in (2) of FIG. 13, when the comparison result signal COUT is maintained at the low level when the output signal OUT is at the low level, it is determined that the N pole signal is not detected. The logic operation signal LOUT is maintained at a low level in order to maintain the logic of the output signal OUT at the current state.

The D-type flip-flop 62 latches the logical operation signal LOUT generated by the logic circuit 61 in synchronization with the rising edge of the clock signal CLK_SH, and outputs this as the output signal OUT. Accordingly, in (3) of FIG. 13, the output signal OUT is switched from the low level to the high level, and in (2) of FIG. 13, the output signal OUT is maintained at the low level.

The above-described alternating magnetic field detection operation (output signal OUT generation operation) will be generally described with reference to the flowchart of FIG.

FIG. 14 is a flowchart for explaining the operation of the magnetic sensor device 1 according to the present invention.

When detecting the alternating magnetic field, in step S1, it is determined whether the output signal OUT is at a high level or a low level. If it is determined that the output signal OUT is at a high level, the flow proceeds to step S2. On the other hand, if it is determined that the output signal OUT is at a low level, the flow proceeds to step S6.

If it is determined in step S1 that the output signal OUT is at a high level, in step S2, the current situation is that after the detection of the N pole signal, the S pole signal should be detected next. Under the recognition, in order to amplify the S pole signal, the switching control of the changeover switch circuit 20X is performed in the order from the first switching state to the second switching state, and the first comparison signal INC1 thus obtained and the second comparison signal are compared. Comparison processing with the signal INC2 (comparison processing between the difference voltage between them and the reference voltage VREF) is performed.

In subsequent step S3, it is determined whether the comparison result signal COUT is at a high level or a low level. Here, if it is determined that the comparison result signal COUT is at the high level (applied magnetic field B> detected magnetic field level Bop of S pole), the flow proceeds to step S4. On the other hand, if it is determined that the comparison result signal COUT is at a low level (applied magnetic field B <detected magnetic field level Bop of S pole), the flow proceeds to step S5.

In step S3, when it is determined that the comparison result signal COUT is at the high level, in step S4, the output signal OUT is changed from the high level to the low level with the recognition that the S pole signal has been detected. Thereafter, the flow returns to step S1.

On the other hand, when it is determined in step S3 that the comparison result signal COUT is at the low level, in step S5, the output signal OUT is maintained at the high level with the recognition that the S pole signal has not been detected. Thereafter, the flow returns to step S1.

If it is determined in step S1 that the output signal OUT is at a low level, in step S6, the current situation is after detection of the S pole signal, and the state where the N pole signal should be detected next. With the recognition that there is, the switching control of the changeover switch circuit 20X is performed in the order from the second switching state to the first switching state in order to amplify the N pole signal, and the first comparison signal INC1 thus obtained and the first switching signal are obtained. Comparison processing with the two comparison signals INC2 (comparison processing between the difference voltage between them and the reference voltage VREF) is performed.

In subsequent step S7, it is determined whether the comparison result signal COUT is at a high level or a low level. Here, if it is determined that the comparison result signal COUT is at the high level (applied magnetic field B <detected magnetic field level Brp with N poles), the flow proceeds to step S8. On the other hand, when it is determined that the comparison result signal COUT is at the low level (applied magnetic field B> N pole detection magnetic field level Brp), the flow proceeds to step S9.

If it is determined in step S7 that the comparison result signal COUT is at a high level, in step S8, the output signal OUT is transitioned from a low level to a high level with the recognition that an N pole signal has been detected. Thereafter, the flow returns to step S1.

On the other hand, when it is determined in step S7 that the comparison result signal COUT is at the low level, in step S9, the output signal OUT is maintained at the low level with the recognition that the N pole signal has not been detected. Thereafter, the flow returns to step S1.

As described above, the magnetic sensor device 1 according to the present invention generates a logical output signal OUT corresponding to the detected polarity (S pole / N pole) of a magnetic field, and includes a Hall element 10X; A changeover switch circuit 20X that switches the detection state of 10X to one of the first switching state and the second switching state; a predetermined comparison process is performed using the detection voltage of the Hall element 10X and a predetermined reference voltage; A comparison circuit 50X that generates a corresponding comparison result signal COUT; and a logic circuit 61 that generates a logical operation signal LOUT for maintaining or inverting the logic of the output signal OUT based on the output signal OUT and the comparison result signal COUT; A D flip-flop 62 that latches the logical operation signal LOUT and outputs it as an output signal OUT; from the first switching state based on the output signal OUT; A control circuit 80X that determines whether to perform switching control of the changeover switch circuit 20X in the order of the two switching states or to perform switching control of the changeover switch circuit 20X in the order of the second switching state to the first switching state; It is set as the structure which comprises;

In this way, the polarity of the reference voltage VREF applied between the input terminals of the comparison circuit 50X is unchanged regardless of whether the S pole signal or the N pole signal is detected, while the first, By determining the order of the second switching state to switch between amplifying the S pole signal and the N pole signal, the non-inverting input terminal (+) and the inverting input of the comparison circuit 50X are temporarily assumed. The detected magnetic field level for detecting the S pole signal and the detected magnetic field level for detecting the N pole signal are compared with each other even when a comparative offset voltage exists between the terminal (−) and the terminal (−). The amount corresponding to the voltage fluctuates with the same tendency. In other words, considering the subtraction of the two, it is possible to cancel the influence of the comparison offset voltage and to give symmetry to the magnetic field detection level of the alternating magnetic field detection.

Therefore, according to the above configuration, since the duty ratio of the pulse appearing in the output signal OUT can be set to an ideal value (50%), it is possible to provide a user-friendly magnetic sensor device.

In addition, according to the above configuration, an alternating magnetic field detection type magnetic sensor device can be obtained by diverting only the logic portion (logic circuit or control circuit) by diverting the circuit configuration based on the conventional switch type magnetic sensor device. Therefore, development costs can be reduced.

Further, according to the above configuration, the polarity switching switch for the reference voltage VREF is not necessary.

The configuration of the present invention can be variously modified in addition to the above-described embodiment without departing from the spirit of the invention. That is, the above-described embodiment is an example in all respects and should not be considered as limiting, and the technical scope of the present invention is not the description of the above-described embodiment, but the claims. It should be understood that all modifications that come within the meaning and range of equivalents of the claims are included.

For example, in the above-described embodiment, the configuration using a Hall element as the magnetoelectric conversion element has been described as an example. However, as the magnetoelectric conversion element, the electrical characteristics are changed according to the change of the applied magnetic field. As long as the output voltage can be extracted according to the change, a magnetoresistive element or the like may be used in addition to the Hall element.

In the above embodiment, the magnetic sensor device 1 is described as an alternating magnetic field detection type as an example. However, the configuration of the present invention is not limited to this, and the magnetic sensor device 1 is a single unit. It may be a polar magnetic field detection type.

In the above-described embodiment, the configuration in which two magnetoelectric conversion elements are integrated in a single chip has been described as an example. However, in order to correspond to a plurality of movement directions, three or more in a single chip are used. These magnetoelectric conversion elements may be integrated.

Moreover, in the said embodiment, although demonstrated by exemplifying the structure which made the magnetic sensor apparatus stationary and made the target which has a magnet movable, the structure of this invention is not limited to this, A magnet is made stationary. The target having the magnetic sensor device may be movable.

The magnetic sensor device according to the present invention can be suitably used, for example, for all applications (mobile phone, digital still camera, digital video camera, etc.) having magnets that are driven to rotate or slide.

DESCRIPTION OF SYMBOLS 1 Magnetic sensor apparatus 2 (2A, 2B) Target 3 Analysis apparatus 10X, 10Y Hall element 20X, 20Y Changeover switch circuit 21-28 Switch 30X, 30Y Amplification circuit 31, 31A, 31B 1st amplification circuit 32, 32A, 32B 2nd Amplifier circuit 33 Feedback resistor 34, 35 Switch circuit 40X, 40Y Sample hold circuit 41, 42 First capacitor, Second capacitor 43, 44 First, second switch circuit 50X, 50Y Comparison circuit 51 Comparator 52, 53 Switch circuit 60X, 60Y latch circuit 61 logic circuit 61-1 and 61-2 inverter 61-3 and 61-4 AND operation unit 61-5 OR operation unit 62 D-type flip-flop 70X and 70Y output circuit 80X and 80Y control Control circuit 81 Start pulse signal generation circuit 82 Shift register 83 OR operation unit 94, 85 Inverter 86 Switching signal generation circuit 86-1, 86-2, 86-3, 86-4 AND operation unit 86-5, 86- 6 OR operator 90 Oscillation circuit 100 Reference voltage generation circuit 100-1 to 100-3 Voltage dividing resistor 100-4 P-type MOS transistor 100-5 N-type MOS transistor 100-6, 100-7 Inverter VDD Power supply voltage Vref1 , Vref2 first and second reference voltages POW power on signal / POW inverted power on signal CTL1, CTL2, CTL3 first, second, third switching signal AOUT1, AOUT2 first, second amplified voltage INC1, INC2 first, Second comparison voltage COUT comparison result signal OUT logic operation signal OUT output signal OUTX first output signal OUTY second output signal CLK_SH clock signal OSC reference clock signal SIG start pulse signal S1, S2 first, second timing signal

Claims

A plurality of magnetoelectric transducers arranged at a predetermined inter-element distance;
A plurality of signal processing circuits that respectively generate a plurality of output signals whose logic levels change according to the intensity or polarity of the magnetic field respectively detected by the plurality of magnetoelectric transducers;
Are integrated in a single semiconductor chip.
Each of the plurality of signal processing circuits is
A changeover switch circuit for switching the detection state of the magnetoelectric conversion element to one of the first and second switching states;
A comparison circuit that performs a predetermined comparison process using a detection voltage of the magnetoelectric conversion element and a predetermined reference voltage, and generates a comparison result signal according to the result;
A logic circuit that generates a logical operation signal for maintaining or inverting the logic of the output signal based on the output signal and the comparison result signal;
A D-type flip-flop that latches the logical operation signal and outputs it as the output signal;
Based on the output signal, the switching control of the selector switch circuit is performed in the order from the first switching state to the second switching state, or in the order from the second switching state to the first switching state, A control circuit for determining whether to perform switching control of the changeover switch circuit;
The magnetic sensor device according to claim 1, comprising:
The magnetic sensor device according to claim 1, wherein each of the plurality of magnetoelectric transducers is a Hall element.
Each of the plurality of signal processing circuits is
A changeover switch circuit for switching the detection state of the magnetoelectric conversion element to one of the first and second switching states;
A comparison circuit that performs a predetermined comparison process using a detection voltage of the magnetoelectric conversion element and a predetermined reference voltage, and generates a comparison result signal according to the result;
A logic circuit that generates a logical operation signal for maintaining or inverting the logic of the output signal based on the output signal and the comparison result signal;
A D-type flip-flop that latches the logical operation signal and outputs it as the output signal;
Based on the output signal, the switching control of the selector switch circuit is performed in the order from the first switching state to the second switching state, or in the order from the second switching state to the first switching state, A control circuit for determining whether to perform switching control of the changeover switch circuit;
The magnetic sensor device according to claim 3, comprising:
A magnetic sensor device according to claim 1;
A target having a magnet;
An analysis device for analyzing the movement of the target based on the plurality of output signals output from the magnetic sensor device;
An electronic device characterized by comprising:
The magnetic sensor device is arranged such that the plurality of magnetoelectric transducers integrated in the magnetic sensor device are arranged along the movement direction of the target,
The analysis device detects an output time difference from a change in the logic level of the first output signal output from the magnetic sensor device to a change in the logic level of the second output signal, and the output time difference and the predetermined value The electronic apparatus according to claim 5, wherein a movement speed of the target is calculated from a distance between elements.
The magnet includes a plurality of S-pole magnetic domains and N-pole magnetic domains arranged alternately along the direction of movement of the target,
6. The electronic apparatus according to claim 5, wherein an alternating magnetic field is applied to the magnetic sensor device as the target moves.
3. The magnetic sensor device according to claim 2, further comprising an oscillator that outputs a reference clock signal having a predetermined frequency, wherein the control circuit operates based on the reference clock signal output from the oscillator.
The control circuit includes:
A start pulse signal generation circuit that generates a start pulse signal based on the reference clock signal;
A shift register that receives the reference clock signal and the start pulse signal, and sequentially captures the start pulse signal based on the reference clock signal;
A switching signal generating circuit for generating a first switching signal, a second switching signal, and a third switching signal based on the output of the shift register and the output signal;
The magnetic sensor device according to claim 8, comprising:
10. The magnetic sensor device according to claim 9, wherein the output of the shift register includes a first timing signal and a second timing signal.
Each of the plurality of signal processing circuits is
A first operational amplifier having a non-inverting input connected to the first output of the changeover switch circuit;
A second operational amplifier having a non-inverting input terminal connected to a second output terminal of the changeover switch circuit;
A first feedback resistor connected between an inverting input terminal and an output terminal of the first operational amplifier;
A second feedback resistor connected between an inverting input terminal of the first operational amplifier and an application terminal of a predetermined reference voltage;
A third feedback resistor connected between the inverting input terminal and the output terminal of the second operational amplifier;
A fourth feedback resistor connected between an inverting input terminal of the second operational amplifier and an application terminal of a predetermined reference voltage;
The magnetic sensor device according to claim 2, comprising:
Each of the plurality of signal processing circuits is
A first operational amplifier having a non-inverting input connected to the first output of the changeover switch circuit;
A second operational amplifier having a non-inverting input terminal connected to a second output terminal of the changeover switch circuit;
A first feedback resistor connected between an inverting input terminal and an output terminal of the first operational amplifier;
A second feedback resistor connected between an inverting input terminal and an output terminal of the second operational amplifier;
A third feedback resistor connected between the inverting input terminal of the first operational amplifier and the inverting input terminal of the second operational amplifier;
The magnetic sensor device according to claim 2, comprising:
The reference voltage generation circuit for generating the reference voltage is:
A voltage dividing resistor that generates the reference voltage by dividing a power supply voltage;
A first transistor connected to the power supply voltage side of the voltage dividing resistor and turned on / off according to a predetermined control signal;
A second transistor connected to the ground side of the voltage dividing resistor and turned on / off according to the control signal;
The magnetic sensor device according to claim 2, comprising:
A magnetic sensor device according to claim 2;
A target having a magnet;
An analysis device for analyzing the movement of the target based on the plurality of output signals output from the magnetic sensor device;
An electronic device characterized by comprising:
A magnetic sensor device according to claim 3,
A target having a magnet;
An analysis device for analyzing the movement of the target based on the plurality of output signals output from the magnetic sensor device;
An electronic device characterized by comprising:
A magnetic sensor device according to claim 4,
A target having a magnet;
An analysis device for analyzing the movement of the target based on the plurality of output signals output from the magnetic sensor device;
An electronic device characterized by comprising:
The magnet includes a plurality of S-pole magnetic domains and N-pole magnetic domains arranged alternately along the direction of movement of the target,
The electronic apparatus according to claim 6, wherein an alternating magnetic field is applied to the magnetic sensor device as the target moves.
Each of the plurality of signal processing circuits is
A first operational amplifier having a non-inverting input connected to the first output of the changeover switch circuit;
A second operational amplifier having a non-inverting input terminal connected to a second output terminal of the changeover switch circuit;
A first feedback resistor connected between an inverting input terminal and an output terminal of the first operational amplifier;
A second feedback resistor connected between an inverting input terminal of the first operational amplifier and an application terminal of a predetermined reference voltage;
A third feedback resistor connected between the inverting input terminal and the output terminal of the second operational amplifier;
A fourth feedback resistor connected between an inverting input terminal of the second operational amplifier and an application terminal of a predetermined reference voltage;
The magnetic sensor device according to claim 4, comprising:
Each of the plurality of signal processing circuits is
A first operational amplifier having a non-inverting input connected to the first output of the changeover switch circuit;
A second operational amplifier having a non-inverting input terminal connected to a second output terminal of the changeover switch circuit;
A first feedback resistor connected between an inverting input terminal and an output terminal of the first operational amplifier;
A second feedback resistor connected between an inverting input terminal and an output terminal of the second operational amplifier;
A third feedback resistor connected between the inverting input terminal of the first operational amplifier and the inverting input terminal of the second operational amplifier;
The magnetic sensor device according to claim 4, comprising:
The reference voltage generation circuit for generating the reference voltage is:
A voltage dividing resistor that generates the reference voltage by dividing a power supply voltage;
A first transistor connected to the power supply voltage side of the voltage dividing resistor and turned on / off according to a predetermined control signal;
A second transistor connected to the ground side of the voltage dividing resistor and turned on / off according to the control signal;
The magnetic sensor device according to claim 4, comprising: