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WO2011086613A1 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
WO2011086613A1
WO2011086613A1 PCT/JP2010/005132 JP2010005132W WO2011086613A1 WO 2011086613 A1 WO2011086613 A1 WO 2011086613A1 JP 2010005132 W JP2010005132 W JP 2010005132W WO 2011086613 A1 WO2011086613 A1 WO 2011086613A1
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WIPO (PCT)
Prior art keywords
substrate
semiconductor chip
semiconductor
wiring
electrode
Prior art date
Application number
PCT/JP2010/005132
Other languages
English (en)
French (fr)
Inventor
伊藤史人
平野博茂
太田行俊
Original Assignee
パナソニック株式会社
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Publication date
Application filed by パナソニック株式会社 filed Critical パナソニック株式会社
Publication of WO2011086613A1 publication Critical patent/WO2011086613A1/ja
Priority to US13/495,861 priority Critical patent/US20120256322A1/en

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Definitions

  • the present disclosure relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device in which semiconductor elements are packaged by a fine process and a manufacturing method thereof.
  • a semiconductor device in which a plurality of semiconductor elements are mounted in one package has a plurality of semiconductor elements flip-chip mounted on a relay substrate, and the relay substrate on which the semiconductor elements are mounted using wires and a ball grid array (BGA).
  • BGA ball grid array
  • a main wiring board such as a board is connected (see, for example, Patent Document 1).
  • the conventional semiconductor device uses a wire for connection between the relay board and the main wiring board. For this reason, a region for connecting wires to the relay board is required, and it is difficult to reduce the size of the relay board.
  • This disclosure is intended to realize a low-cost semiconductor device in which the size of the relay substrate is reduced.
  • the present disclosure has a configuration in which a semiconductor chip is mounted on a substrate having a through wiring, and an electrode formed on the back surface of the substrate and the semiconductor chip are connected by the through wiring. .
  • the exemplary semiconductor device includes a first semiconductor chip in which a first semiconductor element having a plurality of element electrodes is formed, and a first substrate on which the first semiconductor chip is mounted on the element mounting surface.
  • the first substrate is formed on the element mounting surface, the plurality of first electrodes respectively connected to the plurality of element electrodes, and the plurality of first wirings respectively connected to the plurality of first electrodes;
  • a plurality of second electrodes formed on a surface opposite to the element mounting surface, a plurality of second wirings respectively connected to the plurality of second electrodes, and a first substrate penetrating the first substrate.
  • a plurality of through-wirings connecting the wiring and the second wiring; the first substrate and the first semiconductor chip have a planar rectangular shape; and the first side of the first substrate and the first side The first side of the semiconductor chip is arranged in the same direction, and the first side of the first substrate is the first semiconductor. Tsu shorter than the first side of the flops.
  • the first substrate has a plurality of through wirings that connect the first wiring and the second wiring.
  • the element electrode and the second electrode are connected via the first electrode, the first wiring, the through wiring, and the second wiring. Therefore, the connection between the semiconductor device and the outside can be performed through the second electrode formed on the back surface of the first substrate.
  • the side of the first substrate is shorter than the side of the first semiconductor chip arranged in the same direction, the area of the first substrate can be further reduced.
  • the first substrate may have a linear expansion coefficient of 10 ppm / ° C. or less.
  • the exemplary semiconductor device further includes a second substrate having a plurality of substrate connection electrodes on the substrate mounting surface, and the first substrate is mounted on the substrate mounting surface of the second substrate,
  • the substrate connection electrode may be connected via a protruding electrode.
  • the first semiconductor chip only needs to be flip-chip mounted.
  • the exemplary semiconductor device may further include a second semiconductor chip on which a second semiconductor element having a plurality of element electrodes is formed, and the second semiconductor chip may be flip-chip mounted on the element mounting surface.
  • the difference between the height from the first substrate to the top surface of the first semiconductor chip and the height from the first substrate to the top surface of the second semiconductor chip may be 20 ⁇ m or less.
  • the first substrate may include a third semiconductor element.
  • the formation pitch of the first electrode may be narrower than the formation pitch of the second electrode.
  • the minimum wiring width in the first wiring may be smaller than the minimum wiring width in the second wiring.
  • the thickness of the first substrate may be smaller than the thickness of the first semiconductor chip.
  • An example method for manufacturing a semiconductor device includes a step (a) of forming a plurality of first electrodes and a plurality of first wirings respectively connected to the plurality of first electrodes on an element mounting surface of a substrate; (B) after (a), forming a plurality of openings in the substrate from the side opposite to the element mounting surface of the substrate, and forming a through-wiring connected to the first wiring in the formed opening; A step (c) of forming a plurality of second wirings connected to the through-wiring on the second surface and a second electrode respectively connected to the plurality of second wirings, and after the step (c) (D) mounting a semiconductor chip having a plurality of element electrodes on the element mounting surface so as to connect the element electrode and the first electrode; and lowering the semiconductor chip between the semiconductor chip and the substrate A step (e) of injecting a resin in a state where the first substrate is formed.
  • the sides and the first side of the first semiconductor chip is disposed in the same direction, the first side of the first substrate
  • the exemplary semiconductor device manufacturing method injects the resin with the semiconductor chip facing down. For this reason, even when the first side of the first substrate is shorter than the first side of the first semiconductor chip, the resin can be stably filled.
  • the semiconductor device and the manufacturing method thereof according to the present disclosure it is possible to realize a low-cost semiconductor device in which the size of the relay substrate is reduced.
  • (A) And (b) shows the semiconductor device which concerns on one Embodiment, (a) is a top view, (b) is sectional drawing in the Ib-Ib line
  • (A) is a top view which shows arrangement
  • (b) is a top view which shows arrangement
  • FIG. 1A and 1B show a semiconductor device according to an embodiment, where FIG. 1A shows a planar configuration, and FIG. 1B shows a cross-sectional configuration taken along line Ib-Ib in FIG.
  • a first semiconductor chip 111 and a second semiconductor chip 121 are flip-chip mounted on an element mounting surface 101A of a first substrate 101 that is a relay substrate.
  • the first semiconductor chip 111 is a semiconductor substrate on which a first semiconductor element (not shown) is formed, and a plurality of first element electrodes 113 are formed on one surface.
  • the second semiconductor chip 121 is a semiconductor substrate on which a second semiconductor element (not shown) is formed, and a plurality of second element electrodes 123 are formed on one surface.
  • the first electrode 104 is connected to the corresponding first element electrode 113 and second element electrode 123 via the first bump 131.
  • a resin 133 is filled between the element mounting surface 101A and the first semiconductor chip 111 and the second semiconductor chip 121.
  • the width w0 of the first substrate 101 is smaller than the width w1 of the first semiconductor chip 111 and the width w2 of the second semiconductor chip 121.
  • the short side of the first substrate 101 is made shorter than the length of the side along the short side of the first substrate 101 in the first semiconductor chip 111.
  • the semiconductor device can be further downsized.
  • the cost of the first substrate 101 can be reduced.
  • FIG. 1 shows an example in which the width w1 of the first semiconductor chip 111 and the second semiconductor chip w2 are substantially the same, but the width w1 of the first semiconductor chip 111 and the second semiconductor chip 111 are shown. It may be different from the chip w2.
  • only one of the width w1 of the first semiconductor chip 111 and the second semiconductor chip w2 may be larger than the width w0 of the first substrate 101.
  • the second wiring layer 106 including a plurality of second wirings (not shown) and the second wiring are connected.
  • a plurality of second electrodes 107 are formed.
  • the first wiring and the second wiring are connected via a through wiring 109 that penetrates the first substrate 101.
  • the second electrode 107 is connected to a second bump 135 that is a protruding electrode, and the second bump 135 is a substrate formed on the substrate mounting surface 141A of the second substrate 141 that is a resin substrate or the like.
  • the connection electrode 143 is connected.
  • An external connection electrode 145 is formed on the external connection electrode formation surface 141B that is the surface opposite to the substrate mounting surface 141A of the second substrate 141.
  • the substrate connection electrode 143 and the external connection electrode 145 are connected by connection wiring (not shown) formed on the second substrate 141.
  • the connection wiring includes, for example, wiring formed on the substrate mounting surface 141A, wiring formed on the external connection electrode forming surface 141B, wiring penetrating the second substrate 141, and the like.
  • the second substrate 141 may be a mother board constituting a so-called set in which the external connection electrode 145 is not formed.
  • the first element electrode 113 and the second element electrode 123 have the first bump 131, the first electrode 104, the first wiring, the through wiring 109, and the second wiring.
  • the substrate connection electrode 143 of the second substrate 141 is connected through the second bump 135.
  • the second substrate 141 is connected to the external connection electrode 145 formed on the surface opposite to the substrate mounting surface 141A through a through wiring or the like.
  • the first substrate 101 may be a wiring substrate such as a printed circuit board. Further, a silicon substrate or the like may be used so that high-density wiring can be formed.
  • the first substrate 101 may be a stacked chip package as a semiconductor chip on which a third semiconductor element (not shown) is formed.
  • an input / output circuit, a global wiring, or the like may be formed on the first substrate 101.
  • the linear expansion coefficient of the first substrate 101 is preferably substantially equal to that of the first semiconductor chip 111. For this reason, it is preferable that the linear expansion coefficient of the 1st board
  • silicone is 10 ppm / degrees C or less, for example, it is good also as a glass substrate.
  • the minimum pitch P1 of the first electrode 104 is preferably smaller than the minimum pitch P2 of the second electrode 107.
  • the minimum line width of the first wiring is preferably smaller than the minimum line width of the second wiring.
  • the first semiconductor chip 111 and the second semiconductor chip 121 may be any semiconductor chip.
  • the first semiconductor chip 111 can be a system LSI
  • the second semiconductor chip can be a memory element such as a multi-bit dynamic random access memory.
  • various semiconductor chips such as a system LSI, an analog LSI, and a high frequency LSI can be combined.
  • the semiconductor element and the element electrode may be formed on different surfaces of the substrate of the semiconductor chip. However, it is preferable that the semiconductor element and the element electrode are formed on the same surface because it is not necessary to form a through wiring or the like penetrating the semiconductor chip.
  • the difference between the height from the first substrate 101 to the upper surface of the first semiconductor chip 111 and the height from the first substrate 101 to the upper surface of the second semiconductor chip 121 depends on handling properties, attachment of a heat dissipation jig, etc. Is preferably 20 ⁇ m or less.
  • the thickness of the first substrate 101 is thinner than the thickness of the first semiconductor chip 111 and the second semiconductor chip 121 because the through wiring 109 can be easily formed.
  • the thickness of the first semiconductor chip 111 and the second semiconductor chip 121 may be about 200 ⁇ m to 800 ⁇ m, and the thickness of the first substrate 101 may be about 50 ⁇ m to 250 ⁇ m, which is thinner than that.
  • FIG. 3 shows the semiconductor device manufacturing method of this embodiment in the order of steps.
  • the first wiring layer 103 having the first electrode 104 and the first wiring connected to the first electrode 104 on the element mounting surface 101 ⁇ / b> A of the first substrate 101.
  • a through wiring 109 connected to the first wiring is formed by embedding a conductive material in the through hole.
  • a second wiring layer 106 including a second wiring connected to the through wiring 109 and a second electrode 107 connected to the second wiring are formed on the back surface.
  • the first semiconductor chip 111 having the first element electrode 113 and the second semiconductor chip 121 having the second element electrode 123 are formed on the first substrate 101.
  • Flip chip mounting is performed on the element mounting surface 101A.
  • the flip chip mounting may be performed by fusion bonding using solder for the first bump 131.
  • the first bump 131 may be a stud bump or a plating bump, and may be performed by a method using ACF (anisotropic conductive film) or NCF (non-conductive film).
  • a resin 133 is filled in a connection gap between the element mounting surface 101 ⁇ / b> A and the first semiconductor chip 111 and the second semiconductor chip 121.
  • the resin 133 may be filled with the element mounting surface 101A facing down. In this way, even when the width of the first substrate 101 is smaller than the width of the first semiconductor chip 111, the resin 133 can be stably filled.
  • the distance between the element mounting surface 101A and the formation surface of the first element electrode 113 of the first semiconductor chip 111 and the formation surface of the second element electrode 123 of the second semiconductor chip 121 is 20 ⁇ m or less. It is preferable.
  • the second electrode 107 of the first substrate 101 and the substrate connection electrode 143 of the second substrate 141 are connected using the second bumps 135.
  • third bumps 137 which are projecting electrodes for external connection are mounted on the external connection electrodes 145 of the second substrate 141.
  • the semiconductor device and the manufacturing method thereof according to the present disclosure can realize a low-cost semiconductor device in which the size of the relay substrate is reduced, and particularly as a semiconductor device packaged with a fine process semiconductor element, a manufacturing method thereof, and the like Useful.

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Abstract

　半導体装置は、複数の素子電極１１３を有する第１の半導体素子が形成された第１の半導体チップ１１１と、素子搭載面１０１Ａに第１の半導体チップ１１１を搭載した第１の基板１０１とを備えている。第１の基板１０１は、素子搭載面１０１Ａに形成された、複数の第１の電極１０４及び第１の電極１０４と接続された複数の第１の配線と、素子搭載面１１１Ａと反対側の面１１１Ｂに形成された、複数の第２の電極１０７及び第２の電極１０７と接続された複数の第２の配線と、第１の基板１０１を貫通し第１の配線と第２の配線とを接続する複数の貫通配線１０９とを有している。第１の基板１０１の第１の辺は、第１の半導体チップ１１１の第１の辺よりも短い。

Description

半導体装置及びその製造方法
　本開示は、半導体装置及びその製造方法に関し、特に微細プロセスによる半導体素子をパッケージ化した半導体装置及びその製造方法に関する。
　近年、半導体素子の高機能化及び周辺に配置される高速メモリ等との伝送課題を受け、複数の半導体素子を１つのパッケージに搭載した、高機能なシステム・イン・パッケージの要望が増している。
　従来、複数の半導体素子を１つのパッケージに搭載した半導体装置は、中継基板の上に複数の半導体素子をフリップチップ実装し、ワイヤを用いて半導体素子が実装された中継基板とボールグリッドアレイ（ＢＧＡ）基板等の主配線基板とを接続している（例えば、特許文献１を参照。）。
特開２００８－２４４１０４号公報
　しかしながら、従来の半導体装置は、中継基板と主配線基板との接続にワイヤを用いている。このため、中継基板にワイヤを接続する領域が必要となり、中継基板のサイズを小さくすることが困難である。
　本開示は、中継基板のサイズを縮小した低コストな半導体装置を実現できるようにすることを目的とする。
　前記の目的を達成するため、本開示は半導体装置を、貫通配線を有する基板の上に半導体チップを搭載し、基板の裏面に形成された電極と半導体チップとを貫通配線により接続する構成とする。
　具体的に、例示の半導体装置は、複数の素子電極を有する第１の半導体素子が形成された第１の半導体チップと、素子搭載面に第１の半導体チップを搭載した第１の基板とを備え、第１の基板は、素子搭載面に形成され、複数の素子電極とそれぞれ接続された複数の第１の電極及び該複数の第１の電極とそれぞれ接続された複数の第１の配線と、素子搭載面と反対側の面に形成された複数の第２の電極及び該複数の第２の電極とそれぞれ接続された複数の第２の配線と、第１の基板を貫通し第１の配線と第２の配線とを接続する複数の貫通配線とを有し、第１の基板及び第１の半導体チップは、平面方形状であり、第１の基板の第１の辺と第１の半導体チップの第１の辺とは同一の方向に配置され、第１の基板の第１の辺は、第１の半導体チップの第１の辺よりも短い。
　例示の半導体装置は、第１の基板が第１の配線と第２の配線とを接続する複数の貫通配線を有している。このため、素子電極と第２の電極とは、第１の電極、第１の配線、貫通配線及び第２の配線を介して接続されている。従って、半導体装置と外部との接続を第１の基板の裏面に形成した第２の電極を介して行うことができる。その結果、第１の基板の素子搭載面にワイヤボンドのための領域を設ける必要がなく、第１の基板の面積を縮小することが可能となる。さらに、第１の基板の辺が同一方向に配置された第１の半導体チップの辺よりも短いため、第１の基板の面積をさらに縮小することが可能となる。
　例示の半導体装置において、第１の基板は、線膨張係数が１０ｐｐｍ／℃以下とすればよい。
　例示の半導体装置は、基板搭載面に複数の基板接続電極を有する第２の基板をさらに備え、第１の基板は、第２の基板の基板搭載面の上に搭載され、第２の電極と基板接続電極とは突起電極を介して接続されていてもよい。
　例示の半導体装置において、第１の半導体チップは、フリップチップ実装されていればよい。
　例示の半導体装置は、複数の素子電極を有する第２の半導体素子が形成された第２の半導体チップをさらに備え、第２の半導体チップは、素子搭載面にフリップチップ実装されていてもよい。
　例示の半導体装置において、第１の基板から第１の半導体チップの上面までの高さと、第１の基板と第２の半導体チップの上面までの高さとの差は２０μｍ以下とすればよい。
　例示の半導体装置において、第１の基板は、第３の半導体素子を有していてもよい。
　例示の半導体装置において、第１の電極の形成ピッチは、第２の電極の形成ピッチよりも狭い構成としてもよい。
　例示の半導体装置において、第１の配線における最小の配線幅は、第２の配線における最小の配線幅よりも小さい構成としてもよい。
　例示の半導体装置において、第１の基板の厚さは、第１の半導体チップの厚さよりも薄くしてもよい。
　例示の半導体装置の製造方法は、基板の素子搭載面に複数の第１の電極及び該複数の第１の電極とそれぞれ接続された複数の第１の配線を形成する工程（ａ）と、工程（ａ）よりも後に、基板の素子搭載面と反対側から基板に複数の開口部を形成し、形成した開口部に第１の配線と接続された貫通配線を形成する工程（ｂ）と、第２の面に貫通配線と接続された複数の第２の配線及び該複数の第２の配線とそれぞれ接続された第２の電極を形成する工程（ｃ）と、工程（ｃ）よりも後に、複数の素子電極を有する半導体チップを、素子電極と第１の電極とを接続するようにして素子搭載面に搭載する工程（ｄ）と、半導体チップと基板との間に半導体チップを下側にした状態において樹脂を注入する工程（ｅ）とを備え、第１の基板の第１の辺と第１の半導体チップの第１の辺とは同一の方向に配置され、第１の基板の第１の辺は、第１の半導体チップの第１の辺よりも短い。
　例示の半導体装置の製造方法は、半導体チップを下側にした状態において樹脂を注入する。このため、第１の基板の第１の辺は、第１の半導体チップの第１の辺よりも短い場合においても、樹脂の充填を安定して行うことができる。
　本開示に係る半導体装置及びその製造方法によれば、中継基板のサイズを縮小した低コストな半導体装置を実現することが可能となる。
（ａ）及び（ｂ）は一実施形態に係る半導体装置を示し、（ａ）は平面図であり、（ｂ）は（ａ）のＩｂ－Ｉｂ線における断面図である。 （ａ）は第１の基板における第１の電極の配置を示す平面図であり、（ｂ）は第１の基板における第２の電極の配置を示す平面図である。 一実施形態に係る半導体装置の製造方法を工程順に示す断面図である。 一実施形態に係る半導体装置の製造方法を工程順に示す断面図である。
　図１（ａ）及び（ｂ）は、一実施形態に係る半導体装置であり、（ａ）は平面構成を示し（ｂ）は（ａ）のＩｂ－Ｉｂ線における断面構成を示している。図１に示すように、中継基板である第１の基板１０１の素子搭載面１０１Ａの上に第１の半導体チップ１１１及び第２の半導体チップ１２１がフリップチップ実装されている。第１の半導体チップ１１１は、第１の半導体素子（図示せず）が形成された半導体基板であり、一方の面に複数の第１の素子電極１１３が形成されている。第２の半導体チップ１２１は、第２の半導体素子（図示せず）が形成された半導体基板であり、一方の面に複数の第２の素子電極１２３が形成されている。
　第１の基板１０１の素子搭載面１０１Ａには、複数の第１の配線（図示せず）を含む第１の配線層１０３と、第１の配線と接続された複数の第１の電極１０４とが形成されている。第１の電極１０４は、対応する第１の素子電極１１３及び第２の素子電極１２３と、第１のバンプ１３１を介して接続されている。素子搭載面１０１Ａと第１の半導体チップ１１１及び第２の半導体チップ１２１との間には、樹脂１３３が充填されている。
　本実施形態においては、図１に示すように、第１の基板１０１の幅ｗ０は、第１の半導体チップ１１１の幅ｗ１及び第２の半導体チップ１２１の幅ｗ２よりも小さくなっている。具体的には、第１の基板１０１の短辺を、第１の半導体チップ１１１における第１の基板１０１の短辺に沿った辺の長さよりも短くしている。このような構成とすることにより、半導体装置をさらに小型化することができる。また、第１の基板１０１のコストを削減することもできる。なお、図１においては、第１の半導体チップ１１１の幅ｗ１と第２の半導体チップｗ２とがほぼ同じである例を示しているが、第１の半導体チップ１１１の幅ｗ１と第２の半導体チップｗ２とは異なっていてもよい。また、第１の半導体チップ１１１の幅ｗ１と第２の半導体チップｗ２の一方だけが第１の基板１０１の幅ｗ０よりも大きい構成であってもよい。
　第１の基板１０１における、素子搭載面１０１Ａと反対側の面（裏面）１０１Ｂには、複数の第２の配線（図示せず）を含む第２の配線層１０６と、第２の配線と接続された複数の第２の電極１０７とが形成されている。第１の配線と第２の配線とは、第１の基板１０１を貫通する貫通配線１０９を介して接続されている。
　第２の電極１０７には、突起電極である第２のバンプ１３５が接続されており、第２のバンプ１３５は、樹脂基板等である第２の基板１４１の基板搭載面１４１Ａに形成された基板接続電極１４３と接続されている。第２の基板１４１の基板搭載面１４１Ａと反対側の面である外部接続電極形成面１４１Ｂには、外部接続電極１４５が形成されている。基板接続電極１４３と外部接続電極１４５とは、第２の基板１４１に形成された接続配線（図示せず）により接続されている。接続配線は、例えば基板搭載面１４１Ａに形成された配線、外部接続電極形成面１４１Ｂに形成された配線及び第２の基板１４１を貫通する配線等を含む。なお、第２の基板１４１は、外部接続電極１４５が形成されていないいわゆるセットを構成するマザーボードであってもよい。
　このような構成とすることにより、第１の素子電極１１３及び第２の素子電極１２３は、第１のバンプ１３１、第１の電極１０４、第１の配線、貫通配線１０９及び第２の配線を介して、第１の基板１０１の裏面１０１Ｂに設けられた第２の電極１０７と接続される。また、第２のバンプ１３５を介して第２の基板１４１の基板接続電極１４３と接続される。第２の基板１４１の構成によっては、基板搭載面１４１Ａと反対側の面に形成された外部接続電極１４５と貫通配線等を介して接続される。このため、ワイヤを介することなく半導体チップの電極を半導体装置の外部に引き出すことが可能となる。従って、第１の基板１０１にワイヤ接続領域を設ける必要がなく、半導体装置を小型化することが可能となる。また、基板１０１の面積が縮小できることでコストの低減を行うこともできる。
　第１の基板１０１は、プリント基板等の配線基板とすればよい。また、高密度の配線を形成できるようにシリコン基板等としてもよい。第１の基板１０１を第３の半導体素子（図示せず）が形成された半導体チップとしてスタックドチップパッケージとしてもよい。また、第１の基板１０１に入出力回路又はグローバル配線等が形成されていてもよい。第１の基板１０１の線膨張係数は第１の半導体チップ１１１とほぼ等しいことが好ましい。このため、シリコンの線膨張係数である第１の基板１０１の線膨張係数は１０ｐｐｍ／℃以下であることが好ましく、例えばガラス基板等としてもよい。
　図２（ａ）及び（ｂ）は、それぞれ素子搭載面１０１Ａに形成された第１の電極１０４の配置と、裏面１０１Ｂに形成された第２の電極１０７の配置とを示している。図２に示すように、第１の電極１０４の最小ピッチＰ１は、第２の電極１０７の最小ピッチＰ２よりも小さくすることが好ましい。また、第１の配線の最小ライン幅は第２の配線の最小ライン幅よりも小さいことが好ましい。このような構成とすれば、第１の基板１０１における配線密度を小さくすることができる。
　第１の半導体チップ１１１及び第２の半導体チップ１２１はどの様な半導体チップであってもよい。例えば、第１の半導体チップ１１１をシステムＬＳＩとし、第２の半導体チップを多ビットのダイナミックランダムアクセスメモリ等のメモリ素子とすることができる。また、この他にもシステムＬＳＩ、アナログＬＳＩ及び高周波ＬＳＩ等の種々の半導体チップを組み合わせることができる。半導体素子と素子電極とは、半導体チップの基板の異なる面に形成されていてもよいが、同じ面に形成されていれば半導体チップを貫通する貫通配線等を形成する必要がなく好ましい。
　第１の基板１０１から第１の半導体チップ１１１の上面までの高さと、第１の基板１０１から第２の半導体チップ１２１の上面までの高さとの差は、ハンドリング性及び放熱治具の取り付け等を考慮すると２０μｍ以下とすることが好ましい。一方、第１の基板１０１の厚さは、第１の半導体チップ１１１及び第２の半導体チップ１２１の厚さよりも薄い方が、貫通配線１０９の形成が容易となるため好ましい。例えば、第１の半導体チップ１１１及び第２の半導体チップ１２１の厚さを２００μｍ～８００μｍ程度とし、第１の基板１０１の厚さをそれより薄い５０μｍ～２５０μｍ程度とすればよい。
　図３は、本実施形態の半導体装置の製造方法を工程順に示している。まず、図３（ａ）に示すように、第１の基板１０１の素子搭載面１０１Ａに第１の電極１０４及び第１の電極１０４と接続された第１の配線を有する第１の配線層１０３を形成する。続いて、第１の基板１０１の裏面１０１Ｂ側から素子搭載面１０１Ａに貫通する貫通孔を形成した後、貫通孔に導電性材料を埋め込むことにより第１の配線と接続された貫通配線１０９を形成する。続いて、裏面に貫通配線１０９と接続された第２の配線を含む第２の配線層１０６及び第２の配線と接続された第２の電極１０７を形成する。
　次に、図３（ｂ）に示すように、第１の素子電極１１３を有する第１の半導体チップ１１１及び第２の素子電極１２３を有する第２の半導体チップ１２１を、第１の基板１０１の素子搭載面１０１Ａにフリップチップ実装する。フリップチップ実装は、第１のバンプ１３１にはんだを用いて、溶融接合により行えばよい。また、第１のバンプ１３１をスタッドバンプ又はめっきバンプとし、ＡＣＦ（異方性導電フィルム）又はＮＣＦ（非導電性フィルム）を用いた方法により行ってもよい。
　次に、図３（ｃ）に示すように、素子搭載面１０１Ａと第１の半導体チップ１１１及び第２の半導体チップ１２１との接続ギャップに樹脂１３３を充填する。樹脂１３３の充填は、素子搭載面１０１Ａを下にした状態で行えばよい。このようにすれば、第１の基板１０１の幅が、第１の半導体チップ１１１の幅よりも小さい場合においても、樹脂１３３の充填を安定して行うことができる。
　なお、素子搭載面１０１Ａと第１の半導体チップ１１１の第１の素子電極１１３の形成面及び第２の半導体チップ１２１の第２の素子電極１２３の形成面との間の間隔は２０μｍ以下とすることが好ましい。
　次に、図４（ａ）に示すように第１の基板１０１の第２の電極１０７と第２の基板１４１の基板接続電極１４３とを第２のバンプ１３５を用いて接続する。
　次に、図４（ｂ）に示すように、第２の基板１４１の外部接続電極１４５に外部接続用の突起電極である第３のバンプ１３７を搭載する。
　本実施形態において示した、材料及び数値は好ましい例であり、この形態に限定されない。また本発明の思想の範囲を逸脱しない範囲で、適宜変更が可能である。
　本開示に係る半導体装置及びその製造方法は、中継基板のサイズを縮小した低コストな半導体装置を実現することが可能となり、特に微細プロセスの半導体素子をパッケージ化した半導体装置及びその製造方法等として有用である。
１０１　　　第１の基板
１０１Ａ　　素子搭載面
１０１Ｂ　　裏面
１０３　　　第１の配線層
１０４　　　第１の電極
１０６　　　第２の配線層
１０７　　　第２の電極
１０９　　　貫通配線
１１１　　　第１の半導体チップ
１１３　　　第１の素子電極
１２１　　　第２の半導体チップ
１２３　　　第２の素子電極
１３１　　　第１のバンプ
１３３　　　樹脂
１３５　　　第２のバンプ
１３７　　　第３のバンプ
１４１　　　第２の基板
１４１Ａ　　基板搭載面
１４１Ｂ　　外部接続電極形成面
１４３　　　基板接続電極
１４５　　　外部接続電極

Claims (11)

  1. 　半導体装置は、
    　複数の素子電極を有する第１の半導体素子が形成された第１の半導体チップと、
    　素子搭載面に第１の半導体チップを搭載した第１の基板とを備え、
    　前記第１の基板は、
    　前記素子搭載面に形成され、前記複数の素子電極とそれぞれ接続された複数の第１の電極及び前記複数の第１の電極とそれぞれ接続された複数の第１の配線と、
    　前記素子搭載面と反対側の面に形成された複数の第２の電極及び前記複数の第２の電極とそれぞれ接続された複数の第２の配線と、
    　前記第１の基板を貫通し前記第１の配線と前記第２の配線とを接続する複数の貫通配線とを有し、
    　前記第１の基板及び第１の半導体チップは、平面方形状であり、
    　前記第１の基板の第１の辺と前記第１の半導体チップの第１の辺とは同一の方向に配置され、
    　前記第１の基板の第１の辺は、前記第１の半導体チップの第１の辺よりも短い。
  2. 　請求項１に記載の半導体装置において、
    　前記第１の基板は、線膨張係数が１０ｐｐｍ／℃以下である。
  3. 　請求項１に記載の半導体装置は、
    　基板搭載面に複数の基板接続電極を有する第２の基板をさらに備え、
    　前記第１の基板は、前記第２の基板の基板搭載面の上に搭載され、
    　前記第２の電極と前記基板接続電極とは突起電極を介して接続されている。
  4. 　請求項１に記載の半導体装置において、
    　前記第１の半導体チップは、フリップチップ実装されている。
  5. 　請求項１に記載の半導体装置は、
    　複数の素子電極を有する第２の半導体素子が形成された第２の半導体チップをさらに備え、
    　前記第２の半導体チップは、前記素子搭載面にフリップチップ実装されている。
  6. 　請求項５に記載の半導体装置において、
    　前記第１の基板から前記第１の半導体チップの上面までの高さと、前記第１の基板と前記第２の半導体チップの上面までの高さとの差は２０μｍ以下である。
  7. 　請求項１に記載の半導体装置において、
    　前記第１の基板は、第３の半導体素子を有する。
  8. 　請求項１に記載の半導体装置において、
    　前記第１の電極の形成ピッチは、前記第２の電極の形成ピッチよりも狭い。
  9. 　請求項１に記載の半導体装置において、
    　前記第１の配線における最小の配線幅は、前記第２の配線における最小の配線幅よりも小さい。
  10. 　請求項１に記載の半導体装置において、
    　前記第１の基板の厚さは、前記第１の半導体チップの厚さよりも薄い。
  11. 　半導体装置の製造方法は、
    　基板の素子搭載面に複数の第１の電極及び前記複数の第１の電極とそれぞれ接続された複数の第１の配線を形成する工程（ａ）と、
    　前記工程（ａ）よりも後に、前記基板の前記素子搭載面と反対側から前記基板に複数の開口部を形成し、形成した開口部に前記第１の配線と接続された貫通配線を形成する工程（ｂ）と、
    　前記第２の面に前記貫通配線と接続された複数の第２の配線及び前記複数の第２の配線とそれぞれ接続された第２の電極を形成する工程（ｃ）と、
    　前記工程（ｃ）よりも後に、複数の素子電極を有する半導体チップを、前記素子電極と前記第１の電極とを接続するようにして前記素子搭載面に搭載する工程（ｄ）と、
    　前記半導体チップと前記基板との間に前記半導体チップを下側にした状態において樹脂を注入する工程（ｅ）とを備え、
    　前記第１の基板の第１の辺と前記第１の半導体チップの第１の辺とは同一の方向に配置され、
    　前記第１の基板の第１の辺は、前記第１の半導体チップの第１の辺よりも短い。
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