WO2010045842A1 - A method for calculating extrinsic information during decoding, a decoder and a turbo decoder - Google Patents
A method for calculating extrinsic information during decoding, a decoder and a turbo decoder Download PDFInfo
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- WO2010045842A1 WO2010045842A1 PCT/CN2009/074367 CN2009074367W WO2010045842A1 WO 2010045842 A1 WO2010045842 A1 WO 2010045842A1 CN 2009074367 W CN2009074367 W CN 2009074367W WO 2010045842 A1 WO2010045842 A1 WO 2010045842A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/3905—Maximum a posteriori probability [MAP] decoding or approximations thereof based on trellis or lattice decoding, e.g. forward-backward algorithm, log-MAP decoding, max-log-MAP decoding
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- the present invention claims to be submitted to the Chinese Patent Office on October 23, 2008, and the application number is 200810218595.2.
- the invention is entitled "A Decoding Method, Decoder”
- the priority of the Chinese patent application of the "Turbo Code Decoder” is incorporated herein by reference.
- TECHNICAL FIELD The present invention relates to the field of communications, and in particular, to a method for decoding Chinese and foreign information, a decoder, and a Turbo code decoder. Background of the invention
- the Turbo code is an efficient and commonly used channel coding method. Turbo codes have performance close to Shannon's theoretical limits. In addition to applications in deep space communications, satellite communications, and multimedia communications, Turbo codes are becoming more widely used in wireless mobile communications systems. However, due to the large amount of iterative decoding required for the decoding algorithm of Turbo codes, the decoding of Turbo codes causes a large delay. How to reduce the decoding delay of Turbo codes as much as possible has been studied. Hot Issues.
- Turbo code also known as Parallel Concatenated Convolutional Code (PCCC)
- PCCC Parallel Concatenated Convolutional Code
- the encoder is composed of two identical 1/2 code component code encoders, specifically the upper component code encoder and the lower component code encoder are connected in parallel.
- the code block length be, and the code input sequence be ⁇ : ⁇ , ⁇ , ⁇ ,..., ⁇ - 1 ]
- the initial value of the register is 0.
- the code encoder inputs 1 bit of data at a time, and the encoder delay is 1.
- the coding adopts trellis termination mode, which can refer to 3GPPTS 36.212 (V8.3.0), the output code is system bit, and Zk 'is the first check bit and The second check digit.
- the following is a schematic diagram of the prior art Turbo code decoding shown in FIG. 2, which details the iterative decoding principle of the Turbo code.
- the typical Turbo code decoder consists of two soft input soft outputs (SISO, Soft Input Soft Output).
- the decoders DEC1 and DEC2 are formed in series, that is, the two component code decoders DEC1 and the component code decoders DEC2 are connected in series, and the interleaver in the turbo code decoder is the same as the interleaver used in the turbo code encoding.
- the component code decoder DEC1 decodes the component code of the upper layer, generates likelihood information about each bit in the information sequence C, and interleaves the outer information into the component code decoder DEC2, and converts the component code.
- the decoder DEC2 uses this information as a priori information, decodes the component code of the lower layer, generates likelihood ratio information about each bit in the interleaved information sequence C, and then deinterleaves the outer information into components.
- the code decoder DEC1 performs the next decoding. After several iterations, the external information of the component code decoder DEC1 and the component code decoder DEC2 tends to be stable, and finally the hard decision is made on the likelihood ratio to obtain the best estimate of each bit of the information sequence c.
- the Maximum A Posteriori (MAP) algorithm or the Max-Log-MAP algorithm on the logarithmic domain is usually used as the SISO decoding method of the component code.
- MAP Maximum A Posteriori
- Max-Log-MAP algorithm on the logarithmic domain is usually used as the SISO decoding method of the component code.
- Different decoding methods of component codes in the prior art are described below. 1. Serial decoding algorithm for component codes.
- the component code decoder after receiving the data sequence, the component code decoder first reversely calculates the backward state metric ⁇ , that is, from the end of the data sequence, the inverse state metric ⁇ , , ..., ⁇ , and the forward direction metric are calculated from the initial value, and then the forward state metric and the branch metric are calculated from the data sequence.
- the head end is calculated by the initial value " ⁇ "
- the initial value of the first parallel branch TM and the initial value of the last branch are set as described above.
- the initial value of " ⁇ and ⁇ " 1 of the training sequence of the other branches is set to 1 (the initial value is 0 when the logarithmic domain algorithm is used).
- Embodiments of the present invention provide a method for decoding Chinese and foreign information, a decoder, and a Turbo code.
- the decoder improves the decoding speed of the turbo code by improving the algorithm for calculating the external information in the decoding process, reduces the delay of the turbo code decoding, and ensures the reliability of the decoding of the turbo code.
- an embodiment of the present invention provides a method for decoding Chinese and foreign information calculations, including the following steps:
- Backward state metrics and branch metrics are inversely calculated from the end of the data sequence
- the outer information of the bits in the data sequence is output based on the calculated backward state metric, forward state metric, and branch metric.
- an embodiment of the present invention further discloses a decoder, including:
- a metric calculation module configured to inversely calculate a backward state metric and a branch metric from the end of the data sequence after receiving the data sequence, and before calculating the backward state metric and the branch metric
- the head end of the data sequence sequentially calculates the forward state metric and the branch metric in turn;
- an information calculation module configured to calculate, by using the backward state metric, the forward state metric, and the branch metric calculated by the metric calculation module, the outer information of the bits in the data sequence.
- an embodiment of the present invention further discloses a Turbo code decoder, including the above decoder.
- the order of calculating the output external information is changed from left to right (ie, from the head end to the end) to the middle to the two sides, thereby improving the Turbo code.
- the speed of decoding reduces the delay of Turbo code decoding and ensures the reliability of decoding of Turbo codes.
- FIG. 2 is a schematic diagram showing the principle of decoding of a Turbo code in the prior art
- FIG. 3 is a schematic diagram showing the principle of a serial decoding algorithm of a component code
- FIG. 4 is a schematic diagram showing the principle of a parallel decoding algorithm of component codes
- Figure 5 is a flow diagram of one embodiment of a method of decoding of the present invention
- FIG. 6 is a schematic diagram of an embodiment of a decoding principle of a component code of the present invention.
- FIG. 7 is a schematic diagram of still another embodiment of the decoding principle of the component code of the present invention.
- Figure 8 is a block diagram showing an embodiment of a decoder of the present invention.
- FIG. 9 is a schematic structural diagram of a first information calculation module according to an embodiment of the present invention.
- FIG. 10 is a schematic structural diagram of a first information calculation output unit according to an embodiment of the present invention.
- Figure 11 is a block diagram showing another embodiment of the decoder of the present invention.
- FIG. 12 is a schematic structural diagram of a second information calculation module according to an embodiment of the present invention.
- FIG. 13 is a schematic structural diagram of a second information calculation output unit according to an embodiment of the present invention. Mode for carrying out the invention
- Embodiments of the present invention provide a decoding method, a decoder, and a Turbo code decoder.
- the Turbo code decoding speed is improved, and Turbo is reduced.
- the delay of code decoding and guarantees the reliability of decoding of the turbo code.
- the decoding algorithm of the component code is analyzed.
- the representation of the component code decoder DEC2 of the lower layer is similar to that of the component code decoder DEC1 of the upper layer.
- the component code decoder DEC1 of the upper layer is taken as an example, and the log likelihood ratio of the bit is described by the MAP algorithm (LLR, Log The calculation process of Likelihood Ratio ).
- Pf ( is a prior probability.
- ⁇ ( ) is the a priori information
- ⁇ ⁇ ) is the channel information
- ⁇ ( ) is the outer information and it is the information transmitted between the two component code decoders in the iterative decoding.
- the initial value of ⁇ has the following two equivalent setting methods:
- the a priori information of each bit has an initial value of zero. 2 is taken as a job. Since the channel information ⁇ ( ) is known, it can be obtained by the iterative decoding principle. In order to obtain external information,
- ⁇ ⁇ 12 in the Max-Log-MAP algorithm, approximates 1 ⁇ ⁇ max ⁇ x , y ⁇ as follows. Combining the definitions of 0 ⁇ and ⁇ " can calculate TM and "". In the prior art, each time the component code is decoded, the backward state metric is calculated first, and then the forward state metric "and the branch" are calculated. The metrics therefore all the external information needs to be calculated once and for all, that is, from the first and last ends of the data sequence.
- Step S501 receiving a data sequence; sequentially calculating a backward state metric and a branch metric from the end of the data sequence; from the head end of the data sequence before calculating the backward state metric and the branch metric Forward direction metrics and branch metrics are calculated in turn;
- Step S502 Calculate out-of-band information of the bits in the data sequence by the calculated backward state metric, forward state metric, and branch metric.
- the foregoing embodiment is a method for serial decoding of the improved component code.
- a schematic diagram of an embodiment of the decoding principle of the component code of the present invention shown in FIG. 6 is described in detail below.
- a method of decoding a component code of the invention It can be known from the calculation formula (1) of the log-likelihood ratio that only the forward state metric 0 ⁇ of the current time, the backward state metric of the next time, and the time and time are required for the calculation.
- the branch metric ⁇ therefore, the embodiment of the present invention reversely calculates the backward state metric and the branch metric from the end of the received data sequence, that is, from the last time after receiving the data sequence to the first time respectively Calculating a backward state metric and a branch metric at each moment, and calculating a forward state metric and a branch metric from the head end of the data sequence before calculating the backward state metric and the tributary metric, ie
- the backward calculated state metric and the forward calculated forward state metric are calculated. After the sum of the numbers is greater than the number of code lengths of the data sequence of the branch, the calculated backward state metric A TM +1 , the forward state metric m, and the branch metric combining formula (1 ) can calculate the current moment. ⁇ ), and then calculated by combining formula (2) Information, that is, the log likelihood ratio and the outer information of the output two bits can be calculated. After calculating the log likelihood ratio and the outer information of all the bits, the outer information is used as the prior information, and the next component is performed.
- the LLR value and the outer information of the bit that is, the LLR value and the outer information of the bit " ⁇ , and then the log likelihood ratio information of the j+1-q and j+1+q two bits can be calculated in turn.
- the decoding method in the embodiment of the present invention is applicable to Decoding of different code block lengths.
- the accelerated serial decoding algorithm changes the order of calculating the output LLR value and the external information from left to right (ie, from the head end to the end) to the middle to the both sides, improving the calculation in the decoding process.
- the algorithm of external information achieves the purpose of speeding up decoding, and the calculation is accurate, there is no performance loss, and the reliability of Turbo code decoding is guaranteed. It can be understood that, in step S501 of this embodiment and the specific description in conjunction with FIG. 6, "the backward state metric and the branch metric are inversely calculated from the end of the data sequence, and the backward state metric and the branch are calculated. Before the road metric, the forward state metric and the branch metric are calculated forwardly from the head end of the data sequence.
- the data sequence has two ends, and the data sequence is sequentially calculated from one end of the data sequence. a backward state metric and a branch metric, and the forward state metric and the branch metric of the data sequence are calculated in turn from the opposite end of the data sequence before the backward state metric and the tributary metric are calculated ".
- the end and the head end are interchangeable. The end may represent the beginning of the received data sequence or the terminating end of the data sequence. In the embodiment of the present invention, the head end and the end end can be used to indicate the meaning of the opposite ends of the data sequence in opposite directions.
- the above embodiment is a method for serial decoding of the improved component code. Specifically, when the data sequence received by the foregoing embodiment is a data sequence of at least two branches received in parallel, it needs to be performed. Parallel decoding of component codes, and a method for parallel decoding of component codes will be described in detail below with reference to a further embodiment of the decoding principle of the component code of the present invention shown in FIG.
- the embodiment assumes a data sequence of P branches, where P 2 , the decoding process of each branch is similar to the improved serial decoding described above, and the implementation
- the backward state metric and the branch metric are inversely calculated from the end of the data sequence of each branch, that is, the backward state metric and the branch at each moment are calculated from the last time after receiving the data sequence of each branch to the first time.
- the forward state metric and the branch metric are calculated forward from the head end of the data sequence of each branch, and when the calculation of the two directions is "intersect", that is, the backward state metric of the branch is inversely calculated After the sum of the forward state metrics of the forward calculation is greater than the code length of the data sequence of the branch,
- the likelihood ratio is hardly determined. , to get the best valuation.
- the log likelihood ratio information and the outer information of the bits wherein the values of q are sequentially from 1 to j, that is, the LLR values and the outer information of the two bits "" ⁇ and then can be calculated in turn, wherein the values of q are sequentially From 1 to J; when the length of the branch data sequence block is an even number ⁇ : 2 "/', where j is a preset fixed integer value, the jth sum in the branch data sequence is first
- the decoding method in the embodiment of the present invention is applicable to Decoding of different code block lengths.
- the accelerated parallel decoding algorithm changes the order of outputting the LLR value and the external information of each branch from left to right (ie, from the head end to the end) to the middle to the two sides, and achieves the decoding speed increase.
- the purpose, and the calculation is accurate, there will be no performance loss, and the reliability of Turbo code decoding is guaranteed.
- the typical Turbo code decoding process is a two-dimensional decoding process, that is, only two layer component code decoders, and correspondingly, the iterative decoding structure can be extended to multi-dimensional decoding, that is, there are many a layer component code decoder, the decoding process of the component code decoder is similar to the decoding process of the component code decoder in a typical decoding process. Therefore, the decoding method of the embodiment of the present invention can be applied in addition to In the typical Turbo code decoding process, in addition to being applicable to the 2-dimensional decoding process, it can also be applied to the M-dimensional Turbo code decoding process, where M 2 .
- the decoding method of the present invention is applicable to all communication systems using Turbo codes as channel coding and general turbo code decoders.
- a first metric calculation module 81 configured to inversely calculate a backward state metric and a branch metric from the end of the data sequence after receiving the data sequence, and calculate the backward state metric and the branch after calculating Forward state metrics and branch metrics are calculated forwardly from the head end of the data sequence before the metric;
- the first information calculation module 82 is configured to calculate, by the first metric calculation module 81, the backward state metric, the forward state metric, and the branch metric calculation to output the outer information of the bits in the data sequence.
- FIG. 9 is a schematic structural diagram of a first information calculation module according to an embodiment of the present invention, and the first information calculation module 82 includes a first information calculation output unit 821.
- the first information calculation output unit 821 can calculate the current position " ⁇ ) from the calculated backward state metric ⁇ " +1 , the forward state metric 0 ⁇ , and the branch metric ⁇ , in combination with the formula (1).
- the external information is calculated by " ) combined with the formula (2), that is, the log likelihood ratio and the outer information of the output two bits can be calculated, and after calculating the log likelihood ratio and the outer information of all the bits, the The outer information is transmitted as a priori information to the next component code decoder for the next component code.
- FIG. 1 a schematic diagram of a first information calculation output unit of the embodiment of the present invention as shown in FIG.
- the LLR value and the outer information of the bit that is, the LLR value and the outer information of the bit, and then the log likelihood ratio information and the outer information of the j+1-q and j+1+q two bits can be calculated in turn.
- the second information calculation subunit 8212 first calculates log likelihood ratio information and external information of the jth and j+1th bits in the data sequence.
- the data sequence can be calculated in turn
- the decoding method in the embodiment of the present invention is applicable to Decoding of different code block lengths.
- the foregoing embodiment is a structure of the improved component code serial decoder. Specifically, when the received data sequence is a data sequence of at least two branches received in parallel, a component code is required. And Line decoding, the structure of the decoder of the embodiment of the present invention is described below with reference to the structure of the second embodiment of the decoder of the present invention shown in FIG.
- the second metric calculation module 111 is configured to, after receiving the data sequence of the at least two branches in parallel, sequentially calculate the backward state metric and the branch metric from the end of the data sequence of each branch, and calculate each of the The backward state metric and the branch metric of the branch are forwardly calculated from the head end of each branch of the data sequence to the forward state metric and the branch metric;
- the second information calculation module 112 is configured to calculate, by the second metric calculation module 111, the backward state metric, the forward state metric, and the branch metric calculation to output the outer information of the bits in the data sequence of the branch.
- FIG. 12 is a schematic structural diagram of a second information calculation module according to an embodiment of the present invention, and the second information calculation module 112 includes a second information calculation output unit 1121.
- the second information calculation output unit 1121 combines the calculated backward state metric ⁇ " «, the forward state metric, and the branch metric ⁇ , in combination with the formula (1)
- External information that is, the log likelihood ratio and the outer information of the output two bits can be calculated.
- the second information calculation output unit 1121 includes a third information calculation subunit 11211 and a fourth information calculation subunit 11212, in the opposite direction.
- the third information calculation sub-unit 11211 After calculating the "intersection", when the length of the branch data sequence block is an odd number ⁇ 2 1 , the third information calculation sub-unit 11211 first calculates an LLR that generates the j+1th bit in the branch data sequence.
- the value and the outer information that is, the LLR value and the outer information of the bit, and then the log likelihood ratio information of the j+1-q and j+1+q two bits can be calculated in turn Information, wherein the value of q is sequentially from 1 to j, that is, the LLR value and the outer information of the two bits ⁇ and can be calculated in turn, wherein the value of q is sequentially from 1 to j; when the branch data sequence is long
- the fourth information calculation subunit 11212 first calculates the log likelihood ratio information and the outer information of the jth and j+1th bits in the branch data sequence.
- the log likelihood ratio information and the outer information of the jqth and j+1+q two bits in the data sequence may be sequentially calculated, where the value of q
- the LLR value and the external information of two bits - ⁇ and ' in turn, can be calculated sequentially from 1 to jl, wherein the values of q are sequentially from 1 to jl.
- the decoding method in the embodiment of the present invention is applicable to Decoding of different code block lengths.
- the turbo code decoder of the embodiment of the present invention further includes the decoder of the foregoing embodiment, and the decoder may be a component code serial decoder, or It is a component code parallel decoder.
- the decoder may be a component code serial decoder, or It is a component code parallel decoder.
- a typical Turbo code decoder is a 2-dimensional decoding process, that is, only a two-layer component code decoder, and accordingly, the iterative decoding structure can be extended to multi-dimensional decoding, that is, there are many a layer component code decoder, the decoding process of the component code decoder is similar to the decoding process of the component code decoder in a typical decoding process, and therefore, the decoder and the turbo code decoder of the present invention are It can be applied in the typical Turbo code decoding process, that is, in addition to being applicable to the 2-dimensional decoding process, it can also be applied to the M-dimensional Turbo code decoding process, where M 2 .
- the decoder of the present invention and the turbo code decoder are applicable to all communication systems using Turbo codes as channel coding.
- the decoding speed of the original algorithm and the acceleration algorithm of the present invention is compared by mathematical theory. Let the Turbo code block be long. The state of each state is calculated from the tail bit as an initial value. The chip's clock frequency is F MHz. It is assumed that one system bit soft bit and the corresponding two parity bit soft bits can be written into the input data buffer inside the Turbo decoder every cycle. The number of decoding iterations is .
- the decoding speed of a general serial algorithm is: ⁇ — 6 Mbit F
- the decoding speed of the accelerated serial algorithm of the present invention is:
- the accelerated parallel algorithm decoding speed of the present invention is:
- the acceleration algorithm of the present invention almost doubles the decoding speed of the original algorithm, and the decoding delay can be effectively reduced.
- the parallel decoding device if the decoding speed is the same, the number of parallel branches required by the acceleration algorithm of the present invention is half of that of the original algorithm. Since the number of branches is halved, the training sequence is also halved, and the performance is improved. If the number of branches is the same, the acceleration algorithm of the present invention has the same performance as the original algorithm, but can achieve a higher decoding speed.
- the following table gives the decoding speeds that can be achieved by the original algorithm and the acceleration algorithm of the present invention for different parallel branch numbers.
- the accelerated parallel algorithm with 16 parallel branches has a speed of more than 40% than the parallel parallel algorithm with 16 branches.
- the following table shows the floating-point performance loss of parallel decoding versus serial decoding for different encoding block lengths.
- the performance loss is also greatly reduced (close to 50%). If the same decoding speed is to be achieved, the number of parallel branches used by the acceleration algorithm of the present invention is half that of the original algorithm, and the performance of the acceleration algorithm of the present invention is significantly improved over the original algorithm.
- the sequence of calculating the output LLR value and the external information is changed from left to right (ie, from the head end to the end) to the middle to the two sides by an accelerated serial decoding algorithm.
- the purpose of decoding speed is achieved, and the calculation is accurate, there is no performance loss, and the reliability of Turbo code decoding is guaranteed.
- serial decoding the decoding speed is nearly doubled compared with the original decoding algorithm, and there is no performance loss; in parallel decoding, if the number of parallel branches is the same, it is higher than the original decoding algorithm.
- the percentage of high decoding speed is There is no performance loss at this time, but the decoding delay can be significantly reduced.
- the number of parallel branches required by the accelerated decoding algorithm of the present invention is half of the original decoding algorithm, and the training sequence is also reduced by half, and the performance is large. of Improve.
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Abstract
A method for calculating extrinsic information during decoding involves receiving a data sequence; back calculating back state metric and branch metric in turn from the bottom of the data sequence, and before finishing the calculation of the back state metric and the branch metric, forward calculating forward state metric and branch metric in turn from the top of the data sequence; calculating and outputting the extrinsic information of the data sequence bit from the calculated back state metric,, forward state metric and the branch metric. Accordingly a decoder and a turbo decoder are disclosed.
Description
种译码中外信息计算方法、 译码器以及 Turbo码译码器 本申请要求于 2008年 10月 23日提交中国专利局、 申请号为 200810218595.2发明 名称为 "一种译码的方法、 译码器以及 Turbo码译码器"的中国专利申请的优先权, 其全 部内容通过引用结合在本申请中。 技术领域 本发明涉及通信领域, 尤其涉及一种译码中外信息计算方法、 一种译码器以及一种 Turbo码译码器。 发明背景 The present invention claims to be submitted to the Chinese Patent Office on October 23, 2008, and the application number is 200810218595.2. The invention is entitled "A Decoding Method, Decoder" The priority of the Chinese patent application of the "Turbo Code Decoder" is incorporated herein by reference. TECHNICAL FIELD The present invention relates to the field of communications, and in particular, to a method for decoding Chinese and foreign information, a decoder, and a Turbo code decoder. Background of the invention
Turbo (特博) 码是一种有效且常用的信道编码方法, Turbo 码具有接近香农 (Shannon) 理论极限的性能。 除了在深空通信、 卫星通信以及多媒体通信等领域的应 用外, Turbo码在无线移动通信系统中的应用也越来越广泛。 然而由于 Turbo码的译码 算法所需的迭代译码计算量较大, 给 Turbo码的译码造成了很大的时延, 如何尽可能地 减少 Turbo码的译码时延是人们一直研究的热点问题。 The Turbo code is an efficient and commonly used channel coding method. Turbo codes have performance close to Shannon's theoretical limits. In addition to applications in deep space communications, satellite communications, and multimedia communications, Turbo codes are becoming more widely used in wireless mobile communications systems. However, due to the large amount of iterative decoding required for the decoding algorithm of Turbo codes, the decoding of Turbo codes causes a large delay. How to reduce the decoding delay of Turbo codes as much as possible has been studied. Hot Issues.
Turbo码又称为并行级联卷积码(PCCC, Parallel Concatenated Convolutional Code) , 它巧妙地将分量码编码器和随机交织器结合在一起,其中分量码的最佳选择是递归系统 卷积码,在实现随机编码思想的同时,通过交织器实现由短码(分量码)构造长码(Turbo 码) 的方法, 并采用软输出迭代译码来逼近最大似然译码, 通过分量码译码器之间外信 息或软信息的交换来提高译码性能, 下面通过典型的 Turbo码编码和译码的过程进行详 细的说明。 Turbo code, also known as Parallel Concatenated Convolutional Code (PCCC), subtly combines a component code encoder and a random interleaver, where the best choice of component code is a recursive systematic convolutional code. While implementing the idea of random coding, a method of constructing a long code (Turbo code) from a short code (component code) is implemented by an interleaver, and a soft output iterative decoding is used to approximate the maximum likelihood decoding, through a component code decoder. The exchange of external information or soft information improves the decoding performance. The following is a detailed description of the typical Turbo code encoding and decoding process.
请参阅图 1示出的现有技术的 Turbo码编码的原理示意图, 编码器由两个相同的 1/2 码率分量码编码器, 具体为上层分量码编码器和下层分量码编码器并联而成, 分量码为 递归系统卷积码, 传输函数为:
其中 gl (D) = l + L> + Z)3, g0 (D) = l + Dz + D 设编码码块长为 , 编码输入序列为 ^:^^,^,^,…,^-1], 经过内部交织器交 织后得到的序列为 e = [«'·Ά-1 ]。分量码的状态集合为8 ^771 '772^ '^ 其中 w 为总状态数且 W = 2M, M为编码器中移位寄存器的个数。寄存器初始值均为 0。假设分
量码编码器一次输入 1比特数据,编码器时延为 1。如比特 ^和 ^ (取值 0或 1)在时刻 f = 分别送入上下两层分量码编码器( = ι,Λ,^— 这样在 ^ = fc+i时刻, 比特 和 的编码完成并且比特 和 分别送入分量码编码器。 编码采用格形终止 (trellis termination)方式,具体可参考 3GPPTS 36.212 (V8.3.0), 图中输出编码 为系统位, 和 Zk'分别为第一校验位和第二校验位。 Please refer to the schematic diagram of the prior art Turbo code coding shown in FIG. 1. The encoder is composed of two identical 1/2 code component code encoders, specifically the upper component code encoder and the lower component code encoder are connected in parallel. The component code is a recursive system convolutional code, and the transfer function is: Where gl (D) = l + L> + Z) 3 , g 0 (D) = l + D z + D Let the code block length be, and the code input sequence be ^:^^,^,^,...,^ - 1 ], the sequence obtained by interleaving with the internal interleaver is e = [ «'·Ά- 1 ] . The state set of the component code is 8 ^ 771 ' 772 ^ '^ where w is the total state number and W = 2 M , where M is the number of shift registers in the encoder. The initial value of the register is 0. Hypothesis The code encoder inputs 1 bit of data at a time, and the encoder delay is 1. For example, bits ^ and ^ (value 0 or 1) are sent to the upper and lower two-layer component code encoders at time f = ( = ι , Λ , ^ - such that at ^ = fc+i, the encoding of the bit sum is completed and the bits And respectively input the component code encoder. The coding adopts trellis termination mode, which can refer to 3GPPTS 36.212 (V8.3.0), the output code is system bit, and Zk 'is the first check bit and The second check digit.
经过 Turbo编码及格形终止后得到的码字序列写成向量形式为: The code word sequence obtained after Turbo coding and trellis termination is written as a vector form:
D = [^0), ),A ,d^+i,d^, ,« )Λ , ÷3]。 经过映射 0→-1, 1→1后的发射序列为 (发射能量为 1): D = [^ 0) , ) , A , d^ +i , d^, , « )Λ , ÷ 3 ]. After the mapping 0→-1, 1→1, the transmission sequence is (the emission energy is 1):
Ε = \e(0) em A e em A e(1) e(2) A e(2) 1 其经过加成性高斯白噪声 (AWGN, Additive white Gaussian noise) 信道后得到的 接收数据序列为:Ε = \e (0) e m A ee m A e (1) e (2) A e (2) 1 Received data sequence obtained after the AWGN (Additive white Gaussian noise) channel for:
满足: yk = +r , 其中 为独立噪声, 满足期望为 0方差为 的实 Gauss分 布( Satisfaction: yk = +r , where is independent noise, satisfying the real Gauss distribution expected to be 0 variance (
下面结合图 2示出的现有技术的 Turbo码译码的原理示意图, 详细说明 Turbo码的迭 代译码原理, 典型的 Turbo码译码器由两个软输入软输出 (SISO, Soft Input Soft Output) 译码器 DEC1和 DEC2串联组成, 即两个分量码译码器 DEC1和分量码译码器 DEC2串联组 成, Turbo码译码器中的交织器与 Turbo码编码时所使用的交织器相同。 分量码译码器 DEC1对上层的分量码进行译码, 产生关于信息序列 C中每一比特的似然信息, 并将其 中的外信息经过交织后送给分量码译码器 DEC2,分量码译码器 DEC2将此信息作为先验 信息, 对下层的分量码进行译码, 产生关于交织后的信息序列 C中每一比特的似然比 信息, 然后将其中的外信息经过解交织送给分量码译码器 DEC1, 进行下一次译码。 经 过多次迭代, 分量码译码器 DEC1与分量码译码器 DEC2的外信息趋于稳定, 最后对似然 比进行硬判决, 即可得到信息序列 c的每一比特的最佳估值 。 The following is a schematic diagram of the prior art Turbo code decoding shown in FIG. 2, which details the iterative decoding principle of the Turbo code. The typical Turbo code decoder consists of two soft input soft outputs (SISO, Soft Input Soft Output). The decoders DEC1 and DEC2 are formed in series, that is, the two component code decoders DEC1 and the component code decoders DEC2 are connected in series, and the interleaver in the turbo code decoder is the same as the interleaver used in the turbo code encoding. The component code decoder DEC1 decodes the component code of the upper layer, generates likelihood information about each bit in the information sequence C, and interleaves the outer information into the component code decoder DEC2, and converts the component code. The decoder DEC2 uses this information as a priori information, decodes the component code of the lower layer, generates likelihood ratio information about each bit in the interleaved information sequence C, and then deinterleaves the outer information into components. The code decoder DEC1 performs the next decoding. After several iterations, the external information of the component code decoder DEC1 and the component code decoder DEC2 tends to be stable, and finally the hard decision is made on the likelihood ratio to obtain the best estimate of each bit of the information sequence c.
实际中通常用最大后验概率 (MAP, Maximum A Posteriori) 算法或对数域上的 Max-Log-MAP算法作为分量码的 SISO译码方法。 下面介绍现有技术中的分量码的不同 译码方法。
1、 分量码的串行译码算法。 In practice, the Maximum A Posteriori (MAP) algorithm or the Max-Log-MAP algorithm on the logarithmic domain is usually used as the SISO decoding method of the component code. Different decoding methods of component codes in the prior art are described below. 1. Serial decoding algorithm for component codes.
请参阅图 3示出的分量码的串行译码算法的原理示意图, 在目前的 Max-Log-MAP 算法中, 分量码译码器接收到数据序列后, 先反向计算后向状态度量 ^, 即从所述数据 序列的末端由初值 衣次计算反向状态度量 ^^、 、 ……、 β 、 , 再正向计 算前向状态度量 和支路度量^ \ 即从所述数据序列的首端由初值" ^依次计算 Referring to the schematic diagram of the serial decoding algorithm of the component code shown in FIG. 3, in the current Max-Log-MAP algorithm, after receiving the data sequence, the component code decoder first reversely calculates the backward state metric ^ , that is, from the end of the data sequence, the inverse state metric ^^, , ..., β, and the forward direction metric are calculated from the initial value, and then the forward state metric and the branch metric are calculated from the data sequence. The head end is calculated by the initial value "^"
(ο"、 ……、 并同时输出所述数据序列中相应比特的对数 似然比 (L ) ) 和外信息 (^(^ ) ) k = 0,l,A , K - l o 因此, 现有技术的串行译码 算法对译码块长为 的序列进行译码, 时延为 ( 2倍的码块长度)个时钟周期(不计 算 初始值所用的时延), 给译码时延造成很大的影响。 (ο", ..., and simultaneously output the log likelihood ratio ( L ) of the corresponding bit in the data sequence and the outer information (^(^)) k = 0, l, A, K - l o The prior art serial decoding algorithm decodes the sequence of the decoding block length, and the delay is (2 times the code block length) clock cycles (the delay used for the initial value is not calculated). The delay has a big impact.
2、 分量码的并行译码算法。 2. Parallel decoding algorithm for component codes.
请参阅图 4示出的分量码的并行译码算法的原理示意图, 设并行分支长为 P, 并 Please refer to the schematic diagram of the parallel decoding algorithm of the component code shown in FIG. 4, and set the parallel branch length to P, and
& Κ = Κ^ Χ Ρ , 即并行分支数为 。 当并行接收到数据序列后, 并行地计算各分支内各 比特的对数似然比, 直到计算出所有比特的对数似然比" ), 此时并行进行外信息的 交织或解交织操作 (此时需要 Turbo编码器中的内部交织器满足内存访问无竞争 (contention free) 特性)。 在每一个并行分支的计算中, 为了给 "*""和 Α™设定初始值, 需要在分支前后额外各增加 ^和1 ^个比特作为训练序列(第一分支0 ^的初值和最后一 个分支 Α™的初值例外)。对于第一个并行分支 ™的初始值以及最后一个分支的 的初 始值按照前面的叙述设定。 其他各分支的训练序列的" ^和^"1的初始值设为 1 (当用对 数域算法时初始值为 0)。 & Κ = Κ ^ Χ Ρ , that is, the number of parallel branches is . After receiving the data sequence in parallel, the log likelihood ratio of each bit in each branch is calculated in parallel until the log likelihood ratio of all bits is calculated, and the interleaving or deinterleaving operation of the external information is performed in parallel ( In this case, the internal interleaver in the Turbo encoder is required to satisfy the memory access contention free feature. In the calculation of each parallel branch, in order to set the initial values for "*"" and Α TM, it is necessary to be before and after the branch. An additional ^ and 1 ^ bits are additionally added as the training sequence (the initial value of the first branch 0 ^ and the initial value of the last branch Α TM are excluded). The initial value of the first parallel branch TM and the initial value of the last branch are set as described above. The initial value of "^ and ^" 1 of the training sequence of the other branches is set to 1 (the initial value is 0 when the logarithmic domain algorithm is used).
由于并行译码算法中每个分支的译码过程相当于串行译码, 现有的并行译码算法 对每个分支的译码块长为 的序列进行译码, 那么在每次分量码译码时所有比特的外 信息产生需要 ( 2倍的并行分支长度) 个时钟周期, 同样给译码时延造成很大的影 响。 发明内容 本发明实施例在于提供一种译码中外信息计算方法、一种译码器以及一种 Turbo码
译码器, 通过改进译码过程中计算外信息的算法, 从而提高 Turbo码译码的速度, 减少 Turbo码译码的时延, 并且保证 Turbo码的译码的可靠性。 Since the decoding process of each branch in the parallel decoding algorithm is equivalent to serial decoding, the existing parallel decoding algorithm decodes the sequence of the coding block length of each branch, then each component code translation When the code is used, the external information of all bits is generated (2 times the length of the parallel branch) clock cycles, which also has a great influence on the decoding delay. SUMMARY OF THE INVENTION Embodiments of the present invention provide a method for decoding Chinese and foreign information, a decoder, and a Turbo code. The decoder improves the decoding speed of the turbo code by improving the algorithm for calculating the external information in the decoding process, reduces the delay of the turbo code decoding, and ensures the reliability of the decoding of the turbo code.
为了达到上述技术效果,本发明实施例提出了一种译码中外信息计算的方法,包括以 下步骤: In order to achieve the above technical effects, an embodiment of the present invention provides a method for decoding Chinese and foreign information calculations, including the following steps:
接收到数据序列; Receiving a sequence of data;
从所述数据序列的末端依次反向计算后向状态度量和支路度量; Backward state metrics and branch metrics are inversely calculated from the end of the data sequence;
在计算完所述后向状态度量和支路度量之前从所述数据序列的首端依次正向计算 前向状态度量和支路度量; Calculating forward state metrics and branch metrics in order from the head end of the data sequence before calculating the backward state metrics and branch metrics;
根据计算出的后向状态度量、 前向状态度量以及支路度量计算输出所述数据序列中 的比特的外信息。 The outer information of the bits in the data sequence is output based on the calculated backward state metric, forward state metric, and branch metric.
相应地, 本发明实施例还公开了一种译码器, 其包括: Correspondingly, an embodiment of the present invention further discloses a decoder, including:
度量计算模块, 用于当接收到数据序列后, 从所述数据序列的末端依次反向计算后 向状态度量和支路度量, 并在计算完所述后向状态度量和支路度量之前从所述数据序列 的首端依次正向计算前向状态度量和支路度量; a metric calculation module, configured to inversely calculate a backward state metric and a branch metric from the end of the data sequence after receiving the data sequence, and before calculating the backward state metric and the branch metric The head end of the data sequence sequentially calculates the forward state metric and the branch metric in turn;
信息计算模块, 用于跟所述度量计算模块计算出的后向状态度量、 前向状态度量以 及支路度量计算输出所述数据序列中的比特的外信息。 And an information calculation module, configured to calculate, by using the backward state metric, the forward state metric, and the branch metric calculated by the metric calculation module, the outer information of the bits in the data sequence.
相应地, 本发明实施例还公开了一种 Turbo码译码器, 包括上述的译码器。 Correspondingly, an embodiment of the present invention further discloses a Turbo code decoder, including the above decoder.
实施本发明实施例, 通过改进译码过程中计算外信息的算法, 将原来计算输出外信 息的顺序由从左到右 (即从首端到末端) 改变为从中间到两边, 从而提高 Turbo码译码 的速度, 减少 Turbo码译码的时延, 并且保证 Turbo码的译码的可靠性。 附图简要说明 In the embodiment of the present invention, by improving the algorithm for calculating the external information in the decoding process, the order of calculating the output external information is changed from left to right (ie, from the head end to the end) to the middle to the two sides, thereby improving the Turbo code. The speed of decoding reduces the delay of Turbo code decoding and ensures the reliability of decoding of Turbo codes. BRIEF DESCRIPTION OF THE DRAWINGS
为了更清楚地说明本发明实施例或现有技术中的技术方案, 下面将对实施例或现 有技术描述中所需要使用的附图作简单地介绍, 显而易见地, 下面描述中的附图仅仅是 本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动性的前提下, 还可以根据这些附图获得其他的附图。 In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below. Obviously, the drawings in the following description are only It is a certain embodiment of the present invention, and other drawings can be obtained from those skilled in the art without any inventive labor.
图 1是现有技术的 Turbo码编码的原理示意图; 1 is a schematic diagram of the principle of Turbo code coding in the prior art;
图 2是现有技术的 Turbo码译码的原理示意图; 2 is a schematic diagram showing the principle of decoding of a Turbo code in the prior art;
图 3是分量码的串行译码算法的原理示意图; 3 is a schematic diagram showing the principle of a serial decoding algorithm of a component code;
图 4是分量码的并行译码算法的原理示意图;
图 5是本发明的译码的方法的一个实施例流程图; 4 is a schematic diagram showing the principle of a parallel decoding algorithm of component codes; Figure 5 is a flow diagram of one embodiment of a method of decoding of the present invention;
图 6是本发明的分量码的译码原理的一个实施例示意图; 6 is a schematic diagram of an embodiment of a decoding principle of a component code of the present invention;
图 7是本发明的分量码的译码原理的又一实施例示意图; 7 is a schematic diagram of still another embodiment of the decoding principle of the component code of the present invention;
图 8是本发明的译码器的一个实施例结构示意图; Figure 8 is a block diagram showing an embodiment of a decoder of the present invention;
图 9是本发明实施例的第一信息计算模块的结构示意图; 9 is a schematic structural diagram of a first information calculation module according to an embodiment of the present invention;
图 10是本发明实施例的第一信息计算输出单元的结构示意图; FIG. 10 is a schematic structural diagram of a first information calculation output unit according to an embodiment of the present invention; FIG.
图 11是本发明的译码器的又一实施例结构示意图; Figure 11 is a block diagram showing another embodiment of the decoder of the present invention;
图 12是本发明实施例的第二信息计算模块的结构示意图; FIG. 12 is a schematic structural diagram of a second information calculation module according to an embodiment of the present invention; FIG.
图 13是本发明实施例的第二信息计算输出单元的结构示意图。 实施本发明的方式 FIG. 13 is a schematic structural diagram of a second information calculation output unit according to an embodiment of the present invention. Mode for carrying out the invention
本发明实施例提供了一种译码的方法、 一种译码器以及一种 Turbo码译码器, 通过 改进译码过程中计算外信息的算法, 从而提高 Turbo码译码的速度, 减少 Turbo码译码的 时延, 并且保证 Turbo码的译码的可靠性。 Embodiments of the present invention provide a decoding method, a decoder, and a Turbo code decoder. By improving an algorithm for calculating external information in a decoding process, the Turbo code decoding speed is improved, and Turbo is reduced. The delay of code decoding, and guarantees the reliability of decoding of the turbo code.
下面结合附图详细说明本发明的优选实施例。 Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
结合图 2, 对分量码的译码算法进行分析。 对于上层的分量码译码器 DEC1, 输入 为系统位接收序列 和第一校验位接收序列 ^¾, k = °'!'Λ,( + 4)―1,输入序列记为 Κ = [Κ0;Κι;Λ ;Κ,;Λ ;ΚΜ] , 其 中 R^ ^),)^)] , R^CR^R^A iR. J , Combined with Figure 2, the decoding algorithm of the component code is analyzed. For the upper component code decoder DEC1, the input is the systematic bit reception sequence and the first parity reception sequence ^ 3⁄4 , k = ° ' ! ' Λ , ( + 4) ― 1 , and the input sequence is denoted as Κ = [Κ 0 ;Κ ι; Λ ;Κ,;Λ ;Κ Μ ] , where R^ ^),)^)] , R^CR^R^A iR. J ,
=[Rt+1 R +2^ ;Ri+3]。 令在时刻 = 时编码器状态记为 , 输入比特 ^, 此时编 码器状态变为 +1。 下层的分量码译码器 DEC2的表示与上层的分量码译码器 DEC1的类 似, 这里以上层的分量码译码器 DEC1为例, 以 MAP算法描述比特的对数似然比(LLR, Log Likelihood Ratio ) 的计算过程。 =[R t+1 R +2 ^ ; R i+3 ]. Let the encoder state be recorded as time at time =, enter bit ^, and the encoder state will change to +1 . The representation of the component code decoder DEC2 of the lower layer is similar to that of the component code decoder DEC1 of the upper layer. Here, the component code decoder DEC1 of the upper layer is taken as an example, and the log likelihood ratio of the bit is described by the MAP algorithm (LLR, Log The calculation process of Likelihood Ratio ).
比特 ( ^ = 0,1,Λ ,^-1 ) 的对数似然比 LLR定义为: The log likelihood ratio of bits ( ^ = 0,1,Λ ,^-1 ) is defined as:
τί 、 , Pr(c, =1IR) τ ί , , Pr(c, =1IR)
L(ck ) = In L(c k ) = In
Pr(c, = 01 R) Pr(c, = 01 R)
令 2 =Pr( =, =mlli), 前向状态度量 =Pr(J^ I =m;), 支路度量 : Pr< = m,ck =i,~Rk) , 后向状态度量 /+( ) = Pr(R¾ I sk+1 = f(m,i)) , 其中 表示 ί = 时刻在 s k =m状态处输入比特 = 后到达的 ί = + 1时刻的状
态。 则有 Let 2 =Pr( =, =mlli), forward state metric =Pr(J^ I =m;), branch metric: Pr < = m,c k =i,~R k ) , backward state metric / + ( ) = Pr ( R 3⁄4 I s k+1 = f(m,i)) , where ί = time at the s k = m state input bit = post-arrived ί = + 1 time State. Then there is
L(ck) = In =ln , L(c k ) = In =ln ,
(1) a"Pw 有如下递推公式: ,
, 其中 ¾ = b(m, i、轰示 t = k时刻在状态 = bi , i)处输入比特 = 后到达 = + 1 时刻的状态 =m。 '经过简化可得:
其中 为只与时刻 k有关的常数, = Pf( = 为先验概率。 (1) a"Pw has the following recursion formula: , where 3⁄4 = b(m, i, the time at which t = k is at the state = bi, i), the input bit = the arrival = the state at the time of + 1 = m . 'Simplified and available: Where is the constant only related to time k, = Pf ( = is a prior probability.
由以上各式可得: From the above formulas are available:
= La (ck ) + Lch (ck ) + Le (ck ) (k = 0,1,2,Λ ,^-l) = L a (c k ) + L ch (c k ) + L e (c k ) (k = 0,1,2,Λ ,^-l)
(2) 其中 ^( )为先验信息, ^ ^)为信道信息, ^( )为外信息并且它是迭代译码 中两个分量码译码器之间传递的信息。 (2) where ^( ) is the a priori information, ^ ^) is the channel information, ^( ) is the outer information and it is the information transmitted between the two component code decoders in the iterative decoding.
^的初始值设为: =1' =o ≠o)。 β^的初始值有如下两种等价的设定方法: The initial value of ^ is set to: =1 ' =o ≠o). The initial value of β^ has the following two equivalent setting methods:
设定 (Κ + 3)时刻各状态的初值如下: Ρκ° = = 0 ≠ 0)。 The initial values of the states at the time of setting (Κ + 3 ) are as follows: Ρκ° = = 0 ≠ 0).
设定 时刻各状态的初值。 由于 Turbo码采用格形终止方法, 即序列 C编码后再输 入 3个尾比特 0。 于是 Turbo编码网格图中相应于尾比特的三段时间内的状态转移只由比 特 0产生。 这样可以由 的递推公式和相应于最后 3个尾比特的网格图, 由 = 1, βκ+3 =0(m≠0)计算出各个 作为初始值。 以下按照方法 (2) 得到^ 的初始值。 Set the initial value of each state at the time. Since the Turbo code uses the trellis termination method, that is, the sequence C is encoded and then 3 tail bits are input. The state transitions in the Turbo coded trellis diagram corresponding to the three bits of the tail bit are then only generated by bit 0. In this way, the recurrence formula and the grid pattern corresponding to the last three tail bits can be calculated as =1, βκ +3 =0(m≠0) as the initial value. The initial value of ^ is obtained by the following method (2).
各比特的先验信息初始值为 0。 2取为工。
由于信道信息 ^ ( )是已知的, 由迭代译码原理可得, 为了得到外信息, 需 The a priori information of each bit has an initial value of zero. 2 is taken as a job. Since the channel information ^ ( ) is known, it can be obtained by the iterative decoding principle. In order to obtain external information,
L{ck ) = \n- "Γ^Γ'0 β[{ιη'0) L{c k ) = \n- "Γ^Γ' 0 β[ {ιη ' 0)
要计算出比特的对数似然比 k k k+i , 进而必须最先计算各个时 刻的参数 ^^" 和^' '。 To calculate the log likelihood ratio kk k+i of the bit, the parameters ^^" and ^'' at each moment must be calculated first.
前面介绍的 MAP算法中需要执行大量的指数运算,在对数域进行各个参数的计算, 令 In the MAP algorithm introduced above, a large number of exponential operations need to be performed, and various parameters are calculated in the logarithmic domain.
= ln = ln
= 1 = 1
l)j(l) l)j(l)
k k
σι 12 , 在 Max-Log-MAP算法中, 作如下近似1 η ^ max{x,y}。 结合0 ^和^ "的定 义可计算出 ™和 " "。 现有技术中在每次分量码译码时, 先反向计算后向状态度量 , 再正向计算前向状态度量"和支路度量 因此外信息全部产生需要正反向各计算一 遍, 即从数据序列的首末两端各计算一遍。 σ ι 12 , in the Max-Log-MAP algorithm, approximates 1 η ^ max { x , y} as follows. Combining the definitions of 0 ^ and ^ " can calculate TM and "". In the prior art, each time the component code is decoded, the backward state metric is calculated first, and then the forward state metric "and the branch" are calculated. The metrics therefore all the external information needs to be calculated once and for all, that is, from the first and last ends of the data sequence.
下面结合图 5示出的本发明的译码的方法的一个实施例流程图, 详细说明译码过程 中计算外信息的算法, 包括如下步骤: The algorithm for calculating the external information in the decoding process is described in detail below with reference to the flowchart of one embodiment of the decoding method of the present invention shown in FIG. 5, including the following steps:
步骤 S501 : 接收到数据序列; 从所述数据序列的末端依次反向计算后向状态度量 和支路度量;在计算完所述后向状态度量和支路度量之前从所述数据序列的首端依次正 向计算前向状态度量和支路度量; Step S501: receiving a data sequence; sequentially calculating a backward state metric and a branch metric from the end of the data sequence; from the head end of the data sequence before calculating the backward state metric and the branch metric Forward direction metrics and branch metrics are calculated in turn;
步骤 S502: 由计算出的后向状态度量、 前向状态度量以及支路度量计算输出所述 数据序列中的比特的外信息。 Step S502: Calculate out-of-band information of the bits in the data sequence by the calculated backward state metric, forward state metric, and branch metric.
需要说明的是, 上述实施例为改进后的分量码的串行译码的方法, 具体地, 下面 结合图 6示出的本发明的分量码的译码原理的一个实施例示意图, 详细说明本发明的分 量码的译码方法。 从对数似然比的计算公式(1 ) 中可以得知, 计算 时只需要已知 当前时刻 的前向状态度量0^、 下一时刻 的后向状态度量 以及时刻 和时刻 两个时刻之间的支路度量 ^, 因此, 本发明实施例从接收的数据序列的末端依次 反向计算后向状态度量和支路度量, 即从接收到数据序列后的最后时刻到第 1时刻分别
计算各个时刻的后向状态度量和支路度量, 并在计算完所述后向状态度量和支路度量之 前从所述数据序列的首端依次正向计算前向状态度量和支路度量, 即从接收到数据序列 后的第 1时刻到最后时刻分别计算各个时刻的前向状态度量和支路度量, 最优地, 从接 收数据的首末两端同时相向计算 °^''," ) (其中 = 0,1,2,Λ ) 和 (其中 k ^ K ~ K - 2,A ), 即从所述数据序列的末端依次反向计算后向状态度量和支路度量 的同时, 从所述数据序列的首端依次正向计算前向状态度量和支路度量, 当两个方向的 计算 "相交"后, 即反向计算的后向状态度量个数与正向计算的前向状态度量个数之和 大于所述分支的数据序列的码长个数后, 由计算出的后向状态度量 A™+1、 前向状态度量 m以及支路度量 结合公式 (1 ) 能够计算当前时刻的 "^ ), 然后由 结合公 式 (2) 计算出外信息, 即可以计算输出两个比特的对数似然比和外信息, 当计算出所 有比特的对数似然比和外信息后, 将所述外信息作为先验信息, 进行下一次的分量码的 译码, 经过多次迭代直到外信息趋于稳定后, 才对似然比进行硬判决, 得出最佳估值。 具体地, 在相向计算 "相交"后, 当块长个数为奇数 Κ = 2· + 1时, 其中 j为预设的固定 的整数值,首先会计算所述数据序列中第 j+1个比特的 LLR值和外信息, 即比特 " ^的 LLR 值和外信息, 之后依次可以计算第 j+1-q个和第 j+1+q个两个比特的对数似然比信息和外 信息, 其中 q的取值依次从 1到』, 即之后依次可以计算两个比特 和£ 的 LLR值和外 信息, 其中 q的取值依次从 1到 j; 当块长个数为偶数 = 2 ^'时, 其中 j为预设的固定的整 数值,首先会计算所述数据序列中第 j个和第 j+1个两个比特的对数似然比信息和外信息, 即比特 ^-1和 C]的 LLR值和外信息,之后依次可以计算所述数据序列中第 j-q个和第 j+1+q 个两个比特的对数似然比信息和外信息,其中 q的取值依次从 1到 j-l, 即之后依次可以计 算两个比特 ^ 和^ 的 LLR值和外信息, 其中 q的取值依次从 1到 j-l。 It should be noted that the foregoing embodiment is a method for serial decoding of the improved component code. Specifically, a schematic diagram of an embodiment of the decoding principle of the component code of the present invention shown in FIG. 6 is described in detail below. A method of decoding a component code of the invention. It can be known from the calculation formula (1) of the log-likelihood ratio that only the forward state metric 0 ^ of the current time, the backward state metric of the next time, and the time and time are required for the calculation. The branch metric ^, therefore, the embodiment of the present invention reversely calculates the backward state metric and the branch metric from the end of the received data sequence, that is, from the last time after receiving the data sequence to the first time respectively Calculating a backward state metric and a branch metric at each moment, and calculating a forward state metric and a branch metric from the head end of the data sequence before calculating the backward state metric and the tributary metric, ie The forward state metric and the branch metric at each moment are respectively calculated from the first moment to the last moment after receiving the data sequence, and optimally, from the first and the last ends of the received data, the opposite ends are calculated °^'', ") Wherein = 0,1,2,Λ ) and (where k ^ K ~ K - 2, A ), ie, the backward state metric and the branch metric are inversely calculated from the end of the data sequence, The head end of the data sequence calculates the forward state metric and the branch metric in turn. When the calculation of the two directions is "intersection", the backward calculated state metric and the forward calculated forward state metric are calculated. After the sum of the numbers is greater than the number of code lengths of the data sequence of the branch, the calculated backward state metric A TM +1 , the forward state metric m, and the branch metric combining formula (1 ) can calculate the current moment. ^ ), and then calculated by combining formula (2) Information, that is, the log likelihood ratio and the outer information of the output two bits can be calculated. After calculating the log likelihood ratio and the outer information of all the bits, the outer information is used as the prior information, and the next component is performed. The decoding of the code, after repeated iterations until the external information tends to be stable, makes a hard decision on the likelihood ratio and obtains the best estimate. Specifically, after the phase intersection "intersection", when the block length is odd Κ = 2 · + 1 , where j is a preset fixed integer value, the j+1th in the data sequence is first calculated. The LLR value and the outer information of the bit, that is, the LLR value and the outer information of the bit "^, and then the log likelihood ratio information of the j+1-q and j+1+q two bits can be calculated in turn. Information, where the value of q is sequentially from 1 to 』, that is, the LLR value and the external information of two bits and £ can be calculated in turn, wherein the values of q are sequentially from 1 to j; when the number of blocks is even number = 2 ^', where j is a preset fixed integer value, firstly calculating the log likelihood ratio information and the outer information of the jth and j+1th two bits in the data sequence, that is, the bit ^- The LLR value and the outer information of 1 and C ], and then the log likelihood ratio information and the outer information of the jqth and j+1+q two bits in the data sequence may be sequentially calculated, where the value of q The LLR value and the external information of the two bits ^ and ^ can be calculated sequentially from 1 to jl, that is, the values of q are sequentially from 1 to jl.
需要说明的是, 每次译码过程中的 j可以为不同的整数值, 即每次译码过程中的数 据序列的码长个数可以不同, 因此, 本发明实施例的译码方法适用于不同码块长度的译 码。 It should be noted that the j in the decoding process may be a different integer value, that is, the code length of the data sequence in each decoding process may be different. Therefore, the decoding method in the embodiment of the present invention is applicable to Decoding of different code block lengths.
通过上述实施例,加速的串行译码算法将原来计算输出 LLR值和外信息的顺序由从 左到右(即从首端到末端)改变为从中间到两边,改进了译码过程中计算外信息的算法, 达到了译码提速的目的, 而且计算是准确的, 不会有性能损失, 保证了 Turbo码译码的 可靠性。
可以理解, 本实施例步骤 S501和结合图 6的具体描述中, "从所述数据序列的末端 依次反向计算后向状态度量和支路度量,并在计算完所述后向状态度量和支路度量之前 从所述数据序列的首端依次正向计算前向状态度量和支路度量", 也可以理解为 "数据 序列具有两端点,从所述数据序列的一端向内依次计算该数据序列的后向状态度量和支 路度量,并在计算完所述后向状态度量和支路度量之前从所述数据序列的相对另一端向 内依次计算该数据序列的前向状态度量和支路度量"。 末端和首端是可以互换的。 末端 可以代表所接收到的数据序列的起始端, 也可以代表数据序列的终止端。本发明实施例 中, 首端和末端可用来表示数据序列两端于相反方向的意义。 Through the above embodiment, the accelerated serial decoding algorithm changes the order of calculating the output LLR value and the external information from left to right (ie, from the head end to the end) to the middle to the both sides, improving the calculation in the decoding process. The algorithm of external information achieves the purpose of speeding up decoding, and the calculation is accurate, there is no performance loss, and the reliability of Turbo code decoding is guaranteed. It can be understood that, in step S501 of this embodiment and the specific description in conjunction with FIG. 6, "the backward state metric and the branch metric are inversely calculated from the end of the data sequence, and the backward state metric and the branch are calculated. Before the road metric, the forward state metric and the branch metric are calculated forwardly from the head end of the data sequence. It can also be understood as "the data sequence has two ends, and the data sequence is sequentially calculated from one end of the data sequence. a backward state metric and a branch metric, and the forward state metric and the branch metric of the data sequence are calculated in turn from the opposite end of the data sequence before the backward state metric and the tributary metric are calculated ". The end and the head end are interchangeable. The end may represent the beginning of the received data sequence or the terminating end of the data sequence. In the embodiment of the present invention, the head end and the end end can be used to indicate the meaning of the opposite ends of the data sequence in opposite directions.
需要说明的是, 上述实施例为改进后的分量码的串行译码的方法, 具体地, 当上 述实施例接收到的数据序列为并行接收到的至少两个分支的数据序列时,需要进行分量 码的并行译码, 下面结合图 7示出的本发明的分量码的译码原理的又一实施例示意图, 详细说明分量码的并行译码的方法。译码器并行接收到至少两个分支的数据序列后, 本 实施例假设为 P个分支的数据序列, 其中 P 2, 每个分支的译码过程与上述改进的串行 译码类似,本实施例从各个分支的数据序列的末端依次反向计算后向状态度量和支路度 量, 即从接收到各个分支的数据序列后的最后时刻到第 1时刻分别计算各个时刻的后向 状态度量和支路度量,并在计算完所述各个分支的后向状态度量和支路度量之前从各个 分支的数据序列的首端依次正向计算前向状态度量和支路度量, 即从接收到各个分支的 数据序列后的第 1时刻到最后时刻分别计算各个时刻的前向状态度量和支路度量, 最优 地, 各个分支从接收数据的首末两端同时相向计算(^'" ) (其中 fe = G,l,2,A ) 和 (其中 = Ρ _ 1,ίΓ Ρ _ 2,Λ ), 即从各个分支的数据序列的末端依次反向计算 后向状态度量和支路度量的同时,从各个分支的数据序列的首端依次正向计算前向状态 度量和支路度量, 当两个方向的计算 "相交"后, 即当所述分支的反向计算的后向状态 度量个数与正向计算的前向状态度量个数之和大于所述分支的数据序列的码长个数后, 由计算出的后向状态度量 Am+1、 前向状态度量0^以及支路度量 ^, 结合公式 (1 ) 能 够计算当前时刻的 "^ ), 然后由 结合公式 (2) 计算出外信息, 即可以计算输出 两个比特的对数似然比和外信息, 当计算出所有比特的对数似然比和外信息后, 将所述 外信息作为先验信息, 进行下一次的分量码的译码, 经过多次迭代直到外信息趋于稳定 后, 才对似然比进行硬判决, 得出最佳估值。 具体地, 在相向计算 "相交"后, 当所述 分支数据序列块长个数为奇数^^ = 2^' + 1时, 其中 j为预设的固定的整数值, 首先会计算
产生所述分支数据序列中第 j+1个比特的 LLR值和外信息, 即比特 ^的 LLR值和外信息, 之后依次可以计算第 J+1-q个和第 j+1+q个两个比特的对数似然比信息和外信息, 其中 q 的取值依次从 1到 j, 即之后依次可以计算两个比特""^ ^和 的 LLR值和外信息, 其中 q 的取值依次从 1到 J ; 当所述分支数据序列块长个数为偶数^^:2"/'时, 其中 j为预设的固 定的整数值, 首先会计算所述分支数据序列中第 j个和第 j+1个两个比特的对数似然比信 息和外信息, 即比特 ^'-1和 的 LLR值和外信息, 之后依次可以计算所述数据序列中第 j-q个和第 j+1+q个两个比特的对数似然比信息和外信息, 其中 q的取值依次从 1到 j-l, 即 之后依次可以计算两个比特 C卜 和 C 的 LLR值和外信息, 其中 q的取值依次从 1到 j-1。 It should be noted that the above embodiment is a method for serial decoding of the improved component code. Specifically, when the data sequence received by the foregoing embodiment is a data sequence of at least two branches received in parallel, it needs to be performed. Parallel decoding of component codes, and a method for parallel decoding of component codes will be described in detail below with reference to a further embodiment of the decoding principle of the component code of the present invention shown in FIG. After the decoder receives the data sequence of at least two branches in parallel, the embodiment assumes a data sequence of P branches, where P 2 , the decoding process of each branch is similar to the improved serial decoding described above, and the implementation For example, the backward state metric and the branch metric are inversely calculated from the end of the data sequence of each branch, that is, the backward state metric and the branch at each moment are calculated from the last time after receiving the data sequence of each branch to the first time. a path metric, and forwardly calculating forward state metrics and branch metrics from the head end of each branch of the data sequence before calculating the backward state metrics and branch metrics of the respective branches, ie, from receiving the respective branches The forward state metric and the branch metric at each moment are respectively calculated from the first moment to the last moment after the data sequence, and optimally, each branch is simultaneously calculated from the first and last ends of the received data (^'" ) (where fe = G,l,2,A ) and (where = Ρ _ 1 , Γ Ρ _ 2 , Λ ), that is, from the end of the data sequence of each branch, the backward state metric and the branch metric are simultaneously calculated The forward state metric and the branch metric are calculated forward from the head end of the data sequence of each branch, and when the calculation of the two directions is "intersect", that is, the backward state metric of the branch is inversely calculated After the sum of the forward state metrics of the forward calculation is greater than the code length of the data sequence of the branch, the calculated backward state metric A m+1 , the forward state metric 0 ^, and the branch metric ^, Combine the formula (1) to calculate the "^" at the current moment, and then calculate the outer information by combining the formula (2), that is, the log likelihood ratio and the outer information of the output two bits can be calculated, when all the bits are calculated After the log likelihood ratio and the outer information, the outer information is used as the prior information, and the next component code is decoded. After multiple iterations until the external information tends to be stable, the likelihood ratio is hardly determined. , to get the best valuation. Specifically, after the phase intersection "intersection", when the length of the branch data sequence block is an odd number ^^ = 2 ^' + 1 , where j is a preset fixed integer value, first calculated Generating the LLR value and the outer information of the j+1th bit in the branch data sequence, that is, the LLR value and the outer information of the bit ^, and then calculating the J+1-q and the j+1+q two in order The log likelihood ratio information and the outer information of the bits, wherein the values of q are sequentially from 1 to j, that is, the LLR values and the outer information of the two bits ""^^ and then can be calculated in turn, wherein the values of q are sequentially From 1 to J; when the length of the branch data sequence block is an even number ^^: 2 "/', where j is a preset fixed integer value, the jth sum in the branch data sequence is first calculated The log likelihood ratio information and the outer information of the j+1th two bits, that is, the LLR value and the outer information of the bit ^'- 1, and then the jqth and j+1th in the data sequence may be sequentially calculated. +q log-likelihood ratio information and outer information of two bits, wherein the value of q is sequentially from 1 to jl, that is, the LLR value and the outer information of two bits C and C can be calculated in turn, wherein q The values are from 1 to j-1.
需要说明的是, 每次译码过程中的 j可以为不同的整数值, 即每次译码过程中的数 据序列的码长个数可以不同, 因此, 本发明实施例的译码方法适用于不同码块长度的译 码。 It should be noted that the j in the decoding process may be a different integer value, that is, the code length of the data sequence in each decoding process may be different. Therefore, the decoding method in the embodiment of the present invention is applicable to Decoding of different code block lengths.
通过上述实施例,加速的并行译码算法将原来每个分支计算输出 LLR值和外信息的 顺序由从左到右 (即从首端到末端) 改变为从中间到两边, 达到了译码提速的目的, 而 且计算是准确的, 不会有性能损失, 保证了 Turbo码译码的可靠性。 Through the above embodiment, the accelerated parallel decoding algorithm changes the order of outputting the LLR value and the external information of each branch from left to right (ie, from the head end to the end) to the middle to the two sides, and achieves the decoding speed increase. The purpose, and the calculation is accurate, there will be no performance loss, and the reliability of Turbo code decoding is guaranteed.
需要说明的是, 典型的 Turbo码译码过程为 2维的译码过程, 即只有两层分量码译 码器, 相应地, 从迭代的译码结构可以推广到多维的译码, 即有多层分量码译码器, 该 分量码译码器的译码过程与典型译码过程中的分量码译码器的译码过程相似, 因此, 本 发明实施例的译码的方法除了可以应用在典型的 Turbo码译码过程中外, 即除了可以应 用在 2维的译码过程中外, 还可以应用到 M维的 Turbo码译码过程中, 其中 M 2。 It should be noted that the typical Turbo code decoding process is a two-dimensional decoding process, that is, only two layer component code decoders, and correspondingly, the iterative decoding structure can be extended to multi-dimensional decoding, that is, there are many a layer component code decoder, the decoding process of the component code decoder is similar to the decoding process of the component code decoder in a typical decoding process. Therefore, the decoding method of the embodiment of the present invention can be applied in addition to In the typical Turbo code decoding process, in addition to being applicable to the 2-dimensional decoding process, it can also be applied to the M-dimensional Turbo code decoding process, where M 2 .
需要说明的是, 本发明的译码方法适用于所有以 Turbo码作为信道编码的通信系统 以及一般的 Turbo码译码器。 It should be noted that the decoding method of the present invention is applicable to all communication systems using Turbo codes as channel coding and general turbo code decoders.
下面结合图 8示出的本发明的译码器的第一实施例结构示意图, 说明本发明实施例 的译码器的结构, 包括: The structure of the decoder of the embodiment of the present invention is described below with reference to the structure of the first embodiment of the decoder of the present invention shown in FIG.
第一度量计算模块 81, 用于当接收到数据序列后, 从所述数据序列的末端依次反 向计算后向状态度量和支路度量, 并在计算完所述后向状态度量和支路度量之前从所述 数据序列的首端依次正向计算前向状态度量和支路度量; a first metric calculation module 81, configured to inversely calculate a backward state metric and a branch metric from the end of the data sequence after receiving the data sequence, and calculate the backward state metric and the branch after calculating Forward state metrics and branch metrics are calculated forwardly from the head end of the data sequence before the metric;
第一信息计算模块 82, 用于由第一度量计算模块 81计算出的后向状态度量、 前向 状态度量以及支路度量计算输出所述数据序列中的比特的外信息。 The first information calculation module 82 is configured to calculate, by the first metric calculation module 81, the backward state metric, the forward state metric, and the branch metric calculation to output the outer information of the bits in the data sequence.
具体地, 本实施例对应上述的改进的串行译码方法, 译码器为分量码串行译码器。
如图 9示出的本发明实施例的第一信息计算模块的结构示意图, 第一信息计算模块 82包 括第一信息计算输出单元 821。 最优地, 第一度量计算模块 81从接收数据的首末两端同 时相向计算( ''," 1) (¾φ ^ = 0'1'2'Λ ) 禾口(^" ,Α") (其中 = — 1, _ 2,Λ ), 即 从所述数据序列的末端依次反向计算后向状态度量和支路度量的同时,从所述数据序列 的首端依次正向计算前向状态度量和支路度量, 当两个方向的计算"相交"后, 即反向 计算的后向状态度量个数与正向计算的前向状态度量个数之和大于所述分支的数据序 列的码长个数后, 第一信息计算输出单元 821由计算出的后向状态度量^" +1、 前向状态 度量0 ^以及支路度量 ^, 结合公式 (1 ) 能够计算当前时刻的 "^ ), 然后由 " )结 合公式 (2) 计算出外信息, 即可以计算输出两个比特的对数似然比和外信息, 当计算 出所有比特的对数似然比和外信息后, 将所述外信息作为先验信息, 传送到下一分量码 译码器进行下一次的分量码的译码, 经过多次迭代直到外信息趋于稳定后, 才对似然比 进行硬判决, 得出最佳估值。 具体地, 如图 10示出的本发明实施例的第一信息计算输出 单元的结构示意图, 第一信息计算输出单元 821包括第一信息计算子单元 8211和第二信 息计算子单元 8212, 在相向计算 "相交"后, 当块长个数为奇数 = 2^' + 1时, 其中 j为 预设的固定的整数值, 第一信息计算子单元 8211首先会计算所述数据序列中第 J+l个比 特的 LLR值和外信息, 即比特 的 LLR值和外信息, 之后依次可以计算第 j+1-q个和第 j+1+q个两个比特的对数似然比信息和外信息, 其中 q的取值依次从 1到 j, 即之后依次可 以计算两个比特 和 + 的 LLR值和外信息, 其中 q的取值依次从 1到 j ; 当块长个数为 偶数 = 2·时, 其中 j为预设的固定的整数值, 第二信息计算子单元 8212首先会计算所 述数据序列中第 j个和第 j+1个两个比特的对数似然比信息和外信息, 即比特 和 的 LLR值和外信息, 之后依次可以计算所述数据序列中第 j-q个和第 j+1+q个两个比特的对 数似然比信息和外信息,其中 q的取值依次从 1到 j-l,即之后依次可以计算两个比特^1 -》 和 的 LLR值和外信息, 其中 q的取值依次从 1到 j-1。 Specifically, the present embodiment corresponds to the above improved serial decoding method, and the decoder is a component code serial decoder. FIG. 9 is a schematic structural diagram of a first information calculation module according to an embodiment of the present invention, and the first information calculation module 82 includes a first information calculation output unit 821. Optimally, the first metric calculation module 81 simultaneously calculates (''," 1 ) from the first and last ends of the received data (3⁄4φ ^ = 0 ' 1 ' 2 ' Λ ) and (^" , Α ") (where = - 1, _ 2, Λ ), that is, while calculating the backward state metric and the branch metric from the end of the data sequence, the forward state is calculated in the forward direction from the head end of the data sequence Metrics and branch metrics, when the two directions of the calculation "intersect", that is, the sum of the backward calculated backward state metric and the forward calculated forward state metric is greater than the code of the branch data sequence After a long number, the first information calculation output unit 821 can calculate the current position "^) from the calculated backward state metric ^" +1 , the forward state metric 0 ^, and the branch metric ^, in combination with the formula (1). Then, the external information is calculated by " ) combined with the formula (2), that is, the log likelihood ratio and the outer information of the output two bits can be calculated, and after calculating the log likelihood ratio and the outer information of all the bits, the The outer information is transmitted as a priori information to the next component code decoder for the next component code. Code, after several iterations until the outer information stabilize, fishes likelihood ratio hard decision, optimum valuation. Specifically, a schematic diagram of a first information calculation output unit of the embodiment of the present invention as shown in FIG. 10, the first information calculation output unit 821 includes a first information calculation subunit 8211 and a second information calculation subunit 8212, in the opposite direction After calculating "intersection", when the number of block lengths is odd = 2 ^' + 1 , where j is a preset fixed integer value, the first information calculation subunit 8211 first calculates the J+ l in the data sequence. The LLR value and the outer information of the bit, that is, the LLR value and the outer information of the bit, and then the log likelihood ratio information and the outer information of the j+1-q and j+1+q two bits can be calculated in turn. , wherein the value of q is sequentially from 1 to j, that is, the LLR value and the external information of two bits and + can be calculated in turn, wherein the values of q are sequentially from 1 to j; when the number of blocks is even number = 2 When j is a preset fixed integer value, the second information calculation subunit 8212 first calculates log likelihood ratio information and external information of the jth and j+1th bits in the data sequence. , that is, the LLR value and the outer information of the bit sum, and then the data sequence can be calculated in turn The log likelihood ratio information and the outer information of the jqth and j+1+q two bits, wherein the values of q are sequentially from 1 to jl, that is, two bits ^ 1 -" and LLR value and external information, where q takes the value from 1 to j-1.
需要说明的是, 每次译码过程中的 j可以为不同的整数值, 即每次译码过程中的数 据序列的码长个数可以不同, 因此, 本发明实施例的译码方法适用于不同码块长度的译 码。 It should be noted that the j in the decoding process may be a different integer value, that is, the code length of the data sequence in each decoding process may be different. Therefore, the decoding method in the embodiment of the present invention is applicable to Decoding of different code block lengths.
需要说明的是, 上述实施例为改进后的分量码串行译码器的结构, 具体地, 当上 述接收到的数据序列为并行接收到的至少两个分支的数据序列时, 需要进行分量码的并
行译码, 下面结合图 11示出的本发明的译码器的第二实施例结构示意图, 说明本发明实 施例的译码器的结构, 包括: It should be noted that, the foregoing embodiment is a structure of the improved component code serial decoder. Specifically, when the received data sequence is a data sequence of at least two branches received in parallel, a component code is required. And Line decoding, the structure of the decoder of the embodiment of the present invention is described below with reference to the structure of the second embodiment of the decoder of the present invention shown in FIG.
第二度量计算模块 111, 用于当并行接收到至少两个分支的数据序列后, 从各个分 支的数据序列的末端依次反向计算后向状态度量和支路度量, 并在计算完所述各个分支 的后向状态度量和支路度量之前从各个分支的数据序列的首端依次正向计算前向状态 度量和支路度量; The second metric calculation module 111 is configured to, after receiving the data sequence of the at least two branches in parallel, sequentially calculate the backward state metric and the branch metric from the end of the data sequence of each branch, and calculate each of the The backward state metric and the branch metric of the branch are forwardly calculated from the head end of each branch of the data sequence to the forward state metric and the branch metric;
第二信息计算模块 112,用于由第二度量计算模块 111计算出的后向状态度量、前向 状态度量以及支路度量计算输出所述分支的数据序列中的比特的外信息。 The second information calculation module 112 is configured to calculate, by the second metric calculation module 111, the backward state metric, the forward state metric, and the branch metric calculation to output the outer information of the bits in the data sequence of the branch.
具体地, 本实施例对应上述的改进的并行译码方法, 本实施例的译码器为分量码 并行译码器。 如图 12示出的本发明实施例的第二信息计算模块的结构示意图, 第二信息 计算模块 112包括第二信息计算输出单元 1121。 第二度量计算模块 111在并行接收到至少 两个分支的数据序列后, 本实施例假设为 P个分支的数据序列, 其中 P 2, 每个分支的 译码过程与上述改进的串行译码类似, 最优地, 第二度量计算模块 111从各个分支的接 收数据的首末两端同时相向计算 ^'',α +1 ) (其中 fc = 0,l,2,A ) 和 ^Γ', ) (其中 k = Kp - Kp - 2, ), 即从各个分支的数据序列的末端依次反向计算后向状态度量和 支路度量的同时, 从各个分支的数据序列的首端依次正向计算前向状态度量和支路度 量, 当两个方向的计算 "相交"后, 即当所述分支的反向计算的后向状态度量个数与正 向计算的前向状态度量个数之和大于所述分支的数据序列的码长个数后,第二信息计算 输出单元 1121由计算出的后向状态度量 ^"«、前向状态度量 以及支路度量 ^, 结合 公式(1 ) 能够计算当前时刻的 "^ ), 然后由 结合公式(2)计算出外信息, 即可 以计算输出两个比特的对数似然比和外信息, 当计算出所有比特的对数似然比和外信息 后,将所述外信息作为先验信息,传送到下一分量码译码器进行下一次的分量码的译码, 经过多次迭代直到外信息趋于稳定后,才对似然比进行硬判决,得出最佳估值。具体地, 如图 13示出的本发明实施例的第二信息计算输出单元的结构示意图,第二信息计算输出 单元 1121包括第三信息计算子单元 11211和第四信息计算子单元 11212, 在相向计算 "相 交"后, 当所述分支数据序列块长个数为奇数^^^2 1时, 第三信息计算子单元 11211 首先会计算产生所述分支数据序列中第 j+1个比特的 LLR值和外信息, 即比特 的 LLR 值和外信息, 之后依次可以计算第 j+1-q个和第 j+1+q个两个比特的对数似然比信息和外
信息, 其中 q的取值依次从 1到 j, 即之后依次可以计算两个比特^^和 的 LLR值和外 信息, 其中 q的取值依次从 1到 j; 当所述分支数据序列块长个数为偶数 p: 2 "/'时, 第四 信息计算子单元 11212首先会计算所述分支数据序列中第 j个和第 j+1个两个比特的对数 似然比信息和外信息, 即比特 和 的 LLR值和外信息, 之后依次可以计算所述数据 序列中第 j-q个和第 j+1+q个两个比特的对数似然比信息和外信息, 其中 q的取值依次从 1 到 j-l, 即之后依次可以计算两个比特 -^和 ' 的 LLR值和外信息, 其中 q的取值依次 从 1到 j-l。 Specifically, the embodiment corresponds to the improved parallel decoding method described above, and the decoder of this embodiment is a component code parallel decoder. FIG. 12 is a schematic structural diagram of a second information calculation module according to an embodiment of the present invention, and the second information calculation module 112 includes a second information calculation output unit 1121. After the second metric calculation module 111 receives the data sequence of at least two branches in parallel, the embodiment assumes a data sequence of P branches, where P 2 , the decoding process of each branch and the improved serial decoding described above Similarly, optimally, the second metric calculation module 111 simultaneously calculates ^'', α +1 ) (where fc = 0, l, 2, A) and ^Γ from the first and second ends of the received data of the respective branches. , ) (where k = K p - K p - 2, ), that is, from the end of the data sequence of each branch, the backward state metric and the branch metric are inversely calculated, and the first end of the data sequence of each branch is sequentially Forward calculation of forward state metrics and branch metrics, when the calculations in the two directions "intersect", ie, the number of backward state metrics calculated in the reverse direction of the branch and the forward metrics calculated in the forward direction After the sum is greater than the code length of the data sequence of the branch, the second information calculation output unit 1121 combines the calculated backward state metric ^"«, the forward state metric, and the branch metric ^, in combination with the formula (1) Ability to calculate the "^" of the current time, and then calculate by combining formula (2) External information, that is, the log likelihood ratio and the outer information of the output two bits can be calculated. After calculating the log likelihood ratio and the outer information of all the bits, the external information is transmitted as a priori information to the next The component code decoder performs the decoding of the next component code. After several iterations until the external information tends to be stable, the likelihood ratio is hard-decised and the best estimate is obtained. Specifically, as shown in the structure of the second information calculation output unit of the embodiment of the present invention as shown in FIG. 13, the second information calculation output unit 1121 includes a third information calculation subunit 11211 and a fourth information calculation subunit 11212, in the opposite direction. After calculating the "intersection", when the length of the branch data sequence block is an odd number ^^^ 2 1 , the third information calculation sub-unit 11211 first calculates an LLR that generates the j+1th bit in the branch data sequence. The value and the outer information, that is, the LLR value and the outer information of the bit, and then the log likelihood ratio information of the j+1-q and j+1+q two bits can be calculated in turn Information, wherein the value of q is sequentially from 1 to j, that is, the LLR value and the outer information of the two bits ^^ and can be calculated in turn, wherein the value of q is sequentially from 1 to j; when the branch data sequence is long When the number is even p: 2 "/', the fourth information calculation subunit 11212 first calculates the log likelihood ratio information and the outer information of the jth and j+1th bits in the branch data sequence. , that is, the LLR value and the outer information of the bit sum, and then the log likelihood ratio information and the outer information of the jqth and j+1+q two bits in the data sequence may be sequentially calculated, where the value of q The LLR value and the external information of two bits -^ and ', in turn, can be calculated sequentially from 1 to jl, wherein the values of q are sequentially from 1 to jl.
需要说明的是, 每次译码过程中的 j可以为不同的整数值, 即每次译码过程中的数 据序列的码长个数可以不同, 因此, 本发明实施例的译码方法适用于不同码块长度的译 码。 It should be noted that the j in the decoding process may be a different integer value, that is, the code length of the data sequence in each decoding process may be different. Therefore, the decoding method in the embodiment of the present invention is applicable to Decoding of different code block lengths.
本发明实施例的 Turbo码译码器除了包括交织器、 解交织器、 判决器外, 还包括上 述实施例的译码器,所述译码器可以为分量码串行译码器,也可以为分量码并行译码器。 通过改进的分量码译码器, 将原来计算输出 LLR值和外信息的顺序由从左到右 (即从首 端到末端) 改变为从中间到两边, 达到了译码提速的目的, 而且计算是准确的, 不会有 性能损失, 保证了 Turbo码译码的可靠性。 In addition to the interleaver, the deinterleaver, and the decider, the turbo code decoder of the embodiment of the present invention further includes the decoder of the foregoing embodiment, and the decoder may be a component code serial decoder, or It is a component code parallel decoder. Through the improved component code decoder, the order of calculating the output LLR value and the external information is changed from left to right (ie, from the head end to the end) to the middle to the two sides, and the purpose of decoding speed is achieved, and the calculation is performed. It is accurate, there is no performance loss, and the reliability of Turbo code decoding is guaranteed.
需要说明的是, 典型的 Turbo码译码器为 2维的译码过程, 即只有两层分量码译码 器, 相应地, 从迭代的译码结构可以推广到多维的译码, 即有多层分量码译码器, 该分 量码译码器的译码过程与典型译码过程中的分量码译码器的译码过程相似, 因此, 本发 明的译码器以及 Turbo码译码器除了可以应用在典型的 Turbo码译码过程中外, 即除了可 以应用在 2维的译码过程中外, 还可以应用到 M维的 Turbo码译码过程中, 其中 M 2。 It should be noted that a typical Turbo code decoder is a 2-dimensional decoding process, that is, only a two-layer component code decoder, and accordingly, the iterative decoding structure can be extended to multi-dimensional decoding, that is, there are many a layer component code decoder, the decoding process of the component code decoder is similar to the decoding process of the component code decoder in a typical decoding process, and therefore, the decoder and the turbo code decoder of the present invention are It can be applied in the typical Turbo code decoding process, that is, in addition to being applicable to the 2-dimensional decoding process, it can also be applied to the M-dimensional Turbo code decoding process, where M 2 .
需要说明的是,本发明的译码器以及 Turbo码译码器适用于所有以 Turbo码作为信道 编码的通信系统。 It should be noted that the decoder of the present invention and the turbo code decoder are applicable to all communication systems using Turbo codes as channel coding.
下面通过数学理论来比较原算法和本发明的加速算法的译码速度。 设 Turbo编码块长为 。 由尾比特计算得到各状态的 作为初始值。 芯片的时钟 频率为 F MHz。假设每个时钟周期(cycle)可以将一个系统位软比特和相应的两个校验 位软比特写入到 Turbo译码器内部的输入数据缓存中。 译码迭代次数为 。 The decoding speed of the original algorithm and the acceleration algorithm of the present invention is compared by mathematical theory. Let the Turbo code block be long. The state of each state is calculated from the tail bit as an initial value. The chip's clock frequency is F MHz. It is assumed that one system bit soft bit and the corresponding two parity bit soft bits can be written into the input data buffer inside the Turbo decoder every cycle. The number of decoding iterations is .
一般的串行算法的译码速度为:
θ— 6 Mbit F The decoding speed of a general serial algorithm is: Θ— 6 Mbit F
speed - -Mbit/s Speed - -Mbit/s
(K + 2K-2-Iter) Alter + \ (K + 2K-2-Iter) Alter + \
/OF.10。) 本发明的加速的串行算法的译码速度为: /OF.10. The decoding speed of the accelerated serial algorithm of the present invention is:
, 10— 6 Mbit F , 10- 6 Mbit F
speed = -Mbit/s Speed = -Mbit/s
(K + K-2- Iter) liter + \ (K + K-2- Iter) liter + \
( -106) 在并行译码算法中, 设并行分支数为^, 则每个分支长度为 /P, 分支两端《 和 ^的训练序列长度都为 L (第一分支的 "和最后一分支的 ^不需要训练)。 在译码之 前先用 L个cycle (此时需要双端口 RAM: Random Access Memory, 如果用单端口 RAM, 则需要 2 L个 CyCie ) 计算出每个分支的《和 的初始值。 ( -10 6 ) In the parallel decoding algorithm, if the number of parallel branches is ^, then the length of each branch is /P , and the lengths of the training sequences at both ends of the branch are L (the first branch) and the last one. The branch does not need to be trained.) Use L cycles before decoding (this requires dual port RAM: Random Access Memory, if you use single port RAM, you need 2 L C y C i e ) The initial value of the branch's sum.
本发明的加速的并行算法译码速度为: The accelerated parallel algorithm decoding speed of the present invention is:
Κ · 10— 6 Mbit Κ · 10- 6 Mbit
speed -Mbit/s Speed -Mbit/s
[K + (— + L)-2-Iter] l + 2Iter-(— +—) [K + (- + L)-2-Iter] l + 2Iter-(- +-)
P K 由前面的公式可以看出, 采用串行译码装置时, 本发明的加速算法比原算法的译 码速度几乎翻倍,可以有效的减少译码时延。采用并行译码装置时,如果译码速度相同, 则本发明的加速算法所需的并行分支数是原算法的一半, 由于分支数减半, 训练序列也 相应的减半, 性能会有提升。 如果分支数相同, 则本发明的加速算法与原算法相比, 性 能相同, 但可以达到更高的译码速度。 P K can be seen from the previous formula. When the serial decoding device is used, the acceleration algorithm of the present invention almost doubles the decoding speed of the original algorithm, and the decoding delay can be effectively reduced. When the parallel decoding device is used, if the decoding speed is the same, the number of parallel branches required by the acceleration algorithm of the present invention is half of that of the original algorithm. Since the number of branches is halved, the training sequence is also halved, and the performance is improved. If the number of branches is the same, the acceleration algorithm of the present invention has the same performance as the original algorithm, but can achieve a higher decoding speed.
下表给出了不同并行分支数时原算法和本发明的加速算法所能达到的译码速度。 以 =100, 编码块长 = 6144为例计算译码速度。 The following table gives the decoding speeds that can be achieved by the original algorithm and the acceleration algorithm of the present invention for different parallel branch numbers. The decoding speed is calculated by taking =100, coding block length = 6144 as an example.
峰值译码速度 (Mbps) Peak decoding speed (Mbps)
22 35.77 35.77 52.07 (译码迭代 7次) 22 35.77 35.77 52.07 (decoding iteration 7 times)
峰值译码速度 (Mbps) Peak decoding speed (Mbps)
19.79 32.76 32.76 48.73 (译码迭代 8次) 19.79 32.76 32.76 48.73 (decoding iteration 8 times)
从上表 Turbo码并行译码的峰值速度可得, 并行分支数为 16的加速并行算法比并行 分支数为 16的一般并行算法提高速度在 40%以上。 From the above table, the peak speed of the parallel decoding of the Turbo code is available. The accelerated parallel algorithm with 16 parallel branches has a speed of more than 40% than the parallel parallel algorithm with 16 branches.
下表给出了不同编码块长度时并行译码相对于串行译码的浮点性能损失 The following table shows the floating-point performance loss of parallel decoding versus serial decoding for different encoding block lengths.
数减半, 性能损失也会大幅减少 (接近 50% )。 如果要达到相同的译码速度, 本发明的 加速算法所用的并行分支数目是原算法的一半,此时本发明的加速算法的性能会比原算 法有显著的提高。 By halving the number, the performance loss is also greatly reduced (close to 50%). If the same decoding speed is to be achieved, the number of parallel branches used by the acceleration algorithm of the present invention is half that of the original algorithm, and the performance of the acceleration algorithm of the present invention is significantly improved over the original algorithm.
综上所述,实施本发明实施例,通过加速的串行译码算法将原来计算输出 LLR值和 外信息的顺序由从左到右(即从首端到末端)改变为从中间到两边, 达到了译码提速的 目的, 而且计算是准确的, 不会有性能损失, 保证了 Turbo码译码的可靠性。 具体地, 在串行译码时, 比原译码算法提高译码速度近一倍,并且没有性能损失;在并行译码时, 如果并行分支数相同, 则比原译码算法提 In summary, in the embodiment of the present invention, the sequence of calculating the output LLR value and the external information is changed from left to right (ie, from the head end to the end) to the middle to the two sides by an accelerated serial decoding algorithm. The purpose of decoding speed is achieved, and the calculation is accurate, there is no performance loss, and the reliability of Turbo code decoding is guaranteed. Specifically, in serial decoding, the decoding speed is nearly doubled compared with the original decoding algorithm, and there is no performance loss; in parallel decoding, if the number of parallel branches is the same, it is higher than the original decoding algorithm.
1 高译码速度的百分比为
, 此时没有性能损失, 但可以显著的减少 译码时延。 在并行译码时, 如果要达到相同的译码速度, 则本发明的加速译码算 法所需的并行分支数是原译码算法的一半, 此时训练序列也减少一半, 性能会有较大的
提高。 1 The percentage of high decoding speed is There is no performance loss at this time, but the decoding delay can be significantly reduced. In the parallel decoding, if the same decoding speed is to be achieved, the number of parallel branches required by the accelerated decoding algorithm of the present invention is half of the original decoding algorithm, and the training sequence is also reduced by half, and the performance is large. of Improve.
需要说明的是, 通过以上的实施方式的描述, 本领域的技术人员可以清楚地了解 到本发明可借助软件加必需的硬件平台的方式来实现, 当然也可以全部通过硬件来实 施。基于这样的理解, 本发明的技术方案对背景技术做出贡献的全部或者部分可以以软 件产品的形式体现出来, 该计算机软件产品可以存储在存储介质中, 如 ROM/RAM、 磁 碟、 光盘等, 包括若干指令用以使得一台计算机设备(可以是个人计算机, 服务器, 或 者网络设备等) 执行本发明各个实施例或者实施例的某些部分所述的方法。 It should be noted that, through the description of the above embodiments, those skilled in the art can clearly understand that the present invention can be implemented by means of software plus a necessary hardware platform, and of course, all can be implemented by hardware. Based on such understanding, all or part of the technical solution of the present invention contributing to the background art may be embodied in the form of a software product, which may be stored in a storage medium such as a ROM/RAM, a magnetic disk, an optical disk, or the like. A number of instructions are included to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform the methods described in various embodiments of the present invention or portions of the embodiments.
以上所揭露的仅为本发明实施例中的一种较佳实施例而已, 当然不能以此来限定 本发明之权利范围,因此依本发明权利要求所作的等同变化,仍属本发明所涵盖的范围。
The above is only a preferred embodiment of the present invention, and the scope of the present invention is not limited thereto, and thus equivalent changes according to the claims of the present invention are still covered by the present invention. range.
Claims
1、 一种译码中外信息计算方法, 其特征在于, 包括: A method for decoding Chinese and foreign information, characterized in that it comprises:
接收到数据序列; Receiving a sequence of data;
从所述数据序列的末端依次反向计算后向状态度量和支路度量; Backward state metrics and branch metrics are inversely calculated from the end of the data sequence;
在计算完所述后向状态度量和支路度量之前从所述数据序列的首端依次正向计算 前向状态度量和支路度量; Calculating forward state metrics and branch metrics in order from the head end of the data sequence before calculating the backward state metrics and branch metrics;
根据计算出的后向状态度量、 前向状态度量以及支路度量计算输出所述数据序列 中的比特的外信息。 The outer information of the bits in the data sequence is output based on the calculated backward state metric, forward state metric, and branch metric.
2、 如权利要求 1所述的方法, 其特征在于, 所述根据计算出的后向状态度量、 前 向状态度量以及支路度量计算输出所述数据序列中的比特的外信息包括: 2. The method according to claim 1, wherein the calculating the outbound information of the bits in the data sequence according to the calculated backward state metric, the forward state metric, and the branch metric comprises:
当反向计算的后向状态度量个数与正向计算的前向状态度量个数之和大于所述数 据序列的码长个数后, 根据计算出的后向状态度量、 前向状态度量以及支路度量计算输 出所述数据序列中的比特的外信息。 After the sum of the backward calculated state state metric and the forward calculated forward state metric is greater than the code length of the data sequence, the calculated backward state metric, forward state metric, and The branch metric calculates the outer information of the bits in the data sequence.
3、 如权利要求 2所述的方法, 其特征在于, 所述在计算完所述后向状态度量和支 路度量之前从所述数据序列的首端依次正向计算前向状态度量和支路度量包括: 3. The method of claim 2, wherein the forward state metrics and branches are forwardly calculated from the head end of the data sequence before the backward state metrics and branch metrics are calculated Metrics include:
从所述数据序列的末端依次反向计算后向状态度量和支路度量的同时, 从所述数 据序列的首端依次正向计算前向状态度量和支路度量。 Simultaneously calculating the backward state metric and the branch metric from the end of the data sequence, the forward state metric and the branch metric are forwardly calculated from the head end of the data sequence.
4、 如权利要求 3所述的方法, 其特征在于, 当所述数据序列的码长个数为奇数 K=2j+1时, 其中 j为预设的固定的整数值, 所述根据计算出的后向状态度量、 前向状态 度量以及支路度量计算输出所述数据序列中的比特的外信息包括: 4. The method according to claim 3, wherein when the number of code lengths of the data sequence is an odd number K=2j+1, where j is a preset fixed integer value, the basis is calculated The backward state metric, the forward state metric, and the branch metric calculation output outer information of the bits in the data sequence include:
根据计算出的后向状态度量、 前向状态度量以及支路度量计算所述数据序列中第 j+1个比特的外信息, 之后依次计算第 j+1-q个和第 j+1+q个两个比特的外信息, 其中 q的 取值依次从 1到 Calculating the outer information of the j+1th bit in the data sequence according to the calculated backward state metric, the forward state metric, and the branch metric, and then sequentially calculating the j+1-qth and j+1+q Two bits of external information, where q takes values from 1 to
5、如权利要求 3所述的方法,其特征在于, 当所述数据序列的码长个数为偶数 K=2j 时,其中 j为预设的固定的整数值,所述根据计算出的后向状态度量、前向状态度量以及 支路度量计算输出所述数据序列中的比特的外信息包括: The method according to claim 3, wherein when the number of code lengths of the data sequence is an even number K=2j, where j is a preset fixed integer value, the calculation is based on the calculated The output of the outer information of the bits in the data sequence to the state metric, the forward state metric, and the branch metric calculation includes:
根据计算出的后向状态度量、 前向状态度量以及支路度量计算所述数据序列中第 j 个和第 j+1个两个比特的外信息, 之后依次计算第 j-q个和第 j+1+q个两个比特的外信息, 其中 q的取值依次从 1到 j-l。 Calculating the outer information of the jth and j+1th bits in the data sequence according to the calculated backward state metric, the forward state metric, and the branch metric, and then calculating the jqth and j+1th in order +q two bits of external information, where q takes values from 1 to jl.
6、 如权利要求 1至 5任意一项所述的方法, 其特征在于, 所述接收到的数据序列为
并行接收到的至少两个分支的数据序列。 The method according to any one of claims 1 to 5, wherein the received data sequence is A sequence of data of at least two branches received in parallel.
7、 一种译码器, 其特征在于, 包括- 度量计算模块, 用于当接收到数据序列后, 从所述数据序列的末端依次反向计算 后向状态度量和支路度量,并在计算完所述后向状态度量和支路度量之前从所述数据序 列的首端依次正向计算前向状态度量和支路度量; A decoder, comprising: a metric calculation module, configured to inversely calculate a backward state metric and a branch metric from the end of the data sequence after receiving the data sequence, and calculate Forward state metrics and branch metrics are calculated forwardly from the head end of the data sequence before the backward state metric and branch metric are completed;
信息计算模块, 用于跟所述度量计算模块计算出的后向状态度量、 前向状态度量 以及支路度量计算输出所述数据序列中的比特的外信息。 And an information calculation module, configured to calculate, by the backward state metric, the forward state metric, and the branch metric calculated by the metric calculation module, the outer information of the bits in the data sequence.
8、 如权利要求 7所述的译码器, 其特征在于, 所述信息计算模块包括: 信息计算输出单元, 用于当所述度量计算模块反向计算的后向状态度量个数与正 向计算的前向状态度量个数之和大于所述数据序列的码长个数后,根据计算出的后向状 态度量、 前向状态度量以及支路度量计算输出所述数据序列中的比特的外信息。 The decoder according to claim 7, wherein the information calculation module comprises: an information calculation output unit, and a backward state metric number and a forward direction when the metric calculation module reversely calculates After the sum of the calculated forward state metrics is greater than the code length of the data sequence, the calculated backward state metric, the forward state metric, and the branch metric are calculated to output the bits in the data sequence. information.
9、 如权利要求 8所述的译码器, 其特征在于, 所述度量计算模块从所述数据序列 的末端依次反向计算后向状态度量和支路度量的同时,从所述数据序列的首端依次正向 计算前向状态度量和支路度量, 当所述数据序列的码长个数为奇数 K=2j+1时, 其中 j为 预设的固定的整数值, 所述信息计算输出单元包括: 9. The decoder according to claim 8, wherein the metric calculation module reversely calculates a backward state metric and a branch metric from the end of the data sequence, from the data sequence The head end calculates the forward state metric and the branch metric in turn, and when the number of code lengths of the data sequence is an odd number K=2j+1, where j is a preset fixed integer value, the information is calculated and output. The unit includes:
第一信息计算子单元, 用于由所述度量计算模块计算出的后向状态度量、 前向状 态度量以及支路度量计算所述数据序列中第 J+1个比特的外信息, 之后依次计算 ®_j+l-q 个和第 j+1+q个两个比特的外信息, 其中 q的取值依次从 1莉。 a first information calculation subunit, configured to calculate, by the backward state metric, the forward state metric, and the branch metric calculated by the metric calculation module, external information of the J+1th bit in the data sequence, and then calculate sequentially ®_j+lq and j+1+q two bits of external information, where q takes the value from 1 莉.
10、 如权利要求 8所述的译码器, 其特征在于, 所述度量计算模块从所述数据序列 的末端依次反向计算后向状态度量和支路度量的同时,从所述数据序列的首端依次正向 计算前向状态度量和支路度量, 当所述数据序列的码长个数为偶数 K=2j时, 其中 j为预 设的固定的整数值, 所述信息计算输出单元包括: 10. The decoder according to claim 8, wherein the metric calculation module reversely calculates a backward state metric and a branch metric from the end of the data sequence, from the data sequence The head end sequentially calculates the forward state metric and the branch metric in turn. When the code length of the data sequence is an even number K=2j, where j is a preset fixed integer value, the information calculation output unit includes :
第二信息计算子单元, 用于由所述度量计算模块计算出的后向状态度量、 前向状 态度量以及支路度量计算所述数据序列中第 j个和第 J+1个两个比特的外信息, 之后依次 计算第 j-q个和第 j+1+q个两个比特的外信息, 其中 q的取值依次从 1到 j-1。 a second information calculation subunit, configured to calculate, by the metric calculation module, the backward state metric, the forward state metric, and the branch metric to calculate the jth and J+1th bits in the data sequence The external information, and then the outer information of the jqth and j+1+q two bits are sequentially calculated, wherein the values of q are sequentially from 1 to j-1.
11、 如权利要求 7至 10任意一项所述的译码器, 其特征在于, 所述接收到的数据序 列为并行接收到的至少两个分支的数据序列。 The decoder according to any one of claims 7 to 10, wherein the received data sequence is a data sequence of at least two branches received in parallel.
12、 一种 Turbo码译码器, 其特征在于, 所述 Turbo码译码器包括如权利要求 7至 11 任意一项所述的译码器。
A turbo code decoder, characterized in that the turbo code decoder comprises the decoder according to any one of claims 7 to 11.
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