WO2009104446A1 - Method for manufacturing active matrix substrate and method for manufacturing display device - Google Patents

Abstract

A method for manufacturing an active matrix substrate includes a step of forming a source electrode (63), a source wiring (80), and a drain electrode (64), each of which has a prescribed pattern, by etching a conductive film by using a resist having steps as a mask; a step of removing a portion having a relatively small film thickness by ashing the resist having the steps; a step of forming a remaining resist which includes a cured resist and a partially cured resist, by performing exposure to the remaining resist; a step of forming a planarized resist by performing thermal reflow and chemical reflow to the remaining resist; and a step of forming a semiconductor film (67) having a prescribed pattern by etching the semiconductor film by using the planarized resist as a mask.

Description

Manufacturing method of active matrix substrate and manufacturing method of display device

The present invention relates to a method for manufacturing an active matrix substrate and a method for manufacturing a display device.

In recent years, with the rapid spread of high-precision television receivers and large-sized television receivers, the demand for high-precision display devices is increasing. A liquid crystal display (LCD: Liquid Crystal Display) is a typical flat panel display (FPD: Flat Panel Display) as well as an electroluminescence (EL) display device and a plasma display (PDP). It has advantages such as light weight, space saving, low price, low power consumption, and high-speed response.

Currently, transmissive liquid crystal display devices are the mainstream of liquid crystal display devices used for high-precision television receivers and large-sized television receivers. In the transmissive liquid crystal display device, liquid crystal is injected between two glass substrates on which electrodes are formed, and the liquid crystal molecular orientation of the liquid crystal layer is changed by a voltage applied to the electrodes formed inside the substrate. And by changing the optical characteristics of the liquid crystal layer based on the orientation change of the liquid crystal molecules, display is performed by adjusting the amount of light transmitted from the backlight in the orientation relationship with the polarizing plate attached to the substrate. is there.

This transmissive liquid crystal display device is roughly divided into a passive type and an active type from the viewpoint of a driving system, but the current mainstream is an active type. In an active liquid crystal display device, a switching transistor is provided for each pixel, which controls the operation of each pixel. As a switching transistor, a thin film transistor (TFT: Thin Film Transistor) that is a three-terminal type is used. Commonly used.

The thin film transistor substrate for a liquid crystal display device having the above-described thin film transistor array formed on the entire surface is manufactured by repeating a photolithography process and an etching process a plurality of times. Conventionally, from the viewpoint of reducing the manufacturing cost, the photolithography process has been reduced, that is, the number of used masks has been reduced. Currently, a thin film transistor array substrate is manufactured by five photolithography processes using five types of photomasks. The process to do is common.

On the other hand, for example, Patent Document 1 discloses a manufacturing method using four types of photomasks as opposed to a manufacturing method using five types of photomasks.
JP 2002-334830 A

(Problems to be solved by the invention)
In the process using the four types of photomasks disclosed in Patent Document 1, a method of increasing the planar dimension of the photoresist by dissolution reflow is employed. Specifically, it is as follows.

(A) First, a first conductive film is formed on a glass substrate.
(B) Next, a first photoresist is applied on the first conductive film, and a pattern of a region to be a gate electrode and a gate wiring is formed with the first photoresist using a first photomask.
(C) The gate electrode and the gate wiring are formed by removing the first conductive film in the region not covered with the first photoresist by dry etching or wet etching, and the first photoresist is removed by plasma ashing using oxygen. To do.

(D) Next, a gate insulating film, an intrinsic semiconductor film, a doping semiconductor film, and a second conductive film are successively formed on the gate electrode and the gate wiring.
(E) A second photoresist is applied on the second conductive film, a halftone mask is used as the second photomask, an opening is formed in the channel region, and an inner film is formed on the source / drain electrodes. The step is formed with a thick portion and a thin film portion on the outside.
(F) The second conductive film and the doping semiconductor film in a region not covered with the second photoresist are removed by dry etching or wet etching to form a source electrode, a source wiring, and a drain electrode.
(G) Thereafter, the second photoresist in the thin film portion formed partially thin is removed by ashing using oxygen plasma. Then, dissolution reflow is performed on the remaining second photoresist, and the channel region, the source electrode, and the drain electrode are flattened so as to be covered with the second photoresist.
(H) In this state, the intrinsic semiconductor film in a region not covered with the planarized second photoresist is removed by dry etching, and the planarized second photoresist is removed by ashing using oxygen plasma. .

(I) Next, a passivation film is formed on the entire surface, a third photoresist is applied on the passivation film, and a pattern of a region to be a contact hole is formed on the drain electrode using the third photomask. To do.
(J) The passivation film is etched by dry etching or wet etching to form a contact hole on the drain electrode. Thereafter, the third photoresist is removed by ashing using oxygen plasma.

(K) Next, a transparent conductive film is formed on the entire surface, a fourth photoresist is applied on the transparent conductive film, and a pattern of a region to be a pixel electrode is formed on the transparent conductive film using a fourth photomask. Form.
(L) The transparent conductive film is etched by dry etching or wet etching to form a pattern to be a pixel electrode on the passivation film. Thereafter, the fourth photoresist is removed by ashing using oxygen plasma.
That's it.

In such a process using four types of photomasks, the second photoresist is planarized by using dissolution reflow, so that the flowability during reflow is high and the wide channel region is covered. There is a merit that can be. On the other hand, since the width tends to increase, the width of the intrinsic semiconductor film below the TFT region becomes larger than the width of the source electrode and the signal line, which may cause problems such as an increase in parasitic capacitance. That is, at the time of dissolution reflow, the second photoresist spreads over the intrinsic semiconductor film, and thus the width of the intrinsic semiconductor film may be expanded by subsequent etching.

The present invention has been made in view of the above problems, and an active matrix manufacturing method capable of providing an active matrix substrate having a configuration in which problems such as an increase in parasitic capacitance hardly occur, and uses the same. It is an object of the present invention to provide a method for manufacturing a display device.

(Means for solving the problem)
In order to solve the above problems, an active matrix substrate manufacturing method of the present invention includes a gate portion forming step of forming a gate electrode and a gate wiring of a predetermined pattern on a substrate, and the gate electrode and the gate wiring formed. On top of that, a lamination step of sequentially forming an insulating film, a semiconductor film, and a conductive film, a resist coating step of applying a resist on the conductive film, and exposing the resist through a photomask, Thereafter, development is performed to form a film thickness of the resist covering a part of the region to be the source electrode and the drain electrode in the conductive film, and an outer edge portion or an outer edge of the region to be the source wiring, the source electrode, and the drain electrode. The film thickness of the resist covering a part of the portion is determined according to the resist covering the inner portion of the region to be the source wiring, the source electrode, and the drain electrode. And the width of the resist covering a part of the region to be the source electrode and the drain electrode is set to be an outer edge portion or an outer edge portion of the region to be the source wiring, the source electrode, and the drain electrode. A stepped resist creating step of creating a stepped resist that is larger than the width of the resist covering a part of the resist, and etching the conductive film using the stepped resist as a mask, and a source electrode of a predetermined pattern, Conductive pattern forming step for forming source wiring and drain electrode, ashing for the stepped resist, ashing step for removing a relatively small portion of the stepped resist, and after the ashing step By exposing the remaining resist, the source wiring and the source electrode And a cured resist obtained by curing the resist covering the outer edge part of the drain electrode or a part of the outer edge part, and a form in which the uncured part remains inside the resist covering a part of the source electrode and the drain electrode. An exposure step of forming a residual resist including a partially cured resist cured in step (a), and performing thermal reflow on the residual resist, causing the uncured portion of the partially cured resist to flow, and the curing covered on the outside A thermal reflow process for flowing out from a portion to the outside, a chemical reflow process for performing a chemical reflow on the remaining resist, planarizing the resist in a region inside the cured resist, and creating a planarized resist; The semiconductor film is etched using the planarizing resist as a mask to form a semiconductor film with a predetermined pattern. And a semiconductor pattern forming step.

According to such a manufacturing method, it is possible to accurately form a semiconductor pattern into a desired pattern. That is, by forming a resist for forming a semiconductor pattern (here, a planarizing resist) as designed, the semiconductor film can be formed into a predetermined pattern by etching using the resist as a mask. Problems such as an increase in parasitic capacitance due to width expansion are unlikely to occur. In the present invention, a resist (planarization resist) for forming a semiconductor pattern is used by modifying the resist (stepped resist) used when etching the conductive film thereon. This is because it was possible to carry out exactly as designed. Specifically, the film thickness of the resist covering a part of the region to be the source electrode and the drain electrode, and the outer edge portion of the region to be the source wiring, the source electrode and the drain electrode, or a part of the outer edge portion of the resist to be covered. The film thickness is made larger than the film thickness of the resist covering the inner part of the region to be the source wiring, the source electrode and the drain electrode, and the width of the resist covering a part of the region to be the source electrode and the drain electrode is By forming the resist with a step by making it larger than the width of the resist covering the outer edge portion of the region to be the source wiring, the source electrode, and the drain electrode, a portion having a small film thickness (source wiring, source electrode) And the resist covering the inner portion of the region to be the drain electrode) can be selectively removed by ashing, and the remaining thick film portion The resist is cured by curing the resist covering the outer edge part of the source wiring, the source electrode and the drain electrode or a part of the outer edge part, and the resist covering a part of the source electrode and the drain electrode is formed inside the uncured part. The residual resist can be formed as a partially cured resist by being cured in the form of remaining. Then, thermal reflow is performed on the remaining resist, the uncured portion of the partially cured resist is caused to flow, and the cured portion covered with the outside flows out to the outside, and chemical reflow is performed, and the region inside the cured resist. Thus, the resist can be flattened to produce a flattened resist. In this case, since the hardened resist becomes a wall (weir) at the time of reflow, it is possible to prevent or suppress the occurrence of the problem that the fluidized resist spreads outside. In particular, since the entire cured resist is hardened, it does not flow at the time of thermal reflow and is not destroyed by chemical reflow. On the other hand, in the partially cured resist, the uncured portion inside is fluidized by thermal reflow, the cured portion covering the outside is destroyed by the flow or volume expansion, and flows out to the outside. Then, by chemical reflow, the region surrounded by the cured resist spreads evenly.

Of the steps in the manufacturing method, in the step-formed resist forming step, the step-formed resist has an opening at a position overlapping with a portion of the conductive film where a channel is formed by the semiconductor film. It can be formed.
In this case, the pattern of the conductive film can be a pattern in which the conductive film is not formed in a portion where the channel is formed, and the channel using the semiconductor film can be surely formed.

In the chemical reflow step, as the planarizing resist, a conductive film that covers a position overlapping with a portion where a channel is formed by the semiconductor film can be formed.
In this case, the pattern of the semiconductor film can be a pattern in which the semiconductor film is formed in a portion where the channel is formed, and the channel by the semiconductor film can be surely formed.

In the stacking step, as the conductive film, a doped semiconductor film to which an impurity is added from the semiconductor film side and a metal conductive film can be stacked.
In this case, the bonding property between the semiconductor film and the metal conductive film is increased, and it is possible to realize good film characteristics and conductive characteristics.

In the exposure step, the thickness of the cured portion of the partially cured resist may be equal to or greater than the width of the cured resist.
By performing such exposure, it is possible to completely cure the entire cured resist, and it is possible to prevent or suppress the problem of fluidization of the cured resist in a reflow process performed later.

In the exposure step, the exposure may be performed under the conditions of an irradiation wavelength of 200 nm to 400 nm, an irradiation intensity of 1 mW / cm ² to 10 mW / cm ² , and an irradiation time of 1 minute to 5 minutes.
By performing such exposure, it is possible to suitably prepare a partially cured resist that partially cures the outer portion and leaves an uncured portion inside.

In the thermal reflow step, the substrate may be exposed to an environment where the temperature of the substrate is 200 ° C. to 300 ° C. for 10 to 30 minutes.
Under such conditions, the uncured portion of the partially cured resist can be suitably fluidized.

In the chemical reflow process, alcohol, ether or ester may be used as the solvent, and the substrate may be exposed to the solvent vapor at room temperature.
Under such conditions, the remaining resist can be suitably planarized inside the cured resist.

In the chemical reflow step, alcohol, ether or ester may be used as the solvent, and the substrate may be immersed in the solvent at room temperature.
Under such conditions, the remaining resist can be suitably planarized inside the cured resist.

In the stepped resist forming step, a halftone mask made of a semi-transmissive film or a gray tone mask including a semi-transmissive region by a slit can be used as the photomask.
By using such a mask, it becomes possible to suitably form a stepped resist.

In the gate part creating step, a glass substrate is used as the substrate, a gate conductive film is formed on the glass substrate, a gate resist is applied on the gate conductive film, and a gate photo The step of performing exposure and development through a mask, and dry etching or wet etching remove the gate conductive film in the region not covered with the gate resist to form a gate electrode and a gate wiring, and ashing And the step of removing the gate resist.
Such a process makes it possible to reliably produce a desired gate electrode and gate wiring.

The stacking step includes forming a gate insulating film using silicon nitride or silicon oxide as the insulating film on the gate electrode and the gate wiring, and using amorphous silicon as the semiconductor film on the insulating film. Forming an intrinsic semiconductor film, forming a doped semiconductor film using amorphous silicon doped with n-type impurities on the semiconductor film, and further forming the conductive film on the doped semiconductor film. And a step of forming a single metal film made of any one of aluminum, chromium, tantalum, and titanium or any metal nitride film.
Through such a process, a laminated film including a gate insulating film, an intrinsic semiconductor film, a doping semiconductor film, and a single metal film (metal nitride film) can be suitably formed.

After the semiconductor pattern forming step, a step of removing the planarizing resist by ashing, a step of forming a passivation film on the conductive pattern, a contact resist is applied on the passivation film, and a contact photomask is formed. A step of performing exposure and development, a step of removing the passivation film in a region not covered with the contact resist by dry etching or wet etching, and forming a contact portion on the drain electrode; Removing the contact resist by ashing; applying a light-transmitting conductive film to the entire surface of the substrate; applying a pixel electrode resist on the light-transmitting conductive film; Exposure and development, and dry etching or wetting. Removing the light-transmitting conductive film in a region not covered with the pixel electrode resist by etching to form a pixel electrode on the passivation film; and removing the pixel electrode resist by ashing. And can be included.
By such a process after the semiconductor pattern forming process, an active matrix substrate including a pixel electrode can be preferably formed.

Next, in order to solve the above-described problem, the display device manufacturing method of the present invention includes a step of creating an active matrix substrate by the above-described method, a step of creating a counter substrate including a common electrode on the substrate, A step of bonding an active matrix substrate and the counter substrate to form a liquid crystal panel in which a liquid crystal layer is formed between the active matrix substrate and the counter substrate. With such a method, it is possible to reliably provide a display device with excellent reliability.

(The invention's effect)
According to the present invention, it is possible to provide an active matrix manufacturing method capable of providing an active matrix substrate having a configuration in which problems such as an increase in parasitic capacitance hardly occur, and to provide a highly reliable display device manufacturing method. Is possible.

1 is a perspective view showing a schematic configuration of a liquid crystal display device of an embodiment. FIG. 2 is a cross-sectional view illustrating a schematic configuration of the liquid crystal display device of FIG. 1. Sectional drawing shown about the principal part structure (part of liquid crystal panel) of the liquid crystal display device of FIG. FIG. 2 is a plan view illustrating a pixel configuration of the liquid crystal display device of FIG. 1. FIG. 5 is a sectional view taken along line A-A ′ of FIG. 4. Explanatory drawing which shows 1 process concerning the manufacturing method of the liquid crystal display device of FIG. Explanatory drawing which shows 1 process concerning the manufacturing method of the liquid crystal display device of FIG. Explanatory drawing which shows 1 process concerning the manufacturing method of the liquid crystal display device of FIG. Explanatory drawing which shows 1 process concerning the manufacturing method of the liquid crystal display device of FIG. Explanatory drawing which shows 1 process concerning the manufacturing method of the liquid crystal display device of FIG. Explanatory drawing which shows 1 process concerning the manufacturing method of the liquid crystal display device of FIG. Explanatory drawing which shows 1 process concerning the manufacturing method of the liquid crystal display device of FIG. Explanatory drawing which shows 1 process concerning the manufacturing method of the liquid crystal display device of FIG. Explanatory drawing which shows 1 process concerning the manufacturing method of the liquid crystal display device of FIG. Explanatory drawing which shows 1 process concerning the manufacturing method of the liquid crystal display device of FIG. Explanatory drawing which shows 1 process concerning the manufacturing method of the liquid crystal display device of FIG. Explanatory drawing which shows 1 process concerning the manufacturing method of the liquid crystal display device of FIG. Explanatory drawing which shows 1 process concerning the manufacturing method of the liquid crystal display device of FIG. Explanatory drawing which shows 1 process concerning the manufacturing method of the liquid crystal display device of FIG. Explanatory drawing which shows 1 process concerning the manufacturing method of the liquid crystal display device of FIG. Explanatory drawing which shows 1 process concerning the manufacturing method of the liquid crystal display device of FIG. Explanatory drawing which shows 1 process concerning the manufacturing method of the liquid crystal display device of FIG. The top view which shows the plane positional relationship of each resist part with which a resist with a level | step difference is provided.

Explanation of symbols

DESCRIPTION OF SYMBOLS 41 ... Glass substrate (substrate), 61 ... Conductive film (doping semiconductor film), 62 ... Conductive film (metal conductive film), 63 ... Source electrode, 64 ... Drain electrode, 65 ... Gate electrode, 66 ... Gate insulating film, 67 ... Semiconductor film, 67a ... Channel region, 80 ... Source wiring, 90 ... Gate wiring, 201 ... Photoresist (resist with step), 201b ... Residual resist, 201c ... Flattening resist

Embodiments according to the present invention will be described below with reference to the drawings.
1 is an exploded perspective view showing a schematic configuration of a liquid crystal display device produced by the manufacturing method according to the present invention, FIG. 2 is a cross-sectional view showing the schematic configuration of the liquid crystal display device, and FIG. 3 is a liquid crystal display device. FIG. 4 is a plan view showing a pixel configuration of the liquid crystal display device, and FIG. 5 is a cross-sectional view taken along line AA ′ of FIG.

A liquid crystal display device (display device) 10 shown in FIG. 1 and FIG. 2 includes a rectangular liquid crystal panel 11 and a backlight device 12 as an external light source, and these are integrally held by a bezel 13 or the like. It is like that.
The backlight device 12 is a so-called direct-type backlight device, and a light source (here, a cold cathode tube 17) is arranged in parallel along the panel surface immediately below the back surface of the panel surface (display surface) of the liquid crystal panel 11. The structure is provided. The backlight device 12 includes a rectangular metal base 14 having an opening on the upper surface side, and a plurality of optical members 15 (diffuser plates in order from the lower side in the figure) attached so as to cover the opening of the base 14. A diffusion sheet, a lens sheet, an optical sheet), a frame 16 for holding these optical members 15 on the base 14, a cold cathode tube 17 which is a lamp accommodated in the base 14, and both ends of the cold cathode tube 17 A holder 18 made of rubber (for example, made of silicon rubber) for holding the lamp, a lamp holder 19 that collectively covers the cold cathode tube 17 group and the holder 18 group, and a portion in the middle of the cold cathode tube 17 excluding both ends. The lamp clip 20 is provided.

As shown in FIG. 3, the liquid crystal panel 11 is configured such that a pair of substrates 30 and 40 are bonded together with a predetermined gap therebetween, and liquid crystal is sealed between the substrates 30 and 40. Thus, the liquid crystal layer 50 is formed.
The substrate 40 is an element substrate (active matrix substrate), a thin film transistor (TFT) 60 as a semiconductor element formed on the liquid crystal layer 50 side of the glass substrate 41, and a pixel electrically connected to the thin film transistor 60. An electrode 44 and an alignment film 45 formed on the liquid crystal layer 50 side of the thin film transistor 60 and the pixel electrode 44 are provided. A polarizing plate 42 is disposed on the opposite side of the glass substrate 41 from the liquid crystal layer 50 side.

The pixel electrode 44 is made of a transparent conductive film such as ITO (indium tin oxide), and is formed in a matrix pattern on the liquid crystal layer 50 side of the element substrate 40. Specifically, it is connected to the drain electrode 64 (see FIGS. 4 and 5) of the thin film transistor 60, and a voltage is selectively applied by the switching operation of the thin film transistor 60. The alignment film 45 is composed of, for example, a polyimide rubbing alignment film, and the polarizing plate 42 employs a film obtained by stretching a transparent film soaked with iodine or a dye in one direction.

On the other hand, the substrate 30 is a counter substrate, which is formed on the liquid crystal layer 50 side of the glass substrate 31, and is a colored portion R capable of selectively transmitting R (red), G (green), and B (blue) light. , G and B, a counter electrode 34 formed on the liquid crystal layer 50 side of the color filter 33, and an alignment film 35 formed on the liquid crystal layer 50 side of the counter electrode 34. . A polarizing plate 32 is disposed on the opposite side of the glass substrate 31 from the liquid crystal layer 50 side.

The color filter 33 includes a black matrix BM arranged at the boundary between the colored portions R, G, and B, and the black matrix BM covers a non-pixel portion (that is, a region where the thin film transistor 60 is formed) of the element substrate 40. Are superimposed on the non-pixel portion. The counter electrode 34 is made of a transparent conductive film such as ITO (Indium Tin Oxide), for example, and is formed in a solid shape on the entire surface of the counter substrate 30 on the liquid crystal layer 50 side. The alignment film 35 is composed of, for example, a polyimide rubbing alignment film, and the polarizing plate 32 employs, for example, a transparent film soaked with iodine or dye and stretched in one direction.

As described above, the liquid crystal display device 10 of the present embodiment includes the thin film transistor 60 as a semiconductor element, and the pixel including the thin film transistor 60 has a configuration as shown in FIGS.
In the liquid crystal display device 10 of the present embodiment, a plurality of pixels 49 are configured in a matrix, and a thin film transistor 60 is formed in each of these pixels 49 as a semiconductor element for pixel switching.

The thin film transistor 60 includes a source electrode 63, a drain electrode 64, and a gate electrode 65, and a source wiring 80 that supplies an image signal is connected to the source electrode 63. The image signal written to the source wiring 80 may be supplied line-sequentially or may be supplied for each group to a plurality of adjacent source wirings 80. The source wiring 80 is connected to a driving circuit for supplying an image signal via a contact hole 81 and a wiring 82 as shown in FIG.
Further, a gate wiring 90 is connected to the gate electrode 65 of the thin film transistor 60, and a scanning signal is applied to the gate wiring 90 in a pulse-sequential manner at a predetermined timing.

The pixel electrode 44 is connected to the drain electrode 64 of the thin film transistor 60 via a contact hole 68. By turning on the thin film transistor 60 that is a switching element for a certain period, an image signal supplied from the source wiring 80 is received. Writing is performed to each pixel 49 at a predetermined timing. The image signal of a predetermined level written in the liquid crystal through the pixel electrode 44 in this way is held for a certain period with the counter electrode 34 (see FIG. 3). In order to prevent the held image signal from leaking, a storage capacitor (not shown) is added in parallel with the liquid crystal capacitor formed between the pixel electrode 44 and the counter electrode 34 (see FIG. 3). .

As described above, the thin film transistor 60 is disposed on the glass substrate 41 constituting the element substrate 40. Specifically, as shown in FIG. 5, a gate electrode 65 formed on the glass substrate 41, a gate insulating film 66 formed on the gate electrode 65, a gate insulating film 66, and a channel region 67a. A semiconductor film 67 provided; a source electrode 63 connected to one end of the semiconductor film 67; a drain electrode 64 connected to the other end of the semiconductor film 67 and connected to the source electrode 63 via a channel region 67a; It is configured with.

The gate electrode 65 can be formed of, for example, a metal film alone such as chromium (Cr), tantalum (Ta), titanium (Ti), or a laminated film of these metal nitrides in addition to aluminum (Al).
The gate insulating film 66 can be formed of, for example, silicon oxide (SiOx) other than silicon nitride (SiNx).
The semiconductor film 67 can be formed of, for example, amorphous silicon (a-Si).

The source electrode 63, the drain electrode 64, and the source wiring 80 connected to the source electrode 63 have a configuration in which conductive films 61 and 62 are stacked. The lower conductive film 61 can be formed of amorphous silicon (n ⁺ Si) or the like doped with an n-type impurity such as phosphorus (P) at a high concentration. The upper conductive film 62 may be formed of, for example, a single metal film such as chromium (Cr), tantalum (Ta), titanium (Ti), or a laminated film of these metal nitrides in addition to aluminum (Al). it can.

Further, an interlayer insulating film (passivation film) 70 is formed on the source electrode 63 and the drain electrode 64. The drain electrode 64 is connected to the pixel electrode 44 through a contact hole 68 formed in the interlayer insulating film 70. The interlayer insulating film 70 can be formed of an acrylic resin film or the like, in addition to an inorganic insulating film such as silicon nitride (SiNx), for example.

On the other hand, as shown in FIG. 5, a gate wiring 90 for supplying a scanning signal to the gate electrode 65 is formed on the glass substrate 41. The gate wiring 90 is formed of the same material and the same layer as the gate electrode 65. In addition, an insulating film 69 formed of the same material and in the same layer as the gate insulating film 66 is stacked on the gate wiring 90. An interlayer insulating film 70 is formed so as to cover the gate wiring 90 and the insulating film 69. As shown in FIG. 4, a contact hole 91 is formed in the insulating film 69 and the interlayer insulating film 70, and the gate wiring 90 is connected to the wiring 92 connected to the scanning signal supply circuit through the contact hole 91. Yes.

Next, a method for manufacturing the liquid crystal display device 10 of the present embodiment will be described. Here, in particular, the manufacturing process of the element substrate (active matrix substrate) 40 in the manufacturing method will be described in detail.

First, as shown in FIG. 6, a glass substrate 41 is prepared, and a first conductive film 165 is formed on the glass substrate 41. The first conductive film 165 can be formed by, for example, a sputtering method. As a material to be used, for example, in addition to aluminum (Al), a metal film alone such as chromium (Cr), tantalum (Ta), titanium (Ti), or the like A laminate of these metal nitrides can be used.

Subsequently, as shown in FIG. 7, a first photoresist 101 having a predetermined pattern is formed on the first conductive film 165. Specifically, the first photoresist 101 is left in the region to be the gate electrode 65 and the gate wiring 90 by exposing and developing the first photoresist formed on the entire surface through a photomask having a predetermined pattern. Let the pattern be

Etching is performed on the first conductive film 165 using the first photoresist 101 thus formed as a mask. Here, the etching is performed by wet etching, but it may be performed by dry etching. As a result, as shown in FIG. 8, the gate electrode 65 and the gate wiring 90 made of the first conductive film 165 are formed (gate portion forming step).

Next, as shown in FIG. 9, an insulating film 166, a semiconductor film (intrinsic semiconductor film) 167, a conductive film (doping semiconductor film) 161, and a conductive film (on the glass substrate 41 including the gate electrode 65 and the gate wiring 90 are formed. (Metal conductive film) 162 (these are also referred to as second conductive films) is formed (lamination process). The insulating film 166 can be formed by, for example, a plasma CVD method. As a material to be used, for example, silicon oxide (SiOx) can be used in addition to silicon nitride (SiNx). The semiconductor film 167 can be formed by, for example, a plasma CVD method, and the material used can be, for example, amorphous silicon (a-Si). The conductive film 161 is a doped semiconductor film, and can be formed of amorphous silicon (n ⁺ Si) doped with an n-type impurity such as phosphorus (P) at a high concentration. The conductive film 162 can be formed by, for example, a sputtering method, and as a material to be used, for example, in addition to aluminum (Al), a metal film alone such as chromium (Cr), tantalum (Ta), titanium (Ti), or the like It can be a laminate with a metal nitride.

After forming the laminated film as described above, a second photoresist 201 having a pattern as shown in FIG. 10 is formed on the second conductive film (conductive film 162). Specifically, the photoresist applied on the entire surface is exposed through a photomask and then developed, so that one of the regions to be the source electrode 63 in the second conductive film composed of the conductive films 161 and 162 is obtained. The film thickness of 1.8 μm to 2.3 μm of the resist part 210 covering the part and the film thickness of 1.8 μm to 2.3 μm of the resist part 211 covering a part of the region to be the drain electrode 64 and the region to be the source wiring 80 The source wiring 80 has a thickness of 1.5 μm to 1.8 μm of the resist portion 220 covering the outer edge portion and a thickness of 1.5 μm to 1.8 μm of the resist portion 221 covering the outer edge portion of the region where the contact hole 68 is formed. The film thickness of 0.3 μm to 0.8 μm of the resist portion 230 covering the inner part of the region to be the source electrode and the drain electrode, and the drain electrode 64 and the contact hole 68 are connected. Min larger than the film thickness 0.3 [mu] m ~ 0.8 [mu] m of the resist 231 covering the. Further, the widths of 2.0 μm to 4.0 μm of the resist portions 210 and 211 covering a part of the region that becomes the source electrode 63 and the drain electrode 64 are covered with the outer edge portion of the region that becomes the source wiring 80 and the source and drain electrodes. The width of the resist portion 220 (0.5 μm to 1.0 μm) and the width of the resist portion 221 (0.5 μm to 1.0 μm) covering the outer edge portion of the region where the contact hole 68 is formed are increased to the second. Photoresist (stepped resist) 201 is created (stepped resist creating step). The planar positional relationship between the resist portions 210, 211, 220, and 221 is shown in FIG.

In the step of creating a resist with a step, in order to create the second photoresist 201 as described above, the exposure amount for the photoresist applied on the entire surface is varied for each region. Here, a halftone mask made of a semi-transmissive film or a gray-tone mask including a semi-transmissive region by slits is used as a photomask, so that the region where the remaining resist film thickness is relatively small is exposed relatively. The amount of exposure is relatively reduced in a region where the amount is large and the film thickness of the remaining resist is relatively large. In addition, the second photoresist 201 has the above-described step shape, and has a pattern having an opening 240 at a position overlapping the portion where the channel 67 a is formed by the semiconductor film 67 in the second conductive film. .

After forming the second photoresist 201 as described above, as shown in FIG. 11, the second conductive film 201 (conductive film 162, conductive film 161) is dry-etched or etched using the second photoresist 201 as a mask. Wet etching is performed to form a source electrode 63, a source wiring 80, and a drain electrode 64 having a predetermined pattern (conductive pattern forming step). By this conductive pattern formation step, an opening is formed in the second conductive film also in the region 150a where the channel 67a is formed.

Subsequently, ashing is performed on the second photoresist 201, and a step of removing a relatively small portion of the thickness of the second photoresist 201 is performed (ashing step). More specifically, ashing using oxygen plasma is performed until the thin film portion (that is, the resist portions 230 and 231) of the second photoresist 201 is removed, thereby forming a receding second photoresist 201a as shown in FIG.

Next, after performing the ashing process as described above, as shown in FIG. 13, an exposure process of irradiating the remaining second photoresist 201a with ultraviolet light L is performed. Here, an uncured portion is generated in a part of the resist by adjusting the exposure conditions. Specifically, the resist part 220 and the resist part 221 formed relatively narrowly are cured to form the cured resist 220a and the cured resist 221a, respectively, including the inside, while being formed relatively wide. The resist part 210 and the resist part 211 are cured with the uncured part remaining therein to form a partially cured resist 210c and a partially cured resist 211c, respectively. The cured resists 220a and 221a and the partially cured resists 210c and 211c A remaining resist 201b is formed.

The partially cured resist 210c includes an uncured resist portion 210b inside, and the cured resist portion 210a is covered outside the uncured resist 210b. The partially cured resist 211c includes an uncured resist portion 211b inside. In addition, the cured resist portion 211a is covered outside the uncured resist 211b. The thickness of the cured resist portions 210a and 211a of the partially cured resists 210c and 211c is equal to or greater than the width of the cured resists 220a and 221a. In order to satisfy such a curing condition, in the exposure process shown in FIG. 13, the irradiation wavelength of the ultraviolet light L is 200 nm to 400 nm, the irradiation intensity is 1 mW / cm ² to 10 mW / cm ² , and the irradiation time is 1 minute to 5 minutes.

After performing the above exposure process, thermal reflow is performed on the remaining resist 201b. Specifically, the uncured portions (uncured resist portions 210b and 211b) of the partially cured resists 210c and 211c are caused to flow and exposed from the cured portions (cured resist portions 210a and 211a) covered on the outside. Therefore, the thermal reflow is performed by exposing the glass substrate 41 to an environment where the temperature of the glass substrate 41 is 200 ° C. to 300 ° C. for 10 minutes to 30 minutes.

Following the thermal reflow, chemical reflow using a solvent is performed, and a flattening resist having a pattern covering a position overlapping the portion where the channel 67a is formed (that is, above the gate electrode 65) as shown in FIG. 201c. Specifically, alcohol or ether or ester is used as a solvent and the glass substrate 41 is exposed to solvent vapor at room temperature, or alcohol or ether or ester is used as a solvent and the glass substrate 41 is solvent-free at room temperature. A technique of immersing in the inside can be employed. By such a method, the uncured resist 212 is planarized in a region inside the cured resists 220a and 221a, and a planarized resist 201c is created (chemical reflow process). When the planarization is performed by this chemical reflow, the outer cured resists 220a and 221a have a wall function that prevents the uncured resist 212 from spreading outward.

Subsequently, dry etching is performed on the semiconductor film 167 using the planarization resist 201c as a mask to form a semiconductor film 67 having a pattern as shown in FIG. 15 (semiconductor pattern forming step).

Further, after the semiconductor pattern forming step, the planarizing resist 201c is removed by ashing (FIG. 16), and an insulating film 170 is formed on the entire surface of the substrate including the conductive film 62 (FIG. 17). The insulating film 170 is formed of an inorganic insulating film such as silicon nitride formed using a plasma CVD method, an acrylic resin film, or the like.

Then, a resist is applied on the insulating film 170, and exposure and development are performed through a photomask to form a contact hole resist 301 having a pattern as shown in FIG. 18, and by dry etching or wet etching, The insulating film 170 in a region not covered with the contact hole resist 301 is removed, and a passivation film 70 having a contact hole 68 is formed on the drain electrode 64 (see FIG. 19).

Thereafter, the contact hole resist 301 is removed by ashing, and a light-transmitting conductive film 144 such as ITO or tin oxide is applied to the entire surface of the substrate as shown in FIG. Further, a resist is applied on the light-transmitting conductive film 144, and exposure and development are performed through a photomask to form a pixel electrode resist 401 as shown in FIG. In this state, when the transparent conductive film 144 in the region not covered with the pixel electrode resist 401 is removed by dry etching or wet etching, and the pixel electrode resist 401 is removed by ashing, as shown in FIG. Then, the pixel electrode 44 connected to the drain electrode 64 through the contact hole 68 is formed, and the thin film transistor 60 is finally formed on the glass substrate 41.

22, a polyimide rubbing alignment film 45 as shown in FIG. 3 is formed on the pixel electrode 44 to form an element substrate (active matrix substrate) 40, and a glass substrate. A polarizing plate 42 is formed on the side opposite to the pixel electrode 44 side of 41 (FIG. 3). On the other hand, the color filter 33, the counter electrode 34, and the alignment film 35 are formed on the glass substrate 31 as shown in FIG. 3 to create the counter substrate 30, and the glass substrate 31 is placed on the side opposite to the counter electrode 34 side. A polarizing plate 32 is formed (FIG. 3). Then, the element substrate 40 and the counter substrate 30 are bonded to each other through a sealing material (not shown), and a liquid crystal layer 50 is formed by injecting liquid crystal from an injection port (not shown). Is connected to create the liquid crystal panel 11 (FIG. 3). Furthermore, the liquid crystal display device 10 is created by providing the backlight device 12 as shown in FIG.

The liquid crystal display device 10 including the thin film transistor 60 formed by such a method can accurately form the pattern of the semiconductor film 67 in a desired pattern. That is, when the resist 201c for forming the pattern of the semiconductor film 67 is formed as designed, the semiconductor film 67 can be formed into a predetermined pattern by etching using the resist 201c as a mask, and thus the film width. Problems such as an increase in parasitic capacitance due to expansion are unlikely to occur.

In this embodiment, the resist 201c for forming the pattern of the semiconductor film 67 is used by modifying the resist 201 used at the time of etching the conductive films 62 and 61 on the resist 201c. This is because it is possible to perform as designed. Specifically, as shown in FIG. 10, the film thickness of the resist portions 210 and 211 covering the regions to be the source electrode 63 and the drain electrode 64, the region to be the source wiring 80, and the region where the contact hole 68 is to be formed. The film thickness of the resist portions 220 and 221 that cover the outer edge portion is made larger than the film thickness of the resist portions 230 and 231 that cover the region to be the source wiring 80 and the inner portion of the region between the contact hole 68 and the drain electrode 64. At the same time, the resist 201 is configured by making the width of the resist portions 210 and 211 larger than the width of the resist portions 220 and 221. Accordingly, the resist portions 230 and 231 having a small film thickness can be selectively removed by ashing in a later step (FIG. 12), and the remaining thick film portions of the resist portions 220, 210, 211, and 221 are The resist portions 220 and 221 are cured to be cured resists 220a and 221a, and the resist portions 210 and 211 are cured with an uncured portion remaining therein to form the remaining resist 201b as partially cured resists 210c and 211c. (FIG. 13).

Then, by performing thermal reflow on the remaining resist 201b, the uncured portions 210b and 211b of the partially cured resists 210c and 211c are caused to flow and flow out from the cured portions 210a and 211a covered on the outside. In addition, by performing chemical reflow using a solvent, the resist can be flattened in a region inside the hardened resists 220a and 221a, and the flattened resist 201c can be formed. In this case, since the hardened resists 220a and 221a serve as walls during reflow, it is possible to prevent or suppress the occurrence of a problem that the fluidized resist is excessively spread outside. As a result, the spread of the pattern of the semiconductor film 67 can be prevented or suppressed, and it is possible to provide a highly reliable element substrate (active matrix substrate) 40 and thus a highly reliable liquid crystal display device 10. .

As mentioned above, although embodiment which concerns on this invention was described, this invention is not limited to such embodiment, The following forms are also contained in this invention.
For example, in the present embodiment, a liquid crystal display device including a thin film transistor has been described as an example of the display device of the present invention. However, for example, an EL display device including a thin film transistor, a plasma display device, and the like that are driven by pixels as in the present embodiment. Are also included in the present invention.

Claims (14)

1. A gate portion forming step of forming a gate electrode and a gate wiring of a predetermined pattern on the substrate;
   A stacking step of sequentially forming an insulating film, a semiconductor film, and a conductive film on the formed gate electrode and the gate wiring;
   A resist coating step of coating a resist on the conductive film;
   The resist is exposed through a photomask and then developed, whereby the resist film covering a part of the conductive film and the source electrode and the drain electrode, the source wiring, The film thickness of the resist covering the outer edge part of the region to be the source electrode and the drain electrode or a part of the outer edge part is determined by the thickness of the resist covering the inner part of the region to be the source wiring, the source electrode and the drain electrode. The width of the resist that covers a part of the region that becomes the source electrode and the drain electrode is made larger than the film thickness, and the width of the resist that covers the source wiring, the source electrode, and the drain electrode A stepped resist creating step for creating a stepped resist larger than the width of the resist covering the portion;
   Conductive pattern forming step of etching the conductive film using the stepped resist as a mask to form a source electrode, source wiring, and drain electrode of a predetermined pattern;
   Ashing the stepped resist and removing a relatively thin portion of the stepped resist; and
   The resist remaining after the ashing step is exposed to light so that the resist covering the source wiring, the source electrode, and the drain electrode covers a part of the outer edge portion or a part of the outer edge portion, and the source An exposure step of forming a residual resist including an electrode and a partially cured resist obtained by curing the resist covering a part of the drain electrode with an uncured part remaining therein;
   A thermal reflow step for performing thermal reflow on the remaining resist, causing the uncured portion of the partially cured resist to flow, and flowing out from the cured portion covered outside;
   A chemical reflow process for performing chemical reflow on the remaining resist, planarizing the resist in a region inside the cured resist, and creating a planarized resist;
   A semiconductor pattern forming step of etching the semiconductor film using the planarization resist as a mask to form a semiconductor film having a predetermined pattern;
   A method for manufacturing an active matrix substrate, comprising:
2. The stepped resist forming step is characterized in that the stepped resist is formed in a shape having an opening at a position overlapping with a portion of the conductive film where a channel is formed by the semiconductor film. 2. A method for manufacturing an active matrix substrate according to item 1 of the above.
3. 3. The method of manufacturing an active matrix substrate according to claim 2, wherein, in the chemical reflow step, the planarizing resist is formed so as to cover a portion where a channel is formed by the semiconductor film.
4. 4. The method according to claim 1, wherein in the stacking step, a doped semiconductor film to which an impurity is added and a metal conductive film are sequentially stacked as the conductive film. The manufacturing method of the active-matrix board | substrate as described in a term.
5. In the exposure step, the thickness of the cured portion of the partially cured resist is equal to or greater than the width of the cured resist. 5. The method for producing an active matrix substrate according to any one of items 4.
6. 2. The exposure according to claim 1, wherein in the exposure step, the exposure is performed under the conditions of an irradiation wavelength of 200 nm to 400 nm, an irradiation intensity of 1 mW / cm ² to 10 mW / cm ² , and an irradiation time of 1 minute to 5 minutes. A method for manufacturing an active matrix substrate according to any one of claims 1 to 5.
7. The range of claims 1 to 6, wherein, in the thermal reflow step, the substrate is exposed to an environment where the temperature of the substrate becomes 200 ° C to 300 ° C for 10 minutes to 30 minutes. The method for producing an active matrix substrate according to any one of the above.
8. 8. The method according to claim 1, wherein, in the chemical reflow step, alcohol, ether or ester is used as the solvent, and the substrate is exposed to the vapor of the solvent at room temperature. A method for producing an active matrix substrate according to claim 1.
9. 8. The method according to claim 1, wherein, in the chemical reflow step, alcohol, ether or ester is used as the solvent, and the substrate is immersed in the solvent at room temperature. A method for producing an active matrix substrate according to claim 1.
10. In the step of forming a resist with a step, a halftone mask made of a semi-transmissive film or a gray tone mask including a semi-transmissive region by a slit is used as the photomask. 10. A method for manufacturing an active matrix substrate according to any one of items 9 to 10.
11. The gate part creation step includes
    Using a glass substrate as the substrate and forming a gate conductive film on the glass substrate;
    Applying a gate resist on the gate conductive film, exposing and developing through a gate photomask; and
    Removing the gate conductive film in a region not covered with the gate resist by dry etching or wet etching, forming a gate electrode and a gate wiring, and removing the gate resist by ashing;
    The method of manufacturing an active matrix substrate according to any one of claims 1 to 10, characterized by comprising:
12. The laminating step includes
    Forming a gate insulating film using silicon nitride or silicon oxide as the insulating film on the gate electrode and the gate wiring;
    Forming an intrinsic semiconductor film using amorphous silicon as the semiconductor film on the insulating film;
    A doped semiconductor film using amorphous silicon doped with an n-type impurity is formed as the conductive film on the semiconductor film, and any of aluminum, chromium, tantalum, and titanium is used as the conductive film on the doped semiconductor film. A step of forming a single metal film, or any metal nitride film, or a laminate of any metal single film and metal nitride film,
    The method for manufacturing an active matrix substrate according to any one of claims 1 to 11, characterized by comprising:
13. After the semiconductor pattern forming step,
    Removing the planarizing resist by ashing;
    Forming a passivation film on the conductive film;
    Applying a contact resist on the passivation film, exposing and developing through a contact photomask; and
    Removing the passivation film in a region not covered with the contact resist by dry etching or wet etching, and forming a contact portion on the drain electrode;
    Removing the contact resist by ashing;
    Applying a translucent conductive film to the entire surface of the substrate;
    Applying a pixel electrode resist on the translucent conductive film, exposing and developing through a pixel electrode photomask; and
    Removing the transparent conductive film in a region not covered with the pixel electrode resist by dry etching or wet etching, and forming a pixel electrode on the passivation film; and
    Removing the pixel electrode resist by ashing;
    The method for manufacturing an active matrix substrate according to any one of claims 1 to 12, characterized by comprising:
14. Creating an active matrix substrate by the method of any one of claims 1 to 13; and
    Creating a counter substrate including a common electrode on the substrate;
    Bonding the active matrix substrate and the counter substrate, creating a liquid crystal panel in which a liquid crystal layer is formed between the active matrix substrate and the counter substrate;
    A method for manufacturing a display device, comprising:

Images