Nothing Special   »   [go: up one dir, main page]

WO2008155838A1 - 命令処理装置 - Google Patents

命令処理装置 Download PDF

Info

Publication number
WO2008155838A1
WO2008155838A1 PCT/JP2007/062424 JP2007062424W WO2008155838A1 WO 2008155838 A1 WO2008155838 A1 WO 2008155838A1 JP 2007062424 W JP2007062424 W JP 2007062424W WO 2008155838 A1 WO2008155838 A1 WO 2008155838A1
Authority
WO
WIPO (PCT)
Prior art keywords
register
data
current
transfer path
data transfer
Prior art date
Application number
PCT/JP2007/062424
Other languages
English (en)
French (fr)
Inventor
Toshio Yoshida
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to JP2009520192A priority Critical patent/JP5115555B2/ja
Priority to EP07767262A priority patent/EP2169537B1/en
Priority to PCT/JP2007/062424 priority patent/WO2008155838A1/ja
Publication of WO2008155838A1 publication Critical patent/WO2008155838A1/ja
Priority to US12/654,159 priority patent/US7962732B2/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30123—Organisation of register space, e.g. banked or distributed register file according to context, e.g. thread buffers
    • G06F9/30127—Register windows
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

　複数の命令を有するスレッドを実行するスレッド実行処理部と、複数のレジスタを備えたレジスタウィンドウを有するレジスタファイルと、レジスタウィンドウが入出力可能なレジスタの位置を示すカレントウィンドウポインタと、カレントウィンドウポインタにより指定されるレジスタウィンドウが保持するデータを読み出して保持するカレントレジスタと、レジスタファイルからカレントレジスタに転送されるデータを保持する置換バッファと、レジスタファイル内のデータを置換バッファに転送する第１のデータ転送路と、置換バッファ内のデータをカレントレジスタに転送する第２のデータ転送路と、レジスタウィンドウの切替命令を実行する演算手段と、演算手段が切替命令を実行した場合には、切替命令を有するスレッドに対応して、第１のデータ転送路と第２のデータ転送路を制御する制御手段を備えた。
PCT/JP2007/062424 2007-06-20 2007-06-20 命令処理装置 WO2008155838A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2009520192A JP5115555B2 (ja) 2007-06-20 2007-06-20 演算処理装置
EP07767262A EP2169537B1 (en) 2007-06-20 2007-06-20 Instruction processor
PCT/JP2007/062424 WO2008155838A1 (ja) 2007-06-20 2007-06-20 命令処理装置
US12/654,159 US7962732B2 (en) 2007-06-20 2009-12-11 Instruction processing apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/062424 WO2008155838A1 (ja) 2007-06-20 2007-06-20 命令処理装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/654,159 Continuation US7962732B2 (en) 2007-06-20 2009-12-11 Instruction processing apparatus

Publications (1)

Publication Number Publication Date
WO2008155838A1 true WO2008155838A1 (ja) 2008-12-24

Family

ID=40156004

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/062424 WO2008155838A1 (ja) 2007-06-20 2007-06-20 命令処理装置

Country Status (4)

Country Link
US (1) US7962732B2 (ja)
EP (1) EP2169537B1 (ja)
JP (1) JP5115555B2 (ja)
WO (1) WO2008155838A1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5316407B2 (ja) * 2007-06-20 2013-10-16 富士通株式会社 演算処理装置および演算処理装置の制御方法
JP2015014891A (ja) * 2013-07-04 2015-01-22 富士通株式会社 演算処理装置及び演算処理装置の制御方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103916316A (zh) * 2014-04-11 2014-07-09 国家计算机网络与信息安全管理中心 网络数据包线速捕获方法
JP2016081169A (ja) * 2014-10-14 2016-05-16 富士通株式会社 情報処理装置、データ処理システム、データ処理管理プログラム、及び、データ処理管理方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006039815A (ja) * 2004-07-26 2006-02-09 Fujitsu Ltd マルチスレッドプロセッサおよびレジスタ制御方法
JP2006040141A (ja) * 2004-07-29 2006-02-09 Fujitsu Ltd マルチスレッドプロセッサ
JP2007087108A (ja) * 2005-09-22 2007-04-05 Fujitsu Ltd 演算処理装置，情報処理装置，及びレジスタファイルの制御方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3169779B2 (ja) * 1994-12-19 2001-05-28 日本電気株式会社 マルチスレッドプロセッサ
US5933627A (en) * 1996-07-01 1999-08-03 Sun Microsystems Thread switch on blocked load or store using instruction thread field
US7272703B2 (en) * 1997-08-01 2007-09-18 Micron Technology, Inc. Program controlled embedded-DRAM-DSP architecture and methods
US20040030873A1 (en) * 1998-10-22 2004-02-12 Kyoung Park Single chip multiprocessing microprocessor having synchronization register file
US6542991B1 (en) * 1999-05-11 2003-04-01 Sun Microsystems, Inc. Multiple-thread processor with single-thread interface shared among threads
WO2008155801A1 (ja) * 2007-06-20 2008-12-24 Fujitsu Limited 情報処理装置及びレジスタ制御方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006039815A (ja) * 2004-07-26 2006-02-09 Fujitsu Ltd マルチスレッドプロセッサおよびレジスタ制御方法
JP2006040141A (ja) * 2004-07-29 2006-02-09 Fujitsu Ltd マルチスレッドプロセッサ
JP2007087108A (ja) * 2005-09-22 2007-04-05 Fujitsu Ltd 演算処理装置，情報処理装置，及びレジスタファイルの制御方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5316407B2 (ja) * 2007-06-20 2013-10-16 富士通株式会社 演算処理装置および演算処理装置の制御方法
JP2015014891A (ja) * 2013-07-04 2015-01-22 富士通株式会社 演算処理装置及び演算処理装置の制御方法

Also Published As

Publication number Publication date
EP2169537B1 (en) 2013-02-27
JPWO2008155838A1 (ja) 2010-08-26
EP2169537A4 (en) 2010-09-08
JP5115555B2 (ja) 2013-01-09
US7962732B2 (en) 2011-06-14
US20100095095A1 (en) 2010-04-15
EP2169537A1 (en) 2010-03-31

Similar Documents

Publication Publication Date Title
WO2013188120A3 (en) Zero cycle load
WO2012138950A3 (en) Conditional load instructions in an out-of-order execution microprocessor
EP3362889B1 (en) Move prefix instruction
JP6143872B2 (ja) 装置、方法、およびシステム
KR101712864B1 (ko) 다수의 테스트 소스에 대한 or-테스트 및 and-테스트 기능을 제공하는 명령어를 융합하는 방법 및 장치
WO2014004050A3 (en) Systems, apparatuses, and methods for performing a shuffle and operation (shuffle-op)
GB2447968B (en) Improvements in and relating to floating point operations
WO2008030093A3 (en) Data processing circuit with a plurality of instruction modes
TW200710718A (en) Register file for a digital signal processor operating in an interleaved multi-threaded environment
GB201211274D0 (en) Method and system method for pipelining out-of-order instructions
WO2009099558A3 (en) Computer system including a main processor and a bound security coprocessor
WO2008061105A3 (en) Method and system for instruction stuffing operations during non-intrusive digital signal processor debugging
EP2660715A3 (en) Optimizing register initialization operations
EP4250101A3 (en) Vector friendly instruction format and execution thereof
EP2508979A3 (en) Efficient conditional ALU instruction in read-port limited register file microprocessor
ATE514998T1 (de) Getaktete ports
TW200704216A (en) Selection of a communication interface
WO2012078735A3 (en) Performing function calls using single instruction multiple data (simd) registers
WO2014051733A3 (en) Vector move instruction controlled by read and write masks
TW200731739A (en) Cryptography system and elliptic curve operation method involved thereof
WO2007107707A3 (en) Computer architecture
WO2008155838A1 (ja) 命令処理装置
EP2796990A3 (en) Apparatus and method for supporting multi-modes of processor
EP1768020A3 (en) Arithmetic operation apparatus, information processing apparatus and register file control method
TW200519752A (en) Mechanism for enabling a program to be executed while the execution of an operating system is suspended

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07767262

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2009520192

Country of ref document: JP

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 2007767262

Country of ref document: EP

NENP Non-entry into the national phase

Ref country code: DE