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WO2008149446A1 - 半導体製造装置および方法 - Google Patents

半導体製造装置および方法 Download PDF

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Publication number
WO2008149446A1
WO2008149446A1 PCT/JP2007/061570 JP2007061570W WO2008149446A1 WO 2008149446 A1 WO2008149446 A1 WO 2008149446A1 JP 2007061570 W JP2007061570 W JP 2007061570W WO 2008149446 A1 WO2008149446 A1 WO 2008149446A1
Authority
WO
WIPO (PCT)
Prior art keywords
treating chamber
film
chamber
dielectric constant
high dielectric
Prior art date
Application number
PCT/JP2007/061570
Other languages
English (en)
French (fr)
Inventor
Naomu Kitano
Takashi Minami
Motomu Kosuda
Heiji Watanabe
Original Assignee
Canon Anelva Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Anelva Corporation filed Critical Canon Anelva Corporation
Priority to PCT/JP2007/061570 priority Critical patent/WO2008149446A1/ja
Priority to TW097112008A priority patent/TWI392022B/zh
Publication of WO2008149446A1 publication Critical patent/WO2008149446A1/ja
Priority to US12/631,286 priority patent/US8088678B2/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67207—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28229—Making the insulator by deposition of a layer, e.g. metal, metal compound or poysilicon, followed by transformation thereof into an insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
    • H01L21/31683—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of metallic layers, e.g. Al deposited on the body, e.g. formation of multi-layer insulating structures
    • H01L29/513—
    • H01L29/517—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02142—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides
    • H01L21/02148—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides the material containing hafnium, e.g. HfSiOx or HfSiON
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02244—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of a metallic layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Formation Of Insulating Films (AREA)
  • Chemical Vapour Deposition (AREA)
  • Physical Vapour Deposition (AREA)

Abstract

本発明の第１の側面は、ロードロック室と搬送室とプラズマを用いた処理を行う処理室1と処理室2を有し、処理室2においては、排気手段に、酸素分圧が1×10-5[Pa]以下にするための制御手段が取り付けられていることを特徴とする半導体製造装置である。本発明の第２の側面は、高誘電率膜と金属電極を連続で形成する方法であって、処理室1で、シリコン酸化膜または、シリコン酸窒化膜上に金属膜を堆積させるステップ1と処理室2において処理室1で形成した金属膜を用いて高誘電率膜に形成するステップ2と処理室1もしくは、増設した処理室3において処理室2で形成した高誘電膜上に金属電極材料を堆積させるステップ3を含む方法において、大気に晒すことなく、各ステップが連続的に行われることを特徴とする。
PCT/JP2007/061570 2007-06-07 2007-06-07 半導体製造装置および方法 WO2008149446A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
PCT/JP2007/061570 WO2008149446A1 (ja) 2007-06-07 2007-06-07 半導体製造装置および方法
TW097112008A TWI392022B (zh) 2007-06-07 2008-04-02 Semiconductor device manufacturing apparatus and method
US12/631,286 US8088678B2 (en) 2007-06-07 2009-12-04 Semiconductor manufacturing apparatus and method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/061570 WO2008149446A1 (ja) 2007-06-07 2007-06-07 半導体製造装置および方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/631,286 Continuation US8088678B2 (en) 2007-06-07 2009-12-04 Semiconductor manufacturing apparatus and method

Publications (1)

Publication Number Publication Date
WO2008149446A1 true WO2008149446A1 (ja) 2008-12-11

Family

ID=40093281

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/061570 WO2008149446A1 (ja) 2007-06-07 2007-06-07 半導体製造装置および方法

Country Status (3)

Country Link
US (1) US8088678B2 (ja)
TW (1) TWI392022B (ja)
WO (1) WO2008149446A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019515490A (ja) * 2016-04-20 2019-06-06 トルンプフ フォトニクス インコーポレイテッドＴｒｕｍｐｆ Ｐｈｏｔｏｎｉｃｓ Ｉｎｃ． レーザ切子面のパッシベーションおよび当該パッシベーションを実施するためのシステム

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* Cited by examiner, † Cited by third party
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WO2009157341A1 (ja) 2008-06-25 2009-12-30 キヤノンアネルバ株式会社 スパッタリング装置及びその制御用プログラムを記録した記録媒体
WO2010008021A1 (ja) * 2008-07-15 2010-01-21 キヤノンアネルバ株式会社 プラズマ処理方法及びプラズマ処理装置
KR101052587B1 (ko) 2008-10-31 2011-07-29 캐논 아네르바 가부시키가이샤 유전체막 및 유전체막을 사용하는 반도체 디바이스
KR101126650B1 (ko) * 2008-10-31 2012-03-26 캐논 아네르바 가부시키가이샤 유전체막의 제조 방법
JP5247619B2 (ja) * 2009-07-28 2013-07-24 キヤノンアネルバ株式会社 誘電体膜、誘電体膜を用いた半導体装置の製造方法及び半導体製造装置
JP2011151366A (ja) 2009-12-26 2011-08-04 Canon Anelva Corp 誘電体膜の製造方法
JP5937297B2 (ja) * 2010-03-01 2016-06-22 キヤノンアネルバ株式会社 金属窒化膜、該金属窒化膜を用いた半導体装置、および半導体装置の製造方法
KR101409433B1 (ko) 2010-12-28 2014-06-24 캐논 아네르바 가부시키가이샤 반도체 디바이스 제조방법 및 장치
US9305998B2 (en) * 2013-02-11 2016-04-05 Texas Instruments Incorporated Adhesion of ferroelectric material to underlying conductive capacitor plate
TWI635539B (zh) * 2017-09-15 2018-09-11 金巨達國際股份有限公司 高介電常數介電層、其製造方法及執行該方法之多功能設備
US10998209B2 (en) 2019-05-31 2021-05-04 Applied Materials, Inc. Substrate processing platforms including multiple processing chambers
US12080571B2 (en) 2020-07-08 2024-09-03 Applied Materials, Inc. Substrate processing module and method of moving a workpiece
US11817331B2 (en) 2020-07-27 2023-11-14 Applied Materials, Inc. Substrate holder replacement with protective disk during pasting process
US11749542B2 (en) 2020-07-27 2023-09-05 Applied Materials, Inc. Apparatus, system, and method for non-contact temperature monitoring of substrate supports
US11600507B2 (en) 2020-09-09 2023-03-07 Applied Materials, Inc. Pedestal assembly for a substrate processing chamber
US11610799B2 (en) 2020-09-18 2023-03-21 Applied Materials, Inc. Electrostatic chuck having a heating and chucking capabilities
US11674227B2 (en) 2021-02-03 2023-06-13 Applied Materials, Inc. Symmetric pump down mini-volume with laminar flow cavity gas injection for high and low pressure
US12002668B2 (en) 2021-06-25 2024-06-04 Applied Materials, Inc. Thermal management hardware for uniform temperature control for enhanced bake-out for cluster tool
US20230323524A1 (en) * 2022-04-07 2023-10-12 Cantech Inc. Quartz crystal sensor coated with gold-aluminum by magnetron sputtering

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JP2002184773A (ja) * 2000-12-19 2002-06-28 Nec Corp 高誘電率薄膜の成膜方法及び高誘電率薄膜を用いた半導体装置の製造方法
JP2003249497A (ja) * 2001-12-18 2003-09-05 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
WO2004008544A1 (ja) * 2002-07-16 2004-01-22 Nec Corporation 半導体装置、その製造方法およびその製造装置
JP2006237371A (ja) * 2005-02-25 2006-09-07 Canon Anelva Corp ｈｉｇｈ−Ｋ誘電膜上に金属ゲートを蒸着する方法及び、ｈｉｇｈ−Ｋ誘電膜と金属ゲートとの界面を向上させる方法、並びに、基板処理システム

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019515490A (ja) * 2016-04-20 2019-06-06 トルンプフ フォトニクス インコーポレイテッドＴｒｕｍｐｆ Ｐｈｏｔｏｎｉｃｓ Ｉｎｃ． レーザ切子面のパッシベーションおよび当該パッシベーションを実施するためのシステム

Also Published As

Publication number Publication date
US20100120238A1 (en) 2010-05-13
US8088678B2 (en) 2012-01-03
TWI392022B (zh) 2013-04-01
TW200903639A (en) 2009-01-16

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