WO2007110940A1 - Semiconductor device and its fabrication process - Google Patents
Semiconductor device and its fabrication process Download PDFInfo
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- WO2007110940A1 WO2007110940A1 PCT/JP2006/306424 JP2006306424W WO2007110940A1 WO 2007110940 A1 WO2007110940 A1 WO 2007110940A1 JP 2006306424 W JP2006306424 W JP 2006306424W WO 2007110940 A1 WO2007110940 A1 WO 2007110940A1
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- metal
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- gate electrode
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- insulating layer
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 49
- 238000000034 method Methods 0.000 title claims abstract description 46
- 238000004519 manufacturing process Methods 0.000 title claims description 39
- 229910052751 metal Inorganic materials 0.000 claims abstract description 261
- 239000002184 metal Substances 0.000 claims abstract description 261
- 239000013078 crystal Substances 0.000 claims abstract description 24
- 239000012535 impurity Substances 0.000 claims description 42
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 33
- 239000000758 substrate Substances 0.000 claims description 25
- 238000010438 heat treatment Methods 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 16
- 239000007790 solid phase Substances 0.000 claims description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052759 nickel Inorganic materials 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 9
- 239000010949 copper Substances 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 8
- 239000010931 gold Substances 0.000 claims description 8
- 238000005286 illumination Methods 0.000 claims description 6
- 230000008018 melting Effects 0.000 claims description 6
- 238000002844 melting Methods 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 2
- 229910052732 germanium Inorganic materials 0.000 claims description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims 3
- 238000009413 insulation Methods 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 147
- 229910021417 amorphous silicon Inorganic materials 0.000 description 69
- 230000001681 protective effect Effects 0.000 description 41
- 238000002955 isolation Methods 0.000 description 24
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 24
- 238000010586 diagram Methods 0.000 description 15
- 238000005229 chemical vapour deposition Methods 0.000 description 13
- 230000005684 electric field Effects 0.000 description 10
- 239000011229 interlayer Substances 0.000 description 9
- 238000000206 photolithography Methods 0.000 description 9
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 8
- 238000005468 ion implantation Methods 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 239000003870 refractory metal Substances 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 238000003892 spreading Methods 0.000 description 2
- MMOXZBCLCQITDF-UHFFFAOYSA-N N,N-diethyl-m-toluamide Chemical compound CCN(CC)C(=O)C1=CC=CC(C)=C1 MMOXZBCLCQITDF-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- RJCRUVXAWQRZKQ-UHFFFAOYSA-N oxosilicon;silicon Chemical compound [Si].[Si]=O RJCRUVXAWQRZKQ-UHFFFAOYSA-N 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
- H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
Definitions
- the present invention relates to a semiconductor device having a MISFET (Metal Insulator Semiconductor Field Effect Transistor) and a manufacturing method thereof, and more particularly to a semiconductor device having a MISFET having a multi-gate structure and a manufacturing method thereof.
- MISFET Metal Insulator Semiconductor Field Effect Transistor
- MISFETs having a gate electrode and source / drain regions are expected to improve the performance of MISFETs as the distance between the source and the drain decreases as the width of the gate electrode is reduced.
- MISFET performance for example, on-current, does not improve by reducing the width of the gate electrode.
- the MISFET on-resistance is composed of the source and drain resistance and the resistance between the source and drain when the channel region directly under the gate electrode is turned on. This is because the on-resistance of the entire MISFET does not decrease.
- the other reason why the on-current is not improved is that polycrystalline silicon is also a semiconductor, and therefore a depletion layer is generated on the polycrystalline silicon side at the interface between the polycrystalline silicon constituting the electrode and the gate insulating film.
- Patent Document 1 discloses a MISFET having a so-called multi-gate electrode structure in which a gate electrode is disposed so as to sandwich a channel region having a rectangular cross section from two opposing directions.
- a MISFET having a structure in which source and drain electrodes are arranged in two opposite directions is disclosed. Therefore, a two-direction force electric field is generated in the channel region by the gate electrode made of polycrystalline silicon arranged in two directions. Then, the leakage current between the source and drain is prevented by the electric field from two directions.
- the source and drain electrode forces are placed in direct contact with the channel region from the other two opposing directions, with no distance. Then, the structure has almost no source / drain resistance.
- Patent Document 1 Japanese Patent Laid-Open No. 2001-284598
- the gate electrode is made of polycrystalline silicon. If the electric field generated in the channel region is reduced by the depletion layer generated on the polycrystalline silicon side, the phenomenon cannot be suppressed. .
- the heat treatment is as low as about 500 ° C.
- the crystallinity is very poor, and a leakage current is generated between the source and drain due to the current transmitted through the silicon grain boundary. It is an object of the present invention to provide a MISFET having a metal gate electrode and a multi-gate electrode structure in which a leakage current between a source and a drain is reduced, and a method for manufacturing the MISF ET.
- the MISFET according to the present invention includes a first metal gate electrode, a second metal gate electrode disposed in parallel with the extending direction of the first metal gate electrode and in parallel with the first metal gate electrode, A first semiconductor layer sandwiched between a first metal gate electrode and the second metal gate electrode via a gate insulating film; adjacent to both sides of the first semiconductor layer; and A second semiconductor layer adjacent to both sides of the first metal gate electrode and the second metal gate electrode, wherein a source is formed on one side and a drain is formed on the other side.
- One semiconductor layer has needle-like crystal grains perpendicular to the extending direction of the first metal gate electrode and the second metal gate electrode.
- the present invention provides a method for manufacturing the following MISFET.
- Method of manufacturing MISFET A second metal in the same direction and parallel to the extending direction of the first metal gate electrode so that a cavity is formed between the first metal gate electrode and the first metal gate.
- the present invention can provide a MISFET having a metal gate electrode, a multi-gate electrode structure, and a structure in which a leakage current between a source and a drain is reduced, and a method for manufacturing the MISFET.
- FIG. 1 is a plan view of a MISFET of Example 1.
- FIG. 2A and FIG. 2B are cross-sectional views showing a cross section taken along the line AB of FIG. 1 and a cross section taken along the line CD.
- FIG. 3A to FIG. 3F are cross-sectional views showing a part of the process for manufacturing the MISFET 1 of the first embodiment.
- FIG. 4A to 4F are cross-sectional views showing a part of the process for manufacturing the MISFET 1 of Example 1.
- FIG. 4A to 4F are cross-sectional views showing a part of the process for manufacturing the MISFET 1 of Example 1.
- FIG. 5A to FIG. 5F are cross-sectional views showing a part of the process for manufacturing the MISFET 1 of the first embodiment.
- FIG. 6A to 6F are cross-sectional views showing a part of a process for manufacturing the MISFET 1 of Example 1.
- FIG. 6A to 6F are cross-sectional views showing a part of a process for manufacturing the MISFET 1 of Example 1.
- FIG. 7A to FIG. 7F are cross-sectional views showing a part of the process for manufacturing the MISFET 1 of the first embodiment.
- FIG. 8A to FIG. 8F are cross-sectional views showing a part of the steps constituting the manufacturing method of the MISFET 1 of Example 3.
- FIG. 9A to FIG. 9F are cross-sectional views showing a part of the steps constituting the manufacturing method of the MISFET 1 of Example 3.
- FIG. 10A and FIG. 10B are cross-sectional views showing a part of the steps constituting the manufacturing method of the MISFET 1 of Example 3.
- Example 1 Example 1, Example 2, and Example 3 of the present invention will be described. [0012] (Example 1)
- Example 1 relates to a MIS FET which is a metal gate electrode and has a multi-gate electrode structure. Example 1 will be described with reference to FIGS. 1, 2A, and 2B.
- FIG. 1 is a plan view of the MISFET according to the first embodiment. 1 shows a field region 2 that defines MISFET 1, an upper metal gate electrode 3, a lower metal gate electrode 4, needle-like crystal grains 5, a channel region 6 of MISFET 1, a region 7 into which metal impurities are introduced, An insulating layer 8 for element isolation, a source / drain region 12 of the MISFET, and a contact window 15 connected to the source / drain region 12 are shown.
- the field region 2 that defines the MISFET 1 is surrounded by an insulating layer 8 for element isolation.
- the field region 2 is, for example, a rectangle having a horizontal width of 3 to 10 ⁇ m and a vertical width of 4 to 5 ⁇ m.
- the vertical direction is the direction connecting the source and drain of the MISFET
- the horizontal direction is the direction perpendicular to the direction connecting the source and drain of the MISFET.
- the channel region 6 of the MISFET 1 is located at the center of the field region 2 that defines the MISFET 1.
- the channel region 2 is, for example, a rectangle having a channel width of 2 to 3 ⁇ m and a channel length of 5 Onm.
- the channel length is the length of the channel region 2 in the direction connecting the source and drain of the MISFET
- the channel width is the channel region 2 in the direction perpendicular to the direction connecting the source and drain of the MISFET. Length!
- the lower metal gate electrode 4 is a metal gate electrode disposed under the channel region 6.
- the lower metal gate electrode 4 extends in the field region 2 in a direction perpendicular to the direction connecting the source and drain of the MISFET. Therefore, the lower metal gate electrode 4 has a rectangular shape.
- the width is 50 nm as in the channel length, and the length is 4 to 5 ⁇ m as in the vertical width of the field region 2.
- the upper metal gate electrode 3 is a metal gate electrode disposed above the channel region 6.
- the upper metal gate electrode 3 extends in a direction perpendicular to the direction connecting the source and drain of the MISFET. That is, the upper metal gate electrode 3 is arranged in parallel with the lower metal gate electrode 4 in the same direction as the direction in which the lower metal gate electrode 4 extends.
- the upper metal gate electrode 3 and the lower metal gate electrode 4 Are placed across the channel region 6. Therefore, the width of the upper metal gate electrode is, for example, 50 nm, similar to the channel length.
- the source / drain region 12 is disposed adjacent to both sides of the upper metal gate electrode 3 and the lower metal gate electrode 4. Therefore, the source / drain region 12 is also adjacent to both sides of the channel region 6.
- the region 7 into which the metal impurity has been introduced is disposed in the source / drain region 12 and is a rectangular region.
- the upper metal gate electrode is arranged on both sides of the channel region 6.
- the needle-like crystal grains 5 exist in the source / drain region 12 and the channel region 6 and between the regions 7 into which metal impurities are introduced. And the longitudinal direction of the acicular crystal grains 5 is
- the contact window 15 is an opening for connecting a wiring to the source / drain region 12.
- 2A and 2B are cross-sectional views showing a cross section taken along the line AB of FIG. 1 and a cross section taken along the line CD.
- 2A and 2B show a field region 2 that defines the MISFET 1, an upper metal gate electrode 3, a lower metal gate electrode 4, and needle-like crystal grains 5.
- FIG. 2A is a cross-sectional view taken along a dotted line AB in FIG.
- the MISFET 1 is formed on the substrate 13.
- the field region 2 of the MISFET 1 is surrounded by an insulating layer 8 for element isolation.
- the channel region 6 is arranged in the center of the field region 2.
- the channel region 6 includes a gate insulating film 10 between the upper metal gate electrode 3 and the channel region 6 and a lower metal gate electrode 4 by an upper metal gate electrode 3 and a lower metal gate electrode 4. It is sandwiched between the channel region 6 via the gate insulating film 11.
- the channel region 6 is perpendicular to the direction connecting the source and drain of the MISFET.
- the upper metal electrode 3 or the lower metal electrode 4 is sandwiched between the left and right sides.
- the channel region 6 is surrounded by the upper metal gate electrode 3 and the lower metal gate electrode 4 in the cross section along the dotted line AB in FIG.
- the structure surrounded by the upper metal gate electrode 3 and the lower metal gate electrode 4 in the channel region 6 force is called a gate all around structure.
- the channel region 6 is filled with a bundle of needle-like crystal grains 5 extending in the direction connecting the source and drain of the MISFET.
- the lower metal gate electrode 4 is deposited on the substrate 13.
- An interlayer insulating layer 9 is deposited on the upper metal gate electrode 3.
- FIG. 2B is a cross-sectional view taken along the line CD in FIG.
- the field region 2 of the MISFET 1 is surrounded by an insulating layer 8 for element isolation.
- the channel region 6, the lower metal gate electrode 4, and the upper metal gate electrode 3 are arranged in the center of the field region 2.
- a polycrystalline silicon region 18 and a lower metal gate electrode 4 are formed on the substrate 13.
- the polycrystalline silicon region 18 is a region constituted by polycrystalline silicon in the field region 2. That is, the polycrystalline silicon region 18 is a region up to the bottom force substrate of the channel region 6, the source 'drain region 12, and the source' drain region 12, and the lower metal gate electrode 4 and the upper metal region. A region force is arranged on both sides of the gate electrode 3.
- the source / drain region 12 is a semiconductor region adjacent to both sides of the channel region 6, and is a region composed of polycrystalline silicon into which impurities are introduced. Accordingly, the source / drain region 12 is adjacent to both sides of the upper metal gate electrode 3 and the lower metal gate electrode 4.
- the above-mentioned impurities are N-type impurities when MISFET 1 is N-type, and P-type impurities when MISFET 1 is P-type.
- the region 7 into which the metal impurity has been introduced is a region formed on the surface of the source / drain region 12, and is a region arranged so as to extend in parallel to both sides of the channel region 6. . That is, the upper metal gate electrode 3 extends in the region 7 into which the metal impurity is introduced. And extending in parallel to both sides of the upper metal gate electrode. In the region 7 into which the metal impurity is introduced, a metal that causes a metal-induced solid phase growth phenomenon is introduced.
- the metal-induced solid phase growth phenomenon is formed by doping a metal impurity into an amorphous semiconductor (amorphous semiconductor) when heat treatment is applied to the amorphous semiconductor (amorphous semiconductor).
- a metal impurity is a phenomenon in which a semiconductor crystal grows with a compound of a metal and a semiconductor as a nucleus.
- a poly semiconductor layer with good crystallinity can be formed in a short time at a low temperature of less than 600 ° C.
- the semiconductor is silicon (Si), nickel (Ni), copper (Cu), gold (Au), platinum (Pt), etc. are known as metal impurities that cause the above-described induced solid phase growth phenomenon. ing.
- the semiconductor is germanium (Ge), gold (Au) or the like is known as a metal impurity that causes an induced solid phase growth phenomenon.
- gold (Au) or the like is known as a metal impurity that causes an induced solid phase growth phenomenon.
- silicon germanium (SiGe) gold (Au) or the like is known as a metal impurity that causes an induced solid phase growth phenomenon.
- silicon germanium (SiGe) or the like is known as a metal impurity that causes an induced solid phase growth phenomenon.
- the metal introduced into the region 7 into which the metal impurity has been introduced diffuses into the amorphous silicon and grows a silicon crystal.
- a polycrystalline silicon region 18 made of polycrystalline silicon is formed.
- the heat treatment for growing polycrystalline silicon is less than 600 ° C. Therefore, the lower metal gate electrode 4 is not affected by the heat treatment and is maintained.
- the region 7 into which the metal impurities are introduced extends in parallel to both sides of the channel region 6! /, And connects the source and drain of the MISFET. Metal impurities diffuse in the direction. Therefore, acicular crystal grains 5 grow in the channel region 6, and the channel region 6 is constituted by the acicular crystal grains 5.
- the contact window 15 is a window for connecting a metal wiring to the source / drain region 12. Therefore, a resist pattern having an opening corresponding to the contact window 15 is formed on the interlayer insulating layer 9 by a photolithography method, and the interlayer insulating layer 9 is etched using the resist pattern as a mask.
- the gate insulating film 10 and the gate insulating film 11 are formed on the upper metal gate electrode 3 and the lower gate metal electrode 4. Since the channel region 6 sandwiched between them is composed of the needle-like crystal grains 5, the leakage current between the source and the drain is reduced. This is because the carrier carrying the current flowing between the source and the drain flows through the needle-like crystal grains 5 having good crystallinity. The depletion layer generated by the electric field from the upper metal gate electrode 3 and the lower gate metal electrode 4 dominates the current path in the needle-like crystal grains 5. As a result, the carrier responsible for the current flowing between the source and drain is the force that is completely cut off when the MISFET is off. When a plurality of crystal grains exist between the source and the drain, the carrier carrying the current flowing between the source and the drain is transmitted through the grain boundary of the crystal grains and leaks. As a result, a leak current is generated between the source and the drain.
- a MISFET having a metal gate electrode, a multi-gate electrode structure, and a structure in which a leakage current between a source and a drain is reduced.
- Example 2 relates to a method of manufacturing a MIS FET that is a metal gate electrode and has a multi-gate electrode structure.
- Example 2 will be described with reference to FIGS. 3A to 3F, FIGS. 4A to 4F, FIGS. 5A to 5B, FIGS. 6A to 6F, and FIGS. 7A to 7D.
- 3A to 3F are cross-sectional views showing a part of the process for manufacturing the MISFET 1 of the first embodiment.
- 3A, 3B, and 3C are cross-sectional views taken along the line C-D in FIG. 3D
- FIG. 3E, and FIG. 3F show cross-sectional views along the dotted line AB in FIG. 3A to 3F show the substrate 13, the insulating layer 8 for element isolation, the metal layer for the lower metal gate electrode 4, the channel region 6, the amorphous silicon layer (amorphous silicon layer) 19, and the protective film.
- 20 shows a protective film 21 and a sidewall film 23.
- FIGS. 3A and 3D are diagrams showing the following steps.
- an insulating layer 8 for element isolation is deposited on the substrate 13 by the CVD method, and a resist pattern having an opening corresponding to the field region 2 is formed on the insulating layer 8 for element isolation by the photolithography method.
- the insulating layer 8 for element isolation is etched until the surface of the substrate 13 appears, and the resist pattern is removed.
- a metal layer for forming the lower metal gate electrode 4 is deposited on the substrate 13 by a notching method or a CVD method.
- the metal constituting the metal layer is preferably a refractory metal such as tantasten (W) or molybdenum (Mo).
- the protective film 20 is deposited by PECVD (plasma enhanced chemical vapor deposition), LPCVD (low pressure chemical vapor deposition), ALD (atomic layer deposition), or sputtering.
- the protective film 20 may be made of an oxide silicon (SiO 2) film, an oxide silicon nitride (SiO 2)
- N nitride film (SiN) film, high dielectric film (high-k material) may be used.
- FIG. 3B and FIG. 3E are diagrams showing the following steps. First, after the steps shown in FIGS. 3A and 3D are completed, an amorphous silicon layer (amorphous silicon layer) 19 is deposited by a plasma CVD method. Thereafter, the protective film 21 is deposited by the CVD method. Then, a resist is applied on the protective film 21, and a resist pattern is formed so that the resist remains in a region corresponding to the channel region 6 by a photolithography method.
- the protective film 21 By performing anisotropic etching on the protective film 21, the amorphous silicon layer (amorphous silicon layer) 19, and the protective film 20 on the resist pattern mask, the protective film 21, amorphous silicon The layer (amorphous silicon layer) 19 and the protective film 20 are patterned. As a result, the cross-sectional shape shown in the cross-sectional views of FIGS. 3B and 3E is obtained.
- the method of depositing the protective film 21 it is also possible to use the PECVD method or the like as with the protective film 20. Needless to say, the material of the protective film 21 may be a nitride film (SiN) or the like, similar to the protective film 20.
- FIG. 3C and FIG. 3F are views showing the following steps. After completing the steps shown in FIGS. 3B and 3E, a protective film is deposited by CVD. Thereafter, the sidewall film 23 is formed on the side surface of the patterned amorphous silicon layer (amorphous silicon layer) 19 by performing anisotropic etching on the protective film. As a result, the cross-sectional shape shown in the cross-sectional views of FIGS. 3C and 3F is obtained.
- the protective film includes an oxide silicon (SiO 2) film, an oxide silicon nitride (SiON) film, and a nitride film (S
- FIGS. 4A to 4F are diagrams showing a process for manufacturing the MISFET 1 of the first embodiment, following FIG. It is sectional drawing which shows a part.
- 4A, 4B, and 4C are cross-sectional views taken along the line C-D in FIG. 4D, 4E, and 4F show cross-sectional views along the dotted line AB in FIG. 4A to 4F show the substrate 13, the isolation layer 8 for element isolation, the metal layer for the lower metal gate electrode 4, the metal layer for the upper metal gate electrode 3, the channel region 6, the amorphous region.
- a silicon layer (amorphous silicon layer) 19, a protective film 20, a protective film 21, and a side wall film 23 are shown.
- FIG. 4A and FIG. 4D are diagrams showing the following steps. After completing the steps of FIG. 3C and FIG. 3F, a metal layer for the upper metal gate electrode 3 is deposited by sputtering or CVD. As a result, a cross-sectional shape as shown in FIGS. 4A and 4D is obtained.
- the metal of the metal layer is preferably a refractory metal such as tandasten (W), as is the metal of the metal layer for the lower metal gate electrode 4.
- FIG. 4B and FIG. 4E are diagrams showing the following steps. 4A and 4D is completed, a resist is applied on the metal layer of the upper metal gate electrode 3, and a resist pattern corresponding to the gate electrode is formed by a photolithography method. Then, using the above resist pattern as a mask, the upper metal layer for metal gate electrode 3, gate insulating film 10, amorphous silicon layer (amorphous silicon layer) 19, gate insulating film by anisotropic etching 11. Etch the metal layer for the lower metal gate electrode 4. Then, as a result of removing the resist pattern, the cross-sectional shapes of FIGS. 4B and 4E are obtained.
- FIG. 4C and FIG. 4F are views showing the following steps. After the process of FIGS. 4B and 4E is completed, the amorphous silicon layer (amorphous silicon layer) 19 existing in the channel region 6 is etched and removed by an isotropic etching method. As a result, the portion corresponding to the channel region 6 becomes a cavity, and the cross-sectional shapes as shown in FIGS. 4C and 4F are obtained.
- the amorphous silicon layer (amorphous silicon layer) 19 existing in the channel region 6 is etched and removed by an isotropic etching method. As a result, the portion corresponding to the channel region 6 becomes a cavity, and the cross-sectional shapes as shown in FIGS. 4C and 4F are obtained.
- FIGS. 5A to 5F are cross-sectional views illustrating a part of the process for manufacturing the MISFET 1 of Example 1 following FIG. 5A, FIG. 5B, and FIG. 5C show cross-sectional views along the line CD in FIG. 5D, 5E, and 5F are cross-sectional views taken along the dotted line AB in FIG. 5A to 5F show a substrate 13, a field region 2, a region 7 into which a metal impurity is introduced, an insulating layer 8 for element isolation, a metal layer for a lower metal gate electrode 4, and an upper metal gate electrode.
- Metal layer for 3, channel region 6, gate insulating film 10, gate An insulating film 11, an amorphous silicon layer (amorphous silicon layer) 19, an amorphous silicon layer (amorphous silicon layer) 22, and a sidewall film 23 are shown.
- FIG. 5A and FIG. 5D are diagrams showing the following steps. After the process of FIGS. 4C and 4F is completed, the protective film 20 and the protective film 21 are removed by an isotropic dry etching method. After that, an oxide silicon (SiO 2) film is formed on the upper metal gate electrode by PECVD.
- SiO 2 oxide silicon
- FIG. 5B and FIG. 5E are diagrams showing the following steps.
- the amorphous silicon (amorphous silicon) 22 is applied to the channel region 6 in the field region 2 by using a PECVD method in which a directionality is applied by applying a bias. A film is formed so as to fill the cavity.
- the amorphous silicon layer (amorphous silicon layer) 22 is placed in the field region 2 surrounded by the insulating layer 8 for element isolation, on the insulating layer 8 for element isolation, and on the upper side.
- the metal gate electrode 3 is deposited so as to have the same height.
- the amorphous silicon layer (amorphous silicon layer) 22 does not adhere to the vertical wall surface in the stepped portion. Accordingly, the amorphous silicon layer (amorphous silicon layer) 22 in the field region 2 is formed on the amorphous silicon layer (amorphous silicon layer) 22 on the insulating layer 8 for element isolation and the upper metal gate electrode 3.
- the amorphous silicon layer (amorphous silicon layer) 22 can be in an isolated state. Thereafter, as a result of introducing impurities to be introduced into the source / drain regions 12 by ion implantation or solid phase diffusion, the cross-sectional shapes shown in FIGS. 5B and 5E are obtained.
- the channel region 6 and the source / drain region 12 are formed in a self-aligned manner.
- the timing of ion implantation of the impurity introduced into the source / drain region 12 is not limited to the timing of FIGS. 5B and 5E.
- the stage shown in FIG. That is, it may be after the polycrystalline silicon 18 is formed from the amorphous silicon layer (amorphous silicon layer) 22 in the field region 2.
- the temperature at which the above impurities are activated is preferably less than 600 ° C.
- FIG. 5C and FIG. 5F are diagrams showing the following steps. After the steps of FIG. 5B and FIG. 5E are completed, a resist is applied, and a resist pattern in which a portion corresponding to the region 7 into which the metal impurity has been introduced is opened is formed by a photolithography method. As a result, the cross-sectional shape shown in FIGS. 5C and 5F is obtained.
- FIG. 6A to 6F are cross-sectional views illustrating a part of the process for manufacturing the MISFET 1 of the first embodiment, following FIG. 6A, 6B, and 6C are cross-sectional views taken along the line CD in FIG. 6D, 6E, and 6F show cross-sectional views along the dotted line AB in FIG. 6A to 6F show a field region 2, an upper metal gate electrode 3, a lower metal gate electrode 4, needle-like crystal grains 5, a channel region 6, a region 7 into which metal impurities are introduced, and an element isolation Insulating layer 8, gate insulating film 10, gate insulating film 11, substrate 13, nickel (Ni) ion implantation 17, polycrystalline silicon region 18, amorphous silicon layer (amorphous silicon layer) 22, and sidewall film 23 Indicates.
- FIG. 6A, 6B, and 6C are cross-sectional views taken along the line CD in FIG. 6D, 6E, and 6F show cross-sectional views along the dotted line AB in FIG. 6A to 6F show a field
- FIGS. 6A and 6D show nickel (Ni) ion implantation after the steps of FIGS. 5C and 5F are completed.
- FIG. 17 is a view showing a state where nickel (Ni) is introduced as a metal impurity into the region 7 into which the metal impurity has been introduced by performing 17.
- Layer) 22 is not introduced with nickel (Ni).
- FIG. 6B and FIG. 6E are diagrams showing the following steps. After completing the steps of FIG. 6A and FIG. 6D, the resist pattern is removed and heat treatment is performed at a temperature of about 450 ° C. to about 600 ° C. As a result, needle-like crystal grains 5 grow in the channel region 6. Thus, the cross-sectional shape shown in FIGS. 6B and 6E can be obtained.
- the upper limit of the heat treatment temperature is about 600 ° C. because the lower metal gate electrode 4 and the upper metal gate electrode 3 do not melt and the temperature is desired U. Therefore, it goes without saying that the upper limit of the heat treatment temperature can be raised depending on the metal constituting the metal gate electrode.
- the lower limit of the heat treatment temperature is set to about 450 ° C because the temperature at which the metal-induced solid phase growth phenomenon starts. Therefore, the temperature of the above heat treatment should be between 500 ° C and 550 ° C! /.
- FIGS. 6C and 6F show a case where the heat treatment of FIGS.
- amorphous silicon layer (amorphous silicon layer) 22 in the field region 2 is converted into a polycrystalline silicon region by a metal-induced solid phase growth phenomenon. It is a figure which shows the place which became 18.
- FIG. The impurities introduced into the source / drain regions 12 are taken into the silicon crystal lattice and activated by the metal-induced solid phase growth phenomenon.
- amorphous silicon layer (amorphous silicon layer) 22 on the upper metal gate electrode 3 does not contain nickel (Ni), metal-induced solid-phase growth does not occur, and the polycrystalline silicon region 18 It remains.
- FIG. 7A to 7F are cross-sectional views illustrating a part of the process for manufacturing the MISFET 1 of Example 1 following FIG. 7A and 7B are cross-sectional views taken along the line CD in FIG. 7C and 7D show cross-sectional views along the dotted line AB in FIG.
- FIG. 7A to 7D show a field region 2, an upper metal gate electrode 3, a lower metal gate electrode 4, needle-like crystal grains 5, a channel region 6, a region 7 into which metal impurities are introduced, and an element isolation Insulating layer 8, interlayer insulating layer 9, gate insulating film 10, gate insulating film 11, source 'drain region 12, substrate 13, contact window 15, nickel (Ni) ion implantation 17, polycrystalline silicon region 18, An amorphous silicon layer (amorphous silicon layer) 22 and a sidewall film 23 are shown.
- FIGS. 6C and 6F are diagrams showing a state where the amorphous silicon layer (amorphous silicon layer) 22 is removed by isotropic etching after the steps of FIGS. 6C and 6F are completed. . That is, since there is a difference in etching rate between polycrystalline silicon and amorphous silicon, only the amorphous silicon layer (amorphous silicon layer) 22 can be removed.
- FIG. 7B and FIG. 7D are diagrams showing the following steps. After the process of FIGS. 7A and 7D is completed, an interlayer insulating layer 9 is deposited by the CVD method. Thereafter, a resist is applied on the interlayer insulating layer 9, and a resist pattern having an opening corresponding to the contact window 15 is formed by a photolithography method. Then, anisotropic etching is performed using the resist pattern as a mask to form a contact window 15 penetrating the interlayer insulating layer 9. As a result, a cross-sectional shape as shown in FIGS. 7B and 7E is shown.
- the heat treatment temperature is suppressed to a low temperature of less than 600 ° C. in the process performed after the formation of the lower metal gate electrode 4 related to the MISFET manufacturing method of Example 2. Therefore, the metal constituting the lower metal gate electrode 4 and the upper metal gate electrode 3 does not melt.
- the lower metal gate electrode 4 and the channel region 6 and the source / drain region 12 are arranged in a self-aligned manner, the MISFET of the second embodiment that does not require an alignment margin can be reduced in size.
- the channel region 6 is composed of a bundle of acicular crystal grains 5, the crystallinity of the channel region 6 is improved, so that the leakage current between the source and the drain can be suppressed.
- Example 3 is a modification of the manufacturing method of the MISFET of Example 2.
- the present invention relates to a manufacturing method capable of forming the upper gate electrode in a self-aligned manner with respect to the lower gate electrode and the channel region.
- Example 2 will be described with reference to FIGS. 8A to 8F, FIGS. 9A to 9F, and FIGS. 10A to 1OD.
- FIG. 8A to FIG. 8F are cross-sectional views showing a part of the steps constituting the manufacturing method of the MISFET 1 of the third embodiment.
- 8A, 8B, and 8C are cross-sectional views taken along the line CD in FIG. 8D, FIG. 8E, and FIG. 8F show cross-sectional views along the dotted line AB in FIG. 8A to 8F show the substrate 13, the insulating layer 8 for element isolation, the metal layer for the lower metal gate electrode 4, the channel region 6, the resist pattern 17, and the amorphous silicon layer (amorphous silicon layer).
- 19 shows a protective film 20, a protective film 21, and illumination light 26.
- FIG. 8A and FIG. 8D are diagrams showing the following steps. First, an insulating layer 8 for element isolation is deposited on a transparent substrate 13 by a CVD method, and a resist pattern having an opening corresponding to the field region 2 is formed on the insulating layer 8 for element isolation by a photolithography method. Form. The insulating layer 8 for element isolation is etched until the surface of the substrate 13 appears, and the resist pattern is removed.
- a metal layer for forming the lower metal gate electrode 4 is deposited on the substrate 13 by a notching method or a CVD method.
- the metal constituting the metal layer is preferably a refractory metal such as tantasten (W) or molybdenum (Mo).
- a refractory metal such as tantasten (W) or molybdenum (Mo).
- W tantasten
- Mo molybdenum
- the protective film 20 By depositing an insulating layer, which will be the protective film 20, on the metal layer by CVD, it is shown in the cross-sectional views of Figs. 8A and 8D. Get the cross-sectional shape.
- a PECVD method, an LPCVD method, an ALD method, or a sputtering method may be used.
- the protective film 20 is made of an oxide silicon (SiO 2) film, an silicon oxide silicon nitride (SiON) film, a nitride film (SiN) film,
- It may be a dielectric film (high-k material).
- FIG. 8B and FIG. 8E are diagrams showing the following steps.
- an amorphous silicon layer (amorphous silicon layer) 19 and a protective film 21 are sequentially deposited by a plasma CVD method.
- a resist is applied on the protective film 21, and a resist pattern is formed so that the resist remains in a region corresponding to the channel region 6 by a photolithography method.
- anisotropic etching on the protective film 21 and the amorphous silicon layer (amorphous silicon layer) 19 on the resist pattern mask, the amorphous silicon layer (amorphous silicon layer) 19 and the protective film 21 Putting on.
- the insulating layer is volumed and anisotropic etching is performed to form sidewalls on the side walls of the patterned amorphous silicon layer (amorphous silicon layer) 19 and the protective film 21.
- the cross-sectional shapes shown in the cross-sectional views of FIGS. 8B and 8E are obtained.
- the method for depositing the protective film 21 it is also possible to use a PECVD method or the like as with the protective film 20.
- the material of the protective film 21 may be a nitride film (SiN) or the like, similar to the protective film 20.
- FIG. 8C and FIG. 8F are diagrams showing the following steps. After completing the steps shown in FIGS. 8B and 8E, a resist is applied, and a resist pattern 17 is formed so that the resist remains in a region corresponding to the channel region 6 by a photolithography method. Then, using the resist pattern 17 as a mask, anisotropic etching is performed on the metal layer for the lower metal gate electrode 4 to form the lower metal gate electrode 4. As a result, the cross-sectional shapes shown in the cross-sectional views of FIGS. 8C and 8F are obtained.
- FIGS. 9A to 9F are cross-sectional views showing a part of the steps constituting the manufacturing method of the MISFET 1 of the third embodiment.
- 9A, FIG. 9B, and FIG. 9C show cross-sectional views along the line CD in FIG. 9D, 9E, and 9F show cross-sectional views along the dotted line AB in FIG. 9A to 9F show a substrate 13, an insulating layer 8 for element isolation, a metal layer for the upper metal gate electrode 3, a metal layer for the lower metal gate electrode 4, and amorphous silicon.
- a layer (amorphous silicon layer) 19 a protective film 20, a protective film 21, a resist layer 24, and illumination light 26 are shown.
- FIGS. 9A and 9D show a state where a metal layer for the upper metal gate electrode 3 is deposited by sputtering or CVD after the steps of FIGS. 8C and 8F are completed.
- FIG. 9B and FIG. 9E are diagrams showing the following steps. 9A and 9D, a positive resist layer 24 is applied, transparent substrate power illumination is performed, and the resist layer 24 is exposed by light transmitted through the metal layer for the upper metal gate electrode 3. . As a result, the cross-sectional shapes shown in FIGS. 9B to 9E are obtained.
- FIG. 9C and FIG. 9F show the resist pattern formed by removing the exposed portion of the resist layer 24 after the steps of FIG. 9B and FIG. 9E are completed.
- the positive type resist is a resist in which the exposed portion is soluble.
- FIG. 10A and FIG. 10B are cross-sectional views showing a part of the steps constituting the manufacturing method of the MISFET 1 of the third embodiment.
- FIG. 10A shows a cross-sectional view along the line C-D in FIG. Fig. 10B shows a cross-sectional view along the dotted line AB in Fig. 1.
- 10A and 10B show a substrate 13, an insulating layer 8 for element isolation, a metal layer for the upper metal gate electrode 3, a metal layer for the lower metal gate electrode 4, and an amorphous silicon layer (amorphous silicon layer). Layer) 19, protective film 20, protective film 21, and resist layer 24 are shown.
- FIGS. 10A and 10B after the steps of FIGS. 9C and 9F are completed, the upper metal gate electrode 3 is formed by etching the metal layer for the upper metal gate electrode 3 using the resist pattern as a mask. It shows where. As a result, the cross-sectional shape shown in FIGS. 10A and 10B is obtained. Note that the cross-sectional shapes shown in FIGS. 10A and 10B are similar to the cross-sectional shapes shown in FIGS. 4B and 4E.
- FIGS. 8A to 8F, FIGS. 9A to 9F, 10A, and 10B when a modification of the method for manufacturing the MISFET of Example 2 according to Example 3 is used, the lower metal gate is used.
- the upper metal gate electrode 3 can be formed in a self-aligned manner with respect to the electrode 4 and the channel region 6. Therefore, after the modification of the manufacturing method of the MISFET of Example 2,
- the source drain region that can form the upper metal gate electrode 3 in a self-aligned manner is formed in a self-aligned manner with respect to the lower metal gate electrode 4 and the channel region 6. can do.
- the present invention provides a MISFET having a metal gate electrode, a multi-gate electrode structure, and a structure in which a leakage current between the source and drain is reduced, and a method of manufacturing the MISFET. it can.
- Amorphous silicon layer (amorphous silicon layer)
- Amorphous silicon layer (amorphous silicon layer)
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Abstract
[PROBLEMS] To provide an MISFET having a metal gate electrode of multi-gate electrode structure wherein leakage current is reduced between the source and the drain, and to provide a method for fabricating such an MISFET. [MEANS FOR SOLVING PROBLEMS] The MISFET comprises a first metal gate electrode, a second metal gate electrode arranged in parallel with the first metal gate electrode in the extending direction of the first metal gate electrode, a first semiconductor layer sandwiched by the first and second metal gate electrodes through a gate insulation film, and a second semiconductor layer adjacent to the opposite sides of the first semiconductor layer and the opposite sides of the first and second metal gate electrodes. This MISFET is characterized in that acicular crystal grains existing in the first semiconductor layer in the direction perpendicular to the extending direction of the first and second metal gate electrodes.
Description
明 細 書 Specification
半導体装置及びその製造方法 Semiconductor device and manufacturing method thereof
技術分野 Technical field
[0001] 本発明は、 MISFET(Metal InsulatorSemiconductor Field Effect Transistor)を有す る半導体装置及びその製造方法に関し、特にマルチゲート構造を備える MISFET を有する半導体装置及びその製造方法に関する。 The present invention relates to a semiconductor device having a MISFET (Metal Insulator Semiconductor Field Effect Transistor) and a manufacturing method thereof, and more particularly to a semiconductor device having a MISFET having a multi-gate structure and a manufacturing method thereof.
背景技術 Background art
[0002] ゲート電極及びソース ·ドレイン領域を有する MISFETにお!/、て、ゲート電極の幅の 微細化とともに、ソース'ドレイン間の間隔が縮小すると、 MISFETの性能は向上す ることが予想される。し力し、ゲート電極の幅の微細化によっては、 MISFETの性能、 例えば、オン電流は向上しないことが指摘されている。 [0002] MISFETs having a gate electrode and source / drain regions are expected to improve the performance of MISFETs as the distance between the source and the drain decreases as the width of the gate electrode is reduced. The However, it has been pointed out that MISFET performance, for example, on-current, does not improve by reducing the width of the gate electrode.
[0003] オン電流が向上しない理由の一つは、微細化が進んでも、ソース'ドレイン抵抗はそ れに比例して下がらないことにある。ソース'ドレイン抵抗と、ゲート電極直下のチヤネ ル領域がオンしたときのソース ·ドレイン間の抵抗から、 MISFETのオン抵抗は構成 されているため、上記のソース'ドレイン間の抵抗が下がっても、 MISFET全体のォ ン抵抗が下がらないからである。 [0003] One of the reasons why the on-current does not improve is that the source-drain resistance does not decrease in proportion to the progress of miniaturization. The MISFET on-resistance is composed of the source and drain resistance and the resistance between the source and drain when the channel region directly under the gate electrode is turned on. This is because the on-resistance of the entire MISFET does not decrease.
[0004] また、オン電流が向上しない他の理由は、ゲート電極と、 MISFETが構成されている 基板間のトンネル電流が発生するため、ゲート絶縁膜の薄膜ィ匕が困難になってきた ことにある。ゲート絶縁膜が薄膜ィ匕できなければ、ゲート電極直下のチャネル領域に 広がる、ゲート電極に起因する電界の強度があがらず、 MISFETがオフしているとき のソース'ドレイン間のリーク電流を防止することはできないからである。 [0004] Another reason why the on-current is not improved is that a tunnel current is generated between the gate electrode and the substrate on which the MISFET is formed, which makes it difficult to form a thin gate insulating film. is there. If the gate insulating film cannot be made thin, the intensity of the electric field caused by the gate electrode spreading to the channel region directly under the gate electrode will not increase, and leakage current between the source and drain when the MISFET is off is prevented. Because you can't.
[0005] さらに、オン電流が向上しない他の理由は、多結晶シリコンも半導体であるため、電 極を構成する多結晶シリコンと、ゲート絶縁膜の界面に、多結晶シリコン側に空乏層 が発生することにある。ゲート電極と、 MISFETが構成されている基板間に係る電界 力 ゲート絶縁膜に係る電界と、多結晶シリコン内の空乏層に係る電界とに分割され 、ゲート絶縁膜にカゝかる電界が減少する。そうすると、ゲート電極直下のチャネル領 域に広がる、ゲート電極に起因する電界の強度が低下することになるからである。従
つて、 MISFETがオフして!/、るときのソース ·ドレイン間のリーク電流を防止できな!/、こ ととなる。 [0005] Further, the other reason why the on-current is not improved is that polycrystalline silicon is also a semiconductor, and therefore a depletion layer is generated on the polycrystalline silicon side at the interface between the polycrystalline silicon constituting the electrode and the gate insulating film. There is to do. Electric field applied between the gate electrode and the substrate on which the MISFET is configured. Force is divided into an electric field related to the gate insulating film and an electric field related to the depletion layer in the polycrystalline silicon, and the electric field covering the gate insulating film is reduced. . This is because the strength of the electric field caused by the gate electrode spreading in the channel region immediately below the gate electrode is reduced. Obedience Therefore, when the MISFET is turned off! /, The leakage current between the source and drain cannot be prevented! /.
[0006] そこで、上記の理由に対して、ソース'ドレイン間の抵抗を下げる提案がされている 。また、 MISFETがオフしているときのソース'ドレイン間のリーク電流に対して、ゲー ト絶縁膜を薄膜ィ匕するのと同様な効果をあげる提案がされている (例えば、特許文献 D o [0006] For this reason, proposals have been made to reduce the resistance between the source and the drain. In addition, a proposal has been made to give the same effect as a thin gate insulating film against the leakage current between the source and drain when the MISFET is off (for example, Patent Document D o
特許文献 1においては、長方形断面を有するチャネル領域を、対向する 2方向から はさむようにゲート電極を配置し、いわゆる、マルチゲート電極構造を有する MISFE Tが開示されている。また、他の対向する 2方向にはソース'ドレイン電極を配置した 構造の MISFETが開示されている。従って、 2方向に配置された多結晶シリコンから なるゲート電極によって、チャネル領域に 2方向力 電界が発生する。そうすると、ソ ース 'ドレイン間のリーク電流は、 2方向からの電界によって防止される。また、ソース' ドレイン電極力 他の対向する 2方向から、チャネル領域に直に接し、距離をあけず に配置されている。そうすると、ソース'ドレイン抵抗が殆どない構造となっている。 特許文献 1:特開 2001— 284598号公報 Patent Document 1 discloses a MISFET having a so-called multi-gate electrode structure in which a gate electrode is disposed so as to sandwich a channel region having a rectangular cross section from two opposing directions. In addition, a MISFET having a structure in which source and drain electrodes are arranged in two opposite directions is disclosed. Therefore, a two-direction force electric field is generated in the channel region by the gate electrode made of polycrystalline silicon arranged in two directions. Then, the leakage current between the source and drain is prevented by the electric field from two directions. In addition, the source and drain electrode forces are placed in direct contact with the channel region from the other two opposing directions, with no distance. Then, the structure has almost no source / drain resistance. Patent Document 1: Japanese Patent Laid-Open No. 2001-284598
発明の開示 Disclosure of the invention
[0007] (発明が解決しょうとする課題) [0007] (Problems to be solved by the invention)
上記の提案においては、ゲート電極は多結晶シリコンによって構成されており、多 結晶シリコン側に発生する空乏層によって、チャネル領域に発生する電界が低下す ると 、う現象を抑えることはできな 、。 In the above proposal, the gate electrode is made of polycrystalline silicon. If the electric field generated in the channel region is reduced by the depletion layer generated on the polycrystalline silicon side, the phenomenon cannot be suppressed. .
そこで、チャネル領域を対向する 2方向からはさむゲート電極に金属を用いて、い わゆる、メタルゲート電極を実現することが考えられる。 Therefore, it is conceivable to realize a so-called metal gate electrode by using a metal for the gate electrode sandwiching the channel region from two opposite directions.
しかし、メタルゲート電極であって、さらに、マルチゲート電極構造を実現することは 困難である。ゲート電極に金属を用いるため、一方のメタルゲート電極を形成した後 、 MISFETのチャネル領域とソース'ドレイン領域を形成するためには、 600°C以下 の熱処理し力許されないからである。しかし、例えば、ェピ成長を利用してメタルゲー ト電極上にシリコン結晶層力もなるチャネル領域を形成するには、 1000°C以上の熱 が加わる。また、 CVD(chemical vaper. deposition)法により、多結晶シリコン層を堆積
させて、チャネル領域を形成するにも、約 800°C程度の熱が加わる。 However, it is difficult to realize a metal gate electrode and a multi-gate electrode structure. Because metal is used for the gate electrode, heat treatment at 600 ° C. or lower is not allowed to form the channel region and source / drain region of the MISFET after forming one metal gate electrode. However, for example, in order to form a channel region having a silicon crystal layer force on a metal gate electrode by using epi growth, heat of 1000 ° C. or more is applied. A polycrystalline silicon layer is deposited by chemical vapor deposition (CVD). In order to form the channel region, heat of about 800 ° C is applied.
一方、 PECVD法を利用して、チャネル領域を形成するために、アモルファスシリコ ン層を堆積させる場合には、 500°C程度と低温の熱処理となる。しかし、アモルファス シリコン層でチャネル領域を形成した場合には、結晶性が非常に悪いものとなり、シリ コン粒界を伝わる電流等により、ソース'ドレイン間にリーク電流が発生することになる そこで、本発明は、メタルゲート電極であって、かつ、マルチゲート電極構造を有し 、ソース ·ドレイン間のリーク電流が減少する構造を有する MISFET及びその MISF ETの製造方法を提供することを目的とする。 On the other hand, when an amorphous silicon layer is deposited to form a channel region using the PECVD method, the heat treatment is as low as about 500 ° C. However, when the channel region is formed with an amorphous silicon layer, the crystallinity is very poor, and a leakage current is generated between the source and drain due to the current transmitted through the silicon grain boundary. It is an object of the present invention to provide a MISFET having a metal gate electrode and a multi-gate electrode structure in which a leakage current between a source and a drain is reduced, and a method for manufacturing the MISF ET.
(課題を解決するための手段) (Means for solving problems)
上記の課題を解決するため、本発明は以下の MISFETを提供する。本発明に係 わる MISFETは、第 1の金属ゲート電極と、前記第 1の金属ゲート電極の延在方向と 同一方向であって、かつ、平行に配置された第 2の金属ゲート電極と、前記第 1の金 属ゲート電極及び前記第 2の金属ゲート電極に、ゲート絶縁膜を介してはさまれた第 1の半導体層と、前記第 1の半導体層の両側に隣接し、かつ、前記第 1の金属ゲート 電極及び前記第 2の金属ゲート電極の両側に隣接し、一方の側にはソースが、他方 の側にはドレインが形成されている第 2の半導体層と、を備え、前記第 1の半導体層 中に、前記第 1の金属ゲート電極及び前記第 2の金属ゲート電極の延在方向に対し て、垂直方向に針状の結晶粒を有することを特徴とする。 In order to solve the above problems, the present invention provides the following MISFET. The MISFET according to the present invention includes a first metal gate electrode, a second metal gate electrode disposed in parallel with the extending direction of the first metal gate electrode and in parallel with the first metal gate electrode, A first semiconductor layer sandwiched between a first metal gate electrode and the second metal gate electrode via a gate insulating film; adjacent to both sides of the first semiconductor layer; and A second semiconductor layer adjacent to both sides of the first metal gate electrode and the second metal gate electrode, wherein a source is formed on one side and a drain is formed on the other side. One semiconductor layer has needle-like crystal grains perpendicular to the extending direction of the first metal gate electrode and the second metal gate electrode.
上記の課題を解決するため、本発明は以下の MISFETを製造する方法を提供す る。 MISFETを製造する方法第 1の金属ゲート電極と、前記第 1の金属ゲートとの間 に空洞が生じるように、前記第 1の金属ゲート電極の延在方向と同一方向かつ平行 に第 2の金属ゲート電極と、を形成する金属ゲート形成工程と、前記第 1の金属ゲー ト電極及び前記第 2の金属ゲート電極を構成する金属の融点より低温度で、前記第 1 の金属ゲートの両側に隣接する第 1の領域と前記空洞とに、非晶質半導体層を形成 する工程と、前記第 1の領域に含まれ、前記第 1の金属ゲート電極の延在方向と平行 するように、前記第 1の金属ゲート電極の両側に設けられた第 2の領域に、金属不純 物を導入する工程と、前記金属の融点未満の温度、かつ、前記非晶質半導体層に
金属誘起固相成長現象を起こさせる温度以上の温度で、熱処理を行う熱処理工程とIn order to solve the above problems, the present invention provides a method for manufacturing the following MISFET. Method of manufacturing MISFET A second metal in the same direction and parallel to the extending direction of the first metal gate electrode so that a cavity is formed between the first metal gate electrode and the first metal gate. Forming a gate electrode, and adjacent to both sides of the first metal gate at a temperature lower than the melting point of the metal constituting the first metal gate electrode and the second metal gate electrode. Forming an amorphous semiconductor layer in the first region to be formed and the cavity, and the first region included in the first region and parallel to the extending direction of the first metal gate electrode. A step of introducing a metal impurity into the second region provided on both sides of the metal gate electrode, a temperature lower than the melting point of the metal, and the amorphous semiconductor layer. A heat treatment step in which heat treatment is performed at a temperature equal to or higher than a temperature at which metal-induced solid phase growth occurs
、を備えることを特徴とする MISFETの製造方法。 The manufacturing method of MISFET characterized by including these.
[0009] (発明の効果) [Effect of the invention]
本発明は、メタルゲート電極であって、かつ、マルチゲート電極構造を有し、ソース' ドレイン間のリーク電流が減少する構造を有する MISFET及びその MISFETの製 造方法を提供することができる。 The present invention can provide a MISFET having a metal gate electrode, a multi-gate electrode structure, and a structure in which a leakage current between a source and a drain is reduced, and a method for manufacturing the MISFET.
図面の簡単な説明 Brief Description of Drawings
[0010] [図 1]図 1は実施例 1の MISFETの平面図を示す図である。 FIG. 1 is a plan view of a MISFET of Example 1.
[図 2]図 2A及び図 2Bは、図 1の A— B点線に沿った断面と、 C D点線に沿った断 面を示す断面図である。 FIG. 2A and FIG. 2B are cross-sectional views showing a cross section taken along the line AB of FIG. 1 and a cross section taken along the line CD.
[図 3]図 3A乃至図 3Fは実施例 1の MISFET1を製造する工程の一部を示す断面図 である。 FIG. 3A to FIG. 3F are cross-sectional views showing a part of the process for manufacturing the MISFET 1 of the first embodiment.
[図 4]図 4A乃至図 4Fは実施例 1の MISFET1を製造する工程の一部を示す断面図 である。 4A to 4F are cross-sectional views showing a part of the process for manufacturing the MISFET 1 of Example 1. FIG.
[図 5]図 5A乃至図 5Fは実施例 1の MISFET1を製造する工程の一部を示す断面図 である。 FIG. 5A to FIG. 5F are cross-sectional views showing a part of the process for manufacturing the MISFET 1 of the first embodiment.
[図 6]図 6A乃至図 6Fは実施例 1の MISFET1を製造する工程の一部を示す断面図 である。 6A to 6F are cross-sectional views showing a part of a process for manufacturing the MISFET 1 of Example 1. FIG.
[図 7]図 7A乃至図 7Fは実施例 1の MISFET1を製造する工程の一部を示す断面図 である。 FIG. 7A to FIG. 7F are cross-sectional views showing a part of the process for manufacturing the MISFET 1 of the first embodiment.
[図 8]図 8A乃至図 8Fは実施例 3の MISFET1の製造方法を構成する工程の一部を 示す断面図である。 FIG. 8A to FIG. 8F are cross-sectional views showing a part of the steps constituting the manufacturing method of the MISFET 1 of Example 3.
[図 9]図 9A乃至図 9Fは実施例 3の MISFET1の製造方法を構成する工程の一部を 示す断面図である。 FIG. 9A to FIG. 9F are cross-sectional views showing a part of the steps constituting the manufacturing method of the MISFET 1 of Example 3.
[図 10]図 10A及び図 10Bは実施例 3の MISFET1の製造方法を構成する工程の一 部を示す断面図である。 FIG. 10A and FIG. 10B are cross-sectional views showing a part of the steps constituting the manufacturing method of the MISFET 1 of Example 3.
発明を実施するための最良の形態 BEST MODE FOR CARRYING OUT THE INVENTION
[0011] 以下、本発明の実施例 1、実施例 2、及び、実施例 3について説明する
[0012] (実施例 1) [0011] Hereinafter, Example 1, Example 2, and Example 3 of the present invention will be described. [0012] (Example 1)
実施例 1は、メタルゲート電極であって、かつ、マルチゲート電極構造を有する MIS FETに関するものである。そして、実施例 1を図 1、図 2A、及び、図 2Bを用いて説明 する。 Example 1 relates to a MIS FET which is a metal gate electrode and has a multi-gate electrode structure. Example 1 will be described with reference to FIGS. 1, 2A, and 2B.
[0013] 図 1は、実施例 1の MISFETの平面図を示す図である。そして、図 1は、 MISFET1 を画定するフィールド領域 2、上部のメタルゲート電極 3、下部のメタルゲート電極 4、 針状の結晶粒 5、 MISFET1のチャネル領域 6、金属不純物が導入された領域 7、素 子分離用の絶縁層 8、 MISFETのソース'ドレイン領域 12、及び、ソース'ドレイン領 域 12に接続するコンタクト窓 15を示す。 FIG. 1 is a plan view of the MISFET according to the first embodiment. 1 shows a field region 2 that defines MISFET 1, an upper metal gate electrode 3, a lower metal gate electrode 4, needle-like crystal grains 5, a channel region 6 of MISFET 1, a region 7 into which metal impurities are introduced, An insulating layer 8 for element isolation, a source / drain region 12 of the MISFET, and a contact window 15 connected to the source / drain region 12 are shown.
[0014] MISFET1を画定するフィールド領域 2は素子分離用の絶縁層 8に囲まれている。そ して、フィールド領域 2は、例えば、横方向の幅 3〜10 μ m、縦方向の幅 4〜5 μ mの 矩形である。なお、縦方向とは、 MISFETのソースとドレインとをつなぐ方向であり、 横方向とは、 MISFETのソースとドレインとをつなぐ方向に垂直な方向である。 The field region 2 that defines the MISFET 1 is surrounded by an insulating layer 8 for element isolation. The field region 2 is, for example, a rectangle having a horizontal width of 3 to 10 μm and a vertical width of 4 to 5 μm. The vertical direction is the direction connecting the source and drain of the MISFET, and the horizontal direction is the direction perpendicular to the direction connecting the source and drain of the MISFET.
MISFET1のチャネル領域 6は、 MISFET1を画定するフィールド領域 2の中央部 に位置する。そして、チャネル領域 2は、例えば、チャネル幅 2〜3 μ m、チャネル長 5 Onmの矩形である。なお、チャネル長とは、 MISFETのソースとドレインとをつなぐ方 向のチャネル領域 2の長さをいい、チャネル幅とは、 MISFETのソースとドレインとを つなぐ方向に垂直な方向のチャネル領域 2の長さを!、う。 The channel region 6 of the MISFET 1 is located at the center of the field region 2 that defines the MISFET 1. The channel region 2 is, for example, a rectangle having a channel width of 2 to 3 μm and a channel length of 5 Onm. The channel length is the length of the channel region 2 in the direction connecting the source and drain of the MISFET, and the channel width is the channel region 2 in the direction perpendicular to the direction connecting the source and drain of the MISFET. Length!
[0015] 下部のメタルゲート電極 4は、チャネル領域 6の下部に配置されたメタルゲート電極で ある。そして、下部のメタルゲート電極 4は、フィールド領域 2内において、 MISFET のソースとドレインとをつなぐ方向に垂直な方向に延在している。従って、下部のメタ ルゲート電極 4は矩形をしており、例えば、幅はチャネル長と同様に 50nmであり、長 さはフィールド領域 2の縦方向の幅と同様に 4〜5 μ mである。 The lower metal gate electrode 4 is a metal gate electrode disposed under the channel region 6. The lower metal gate electrode 4 extends in the field region 2 in a direction perpendicular to the direction connecting the source and drain of the MISFET. Therefore, the lower metal gate electrode 4 has a rectangular shape. For example, the width is 50 nm as in the channel length, and the length is 4 to 5 μm as in the vertical width of the field region 2.
[0016] 上部のメタルゲート電極 3は、チャネル領域 6の上部に配置されたメタルゲート電極で ある。そして、上部のメタルゲート電極 3は、 MISFETのソースとドレインとをつなぐ方 向に垂直な方向に延在している。すなわち、上部のメタルゲート電極 3は、下部のメタ ルゲート電極 4が延在する方向と同一の方向であって、下部のメタルゲート電極 4に 平行して配置されている。また、上部のメタルゲート電極 3と下部のメタルゲート電極 4
はチャネル領域 6をはさんで配置されている。従って、上部のメタルゲート電極の幅 は、例えば、チャネル長と同様に 50nmである。 The upper metal gate electrode 3 is a metal gate electrode disposed above the channel region 6. The upper metal gate electrode 3 extends in a direction perpendicular to the direction connecting the source and drain of the MISFET. That is, the upper metal gate electrode 3 is arranged in parallel with the lower metal gate electrode 4 in the same direction as the direction in which the lower metal gate electrode 4 extends. The upper metal gate electrode 3 and the lower metal gate electrode 4 Are placed across the channel region 6. Therefore, the width of the upper metal gate electrode is, for example, 50 nm, similar to the channel length.
[0017] ソース'ドレイン領域 12は、上部のメタルゲート電極 3及び下部のメタルゲート電極 4の 両側に隣接して配置されている。従って、ソース'ドレイン領域 12は、チャネル領域 6 の両側にも隣接している。 The source / drain region 12 is disposed adjacent to both sides of the upper metal gate electrode 3 and the lower metal gate electrode 4. Therefore, the source / drain region 12 is also adjacent to both sides of the channel region 6.
金属不純物が導入された領域 7は、ソース'ドレイン領域 12内に配置され、矩形の 領域である。また、チャネル領域 6の両側に配置されており、上部のメタルゲート電極 The region 7 into which the metal impurity has been introduced is disposed in the source / drain region 12 and is a rectangular region. The upper metal gate electrode is arranged on both sides of the channel region 6.
3及び下部のメタルゲート電極 4に平行して延在している。 3 and the lower metal gate electrode 4 extend in parallel.
[0018] 針状の結晶粒 5は、ソース'ドレイン領域 12内及びチャネル領域 6内であって、金属 不純物が導入された領域 7間に存在する。そして、針状の結晶粒 5の長手方向は、The needle-like crystal grains 5 exist in the source / drain region 12 and the channel region 6 and between the regions 7 into which metal impurities are introduced. And the longitudinal direction of the acicular crystal grains 5 is
MISFETのソースとドレインとをつなぐ方向に平行である。 It is parallel to the direction connecting the source and drain of the MISFET.
コンタクト窓 15は、ソース'ドレイン領域 12に配線を接続するための、開口である。 The contact window 15 is an opening for connecting a wiring to the source / drain region 12.
[0019] 図 2A及び図 2Bは、図 1の A— B点線に沿った断面と、 C D点線に沿った断面を 示す断面図である。そして、図 2A及び図 2Bの断面図は、 MISFET1を画定するフィ 一ルド領域 2、上部のメタルゲート電極 3、下部のメタルゲート電極 4、針状の結晶粒 52A and 2B are cross-sectional views showing a cross section taken along the line AB of FIG. 1 and a cross section taken along the line CD. 2A and 2B show a field region 2 that defines the MISFET 1, an upper metal gate electrode 3, a lower metal gate electrode 4, and needle-like crystal grains 5.
、チャネル領域 6、金属不純物が導入された領域 7、素子分離用の絶縁層 8、層間絶 縁層 9、上部のメタルゲート電極 3とチャネル領域 6との間のゲート絶縁膜 10、下部の メタルゲート電極 4とチャネル領域 6との間のゲート絶縁膜 11、ソース'ドレイン領域 12, Channel region 6, region 7 into which metal impurities are introduced, element isolation insulating layer 8, interlayer insulating layer 9, gate insulating film 10 between upper metal gate electrode 3 and channel region 6, lower metal Gate insulating film 11 between gate electrode 4 and channel region 6, source and drain region 12
、基板 13、コンタクト窓 15、及び、多結晶シリコン領域 18を示す。なお、図 1に示すもの と同様なものは、同様な番号を付した。 , Substrate 13, contact window 15, and polycrystalline silicon region 18. The same numbers as those shown in Fig. 1 are given.
[0020] 図 2Aは、図 1の A—B点線に沿った断面図である。基板 13上に MISFET1は形成 されている。 MISFET1のフィールド領域 2は素子分離用の絶縁層 8によって囲まれ ている。 FIG. 2A is a cross-sectional view taken along a dotted line AB in FIG. The MISFET 1 is formed on the substrate 13. The field region 2 of the MISFET 1 is surrounded by an insulating layer 8 for element isolation.
[0021] チャネル領域 6は、フィールド領域 2の中央に配置されて!、る。そして、チャネル領 域 6は、上部のメタルゲート電極 3及び下部のメタルゲート電極 4によって、上部のメタ ルゲート電極 3とチャネル領域 6との間のゲート絶縁膜 10及び下部のメタルゲート電 極 4とチャネル領域 6との間のゲート絶縁膜 11を介して、上下にはさまれている。さら に、チャネル領域 6は、 MISFETのソースとドレインとをつなぐ方向に垂直な方向に
おいて、上部のメタル電極 3又は下部のメタル電極 4によって、左右においてもはさま れている。すなわち、図 1の A—B点線に沿った断面において、チャネル領域 6は、上 部のメタルゲート電極 3及び下部のメタルゲート電極 4によって、囲まれている。なお、 上記のように、チャネル領域 6力 上部のメタルゲート電極 3及び下部のメタルゲート 電極 4によって、囲まれている構造を Gate all around構造という。 [0021] The channel region 6 is arranged in the center of the field region 2. The channel region 6 includes a gate insulating film 10 between the upper metal gate electrode 3 and the channel region 6 and a lower metal gate electrode 4 by an upper metal gate electrode 3 and a lower metal gate electrode 4. It is sandwiched between the channel region 6 via the gate insulating film 11. In addition, the channel region 6 is perpendicular to the direction connecting the source and drain of the MISFET. The upper metal electrode 3 or the lower metal electrode 4 is sandwiched between the left and right sides. In other words, the channel region 6 is surrounded by the upper metal gate electrode 3 and the lower metal gate electrode 4 in the cross section along the dotted line AB in FIG. As described above, the structure surrounded by the upper metal gate electrode 3 and the lower metal gate electrode 4 in the channel region 6 force is called a gate all around structure.
また、チャネル領域 6は、 MISFETのソースとドレインとをつなぐ方向に伸びている 針状の結晶粒 5の束によって、チャネル領域 6は埋めつくされている。 The channel region 6 is filled with a bundle of needle-like crystal grains 5 extending in the direction connecting the source and drain of the MISFET.
下部のメタルゲート電極 4は基板 13上に堆積されている。また、上部のメタルゲート 電極 3の上には、層間絶縁層 9が堆積されている。 The lower metal gate electrode 4 is deposited on the substrate 13. An interlayer insulating layer 9 is deposited on the upper metal gate electrode 3.
[0022] 図 2Bは、図 1の C D点線に沿った断面図である。 MISFET1のフィールド領域 2 は素子分離用の絶縁層 8によって囲まれている。チャネル領域 6、下部のメタルゲー ト電極 4、及び、上部のメタルゲート電極 3は、フィールド領域 2の中央に配置されて いる。 FIG. 2B is a cross-sectional view taken along the line CD in FIG. The field region 2 of the MISFET 1 is surrounded by an insulating layer 8 for element isolation. The channel region 6, the lower metal gate electrode 4, and the upper metal gate electrode 3 are arranged in the center of the field region 2.
基板 13上には、多結晶シリコン領域 18及び下部のメタルゲート電極 4が形成されて いる。 A polycrystalline silicon region 18 and a lower metal gate electrode 4 are formed on the substrate 13.
多結晶シリコン領域 18は、フィールド領域 2中において、多結晶シリコンによって構 成されている領域である。すなわち、多結晶シリコン領域 18は、チャネル領域 6、ソー ス 'ドレイン領域 12、及び、ソース'ドレイン領域 12の底部力 基板までの領域であつ て、かつ、下部のメタルゲート電極 4及び上部のメタルゲート電極 3の両側に配置され て 、る領域力 構成されて 、る。 The polycrystalline silicon region 18 is a region constituted by polycrystalline silicon in the field region 2. That is, the polycrystalline silicon region 18 is a region up to the bottom force substrate of the channel region 6, the source 'drain region 12, and the source' drain region 12, and the lower metal gate electrode 4 and the upper metal region. A region force is arranged on both sides of the gate electrode 3.
[0023] ソース'ドレイン領域 12はチャネル領域 6の両側に隣接した半導体領域であり、不純 物が導入されている多結晶シリコンによって構成されている領域である。従って、ソー ス 'ドレイン領域 12は上部のメタルゲート電極 3及び下部のメタルゲート電極 4の両側 にも隣接している。なお、上記の不純物は MISFET1が N型であるときには N型の不 純物であり、 MISFET1が P型であるときには P型の不純物である。 The source / drain region 12 is a semiconductor region adjacent to both sides of the channel region 6, and is a region composed of polycrystalline silicon into which impurities are introduced. Accordingly, the source / drain region 12 is adjacent to both sides of the upper metal gate electrode 3 and the lower metal gate electrode 4. The above-mentioned impurities are N-type impurities when MISFET 1 is N-type, and P-type impurities when MISFET 1 is P-type.
[0024] 金属不純物が導入された領域 7はソース'ドレイン領域 12の表面に形成された領域 であって、かつ、チャネル領域 6の両側に平行して延在するように配置された領域で ある。すなわち、金属不純物が導入された領域 7は上部のメタルゲート電極 3が延在
する方向であって、上部のメタルゲート電極の両側に平行して延在するように配置さ れている。そして、金属不純物が導入された領域 7には、金属誘起固相成長現象を 起こさせる金属が導入されて!ヽる。 [0024] The region 7 into which the metal impurity has been introduced is a region formed on the surface of the source / drain region 12, and is a region arranged so as to extend in parallel to both sides of the channel region 6. . That is, the upper metal gate electrode 3 extends in the region 7 into which the metal impurity is introduced. And extending in parallel to both sides of the upper metal gate electrode. In the region 7 into which the metal impurity is introduced, a metal that causes a metal-induced solid phase growth phenomenon is introduced.
[0025] ここで、金属誘起固相成長現象とは、非晶質半導体 (アモルファス半導体)に熱処 理を加えたときに、非晶質半導体 (アモルファス半導体)中に金属不純物をドープし て形成させた金属と半導体の化合物を核として、半導体結晶が成長する現象をいう。 そして、金属誘起固相成長現象を利用すると、 600°C未満の低い温度において、短 い時間で結晶性の良好なポリ状の半導体層を形成することができる。なお、半導体 がシリコン (Si)である場合には、ニッケル (Ni)、銅 (Cu)、金 (Au)、白金 (Pt)等が上記の誘 起固相成長現象を起こす金属不純物として知られている。また、半導体がゲルマニウ ム (Ge)である場合には、金 (Au)等が誘起固相成長現象を起こす金属不純物として知 られている。さらに、半導体がシリコンゲルマニウム (SiGe)である場合には、銅 (Cu)等 が誘起固相成長現象を起こす金属不純物として知られて 、る。 [0025] Here, the metal-induced solid phase growth phenomenon is formed by doping a metal impurity into an amorphous semiconductor (amorphous semiconductor) when heat treatment is applied to the amorphous semiconductor (amorphous semiconductor). This is a phenomenon in which a semiconductor crystal grows with a compound of a metal and a semiconductor as a nucleus. If the metal-induced solid phase growth phenomenon is utilized, a poly semiconductor layer with good crystallinity can be formed in a short time at a low temperature of less than 600 ° C. When the semiconductor is silicon (Si), nickel (Ni), copper (Cu), gold (Au), platinum (Pt), etc. are known as metal impurities that cause the above-described induced solid phase growth phenomenon. ing. In addition, when the semiconductor is germanium (Ge), gold (Au) or the like is known as a metal impurity that causes an induced solid phase growth phenomenon. Furthermore, when the semiconductor is silicon germanium (SiGe), copper (Cu) or the like is known as a metal impurity that causes an induced solid phase growth phenomenon.
[0026] 従って、金属不純物が導入された領域 7に導入された金属は、非晶質シリコン内に 拡散し、シリコンの結晶を成長させる。その結果、多結晶シリコンによって構成されて いる多結晶シリコン領域 18が形成される。また、上記のように、多結晶シリコンを成長 させるための熱処理は 600°C未満でょ 、ため、下部のメタルゲート電極 4は上記の熱 処理には影響されず、かつ、維持される。 [0026] Therefore, the metal introduced into the region 7 into which the metal impurity has been introduced diffuses into the amorphous silicon and grows a silicon crystal. As a result, a polycrystalline silicon region 18 made of polycrystalline silicon is formed. Further, as described above, the heat treatment for growing polycrystalline silicon is less than 600 ° C. Therefore, the lower metal gate electrode 4 is not affected by the heat treatment and is maintained.
また、金属不純物は拡散源力も放射状に拡散するため、金属不純物が導入された 領域 7はチャネル領域 6の両側に平行して延在して!/、ると、 MISFETのソースとドレイ ンをつなぐ方向へ金属不純物は拡散する。従って、チャネル領域 6には針状の結晶 粒 5が成長し、針状の結晶粒 5によって、チャネル領域 6は構成される。 In addition, since the metal impurities diffuse radially, the region 7 into which the metal impurities are introduced extends in parallel to both sides of the channel region 6! /, And connects the source and drain of the MISFET. Metal impurities diffuse in the direction. Therefore, acicular crystal grains 5 grow in the channel region 6, and the channel region 6 is constituted by the acicular crystal grains 5.
[0027] コンタクト窓 15はソース'ドレイン領域 12に金属配線を接続するための窓である。従 つて、層間絶縁層 9に対して、フォトリソグラフィ一法によって、コンタクト窓 15に相当 する開口を有するレジストパターンを形成し、そのレジストパターンをマスクに層間絶 縁層 9をエッチングすることによって形成される。 The contact window 15 is a window for connecting a metal wiring to the source / drain region 12. Therefore, a resist pattern having an opening corresponding to the contact window 15 is formed on the interlayer insulating layer 9 by a photolithography method, and the interlayer insulating layer 9 is etched using the resist pattern as a mask. The
[0028] 図 1、図 2A、及び、図 2Bによれば、実施例 1の MISFET1において、上部のメタル ゲート電極 3及び下部のゲートメタル電極 4にゲート絶縁膜 10及びゲート絶縁膜 11を
介してはさまれたチャネル領域 6が針状の結晶粒 5から構成されているため、ソース' ドレイン間のリーク電流が減少する効果がある。なぜなら、ソース'ドレイン間を流れる 電流を担うキヤリャ一は、結晶性の良い針状の結晶粒 5を流れる。また、上部のメタル ゲート電極 3及び下部のゲートメタル電極 4からの電界によって発生する空乏層は、 針状の結晶粒 5中の電流経路を支配する。その結果、ソース'ドレイン間を流れる電 流を担うキヤリャ一は、 MISFETがオフしているときには、完全に遮断されることにな る力 である。なお、ソース'ドレイン間に複数の結晶粒が存在する状態となっている と、ソース'ドレイン間を流れる電流を担うキヤリャ一は、結晶粒の粒界を伝わって、リ ークする。その結果、ソース'ドレイン間にリーク電流が発生する。 According to FIGS. 1, 2A, and 2B, in the MISFET 1 of Example 1, the gate insulating film 10 and the gate insulating film 11 are formed on the upper metal gate electrode 3 and the lower gate metal electrode 4. Since the channel region 6 sandwiched between them is composed of the needle-like crystal grains 5, the leakage current between the source and the drain is reduced. This is because the carrier carrying the current flowing between the source and the drain flows through the needle-like crystal grains 5 having good crystallinity. The depletion layer generated by the electric field from the upper metal gate electrode 3 and the lower gate metal electrode 4 dominates the current path in the needle-like crystal grains 5. As a result, the carrier responsible for the current flowing between the source and drain is the force that is completely cut off when the MISFET is off. When a plurality of crystal grains exist between the source and the drain, the carrier carrying the current flowing between the source and the drain is transmitted through the grain boundary of the crystal grains and leaks. As a result, a leak current is generated between the source and the drain.
[0029] 従って、実施例 1によれば、メタルゲート電極であって、かつ、マルチゲート電極構 造を有し、ソース'ドレイン間のリーク電流が減少する構造を有する MISFETを提供 することができる。 Therefore, according to the first embodiment, it is possible to provide a MISFET having a metal gate electrode, a multi-gate electrode structure, and a structure in which a leakage current between a source and a drain is reduced. .
[0030] (実施例 2) [0030] (Example 2)
実施例 2は、メタルゲート電極であって、かつ、マルチゲート電極構造を有する MIS FETの製造方法に関するものである。そして、実施例 2を図 3A乃至図 3F、図 4A乃 至図 4F、図 5A乃至図 5B、図 6A乃至図 6F、及び、図 7A乃至図 7Dを用いて説明 する。 Example 2 relates to a method of manufacturing a MIS FET that is a metal gate electrode and has a multi-gate electrode structure. Example 2 will be described with reference to FIGS. 3A to 3F, FIGS. 4A to 4F, FIGS. 5A to 5B, FIGS. 6A to 6F, and FIGS. 7A to 7D.
[0031] 図 3A乃至図 3Fは実施例 1の MISFET1を製造する工程の一部を示す断面図であ る。そして、図 3A、図 3B、及び、図 3Cは、図 1の C— D点線に沿った断面図を示す。 また、図 3D、図 3E、及び、図 3Fは、図 1の A—B点線に沿った断面図を示す。そし て、図 3A乃至図 3Fは、基板 13、素子分離用の絶縁層 8、下部のメタルゲート電極 4 用の金属層、チャネル領域 6、非晶質シリコン層(アモルファスシリコン層) 19、保護膜 20、保護膜 21、及び、サイドウォール膜 23を示す。 3A to 3F are cross-sectional views showing a part of the process for manufacturing the MISFET 1 of the first embodiment. 3A, 3B, and 3C are cross-sectional views taken along the line C-D in FIG. 3D, FIG. 3E, and FIG. 3F show cross-sectional views along the dotted line AB in FIG. 3A to 3F show the substrate 13, the insulating layer 8 for element isolation, the metal layer for the lower metal gate electrode 4, the channel region 6, the amorphous silicon layer (amorphous silicon layer) 19, and the protective film. 20 shows a protective film 21 and a sidewall film 23.
[0032] 図 3A及び図 3Dは、以下の工程を行ったところを示す図である。まず、基板 13上に 素子分離用の絶縁層 8を CVD法によって堆積し、素子分離用の絶縁層 8上に、フォ トリソグラフィー法によって、フィールド領域 2に相当する開口を有するレジストパター ンを形成する。素子分離用の絶縁層 8を、基板 13の表面が表れるまでエッチングし、 レジストパターンを除去する。
その後、基板 13の上に、下部のメタルゲート電極 4を形成するための金属層を、ス ノッタ法、又は、 CVD法によって堆積する。なお、金属層を構成する金属には、タン ダステン (W)、モリブデン (Mo)等の高融点金属が望ましい。その金属層の上に保護 膜 20となる絶縁層を CVD法で堆積させることにより、図 3A、図 3Dの断面図に示す 断面形状を得る。なお、保護膜 20を堆積させるには、 PECVD (plasma enhanced che mical vapor depositionノ法、又【ま、 LPCVD(low pressure chemicalvapor deposition) 法、又は、 ALD(atomic layer deposition)法、又は、スパッタ法によることも考えられる 。さらに、保護膜 20の材質については、酸ィ匕シリコン (SiO )膜、酸ィ匕窒化シリコン (SiO [0032] FIGS. 3A and 3D are diagrams showing the following steps. First, an insulating layer 8 for element isolation is deposited on the substrate 13 by the CVD method, and a resist pattern having an opening corresponding to the field region 2 is formed on the insulating layer 8 for element isolation by the photolithography method. To do. The insulating layer 8 for element isolation is etched until the surface of the substrate 13 appears, and the resist pattern is removed. Thereafter, a metal layer for forming the lower metal gate electrode 4 is deposited on the substrate 13 by a notching method or a CVD method. The metal constituting the metal layer is preferably a refractory metal such as tantasten (W) or molybdenum (Mo). By depositing an insulating layer serving as the protective film 20 on the metal layer by the CVD method, the cross-sectional shape shown in the cross-sectional views of FIGS. 3A and 3D is obtained. The protective film 20 is deposited by PECVD (plasma enhanced chemical vapor deposition), LPCVD (low pressure chemical vapor deposition), ALD (atomic layer deposition), or sputtering. In addition, the protective film 20 may be made of an oxide silicon (SiO 2) film, an oxide silicon nitride (SiO 2)
2 2
N)膜、窒化膜 (SiN)膜、高誘電体膜 (high-k材料)であってもよい。 N) film, nitride film (SiN) film, high dielectric film (high-k material) may be used.
[0033] 図 3B及び図 3Eは、以下の工程を行ったところを示す図である。まず、図 3A及び図 3Dに示した工程を終了した後、非晶質シリコン層(アモルファスシリコン層) 19を、プ ラズマ CVD法によって堆積する。その後、 CVD法によって、保護膜 21を堆積する。 そして、保護膜 21上にレジストを塗布し、フォトリソグラフィ一法によって、チャネル領 域 6に相当する領域にレジストが残るようなレジストパターンを形成する。上記のレジ ストパターンマスクに、保護膜 21、非晶質シリコン層(アモルファスシリコン層) 19、及 び、保護膜 20に対して異方性エッチングを行うことにより、保護膜 21、非晶質シリコン 層(アモルファスシリコン層) 19、及び、保護膜 20をパターユングする。その結果、図 3 B、図 3Eの断面図に示す断面形状を得る。なお、保護膜 21の堆積方法について、保 護膜 20と同様に PECVD法等を使用することも可能である。また、保護膜 21の材質に ついても、保護膜 20と同様に、窒化膜 (SiN)等であってもよいことはいうまでもない。 [0033] FIG. 3B and FIG. 3E are diagrams showing the following steps. First, after the steps shown in FIGS. 3A and 3D are completed, an amorphous silicon layer (amorphous silicon layer) 19 is deposited by a plasma CVD method. Thereafter, the protective film 21 is deposited by the CVD method. Then, a resist is applied on the protective film 21, and a resist pattern is formed so that the resist remains in a region corresponding to the channel region 6 by a photolithography method. By performing anisotropic etching on the protective film 21, the amorphous silicon layer (amorphous silicon layer) 19, and the protective film 20 on the resist pattern mask, the protective film 21, amorphous silicon The layer (amorphous silicon layer) 19 and the protective film 20 are patterned. As a result, the cross-sectional shape shown in the cross-sectional views of FIGS. 3B and 3E is obtained. As for the method of depositing the protective film 21, it is also possible to use the PECVD method or the like as with the protective film 20. Needless to say, the material of the protective film 21 may be a nitride film (SiN) or the like, similar to the protective film 20.
[0034] 図 3C及び図 3Fは、以下の工程を行ったところを示す図である。図 3B及び図 3Eに 示した工程を終了した後、 CVD法によって、保護膜を堆積する。その後、保護膜に 対して異方性エッチングを行うことにより、パターユングされた非晶質シリコン層(ァモ ルファスシリコン層) 19の側面にサイドウォール膜 23を形成する。その結果、図 3C, 図 3Fの断面図に示す断面形状を得る。 [0034] FIG. 3C and FIG. 3F are views showing the following steps. After completing the steps shown in FIGS. 3B and 3E, a protective film is deposited by CVD. Thereafter, the sidewall film 23 is formed on the side surface of the patterned amorphous silicon layer (amorphous silicon layer) 19 by performing anisotropic etching on the protective film. As a result, the cross-sectional shape shown in the cross-sectional views of FIGS. 3C and 3F is obtained.
なお、上記の保護膜は酸ィ匕シリコン (SiO )膜、酸ィ匕窒化シリコン (SiON)膜、窒化膜 (S Note that the protective film includes an oxide silicon (SiO 2) film, an oxide silicon nitride (SiON) film, and a nitride film (S
2 2
iN)膜であることが望ましい。 iN) A film is desirable.
[0035] 図 4A乃至図 4Fは、図 3につづいて、実施例 1の MISFET1を製造する工程の一
部を示す断面図である。そして、図 4A、図 4B、及び、図 4Cは、図 1の C— D点線に 沿った断面図を示す。また、図 4D、図 4E、及び、図 4Fは、図 1の A— B点線に沿つ た断面図を示す。そして、図 4A乃至図 4Fは、基板 13、素子分離用の絶縁層 8、下部 のメタルゲート電極 4用の金属層、上部のメタルゲート電極 3用の金属層、チャネル領 域 6、非晶質シリコン層 (アモルファスシリコン層) 19、保護膜 20、保護膜 21、及び、サ イドウォール膜 23を示す。 [0035] FIGS. 4A to 4F are diagrams showing a process for manufacturing the MISFET 1 of the first embodiment, following FIG. It is sectional drawing which shows a part. 4A, 4B, and 4C are cross-sectional views taken along the line C-D in FIG. 4D, 4E, and 4F show cross-sectional views along the dotted line AB in FIG. 4A to 4F show the substrate 13, the isolation layer 8 for element isolation, the metal layer for the lower metal gate electrode 4, the metal layer for the upper metal gate electrode 3, the channel region 6, the amorphous region. A silicon layer (amorphous silicon layer) 19, a protective film 20, a protective film 21, and a side wall film 23 are shown.
[0036] 図 4A及び図 4Dは以下の工程を行ったところを示す図である。図 3C及び図 3Fの 工程を終了した後、上部のメタルゲート電極 3用の金属層をスパッタ法又は CVD法 によって堆積する。その結果、図 4A及び図 4Dのような断面形状を得る。なお、上記 の金属層の金属には、下部のメタルゲート電極 4用の金属層の金属と同様に、タンダ ステン (W)等の高融点金属が望ま 、。 FIG. 4A and FIG. 4D are diagrams showing the following steps. After completing the steps of FIG. 3C and FIG. 3F, a metal layer for the upper metal gate electrode 3 is deposited by sputtering or CVD. As a result, a cross-sectional shape as shown in FIGS. 4A and 4D is obtained. The metal of the metal layer is preferably a refractory metal such as tandasten (W), as is the metal of the metal layer for the lower metal gate electrode 4.
[0037] 図 4B及び図 4Eは以下の工程を行ったところを示す図である。図 4A及び図 4Dのェ 程を終了した後、上部のメタルゲート電極 3の金属層上にレジストを塗布し、フォトリソ グラフィ一法によってゲート電極に相当するレジストパターンを形成する。その後、上 記のレジストパターンをマスクに、異方'性エッチング法によって、上部のメタルゲート 電極 3用の金属層、ゲート絶縁膜 10、非晶質シリコン層(アモルファスシリコン層) 19、 ゲート絶縁膜 11、下部のメタルゲート電極 4用の金属層をエッチングする。そして、上 記のレジストパターンを除去した結果、図 4B及び図 4Eの断面形状を得る。 FIG. 4B and FIG. 4E are diagrams showing the following steps. 4A and 4D is completed, a resist is applied on the metal layer of the upper metal gate electrode 3, and a resist pattern corresponding to the gate electrode is formed by a photolithography method. Then, using the above resist pattern as a mask, the upper metal layer for metal gate electrode 3, gate insulating film 10, amorphous silicon layer (amorphous silicon layer) 19, gate insulating film by anisotropic etching 11. Etch the metal layer for the lower metal gate electrode 4. Then, as a result of removing the resist pattern, the cross-sectional shapes of FIGS. 4B and 4E are obtained.
[0038] 図 4C及び図 4Fは以下の工程を行ったところを示す図である。図 4B及び図 4Eの 工程を終了した後、等方性エッチング法によってチャネル領域 6に存在する非晶質 シリコン層(アモルファスシリコン層) 19をエッチングして除去する。その結果、チヤネ ル領域 6に相当する部分は空洞となり、図 4C及び図 4Fのような断面形状を得る。 [0038] FIG. 4C and FIG. 4F are views showing the following steps. After the process of FIGS. 4B and 4E is completed, the amorphous silicon layer (amorphous silicon layer) 19 existing in the channel region 6 is etched and removed by an isotropic etching method. As a result, the portion corresponding to the channel region 6 becomes a cavity, and the cross-sectional shapes as shown in FIGS. 4C and 4F are obtained.
[0039] 図 5A乃至図 5Fは、図 4につづいて、実施例 1の MISFET1を製造する工程の一 部を示す断面図である。そして、図 5A、図 5B、及び、図 5Cは、図 1の C— D点線に 沿った断面図を示す。また、図 5D、図 5E、及び、図 5Fは、図 1の A— B点線に沿つ た断面図を示す。そして、図 5A乃至図 5Fは、基板 13、フィールド領域 2、金属不純 物が導入された領域 7、素子分離用の絶縁層 8、下部のメタルゲート電極 4用の金属 層、上部のメタルゲート電極 3用の金属層、チャネル領域 6、ゲート絶縁膜 10、ゲート
絶縁膜 11、非晶質シリコン層(アモルファスシリコン層) 19、非晶質シリコン層(ァモル ファスシリコン層) 22、及び、サイドウォール膜 23を示す。 FIGS. 5A to 5F are cross-sectional views illustrating a part of the process for manufacturing the MISFET 1 of Example 1 following FIG. 5A, FIG. 5B, and FIG. 5C show cross-sectional views along the line CD in FIG. 5D, 5E, and 5F are cross-sectional views taken along the dotted line AB in FIG. 5A to 5F show a substrate 13, a field region 2, a region 7 into which a metal impurity is introduced, an insulating layer 8 for element isolation, a metal layer for a lower metal gate electrode 4, and an upper metal gate electrode. Metal layer for 3, channel region 6, gate insulating film 10, gate An insulating film 11, an amorphous silicon layer (amorphous silicon layer) 19, an amorphous silicon layer (amorphous silicon layer) 22, and a sidewall film 23 are shown.
図 5A及び図 5Dは以下の工程を行ったところを示す図である。図 4C及び図 4Fの 工程を終了した後、保護膜 20及び保護膜 21を等方性のドライエッチング法によって 除去する。その後、 PECVD法によって酸ィ匕シリコン (SiO )膜を上部のメタルゲート電 FIG. 5A and FIG. 5D are diagrams showing the following steps. After the process of FIGS. 4C and 4F is completed, the protective film 20 and the protective film 21 are removed by an isotropic dry etching method. After that, an oxide silicon (SiO 2) film is formed on the upper metal gate electrode by PECVD.
2 2
極 3及び下部のメタルゲート電極 4を構成する金属の周囲に堆積させる。その結果、 上部のメタルゲート電極 3に対してはゲート絶縁膜 10が形成され、下部のメタルゲート 電極 4に対してはゲート絶縁膜 11され、図 5 A及び図 5Dのような断面形状を得る。 図 5B及び図 5Eは以下の工程を行ったところを示す図である。図 5A及び図 5Dの 工程を終了した後、非晶質シリコン (アモルファスシリコン) 22を、バイアスをかけること により方向性をもたせるような PECVD法を用いて、フィールド領域 2内のチャネル領 域 6の空洞を埋めるように成膜する。方向性をもたせたため、非晶質シリコン層(ァモ ルファスシリコン層) 22は、素子分離用の絶縁層 8に囲まれたフィールド領域 2内、素 子分離用の絶縁層 8上、及び、上部のメタルゲート電極 3上において同程度の高さに なるように堆積する。ただし、段差部において、非晶質シリコン層(アモルファスシリコ ン層) 22は垂直な壁面には被着しない。従って、フィールド領域 2内の非晶質シリコン 層(アモルファスシリコン層) 22が、素子分離用の絶縁層 8上の非晶質シリコン層(ァ モルファスシリコン層) 22や、上部のメタルゲート電極 3上の非晶質シリコン層(ァモル ファスシリコン層) 22とは孤立したような状態となることが可能である。その後、ソース' ドレイン領域 12に導入する不純物をイオン注入法や固相拡散法により導入した結果 、図 5B及び図 5Eに示す断面形状を得る。 Deposited around the metal constituting the pole 3 and the lower metal gate electrode 4. As a result, a gate insulating film 10 is formed on the upper metal gate electrode 3, and a gate insulating film 11 is formed on the lower metal gate electrode 4, and the cross-sectional shapes as shown in FIGS. 5A and 5D are obtained. . FIG. 5B and FIG. 5E are diagrams showing the following steps. After the process of FIG. 5A and FIG. 5D is completed, the amorphous silicon (amorphous silicon) 22 is applied to the channel region 6 in the field region 2 by using a PECVD method in which a directionality is applied by applying a bias. A film is formed so as to fill the cavity. Due to the directionality, the amorphous silicon layer (amorphous silicon layer) 22 is placed in the field region 2 surrounded by the insulating layer 8 for element isolation, on the insulating layer 8 for element isolation, and on the upper side. The metal gate electrode 3 is deposited so as to have the same height. However, the amorphous silicon layer (amorphous silicon layer) 22 does not adhere to the vertical wall surface in the stepped portion. Accordingly, the amorphous silicon layer (amorphous silicon layer) 22 in the field region 2 is formed on the amorphous silicon layer (amorphous silicon layer) 22 on the insulating layer 8 for element isolation and the upper metal gate electrode 3. The amorphous silicon layer (amorphous silicon layer) 22 can be in an isolated state. Thereafter, as a result of introducing impurities to be introduced into the source / drain regions 12 by ion implantation or solid phase diffusion, the cross-sectional shapes shown in FIGS. 5B and 5E are obtained.
図 5B及び図 5Eによれば、チャネル領域 6とソース'ドレイン領域 12とは自己整合的 に形成される。 According to FIG. 5B and FIG. 5E, the channel region 6 and the source / drain region 12 are formed in a self-aligned manner.
なお、ソース'ドレイン領域 12に導入する不純物をイオン注入する時期は、図 5B及 び図 5Eの時期には限られない。例えば、後に示す図 7Aの段階でもよい。すなわち、 フィールド領域 2内の非晶質シリコン層(アモルファスシリコン層) 22から多結晶シリコ ン 18を形成した後であってもよい。ただし、上記の不純物を活性ィ匕する温度は、 600 °C未満が望ましい。
[0041] 図 5C及び図 5Fは、以下の工程を行ったところを示す図である。図 5B及び図 5Eの 工程を終了後、レジストを塗布し、フォトリソグラフィ一法によって、金属不純物が導入 された領域 7に相当する部分が開口しているレジストパターンを形成する。その結果 、図 5C及び図 5Fに示す断面形状を得る。 Note that the timing of ion implantation of the impurity introduced into the source / drain region 12 is not limited to the timing of FIGS. 5B and 5E. For example, the stage shown in FIG. That is, it may be after the polycrystalline silicon 18 is formed from the amorphous silicon layer (amorphous silicon layer) 22 in the field region 2. However, the temperature at which the above impurities are activated is preferably less than 600 ° C. FIG. 5C and FIG. 5F are diagrams showing the following steps. After the steps of FIG. 5B and FIG. 5E are completed, a resist is applied, and a resist pattern in which a portion corresponding to the region 7 into which the metal impurity has been introduced is opened is formed by a photolithography method. As a result, the cross-sectional shape shown in FIGS. 5C and 5F is obtained.
[0042] 図 6A乃至図 6Fは、図 5につづいて、実施例 1の MISFET1を製造する工程の一 部を示す断面図である。そして、図 6A、図 6B、及び、図 6Cは、図 1の C— D点線に 沿った断面図を示す。また、図 6D、図 6E、及び、図 6Fは、図 1の A— B点線に沿つ た断面図を示す。そして、図 6A乃至図 6Fは、フィールド領域 2、上部のメタルゲート 電極 3、下部のメタルゲート電極 4、針状の結晶粒 5、チャネル領域 6、金属不純物が 導入された領域 7、素子分離用の絶縁層 8、ゲート絶縁膜 10、ゲート絶縁膜 11、基板 13、ニッケル (Ni)イオン注入 17、多結晶シリコン領域 18、非晶質シリコン層(ァモルフ ァスシリコン層) 22、及び、サイドウォール膜 23を示す。 6A to 6F are cross-sectional views illustrating a part of the process for manufacturing the MISFET 1 of the first embodiment, following FIG. 6A, 6B, and 6C are cross-sectional views taken along the line CD in FIG. 6D, 6E, and 6F show cross-sectional views along the dotted line AB in FIG. 6A to 6F show a field region 2, an upper metal gate electrode 3, a lower metal gate electrode 4, needle-like crystal grains 5, a channel region 6, a region 7 into which metal impurities are introduced, and an element isolation Insulating layer 8, gate insulating film 10, gate insulating film 11, substrate 13, nickel (Ni) ion implantation 17, polycrystalline silicon region 18, amorphous silicon layer (amorphous silicon layer) 22, and sidewall film 23 Indicates.
[0043] 図 6A及び図 6Dは、図 5C及び図 5Fの工程が終了した後、ニッケル (Ni)イオン注入 [0043] FIGS. 6A and 6D show nickel (Ni) ion implantation after the steps of FIGS. 5C and 5F are completed.
17を行って、金属不純物が導入された領域 7にニッケル (Ni)を金属不純物として導 入したところを示す図である。 FIG. 17 is a view showing a state where nickel (Ni) is introduced as a metal impurity into the region 7 into which the metal impurity has been introduced by performing 17.
すなわち、金属不純物が導入された領域 7を含むソース ·ドレイン領域 12には、不 純物としてニッケル (Ni)が導入される力 上部のメタルゲート電極 3上の非晶質シリコ ン層(アモルファスシリコン層) 22にはニッケル(Ni)は導入されない。 That is, the amorphous silicon layer (amorphous silicon) on the upper metal gate electrode 3 in which nickel (Ni) is introduced as an impurity in the source / drain region 12 including the region 7 into which the metal impurity has been introduced. Layer) 22 is not introduced with nickel (Ni).
[0044] 図 6B及び図 6Eは、次の工程を行ったところを示す図である。図 6A及び図 6Dのェ 程を終了した後、レジストパターンを除去し、約 450°Cから約 600°Cまでの温度で熱 処理をしたところ、チャネル領域 6に針状の結晶粒 5が成長して、図 6B及び図 6Eに 示す断面形状を得ることができる。 [0044] FIG. 6B and FIG. 6E are diagrams showing the following steps. After completing the steps of FIG. 6A and FIG. 6D, the resist pattern is removed and heat treatment is performed at a temperature of about 450 ° C. to about 600 ° C. As a result, needle-like crystal grains 5 grow in the channel region 6. Thus, the cross-sectional shape shown in FIGS. 6B and 6E can be obtained.
なお、上記の熱処理で、約 600°Cを熱処理温度の上限としたのは、下部のメタルゲ ート電極 4及び上部のメタルゲート電極 3が溶融しな 、温度が望ま U、からである。従 つて、メタルゲート電極を構成する金属によっては、熱処理温度の上限を挙げること ができることはいうまでもない。一方、熱処理温度の下限を約 450°Cとしたのは、金属 誘起固相成長現象が開始する温度だからである。従って、上記の熱処理の温度は、 500°Cから 550°Cまでの温度が望まし!/、。
[0045] 図 6C及び図 6Fは、図 6B及び図 6Eの熱処理をさらに行ない、フィールド領域 2内 の非晶質シリコン層(アモルファスシリコン層) 22が金属誘起固相成長現象によって、 多結晶シリコン領域 18となったところを示す図である。なお、ソース'ドレイン領域 12に 導入された不純物は、金属誘起固相成長現象によって、シリコンの結晶格子にとりこ まれ、活性化する。 In the above heat treatment, the upper limit of the heat treatment temperature is about 600 ° C. because the lower metal gate electrode 4 and the upper metal gate electrode 3 do not melt and the temperature is desired U. Therefore, it goes without saying that the upper limit of the heat treatment temperature can be raised depending on the metal constituting the metal gate electrode. On the other hand, the lower limit of the heat treatment temperature is set to about 450 ° C because the temperature at which the metal-induced solid phase growth phenomenon starts. Therefore, the temperature of the above heat treatment should be between 500 ° C and 550 ° C! /. [0045] FIGS. 6C and 6F show a case where the heat treatment of FIGS. 6B and 6E is further performed, and the amorphous silicon layer (amorphous silicon layer) 22 in the field region 2 is converted into a polycrystalline silicon region by a metal-induced solid phase growth phenomenon. It is a figure which shows the place which became 18. FIG. The impurities introduced into the source / drain regions 12 are taken into the silicon crystal lattice and activated by the metal-induced solid phase growth phenomenon.
一方、上部のメタルゲート電極 3上の非晶質シリコン層(アモルファスシリコン層) 22 は、ニッケル (Ni)を含んでいないため、金属誘起固相成長現象が起きず、多結晶シ リコン領域 18のままである。 On the other hand, since the amorphous silicon layer (amorphous silicon layer) 22 on the upper metal gate electrode 3 does not contain nickel (Ni), metal-induced solid-phase growth does not occur, and the polycrystalline silicon region 18 It remains.
[0046] 図 7A乃至図 7Fは、図 6につづいて、実施例 1の MISFET1を製造する工程の一 部を示す断面図である。そして、図 7A、及び、図 7Bは、図 1の C— D点線に沿った 断面図を示す。また、図 7C、及び、図 7Dは、図 1の A—B点線に沿った断面図を示 す。そして、図 7A乃至図 7Dは、フィールド領域 2、上部のメタルゲート電極 3、下部 のメタルゲート電極 4、針状の結晶粒 5、チャネル領域 6、金属不純物が導入された 領域 7、素子分離用の絶縁層 8、層間絶縁層 9、ゲート絶縁膜 10、ゲート絶縁膜 11、ソ ース 'ドレイン領域 12、基板 13、コンタクト窓 15、ニッケル (Ni)イオン注入 17、多結晶シ リコン領域 18、非晶質シリコン層(アモルファスシリコン層) 22、及び、サイドウォール 膜 23を示す。 7A to 7F are cross-sectional views illustrating a part of the process for manufacturing the MISFET 1 of Example 1 following FIG. 7A and 7B are cross-sectional views taken along the line CD in FIG. 7C and 7D show cross-sectional views along the dotted line AB in FIG. 7A to 7D show a field region 2, an upper metal gate electrode 3, a lower metal gate electrode 4, needle-like crystal grains 5, a channel region 6, a region 7 into which metal impurities are introduced, and an element isolation Insulating layer 8, interlayer insulating layer 9, gate insulating film 10, gate insulating film 11, source 'drain region 12, substrate 13, contact window 15, nickel (Ni) ion implantation 17, polycrystalline silicon region 18, An amorphous silicon layer (amorphous silicon layer) 22 and a sidewall film 23 are shown.
[0047] 図 7A及び図 7Cは、図 6C及び図 6Fの工程が終了した後、非晶質シリコン層(ァモ ルファスシリコン層) 22を、等方性エッチングにより除去したところを示す図である。 すなわち、多結晶シリコンと非晶質シリコンとでは、エッチングレートに差があるため 、非晶質シリコン層(アモルファスシリコン層) 22のみの除去が可能となっている。 7A and 7C are diagrams showing a state where the amorphous silicon layer (amorphous silicon layer) 22 is removed by isotropic etching after the steps of FIGS. 6C and 6F are completed. . That is, since there is a difference in etching rate between polycrystalline silicon and amorphous silicon, only the amorphous silicon layer (amorphous silicon layer) 22 can be removed.
[0048] 図 7B及び図 7Dは、以下の工程を行ったところを示す図である。図 7A及び図 7Dの 工程を終了した後、層間絶縁層 9を CVD法によって堆積させる。その後、層間絶縁 層 9上にレジストを塗布し、フォトフイソグラフィ一法によって、コンタクト窓 15に相当す る部分が開口しているレジストパターンを形成する。そして、そのレジストパターンをマ スクに異方性エッチングを行って、層間絶縁層 9を貫通するコンタクト窓 15を形成する 。その結果、図 7B及び図 7Eに示すような断面形状を示す。 FIG. 7B and FIG. 7D are diagrams showing the following steps. After the process of FIGS. 7A and 7D is completed, an interlayer insulating layer 9 is deposited by the CVD method. Thereafter, a resist is applied on the interlayer insulating layer 9, and a resist pattern having an opening corresponding to the contact window 15 is formed by a photolithography method. Then, anisotropic etching is performed using the resist pattern as a mask to form a contact window 15 penetrating the interlayer insulating layer 9. As a result, a cross-sectional shape as shown in FIGS. 7B and 7E is shown.
[0049] 図 3A乃至図 3F、図 4A乃至図 4F、図 5A乃至図 5B、図 6A乃至図 6F、及び、図 7
A乃至図 7Dによれば、実施例 2の MISFETの製造方法に係わる、下部のメタルゲ ート電極 4の形成後に行われる工程において、熱処理温度は 600°C未満の低温に 抑えられる。従って、下部のメタルゲート電極 4及び上部のメタルゲート電極 3を構成 する金属は溶解しない。また、下部のメタルゲート電極 4、及び、チャネル領域 6と、ソ ース 'ドレイン領域 12が自己整合的に配置されるため、位置合わせ余裕をとる必要が なぐ実施例 2の MISFETを小型化できる。さらに、チャネル領域 6は針状の結晶粒 5 の束より構成されるため、チャネル領域 6の結晶性が向上するので、ソース'ドレイン 間のリーク電流を抑えることができる。 [0049] FIGS. 3A to 3F, FIGS. 4A to 4F, FIGS. 5A to 5B, FIGS. 6A to 6F, and FIG. According to A to FIG. 7D, the heat treatment temperature is suppressed to a low temperature of less than 600 ° C. in the process performed after the formation of the lower metal gate electrode 4 related to the MISFET manufacturing method of Example 2. Therefore, the metal constituting the lower metal gate electrode 4 and the upper metal gate electrode 3 does not melt. In addition, since the lower metal gate electrode 4 and the channel region 6 and the source / drain region 12 are arranged in a self-aligned manner, the MISFET of the second embodiment that does not require an alignment margin can be reduced in size. . Furthermore, since the channel region 6 is composed of a bundle of acicular crystal grains 5, the crystallinity of the channel region 6 is improved, so that the leakage current between the source and the drain can be suppressed.
[0050] (実施例 3) [Example 3]
実施例 3は、実施例 2の MISFETの製造方法の変形例である。特に、下部のゲート 電極及びチャネル領域に対して、上部のゲート電極を自己整合的に形成可能な製 造方法に関する。そして、図 8A乃至図 8F、図 9A乃至図 9F、及び、図 10A乃至図 1 ODを用いて、実施例 2を説明する。 Example 3 is a modification of the manufacturing method of the MISFET of Example 2. In particular, the present invention relates to a manufacturing method capable of forming the upper gate electrode in a self-aligned manner with respect to the lower gate electrode and the channel region. Example 2 will be described with reference to FIGS. 8A to 8F, FIGS. 9A to 9F, and FIGS. 10A to 1OD.
[0051] 図 8A乃至図 8Fは実施例 3の MISFET1の製造方法を構成する工程の一部を示す 断面図である。そして、図 8A、図 8B、及び、図 8Cは、図 1の C— D点線に沿った断 面図を示す。また、図 8D、図 8E、及び、図 8Fは、図 1の A— B点線に沿った断面図 を示す。そして、図 8A乃至図 8Fは、基板 13、素子分離用の絶縁層 8、下部のメタル ゲート電極 4用の金属層、チャネル領域 6、レジストパターン 17、非晶質シリコン層(ァ モルファスシリコン層) 19、保護膜 20、保護膜 21、及び、照明光 26を示す。 FIG. 8A to FIG. 8F are cross-sectional views showing a part of the steps constituting the manufacturing method of the MISFET 1 of the third embodiment. 8A, 8B, and 8C are cross-sectional views taken along the line CD in FIG. 8D, FIG. 8E, and FIG. 8F show cross-sectional views along the dotted line AB in FIG. 8A to 8F show the substrate 13, the insulating layer 8 for element isolation, the metal layer for the lower metal gate electrode 4, the channel region 6, the resist pattern 17, and the amorphous silicon layer (amorphous silicon layer). 19 shows a protective film 20, a protective film 21, and illumination light 26.
[0052] 図 8A及び図 8Dは、以下の工程を行ったところを示す図である。まず、透明な基板 13上に素子分離用の絶縁層 8を CVD法によって堆積し、素子分離用の絶縁層 8上 に、フォトリソグラフィ一法によって、フィールド領域 2に相当する開口を有するレジスト パターンを形成する。素子分離用の絶縁層 8を、基板 13の表面が表れるまでエッチ ングし、レジストパターンを除去する。 [0052] FIG. 8A and FIG. 8D are diagrams showing the following steps. First, an insulating layer 8 for element isolation is deposited on a transparent substrate 13 by a CVD method, and a resist pattern having an opening corresponding to the field region 2 is formed on the insulating layer 8 for element isolation by a photolithography method. Form. The insulating layer 8 for element isolation is etched until the surface of the substrate 13 appears, and the resist pattern is removed.
その後、基板 13の上に、下部のメタルゲート電極 4を形成するための金属層を、ス ノッタ法、又は、 CVD法によって堆積する。なお、金属層を構成する金属には、タン ダステン (W)、モリブデン (Mo)等の高融点金属が望ましい。その金属層の上に保護 膜 20となる絶縁層を CVD法で堆積させることにより、図 8A、図 8Dの断面図に示す
断面形状を得る。なお、保護膜 20を堆積させるには、 PECVD法、又は、 LPCVD法 、又は、 ALD法、又は、スパッタ法〖こよることも考えられる。さらに、保護膜 20の材質 については、酸ィ匕シリコン (SiO )膜、酸ィ匕窒化シリコン (SiON)膜、窒化膜 (SiN)膜、高 Thereafter, a metal layer for forming the lower metal gate electrode 4 is deposited on the substrate 13 by a notching method or a CVD method. The metal constituting the metal layer is preferably a refractory metal such as tantasten (W) or molybdenum (Mo). By depositing an insulating layer, which will be the protective film 20, on the metal layer by CVD, it is shown in the cross-sectional views of Figs. 8A and 8D. Get the cross-sectional shape. In order to deposit the protective film 20, a PECVD method, an LPCVD method, an ALD method, or a sputtering method may be used. Furthermore, the protective film 20 is made of an oxide silicon (SiO 2) film, an silicon oxide silicon nitride (SiON) film, a nitride film (SiN) film, a high
2 2
誘電体膜 (high- k材料)であってもよ 、。 It may be a dielectric film (high-k material).
[0053] 図 8B及び図 8Eは、以下の工程を行ったところを示す図である。まず、図 8A及び図 8Dに示した工程を終了した後、非晶質シリコン層(アモルファスシリコン層) 19、保護 膜 21を、順次、プラズマ CVD法によって堆積する。そして、保護膜 21上にレジストを 塗布し、フォトリソグラフィ一法によって、チャネル領域 6に相当する領域にレジストが 残るようなレジストパターンを形成する。上記のレジストパターンマスクに、保護膜 21と 非晶質シリコン層(アモルファスシリコン層) 19に対して異方性エッチングを行うことに より、非晶質シリコン層(アモルファスシリコン層) 19及び保護膜 21をパターユングする 。その後、絶縁層を体積し、異方性エッチングを行うことにより、パターユングされた非 晶質シリコン層(アモルファスシリコン層) 19及び保護膜 21の側壁にサイドウォールを 形成する。その結果、図 8B、図 8Eの断面図に示す断面形状を得る。なお、保護膜 2 1の堆積方法について、保護膜 20と同様に PECVD法等を使用することも可能である 。また、保護膜 21の材質についても、保護膜 20と同様に、窒化膜 (SiN)等であってもよ いことはいうまでもない。 [0053] FIG. 8B and FIG. 8E are diagrams showing the following steps. First, after completing the steps shown in FIGS. 8A and 8D, an amorphous silicon layer (amorphous silicon layer) 19 and a protective film 21 are sequentially deposited by a plasma CVD method. Then, a resist is applied on the protective film 21, and a resist pattern is formed so that the resist remains in a region corresponding to the channel region 6 by a photolithography method. By performing anisotropic etching on the protective film 21 and the amorphous silicon layer (amorphous silicon layer) 19 on the resist pattern mask, the amorphous silicon layer (amorphous silicon layer) 19 and the protective film 21 Putting on. Thereafter, the insulating layer is volumed and anisotropic etching is performed to form sidewalls on the side walls of the patterned amorphous silicon layer (amorphous silicon layer) 19 and the protective film 21. As a result, the cross-sectional shapes shown in the cross-sectional views of FIGS. 8B and 8E are obtained. As for the method for depositing the protective film 21, it is also possible to use a PECVD method or the like as with the protective film 20. Needless to say, the material of the protective film 21 may be a nitride film (SiN) or the like, similar to the protective film 20.
[0054] 図 8C及び図 8Fは、以下の工程を行ったところを示す図である。図 8B及び図 8Eに 示した工程を終了した後、レジストを塗布し、フォトリソグラフィ一法によって、チャネル 領域 6に相当する領域にレジストが残るようなレジストパターン 17を形成する。そして、 そのレジストパターン 17をマスクに、下部のメタルゲート電極 4用の金属層に対して異 方性エッチングを行って、下部のメタルゲート電極 4を形成する。その結果、図 8C、 図 8Fの断面図に示す断面形状を得る。 [0054] FIG. 8C and FIG. 8F are diagrams showing the following steps. After completing the steps shown in FIGS. 8B and 8E, a resist is applied, and a resist pattern 17 is formed so that the resist remains in a region corresponding to the channel region 6 by a photolithography method. Then, using the resist pattern 17 as a mask, anisotropic etching is performed on the metal layer for the lower metal gate electrode 4 to form the lower metal gate electrode 4. As a result, the cross-sectional shapes shown in the cross-sectional views of FIGS. 8C and 8F are obtained.
[0055] 図 9A乃至図 9Fは実施例 3の MISFET1の製造方法を構成する工程の一部を示 す断面図である。そして、図 9A、図 9B、及び、図 9Cは、図 1の C— D点線に沿った 断面図を示す。また、図 9D、図 9E、及び、図 9Fは、図 1の A— B点線に沿った断面 図を示す。そして、図 9A乃至図 9Fは、基板 13、素子分離用の絶縁層 8、上部のメタ ルゲート電極 3用の金属層、下部のメタルゲート電極 4用の金属層、非晶質シリコン
層(アモルファスシリコン層) 19、保護膜 20、保護膜 21、レジスト層 24、及び、照明光 26 を示す。 FIGS. 9A to 9F are cross-sectional views showing a part of the steps constituting the manufacturing method of the MISFET 1 of the third embodiment. 9A, FIG. 9B, and FIG. 9C show cross-sectional views along the line CD in FIG. 9D, 9E, and 9F show cross-sectional views along the dotted line AB in FIG. 9A to 9F show a substrate 13, an insulating layer 8 for element isolation, a metal layer for the upper metal gate electrode 3, a metal layer for the lower metal gate electrode 4, and amorphous silicon. A layer (amorphous silicon layer) 19, a protective film 20, a protective film 21, a resist layer 24, and illumination light 26 are shown.
[0056] 図 9A及び図 9Dは、図 8C及び図 8Fの工程終了後、上部のメタルゲート電極 3用の 金属層をスパッタ法又は CVD法等で堆積させたところを示す。 FIGS. 9A and 9D show a state where a metal layer for the upper metal gate electrode 3 is deposited by sputtering or CVD after the steps of FIGS. 8C and 8F are completed.
[0057] 図 9B及び図 9Eは、以下の工程を行ったところを示す図である。図 9A及び図 9Dの 工程終了後、ポジ型のレジスト層 24を塗布し、透明な基板力 照明を行ない、上部の メタルゲート電極 3用の金属層を透過した光りによって、レジスト層 24を感光させる。 その結果、図 9B乃至図 9Eに示す断面形状を得る。 FIG. 9B and FIG. 9E are diagrams showing the following steps. 9A and 9D, a positive resist layer 24 is applied, transparent substrate power illumination is performed, and the resist layer 24 is exposed by light transmitted through the metal layer for the upper metal gate electrode 3. . As a result, the cross-sectional shapes shown in FIGS. 9B to 9E are obtained.
[0058] 図 9C及び図 9Fは、図 9B及び図 9Eの工程を終了した後、レジスト層 24の内、感光 した部分を取り除いて、レジストパターン形成したところを示す。なお、ポジ型のレジス トは、感光した部分が可溶性を有することとなるレジストをいう。 FIG. 9C and FIG. 9F show the resist pattern formed by removing the exposed portion of the resist layer 24 after the steps of FIG. 9B and FIG. 9E are completed. Note that the positive type resist is a resist in which the exposed portion is soluble.
[0059] 図 10A及び図 10Bは実施例 3の MISFET1の製造方法を構成する工程の一部を 示す断面図である。そして、図 10Aは、図 1の C— D点線に沿った断面図を示す。ま た、図 10Bは、図 1の A—B点線に沿った断面図を示す。そして、図 10A及び図 10B は、基板 13、素子分離用の絶縁層 8、上部のメタルゲート電極 3用の金属層、下部の メタルゲート電極 4用の金属層、非晶質シリコン層(アモルファスシリコン層) 19、保護 膜 20、保護膜 21、及び、レジスト層 24を示す。 FIG. 10A and FIG. 10B are cross-sectional views showing a part of the steps constituting the manufacturing method of the MISFET 1 of the third embodiment. FIG. 10A shows a cross-sectional view along the line C-D in FIG. Fig. 10B shows a cross-sectional view along the dotted line AB in Fig. 1. 10A and 10B show a substrate 13, an insulating layer 8 for element isolation, a metal layer for the upper metal gate electrode 3, a metal layer for the lower metal gate electrode 4, and an amorphous silicon layer (amorphous silicon layer). Layer) 19, protective film 20, protective film 21, and resist layer 24 are shown.
また、図 10A及び図 10Bは、図 9C及び図 9Fの工程を終了したのち、レジストパタ ーンをマスクに上部のメタルゲート電極 3用の金属層をエッチングし、上部のメタルゲ ート電極 3を形成したところを示す。その結果、図 10A及び図 10Bに示す断面形状を 得る。なお、図 10A及び図 10Bに示す断面形状は、図 4B及び図 4Eに示す断面形 状と同様な形状である。 In FIGS. 10A and 10B, after the steps of FIGS. 9C and 9F are completed, the upper metal gate electrode 3 is formed by etching the metal layer for the upper metal gate electrode 3 using the resist pattern as a mask. It shows where. As a result, the cross-sectional shape shown in FIGS. 10A and 10B is obtained. Note that the cross-sectional shapes shown in FIGS. 10A and 10B are similar to the cross-sectional shapes shown in FIGS. 4B and 4E.
従って、これ以降は、図 4B、図 4C、図 4E、図 4F、図 5A乃至図 5F、図 6A乃至図 6 F、図 7A乃至図 7Dと同様な工程を行って、 MISFETを完成する。 Therefore, the subsequent steps are the same as those shown in FIGS. 4B, 4C, 4E, 4F, 5A to 5F, 6A to 6F, and 7A to 7D to complete the MISFET.
[0060] 図 8A乃至図 8F、図 9A乃至図 9F、図 10A、及び、図 10Bによれば、実施例 3係る実 施例 2の MISFETの製造方法の変形例を用いると、下部のメタルゲート電極 4及び チャネル領域 6に対して上部のメタルゲート電極 3を自己整合的に形成することがで きる。従って、実施例 2の MISFETの製造方法の変形例の後、引き続いて実施例 2
の MISFETの製造方法を行うと、下部のメタルゲート電極 4及びチャネル領域 6に対 して、上部のメタルゲート電極 3を自己整合的に形成できるだけでなぐソース'ドレイ ン領域も自己整合的に形成することができる。 [0060] According to FIGS. 8A to 8F, FIGS. 9A to 9F, 10A, and 10B, when a modification of the method for manufacturing the MISFET of Example 2 according to Example 3 is used, the lower metal gate is used. The upper metal gate electrode 3 can be formed in a self-aligned manner with respect to the electrode 4 and the channel region 6. Therefore, after the modification of the manufacturing method of the MISFET of Example 2, When the MISFET manufacturing method is used, the source drain region that can form the upper metal gate electrode 3 in a self-aligned manner is formed in a self-aligned manner with respect to the lower metal gate electrode 4 and the channel region 6. can do.
産業上の利用可能性 Industrial applicability
[0061] 本発明は、メタルゲート電極であって、かつ、マルチゲート電極構造を有し、ソース'ド レイン間のリーク電流が減少する構造を有する MISFET及びその MISFETの製造 方法を提供することができる。 [0061] The present invention provides a MISFET having a metal gate electrode, a multi-gate electrode structure, and a structure in which a leakage current between the source and drain is reduced, and a method of manufacturing the MISFET. it can.
符号の説明 Explanation of symbols
[0062] 1 MISFET [0062] 1 MISFET
2 フィールド領域 2 Field area
3 上部のメタルゲート電極 3 Upper metal gate electrode
4 下部のメタルゲート電極 4 Lower metal gate electrode
5 針状の結晶粒 5 acicular grains
6 チャネル領域 6 channel region
7 金属不純物が導入された領域 7 Region where metal impurities are introduced
8 素子分離用の絶縁層 8 Insulating layer for element isolation
9 層間絶縁層 9 Interlayer insulation layer
10、 11 ゲート絶縁膜 10, 11 Gate insulation film
12 ソース'ドレイン領域 12 Source and drain regions
13 基板 13 Board
15 コンタクト窓 15 Contact window
17 レジストパターン 17 resist pattern
18 多結晶シリコン領域 18 Polycrystalline silicon region
19 非晶質シリコン層(アモルファスシリコン層) 19 Amorphous silicon layer (amorphous silicon layer)
20、 21 保護膜 20, 21 Protective film
22 非晶質シリコン層(アモルファスシリコン層) 22 Amorphous silicon layer (amorphous silicon layer)
23 サイドウォール膜 23 Side wall film
24 レジスト層
ニッケル (Ni)イオン注入 照明光
24 resist layer Nickel (Ni) ion implantation Illumination light
Claims
[1] 第 1の金属ゲート電極と、 [1] a first metal gate electrode;
前記第 1の金属ゲート電極の延在方向と同一方向であって、かつ、平行に配置され た第 2の金属ゲート電極と、 A second metal gate electrode disposed in parallel with and in the same direction as the extending direction of the first metal gate electrode;
前記第 1の金属ゲート電極及び前記第 2の金属ゲート電極に、ゲート絶縁膜を介し てはさまれたチャネル層と、 A channel layer sandwiched between the first metal gate electrode and the second metal gate electrode via a gate insulating film;
前記第 1の半導体層の両側に配設された不純物拡散層と、を備え、 An impurity diffusion layer disposed on both sides of the first semiconductor layer, and
前記第 1の半導体層中に、前記第 1の金属ゲート電極及び前記第 2の金属ゲート 電極の延在方向に交差するに針状の結晶粒を有することを特徴とする半導体装置。 A semiconductor device, wherein the first semiconductor layer has needle-like crystal grains intersecting with the extending direction of the first metal gate electrode and the second metal gate electrode.
[2] 前記チャネル層及び前記不純物拡散層がゲルマニウム (Ge)、又は、シリコンゲル マニウム(SiGe)、又は、シリコン (Si)を含むことを特徴とする請求項 1に記載された 半導体装置。 [2] The semiconductor device according to [1], wherein the channel layer and the impurity diffusion layer contain germanium (Ge), silicon germanium (SiGe), or silicon (Si).
[3] 前記チャネル層又は前記不純物拡散層に金属誘起固相成長現象を起こさせる金 属不純物が含有されていることを特徴とする請求項 1又は請求項 2に記載された半導 体装置。 [3] The semiconductor device according to [1] or [2], wherein the channel layer or the impurity diffusion layer contains a metal impurity that causes a metal-induced solid phase growth phenomenon.
[4] 前記チャネル層は、前記第 1の金属ゲート電極及び前記第 2の金属ゲート電極によ つて帯状に囲まれ、 [4] The channel layer is surrounded by a band by the first metal gate electrode and the second metal gate electrode,
前記第 1の金属ゲート電極及び前記第 2の金属ゲート電極が一体となっていること を特徴とする請求項 1又は請求項 2又は請求項 3に記載された半導体装置。 4. The semiconductor device according to claim 1, wherein the first metal gate electrode and the second metal gate electrode are integrated. 5.
[5] 前記金属不純物はニッケル (Ni)、銅 (Cu)、金 (Au)、白金 (Pt)の内、少なくとも、 1種 類以上の金属を含むものであることを特徴とする請求項 3に記載した半導体装置。 [5] The metal impurity according to claim 3, wherein the metal impurity contains at least one metal selected from nickel (Ni), copper (Cu), gold (Au), and platinum (Pt). Semiconductor device.
[6] 第 1の金属ゲート電極と、前記第 1の金属ゲート電極との間に空洞が生じるように、 前記第 1の金属ゲート電極の延在方向と同一方向かつ平行な第 2の金属ゲート電極 と、を形成する金属ゲート形成工程と、 [6] A second metal gate that is in the same direction and parallel to the extending direction of the first metal gate electrode so that a cavity is formed between the first metal gate electrode and the first metal gate electrode. A metal gate forming step for forming an electrode;
前記第 1の金属ゲート電極及び前記第 2の金属ゲート電極を構成する金属の融点 より低温度で、前記第 1の金属ゲート電極の両側に隣接する第 1の領域と前記空洞 に、非晶質半導体層を形成する工程と、 The first region adjacent to both sides of the first metal gate electrode and the cavity are amorphous at a temperature lower than the melting point of the metal constituting the first metal gate electrode and the second metal gate electrode. Forming a semiconductor layer;
前記第 1の領域に含まれ、前記第 1の金属ゲート電極の延在方向と平行するように
、前記第 1の金属ゲート電極の両側に設けられた第 2の領域に、金属不純物を導入 する工程と、 Included in the first region and parallel to the extending direction of the first metal gate electrode Introducing a metal impurity into the second region provided on both sides of the first metal gate electrode;
前記金属の融点未満の温度、かつ、前記非晶質半導体層に金属誘起固相成長現 象を起こさせる温度以上の温度で、熱処理を行う熱処理工程と、 A heat treatment step of performing a heat treatment at a temperature lower than the melting point of the metal and at a temperature equal to or higher than a temperature causing a metal induced solid phase growth phenomenon in the amorphous semiconductor layer;
を備えることを特徴とする半導体装置の製造方法。 A method for manufacturing a semiconductor device, comprising:
[7] 前記第 1の領域に不純物を導入する工程を、さらに、備えることを特徴とする請求 項 6に記載された MISFETの製造方法。 7. The MISFET manufacturing method according to claim 6, further comprising a step of introducing an impurity into the first region.
[8] 前記熱処理工程は、前記空洞に形成された前記非晶質半導体層に、前記金属誘 起固相成長現象によって、針状の結晶粒が成長するまで行われることを特徴とする 請求項 6に記載された半導体装置の製造方法。 8. The heat treatment step is performed until acicular crystal grains are grown in the amorphous semiconductor layer formed in the cavity by the metal-induced solid phase growth phenomenon. 6. A method for manufacturing a semiconductor device according to 6.
[9] 前記金属ゲート形成工程は、 [9] The metal gate forming step includes
第 1の金属層を堆積する工程と、 Depositing a first metal layer;
前記第 1の金属層上に第 1の絶縁層を形成する工程と、 Forming a first insulating layer on the first metal layer;
前記第 1の絶縁層上に、第 1の金属層を構成する金属の融点未満の温度で、半導体 層を形成する工程と、 Forming a semiconductor layer on the first insulating layer at a temperature lower than the melting point of the metal constituting the first metal layer;
前記半導体層上に第 2の絶縁層を形成する工程と、 Forming a second insulating layer on the semiconductor layer;
前記第 2の絶縁層上に第 2の金属層を堆積する工程と、 Depositing a second metal layer on the second insulating layer;
前記第 2の金属層、前記第 2の絶縁層、前記半導体層、前記第 1の絶縁層、及び、 前記第 1の金属層をパターユングするパター-ング工程と、を有し、 A patterning step of patterning the second metal layer, the second insulating layer, the semiconductor layer, the first insulating layer, and the first metal layer,
前記パター-ング工程は、前記半導体層を除去することにより、前記第 1の絶縁層と 前記第 2の絶縁層との間に空洞を生じさせる工程を備えることを特徴とする請求項 6 に記載した半導体装置の製造方法。 The patterning step includes a step of generating a cavity between the first insulating layer and the second insulating layer by removing the semiconductor layer. Semiconductor device manufacturing method.
[10] 前記金属ゲート形成工程は、 [10] The metal gate forming step includes
透明基板上に第 1の金属層を堆積する工程と、 Depositing a first metal layer on a transparent substrate;
前記第 1の金属層上に第 1の絶縁層を形成する工程と、 Forming a first insulating layer on the first metal layer;
前記第 1の絶縁層上に、第 1の金属層を構成する金属の融点未満の温度で、半導体 層及び第 2の絶縁層を、順次、形成する工程と、 A step of sequentially forming a semiconductor layer and a second insulating layer on the first insulating layer at a temperature lower than the melting point of the metal constituting the first metal layer;
前記第 2の絶縁層上に前記第 1の金属ゲート電極のパターンに応じて第 1のレジスト
パターンを形成する工程と、 A first resist on the second insulating layer according to a pattern of the first metal gate electrode Forming a pattern;
前記第 1のレジストパターンをマスクに前記半導体層、及び、前記第 2の絶縁層をェ ツチングする工程と、 Etching the semiconductor layer and the second insulating layer using the first resist pattern as a mask; and
前記第 2の絶縁層上に第 3の絶縁層を形成し、前記第 3の絶縁層に対してエツチン グを行って、前記半導体層及び前記第 2の絶縁層の側壁にサイドウォールを形成す る工程と、 Forming a third insulating layer on the second insulating layer, etching the third insulating layer, and forming sidewalls on sidewalls of the semiconductor layer and the second insulating layer; And the process
前記第 2の絶縁層上に前記第 1の金属ゲート電極のパターンに応じて第 2のレジスト パターンを形成する工程と、 Forming a second resist pattern on the second insulating layer in accordance with the pattern of the first metal gate electrode;
前記第 2のレジストパターンをマスクに前記第 1の金属層をエッチングする工程と、 前記第 2の絶縁層上に、前記透明基板の背面カゝら照明をあてた場合に、光が透過す る膜厚で第 2の金属層を堆積する工程と、 Etching the first metal layer using the second resist pattern as a mask, and light is transmitted when illumination is applied to the back surface of the transparent substrate on the second insulating layer. Depositing a second metal layer with a thickness;
前記第 2の金属層上にレジスト層を形成し、前記透明基板の背面力 照明をあて、前 記レジスト層を感光させ、感光したレジスト部分を除去することにより、前記第 1の金属 ゲート電極のパターンに応じて第 3のレジストパターンを形成する工程と、 前記第 2の金属層を前記第 3のレジストパターンをマスクにエッチンングする工程と、 前記半導体層をエッチングすることにより、前記第 1の絶縁層と前記第 2の絶縁層と の間に空洞を生じさせる工程と、 A resist layer is formed on the second metal layer, the back surface illumination of the transparent substrate is applied, the resist layer is exposed, and the exposed resist portion is removed, thereby removing the first metal gate electrode. Forming a third resist pattern in accordance with the pattern; etching the second metal layer using the third resist pattern as a mask; and etching the semiconductor layer to form the first insulating layer. Creating a cavity between the layer and the second insulating layer;
を備えることを特徴とする請求項 6に記載した MISFETの製造方法。 The MISFET manufacturing method according to claim 6, comprising:
前記金属不純物はニッケル (Ni)、銅 (Cu)、金 (Au)、白金 (Pt)の内、少なくとも、 1種 類以上の金属を含むものであることを特徴とする請求項 6に記載された半導体装置 の製造方法。
7. The semiconductor according to claim 6, wherein the metal impurity contains at least one kind of metal among nickel (Ni), copper (Cu), gold (Au), and platinum (Pt). Manufacturing method.
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PCT/JP2006/306424 WO2007110940A1 (en) | 2006-03-29 | 2006-03-29 | Semiconductor device and its fabrication process |
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WO2011096263A1 (en) * | 2010-02-05 | 2011-08-11 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
US8835917B2 (en) | 2010-09-13 | 2014-09-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, power diode, and rectifier |
JP2017022358A (en) * | 2015-03-18 | 2017-01-26 | 株式会社半導体エネルギー研究所 | Semiconductor device and method of manufacturing the same |
JP2018006412A (en) * | 2016-06-28 | 2018-01-11 | 学校法人東北学院 | Semiconductor device |
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Also Published As
Publication number | Publication date |
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JPWO2007110940A1 (en) | 2009-08-06 |
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