WO2006030388A2

WO2006030388A2 - Display devices and methods of driving such

Info

Publication number: WO2006030388A2
Application number: PCT/IB2005/053018
Authority: WO
Inventors: Aleksandar Sevo; Dick Van Den Broeke; Wolfgang Furtner; Frank Matschullat; Ramon Van Gorkom; Martin J. J. Jak; Frank Vossen
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 2004-09-15
Filing date: 2005-09-14
Publication date: 2006-03-23
Also published as: WO2006030388A3

Abstract

A display device comprises an array (10) of pixels (12) arranged in rows and columns and drive circuitry (20,21,22,24) for providing pixel drive signals to the pixels. Each pixel is driveable with two opposite polarity signals (+,-). Each pixel is driven cyclically with a number n of phases where n is 4 or more, n/2 phases with one polarity and n/2 phases with the opposite polarity. During each phase change, the polarity of k x 2/n of the pixels of the display is changed, where k is an integer and k x 2/n is more than 0 and less than 1. Furthermore, the phases in the first half of each cycle are duplicated in the second half of each cycle with opposite polarity. This drive scheme provides a staggered change in polarity and has symmetry to remove a dc offset. Preferably, the polarity changes are always distributed uniformly across the display.

Description

DESCRIPTION

DISPLAY DEVICES AND METHODS OF DRIVING SUCH

The present invention relates to display devices comprising pixels arranged in rows and columns, to drive circuits for such display devices, and to driving or addressing methods for such display devices. The present invention is particularly related to driving schemes in which column drive voltages are inverted to provide inversion schemes.

Liquid crystal display devices (LCDs) are well known, and usually comprise a plurality of pixels arranged in an array of rows and columns.

Conventionally the pixels are addressed or driven as follows. The rows of pixels are selected, or scanned, one at a time, starting with row one and working through the remaining rows in successive order, by application of a selection voltage. This is sometimes referred to as switching of the rows by means of a switching voltage. For display devices, e.g. active matrix liquid crystal display devices, where switching of the pixels is implemented typically using thin film transistors, such selecting or switching of individual rows is sometimes referred to as gating, as the switching voltage is applied to the gates of the transistors of the relevant row.

The pixels within the row currently selected are provided with respective display settings by virtue of respective data voltages being applied to each of the columns. Such data voltages are known by a number of names in the art, including data signals, video signals, image signals, drive voltages, column voltages, and so on.

Selection of each of the rows one by one, with driving of the columns as required during each row selection, provides display of one frame of the image being displayed. The display is then refreshed by a further frame being displayed in the same manner, and so on.

In addition, inversion schemes are implemented in many liquid crystal display devices. According to known inversion schemes, two different polarities of data voltage are employed (note these need not actually be positive and negative in an absolute sense, provided they produce opposite polarity voltages across the light modulating layer, e.g. liquid crystal layer, of the particular display device). Inversion schemes are employed to alleviate degradation of the liquid crystal material that would otherwise occur under continuous single-polarity operation, leading to undesirable effects such as image sticking.

With these inversion schemes, the excitation voltage across the LC cell changes polarity with each frame displayed. The most simple scheme is frame, (or field), inversion in which the polarity for all pixels is inverted for each field.

Figure 1 illustrates graphically an example voltage waveform (V) as a function of time (t) experienced by a typical liquid crystal cell driven using an inversion drive scheme, in this case over five consecutive frames, n-2 to n+2. As well as using an AC voltage across the cell, it is important that the AC voltage does not have a non-zero DC offset.

Any given pixel has different polarities applied to it in different frames (usually alternating frames), i.e. the polarity for the pixel is inverted over time. In addition, in some inversion schemes pixels are also inverted on a positional basis with respect to other pixels, as follows.

Considering first one column of pixels, different pixels are provided with different polarities. Typically, alternate pixels down the column are provided with different polarity of data voltage. This is performed by varying the polarity in time with the row selection procedure. If all the columns are given the same distribution of drive voltage polarity (i.e. all the pixels in a row have the same polarity), the inversion scheme is known as a row inversion scheme. However, if additionally, in each row, adjacent pixels are provided with different polarity, then the inversion scheme is known as a pixel inversion scheme, dot inversion scheme or checker board inversion scheme. Such a scheme is depicted diagrammatical in Figure 2 in which the voltage polarity (+/-) applied to a representative group of pixels in seven columns and four rows in the five frames is shown. This dot-inversion scheme has the advantage also of reducing the visibility of large area flicker in the display image.

Further variants are known in which pairs of adjacent pixels or adjacent rows of pixels are driven with the same polarities and have their polarities switched at the same time.

While the aforementioned inversion drive schemes are beneficial, they are generally only effective in situations where the image (picture) material has the same, or nearly the same, content for subsequent frames, or have only short term deviations, as, for example, in the case for pictures containing movement.

For a TV application of LCDs, it is desirable for the display refreshing to be frame-synchronous with an input video signal. In the case of using a poor performance de-interlacer or no de-interlacer at all, it can happen that video content in odd and even fields significantly differs. (A de-interlacer is employed to convert interlaced video material into a progressive picture. An LCD normally needs a progressive, de-interlaced, picture and usually for every field all the pixel rows of the LCD need to be written). The consequence is that some pixels are driven with a voltage that has different absolute values in odd and even frames. This situation imposes a voltage with a non-zero DC offset on a pixel, and that leads to image sticking (also referred to as image burn-in). In other words, if the pictures have structurally different content in subsequent fields, then cancellation of DC components by use of traditional inversion scheme is not ensured.

The voltage applied to a pixel, with a different content in odd and even field of a video data is illustrated in Figure 3. Here, it becomes apparent that a DC offset voltage exists.

According to the invention, there is provided a display device comprising an array of pixels arranged in rows and columns and drive circuitry for providing pixel drive signals to the pixels, wherein each pixel is driveable with two opposite polarity signals, wherein each pixel is driven cyclically with a number n of phases where n is 4 or more, n/2 phases with one polarity and n/2 phases with the opposite polarity, and wherein during each phase change, the polarity of k x 2/n of the pixels of the display is changed, where k is an integer and k x 2/n is greater than 0 and less than 1, and wherein the phases in the first half of each cycle are duplicated in the second half of each cycle with opposite polarity.

This drive scheme provides a staggered change in polarity, and furthermore provides a symmetric polarity pattern for each pixel over time, so remove dc offset. Preferably, the polarity changes are always distributed uniformly across the display. In one set of examples, n=4 and k=1 , so that there are four phases with half the pixels changing polarity at each phase change.

In one implementation, the four phases comprise: a first checkerboard polarity pattern; a first double column pattern comprising pairs of identical checkerboard columns alternated with pairs of opposite polarity identical checkerboard columns; a second checkerboard polarity pattern opposite to the first checkerboard polarity pattern; and a second double column pattern comprising pairs of identical checkerboard columns alternated with pairs of opposite polarity identical checkerboard columns, the second double column pattern being opposite to the first double column pattern.

A mirror image variation to this is for the four phases to comprise: a first checkerboard polarity pattern; a first double row pattern comprising pairs of identical checkerboard rows alternated with pairs of opposite polarity identical checkerboard rows; a second checkerboard polarity pattern opposite to the first checkerboard polarity pattern; and a second double row pattern comprising pairs of identical checkerboard rows alternated with pairs of opposite polarity identical checkerboard rows, the second double row pattern being opposite to the first row column pattern. In these arrangements, the pixels of a row or column never all have the same polarity within a frame, and neighbouring pixels in the row/column direction are alternated out of phase.

These two arrangements provide half the pixels of the entire frame with one polarity and the other half with the other polarity, and pixels which are changing polarity are spaced across the display area. For each phase change, half the pixels change polarity. These arrangements also avoid the pixels of the same polarity being in any easily visible pattern, such as rows and columns. In another set of examples, n=8. When k=1 , % of the pixels change polarity at each phase change.

For example, the eight phases may comprise: a first quadruple row pattern comprising sets of four identical checkerboard rows alternated with sets of four opposite polarity identical checkerboard rows; seven successive quadruple row patterns, each pattern comprising the previous pattern shifted in a given direction by one row.

When k=2, ^ΛA of the pixels change polarity at each phase change. Preferably, the polarity pattern for each of the 8 phases is different. The drive circuitry may comprise column drive circuitry for controlling the polarity of each pixel (as well as the voltage amplitude), and the device may further comprise a state machine for controlling the column driver circuitry.

The column drive circuitry can comprises a polarity control input for controlling the phase of the first column and an inversion period control input for controlling the period of pixel inversion across a row.

The display device is preferably a liquid crystal display device comprising a pair of substrates and liquid crystal material sandwiched therebetween, for example an active matrix liquid crystal display in which each pixel comprises a thin film transistor.

The invention also provides the drive circuit of the display device of the invention, and a panel on which the drive circuit and pixel array is provided. The invention also provides a method of driving a display comprising an array of pixels arranged in rows and columns, the method comprising: driving the pixel array cyclically with a number n of phases where n is 4 or more, n/2 phases with one polarity and n/2 phases with the opposite polarity, and wherein during each phase change, the polarity of k x 2/n of the pixels of the display is changed, where k is an integer and k x 2/n is greater than 0 and less than 1 , and wherein the phases in the first half of each cycle are duplicated in the second half of each cycle with opposite polarity.

These, and further, features and advantages of the present invention will become apparent from reading of the following description of preferred embodiments, given by way of example only, and with reference to the accompanying drawings, in which: -

Figure 1 is a graph showing the voltage on a typical pixel in an LCD using a known inversion drive scheme over a few consecutive frame periods;

Figure 2 schematically illustrates the polarity of drive voltages applied to a group of pixels over a few consecutive frames in a known inversion drive scheme;

Figure 3 illustrates, for comparison with Figure 1 , the pixel voltage obtained when displaying a particular kind of picture material;

Figure 4 is a schematic diagram of an active matrix liquid crystal display device in which embodiments of invention are implemented;

Figures 5a and 5b show respectively positive and negative polarity data voltages being applied to a pixel of the display device of Figure 4; Figures 6a and 6b illustrate the voltages obtained on a pixel using a first embodiment of pixel inversion drive scheme applied to the display device of Figure 4, wherein Figure 6b illustrates the case where the voltage amplitude of a pixel in subsequent frames is not the same;

Figure 7 illustrates one possible inversion pattern; Figure 8 shows an example data voltage (VCD) applied during row address periods and a resulting pixel voltage (VLC) over a period of time (t); Figure 9 shows simplified the voltage on a pixel for a static image when using the inversion pattern of Figure 7;

Figure 10 shows a first example of inversion pattern of the invention;

Figures 11a to 11d show the voltages against time and luminance against time of two neighbouring pixels when using the inversion pattern of Figure 10;

Figure 12 illustrates a second example of inversion pattern of the invention;

Figures 13a to 13d illustrate how drive voltages (indicated by the grey level) for even and odd frames can differ when a simple interlacer is used on a test image;

Figure 14 illustrates the dc component resulting from the image of Figure 13;

Figure 15 illustrates schematically the manner in which colour information is presented using a SECAM video encoding system;

Figure 16 is a schematic diagram of another LCD in which inversion schemes according to the present invention are implemented; and

Figures 17 to 22 illustrate examples of inversion patterns for interlaced and SECAM material.

FIG. 4 is a schematic diagram of an active matrix liquid crystal display device (AMLCD) in which embodiments of the invention are implemented. The display device, which is suitable for displaying video pictures, comprises an active matrix addressed liquid crystal display panel 10 having a row and column array of pixels which consists of m rows (1 to m) with n horizontally arranged pixels 12 (1 to n) in each row. Only a few of the pixels are shown for simplicity.

Each pixel 12 is associated with a respective switching device in the form of a thin film transistor, TFT, 11. The gate terminals of all TFTs 11 associated with pixels in the same row are connected to a common row conductor 14 to which, in operation, selection (gating) signals are supplied. Likewise, the source terminals associated with all pixels in the same column are connected to a common column conductor 16 to which data (video) signals are applied. The drain terminals of the TFTs are each connected to a respective transparent pixel electrode 20 forming part of, and defining, the pixel. The conductors 14 and 16, TFTs 11 and electrodes 20 are carried on one transparent plate while a second, spaced, transparent plate carries an electrode common to all the pixels (hereinafter referred to as the common electrode). Liquid crystal is disposed between the plates. This structure is used for TN (twisted nematic) and MVA (multiple vertical alignment) panels. For IPS (in plane switching) panels, the electrodes are all in the same plane, and this invention can be applied to all of these, and other, display panel technologies.

The display panel is operated in conventional manner. Light from a light source disposed on one side enters the panel and is modulated according to the transmission characteristics of the pixels 12. The device is driven one row at a time by scanning the row conductors 14 with a selection (gating) signal so as to turn on the rows of TFTs in turn and applying data (video) signals to the column conductors for each row of picture display elements in turn as appropriate and in synchronism with the selection signals so as to build up a complete display frame (picture). The order in which the rows are selected during the scanning will be described below. Using one row at time addressing, all TFTs 11 of the selected row are switched on for a period determined by the duration of the selection signal corresponding to a TV line time during which the video information signals are transferred from the column conductors 16 to the pixels 12. Upon termination of the selection signal, the TFTs 11 of the row are turned off for the remainder of the frame period, thereby isolating the pixels from the conductors 16 and ensuring the applied charge is stored on the pixels until the next time they are addressed in the next frame period.

The row conductors 14 are supplied in their order of selection with selection signals by a row driver circuit 20 comprising a digital shift register controlled by regular timing pulses from a timing and control circuit 21. In the intervals between selection signals, the row conductors 14 are supplied with a substantially constant reference potential by the drive circuit 20. Video information signals are supplied to the column conductors 16 from a column driver circuit 22, comprising one or more shift register/sample and hold circuits. The circuit 22 is supplied with video signals, which have been processed by an input video processing circuit 24, a deinterlacer 42 (if required) and a video processing unit 44. The timing and control circuit 21 controls the timing of the supply of the processed video signals to the column driver circuit 22 in synchronism with row scanning to provide serial to parallel conversion appropriate to the row at a time addressing of the panel 10. The parts of the device integrated onto the display panel are typically the row and column driver circuits and the timing and control circuit.

Means is provided for inverting the drive voltage polarity of the pixels, and this forms part of the column driver circuit in the schematic example of Figure 4. Other details of the liquid crystal display device, except where otherwise stated below in relation to the manner in which the pixels are driven, may be as per any conventional active matrix liquid crystal display device, and are in the present particular embodiments the same as, and operate the same as, the liquid crystal display device disclosed in US 5,130,829, the contents of which are contained herein by reference.

The way in which the data voltage, as applied to the columns, is varied between two polarities will now be explained with reference to FIGS. 5a and 5b. FIGS. 5a and 5b each show schematically (not to scale) an above mentioned pixel 12, formed (inter-alia) from a pixel electrode 20, the common electrode portion 32, and the liquid crystal layer portion 36.

The common electrode 32 is maintained at a constant reference voltage, in this example 8V, as shown in both FIGS. 5a and 5b. FIG. 5a shows the case when a positive polarity data voltage is applied to the pixel. In this example a voltage of 11v is applied to the pixel electrode 20, as shown, providing a potential difference across the liquid crystal layer of +3V (referenced to the common electrode 32). In this example, this is the positive polarity. In a grey scale display the magnitude of this potential difference provides the relevant grey scale, due to voltage magnitude dependence of the electro-optic effect of the light modulating layer, i.e. the liquid crystal layer 36. However, if the display were binary, then the magnitude of the potential difference would simply correspond to a fully on state. FIG. 5b shows the case when a negative polarity data voltage is applied to the pixel. More particularly, the situation shown is when the same magnitude (3V) of potential difference is required as was applied in the FIG. 5a example. Thus in this case a voltage of 5V is applied to the pixel electrode, resulting in the required -3V potential difference across the liquid crystal layer (referenced to the common electrode 32).

It is noted that in both FIGS. 5a and 5b the voltage applied to the pixel electrode 20 is, in an absolute sense, positive. However, the 5V signal provides a negative polarity across the liquid crystal layer 36, whereas the 11 V signal provides a positive polarity across the liquid crystal layer 36. Thus, in this specification, the terminology positive and negative polarity of data voltage is to be understood to include examples such as those described with reference to FIGS. 5a and 5b, as well as other examples where, say, the common electrode is held at OV, and the positive and negative polarity applied data voltages are indeed positive and negative in an absolute sense as well as in the sense of the resulting potential drop across the light modulating layer.

Also, although in the example shown in FIGS. 5a and 5b, the common electrode 32 is held at a d.c. potential (here 8V), in other drive schemes (known as common electrode drive schemes) the common electrode is driven with an inverting square waveform, and the present invention may equally be implemented with such schemes.

As previously described, known kinds of polarity inversion schemes, comprising field inversion, row (line) inversion, and dot (pixel) inversion, have been utilised with a view to preventing DC voltages appearing across the pixel and consequential problems. In particular, charge can build up near an electrode of the pixel cell as a result of ion movement in the LC material if the average voltage across the cell over a period of time is not equal to zero, and this causes an image retention problem. However, these known inversion schemes are not well suited when pictures which inherently have structurally different content are to be displayed in subsequent frames, as in this situation the cancellation of the DC component by inversion in subsequent frames no longer applies. Typically, this is the case when the picture to be displayed is derived from interlaced video material, e.g. a TV signal, through conversion into a progressive picture using a so-called de-interlacer. The video content in odd and even frames can then be significantly different, especially if a poor performance de-interlacer (or no de-interlacer) is employed. The result is that some pixels are driven with a voltage that has different values in odd and even frames.

Improved types of inversion schemes which are capable of reducing or avoiding the aforementioned problems experienced when using the known inversion schemes will now be described.

In a simple, first, embodiment, the build up of a DC component to the voltage applied to a typical pixel is reduced by carrying out polarity inversion once in two frames instead. This scheme is based on the recognition that it takes multiple frames for a non-zero DC offset, AC drive signal to cause visible image retention. Line flicker, in the case of poor performing (or no) de- interlacer may remain, but the DC component is removed by carrying out inversion in this manner.

Numerous inversion patterns can be defined for the whole pixel array which provide a polarity inversion on every pixel similar to that illustrated in Figures 6a and 6b, which show graphically the voltage (v) waveform of a pixel addressed with this manner of inversion over five consecutive frames, n-2 to n+2.

Figure 6a shows in particular the drive voltage polarity on a pixel in the case of a progressive source, while Figure 6b shows the drive voltage in the case where odd and even fields of a video source differ considerably. It is to be noted in Figure 6b that DC offset is cancelled as a result of this scheme. The polarity inversion scheme depicted in Figures 6a and 6b is beneficial also when high resolution and/or high refresh rates are required for the LCD. This is because any incomplete charging of a pixel after the polarity change, due to the restricted time available in the case of high resolution or high refresh rate display devices, is completed when polarity repeats.

One of the simplest patterns is to repeat the polarities for the whole array. Figure 7 illustrates such a pattern, for a group of pixels in seven adjacent columns and four adjacent rows over five consecutive frames, for comparison with the scheme depicted in Figure 2. As can be seen from Figure 7, the polarities for all pixels are repeated twice, with the polarities of any two adjacent pixels being of opposite polarity in any one frame, before being inverted. The kind of pattern shown in Figure 7 may, though, produce large area flicker, particularly for static images, which is caused by an incomplete charging of the pixel's LC cell capacitance, or its associated storage capacitor if present, during the first frame of the two frames with the same polarity. This flicker is not due to the use of a poor de-interlacer. Indeed, it occurs with fully static, progressive pictures as well. This is illustrated in Figure 8, and in a simplified form in Figure 9. In Figure 8, VCD is the data signal voltage applied in a row address period in three successive frames, n-2, n-1 and n, and VLC shows the resulting voltage established across the LC cell. When the polarity does not change, then the voltage on the cell reaches a higher value in the second frame of the same polarity, as indicated by the difference d.

Figure 10 shows a first example of inversion pattern of the invention, in which the polarity of neighbouring pixels is repeated out of phase, so that the effect of the incomplete charge can be compensated.

As shown in Figure 10, the four phases comprise two opposite checkerboard polarity patterns interleaved with two opposite phases where all pixels have the same polarity.

The voltages on any two neighbouring pixels over time are represented in Figure 11 , and the cancellation effect is more clearly evident in Figure 11. Figures 11a and 11b show respectively the voltages against time, t, on the two neighbouring pixels, while Figures 11c and 11d show graphically the light output level, L, against time, t, for the same two pixels. As will be seen, the effects of incomplete charging are effectively cancelled out. There is a possibility that the inversion pattern of Figure 10 may give rise to horizontal cross talk due to the finite common electrode resistance. In particular, those frames in which all pixels on one row have the same polarity (e.g. frames n-1 and n+1 in Figure 10) are likely to cause a problem in this respect. When part of the row is addressed with a relatively high voltage value and another part with a relatively low voltage value, then due to the finite (large) common electrode resistance the part with the low voltage value will "see" a higher voltage value.

A further problem is that large area flicker may result as a consequence of unbalance between positive and negative phases. Preferably, each display output should include equal numbers of pixels driven to the two different phases, unlike frames n-1 and n+1 of Figure 10.

A solution to this potential problem is to use a polarity inversion pattern in which the pixels in one row never all have the same polarity within a frame. One example of such a pattern is illustrated in Figure 12, which shows one preferred scheme of the invention. In this pattern, every pixel repeats the polarity twice, neighbouring pixels are "out of phase", and the possibility of significant horizontal cross talk is removed.

In the pattern of Figure 12, the four phases comprise: a first checkerboard polarity pattern; a first double column pattern comprising pairs of identical checkerboard columns alternated with pairs of opposite polarity identical checkerboard columns; a second checkerboard polarity pattern opposite to the first checkerboard polarity pattern; and a second double column pattern comprising pairs of identical checkerboard columns alternated with pairs of opposite polarity identical checkerboard columns, the second double column pattern being opposite to the first double column pattern. The advantages of this pattern can also be achieved with the mirror image, namely where the double column patterns are replaced with a first double row pattern comprising pairs of identical checkerboard rows alternated with pairs of opposite polarity identical checkerboard rows and a second double row pattern opposite to the first double row pattern.

In a further alternative pattern, not shown in the drawings, the four phases comprise: a first double column pattern comprising pairs of identical checkerboard columns alternated with pairs of opposite polarity identical checkerboard columns; a first full column pattern comprising alternating columns of pixels all with the same polarity a second double column pattern opposite to the first double column pattern; and a second full column pattern opposite in polarity to the first full column pattern.

As has been previously mentioned, known kinds of inversion schemes are not suited for pictures that inherently have structurally different picture content in subsequent fields, as in that case the cancellation of dc component by inversion in subsequent fields no longer works. This typically is the case when the picture is coming from interlaced video material that is converted into progressive picture by a so-called de-interlacer. It is to be noted that LCDs always need a progressive (de-interlaced) picture: every field all the rows of the panel need to be written.

Figures 13a to 13d illustrate what happens with a simple line-based de- interlacer. For generating a progressive picture from the odd interlaced field, it copies the odd lines directly to the output. The even lines are not available because the simple de-interlacer does not have a field memory, so the even lines have to be calculated from the odd lines by means of averaging between the odd line directly above and the odd line directly below the even line that needs to be calculated. For generating the progressive picture from the even field, the process is similar. The picture used in these Figures 13a to 13d is a two-dimensional spatial frequency-sweep (zone plate). Figures 13a and 13b illustrate respectively the image obtained from the odd and even fields respectively from an interlaced input, while Figures 13c and 13d illustrate respectively a progressive field 0 from an odd field and a progressive field 1 from an even field respectively. In particular for areas with vertical detail, it is clearly shown that the progressive picture written into the LCD does not have same content every field.

More advanced de-interlacers can do much better but are considerably more expensive as they need at least 1 field storage, and variants have 2 or even 4 fields of storage. Even so, depending on their implementation, situations can exist where even advanced de-interlacing does not generate a perfect progressive picture. In addition, because of the high data rates to be handled, state of the art de-interlacers can not always apply advanced de- interlacing to HD (high definition) interlaced video with good quality.

Furthermore, LCD devices (an LCD TV or monitor) may get their video signal from an external source that does de-interlacing in its own (and potentially poor) quality and the problem remains.

The resulting DC-component of the line-based de-interlacer with the above described zone plate test picture and the known, simple, pixel-inversion scheme is shown in Figure 14. In this Figure, a 50% grey level indicates a zero DC-component, while deviations towards white and black denote respectively a positive and a negative DC-component.

This figure shows the effect of static DC voltage that builds up over time across the LCD pixels. As the ions of the LC material do not move infinitely fast, it takes some time before the charge builds up to significant value. Typically, time constants are in the order of seconds to minutes. So, image stick typically results if the picture (or parts of it, like a logo) remains unaltered for some time.

Relatively large DC-components can accumulate in the case where a pixel is repeatedly driven black in one frame and white in the next, as can happen for example with vertical details in a non-perfectly de-interlaced video signal. Image sticking as result of any DC-components remaining is particularly visible if after a picture containing vertical details a picture is shown that has uniform luminance.

In the SECAM video encoding system, an additional mechanism exists that disturbs the DC-balance in the panel. As shown in Figure 15, the colour information is transmitted in an alternating pattern between the Bmy and Rmy (also denoted as U and V) components. In addition, the polarity of the alternation changes every second field. This means that for coloured pictures the DC-content of the picture is varying over a period of 4 fields. The information from two lines is used to derive the colour information, with the even lines providing luminance and U data, and the odd lines providing luminance and V data. A dc component results particularly from images with abrupt vertical colour changes.

Two specific types of picture material have been identified as particularly likely to cause image sticking effects in LCDs, but potentially other picture material exists which consists of a repetitive sequence of an arbitrary number of fields that individually contain (slightly) different picture content. Such a sequence may be computer generated graphics as well as video material. The inversion schemes described above in connection with Figures 10 and 12 are particularly suited to solving the problems associated with the use of a de-interlacer. However the principles underlying the inversions scheme can be extended to other applications with remaining dc components, such as SECAM video encoding system. In general terms, under the inversion scheme, each individual pixel of the panel has an inversion period that is integer multiple (here denoted by N) of twice the period of the DC-unbalance. For interlaced material, the DC- unbalance is two fields, and the period is thus 4 display fields, giving the four phase inversion schemes of Figures 10 and 12. For interlaced material from a SECAM source this period is preferably 8 display fields, and examples of an inversion scheme with 8 phases are given further below. Variants for picture material having different cycle lengths can also be envisaged. This multi-phase inversion guarantees that no DC-content can build up across the individual LCD pixel cells.

As in the examples above, neighbouring pixels preferably have different phase of the inversion scheme. This prevents large area flicker in the case of the LCD itself suffering from DC-unbalance: it may happen that the LCD pixel cell transparency for positive excitation is not exactly the same as for negative excitation. This flicker will become visible if the inversion period becomes long (as proposed above) and at the same time a large group of connected pixels have the same inversion phase. Preferably, therefore, it should be prevented that the inversion works exclusively field-by-field, line-by-line or column-by-column, as the human eye will easily see it.

It is preferred that the inversion scheme is implementable without having to modify existing column driver ICs and display controllers by inserting some glue logic between the display panel controller and the column drivers.

This allows for adopting the solution quickly and conveniently in existing LCDs.

Preferably, the inversion scheme is also implementable in the display controller hardware, display controller software, column driver hardware or in any combination of these. This allows for alternative solutions.

A practical implementation of a system which can implement the proposed inversion schemes is shown in Figure 16, and this utilises two control signals of known column drivers available from Philips Electronics (under, for example, the type designation PCA8911). In Figure 16, the LCD panel comprises the active matrix pixel array

"LCD Panel", "Row.Drv" denote row driver ICs and "CoI. Drv" denote column driver ICs of conventional form.

The two control signals referred to above are "POL" (polarity) and

"COL2N". The POL signal determines the phase of the first column. The COL2N signal determines the period of the pixel inversion across the row. If

COL2N is low, the polarity of the inversion changes every column (from left to right). If COL2N is high, the polarity changes every second column. Thus, these two control signals enable the column polarity to be controlled in the following manner:

By controlling the two signals on line-by-line and field-by-field bases, it is possible to make various inversion patterns. This controlling is done in a simple state machine 40, which functions as a pixel inversion state control circuit, and which is controlled by line and field pulses from the panel controller. The state machine drives the column drivers. Two further examples of a four-phase inversion scheme for interlaced material are shown in Figures 17 and 18.

In each case, each column comprises a sequence of two pixels of one polarity and two pixels of the opposite polarity.

In Figure 17, each column has opposite polarity to its adjacent columns, so that there are only two different types of column. Each successive field, the polarity of one row adopts the polarity of the following row from the previous field, so that the polarity pattern effectively scrolls up.

The scheme of Figure 17 is relatively simple (with only two different column types in each field) and can be implemented using only the POL (polarity) control signal of the column drivers.

In Figure 18, all four possible alignments of the columns are provided in each field. Thus, each field has four different column patterns. Again, each successive field, the polarity of one row adopts the polarity of the following row from the previous field to give the same scrolling effect. The scheme of Figure 18 controls both the POL and the COL2N (two column inversion) signals. Two examples of inversion scheme for interlaced material from a SECAM source are illustrated in Figures 19 to 21.

Figures 19 to 21 are eight phase schemes.

In Figure 19, each column comprises a sequence of four pixels of one polarity and four pixels of the opposite polarity. Each column has opposite polarity to its adjacent columns, so that there are only two different types of column. Each successive field, the polarity of one row adopts the polarity of the following row from the previous field, so that the polarity pattern effectively scrolls up. Looked at another way, each field comprises a first quadruple row pattern comprising sets of four identical checkerboard rows alternated with sets of four opposite polarity identical checkerboard rows, with successive patters shifted by one row.

In Figure 19, one quarter of the pixels change polarity at each field change. In Figure 20, a more complicated pattern is used, in which ¹/4 of the pixels change polarity at each field change, but there are still eight different polarity patterns for the eight phases.

There are four different types of column. Two have four pixels of one polarity alternated with four pixels of opposite polarity (like the columns in Figure 18) and are opposite to each other, but the other two (in any group of four) have an irregular pattern (+—+-++-) and are again opposite to each other.

In Figure 21 , each column comprises a sequence of four pixels of one polarity and four pixels of the opposite polarity. There are four different types of column, with two of the columns staggered by two pixels with respect to the other two. Again, each successive field, the polarity of one row adopts the polarity of the following row from the previous field, so that the polarity pattern effectively scrolls up.

In Figure 21, one quarter of the pixels change polarity at each field change.

In Figure 22, the column pattern repeats only every 8 columns, so that there are 8 different types of column, and Figure 22 is another 8 phase system. Again, each successive field, the polarity of one row adopts the polarity of the following row from the previous field, so that the polarity pattern effectively scrolls up.

In Figure 22, three quarters of the pixels change polarity at each field change.

All of the inversion schemes outlined above can be implemented using a state machine. The input to the state machine will essentially comprise the field number, the column number and the pixel number in the column, and the inversion state of each pixel in the column will depend on these inputs as processed by the state machine.

As mentioned previously, inversion induced flicker results if the transparency for positive drive voltages is not exactly the same as the transparency for negative voltages. (DC-unbalance in the panel).

In order to prevent visible flicker, it must be assured that the inversion does not work exclusively field-by-field, line-by-line or column-by-column, as the human eye will easily see it.

A further mechanism that can cause flicker is incomplete pixel charge, such that pixel luminance directly inversion is different from its luminance after recharge by the same polarity (as explained with reference to Figure 8). The inversion schemes of the invention can also provide correction for these effects.

In addition to the components shown in Figure 4, a display device of the invention can further comprise an arrangement for detecting the signal type. This can be used to control the de-interlacer, shown schematically as 42 in Figure 4, if this is required, and this in turn can provide an inversion control signal. A decision is then taken to de-interlace the signal based on the type and content of the input signal and the type of de-interlacer. The inversion control signal can select the type of inversion again depending on the type and content of the input signal and the type of de-interlacer. The inversion control (the state machine) can be in the column driver circuitry, in the panel controller, and implemented as hardware or software. All the proposed inversion schemes described above with reference to Figures 6 to 22 are intended to be used in the driving of LCD panels for LCD- TV applications, LCD monitor, particularly multi-media monitor applications (since personal computers and the like can have the capability of de- interlacing and displaying video from an interlaced source), and LCD panels in portable devices.

As mentioned above, it is desirable that, at each phase change, the pixels which change phase are distributed uniformly across the display area.

This even distribution of polarity changes reduces to a minimum the size of the smallest sub-area of the display area which has the same value of kx2/n as the display as a whole. This reduces large area flicker.

The polarity pattern during each phase, and the transitions between polarity patterns, can preferably minimise crawl visibility. This is achieved by avoiding that the pixels which change polarity in any phase change are arranged in rows, columns or blocks.

A number of possible polarity inversion schemes have been described in detail and shown in the Figures. There are, however, many further possibilities. One further example of four phase scheme is one in which the four phases comprise: a first double column pattern comprising pairs of checkerboard columns alternated with pairs of opposite polarity checkerboard columns; a first column line pattern comprising alternating columns of pixels all with the same polarity a second double column pattern comprising pairs of checkerboard columns alternated with pairs of opposite polarity checkerboard columns, the second double column pattern being opposite in polarity to the first double column pattern; and a second column line pattern comprising alternating columns of pixels all with the same polarity, the second column line pattern being opposite in polarity to the first full column pattern.

Another further example of four phase scheme is one in which the four phases comprise: a first double column pattern comprising pairs of checkerboard columns alternated with pairs of opposite polarity checkerboard columns; a first checkerboard pattern but with square groups of four pixels having the same polarity (so that the resolution of the checkerboard pattern is groups of four pixels rather than individual pixels); a second double column pattern comprising pairs of checkerboard columns alternated with pairs of opposite polarity checkerboard columns, the second double column pattern being opposite in polarity to the first double column pattern; and a second checkerboard pattern, again resolution of four pixels rather than individual pixels, and of opposite polarity to the first checkerboard pattern.

Another further example of four phase scheme is one in which the four phases comprise: a first checkerboard pattern; a first blanket pattern in which all pixels are of one polarity only; a second checkerboard pattern opposite to the first; and a second blanket pattern in which all pixels are of one polarity only, opposite to the first blanket pattern.

In this description and claims, a checkerboard row/column is a row/column of alternating polarity pixels (i.e. + - + - + - ...).

Where fractions are mentioned, it will be understood that some deviation is allowed. For example if there are an odd number of pixels (for example an odd number of rows and columns), it is not possible for exactly half the pixels to change polarity, and the fractions should be understood in this context.

Although the above embodiments have all been described in relation to a particular liquid crystal display device, it will be appreciated that the underlying concepts disclosed may also be applied in other liquid crystal display devices, and in other types of display devices requiring or potentially benefiting from inverted polarity column driving. For example, in the above embodiments, the liquid crystal display device is a transmissive device. However, in other embodiments the liquid crystal display device may be a reflective device or a transflective device.

From the present disclosure, many other modifications and variations will be apparent to persons skilled in the art. Such modifications and variations may involve other features which are already known in the art and which may be used instead of or in addition to features already disclosed herein.

Claims

1. A display device comprising an array (10) of pixels (12) arranged in rows and columns and drive circuitry (20,21 ,22,24) for providing pixel drive signals to the pixels, wherein each pixel is driveable with two opposite polarity signals (+,-), wherein each pixel is driven cyclically with a number n of phases where n is 4 or more, n/2 phases with one polarity and n/2 phases with the opposite polarity, and wherein during each phase change, the polarity of k x 2/n of the pixels of the display is changed, where k is an integer and k x 2/n is greater than 0 and less than 1 , and wherein the phases in the first half of each cycle are duplicated in the second half of each cycle with opposite polarity.

2. A display device as claimed in claim 1 , wherein each pixel is driven cyclically with n/2 phases with one polarity followed by n/2 phases with the opposite polarity.

3. A display device as claimed in claim 1 or 2, wherein n=4 and k=1.

4. A display device as claimed in claim 3, wherein the four phases comprise: a first checkerboard polarity pattern; a first double column pattern comprising identical pairs of checkerboard columns alternated with identical pairs of opposite polarity checkerboard columns; a second checkerboard polarity pattern opposite to the first checkerboard polarity pattern; and a second double column pattern opposite to the first double column pattern.

5. A display device as claimed in claim 3, wherein the four phases comprise: a first checkerboard polarity pattern; a first double row pattern comprising pairs of identical checkerboard rows alternated with pairs of opposite polarity identical checkerboard rows; a second checkerboard polarity pattern opposite to the first checkerboard polarity pattern; and a second double row pattern opposite to the first double row pattern.

6. A display device as claimed in claim 1 , wherein n=8.

7. A display device as claimed in claim 6, wherein k=1.

8. A display device as claimed in claim 7, wherein the eight phases comprise: a first quadruple row pattern comprising sets of four identical checkerboard rows alternated with sets of four opposite polarity identical checkerboard rows; seven successive quadruple row patterns, each pattern comprising the previous pattern shifted in a given direction by one row.

9. A display device as claimed in claim 7, wherein k=2, and wherein the polarity pattern for each of the 8 phases is different.

10. A display device as claimed in any preceding claim, wherein the drive circuitry comprises column drive circuitry (22) for controlling the polarity of each pixel, and wherein the device further comprises a state machine (40) for controlling the column driver circuitry.

11. A display device as claimed in claim 10, wherein the column drive circuitry comprises a polarity control input (POL) for controlling the phase of the first column and an inversion period control input (COL2N) for controlling the period of pixel inversion.

12. A display device as claimed in any preceding claim, comprising a liquid crystal display device comprising a pair of substrates and liquid crystal material sandwiched therebetween.

13. A display device as claimed in claim 12, comprising an active matrix liquid crystal display.

14. A display device as claimed in claim 13, wherein each pixel comprises a thin film transistor (11).

15. A display device as claimed in any preceding claim, further comprising a de-interlacer (42).

16. A method of driving a display comprising an array of pixels (12) arranged in rows and columns, the method comprising: driving the pixel array cyclically with a number n of phases where n is 4 or more, n/2 phases with one polarity and n/2 phases with the opposite polarity, and wherein during each phase change, the polarity of k x 2/n of the pixels of the display is changed, where k is an integer and k x 2/n is greater than 0 and less than 1, and wherein the phases in the first half of each cycle are duplicated in the second half of each cycle with opposite polarity.

17. A method as claimed in claim 16, comprising driving each pixel with n/2 phases with one polarity followed by n/2 phases with the opposite polarity.

18. A method as claimed in claim 16 or 17, wherein n=4 and k=1.

19. A method as claimed in claim 18, wherein the four phases comprise: a first checkerboard polarity pattern; a first double column pattern comprising identical pairs of checkerboard columns alternated with identical pairs of opposite polarity checkerboard columns; a second checkerboard polarity pattern opposite to the first checkerboard polarity pattern; and a second double column pattern opposite to the first double column pattern.

20. A method as claimed in claim 18, wherein the four phases comprise: a first checkerboard polarity pattern; a first double row pattern comprising pairs of identical checkerboard rows alternated with pairs of opposite polarity identical checkerboard rows; a second checkerboard polarity pattern opposite to the first checkerboard polarity pattern; and a second double row pattern opposite to the first double row pattern.

21. A display device as claimed in claim 16, wherein n=8.

22. A method as claimed in claim 21 , wherein k=1.

23. A method as claimed in claim 22, wherein the eight phases comprise: a first quadruple row pattern comprising sets of four identical checkerboard rows alternated with sets of four opposite polarity identical checkerboard rows; seven successive quadruple row patterns, each pattern comprising the previous pattern shifted in a given direction by one row.

24. A method as claimed in claim 20, wherein k=2, and wherein the polarity pattern for each of the 8 phases is different.

25. A method as claimed in one of claims 17 to 24, wherein the polarity of the pixels is controlled by a state machine.

26. A drive circuit (20,21 ,22,24) for a display device comprising an array (10) of pixels (12) arranged in rows and columns, wherein the drive circuit is adapted to provide two opposite polarity pixel drive signals (+,-) to the pixels cyclically, the cycle for each pixel having a number n of phases where n is 4 or more, n/2 phases with one polarity and n/2 phases with the opposite polarity, and wherein during each phase change, the polarity of k x 2/n of the pixels of the display is changed, where k is an integer and k x 2/n is greater than 0 and less than 1 , and wherein the phases in the first half of each cycle are duplicated in the second half of each cycle with opposite polarity.

27. A circuit as claimed in claim 26, comprising column drive circuitry (22), and further comprising a state machine (40) for controlling the column driver circuitry (22).

28. A circuit as claimed in claim 27, wherein the column drive circuitry comprises (22) a polarity control input (POL) for controlling the phase of the first column and an inversion period control input (COL2N) for controlling the period of pixel inversion.

29. A display panel, comprising an array of pixels and a drive circuit as claimed in claim 26, 27 or 28 for providing the pixel drive signals to the array of pixels.