WO2006022915A1 - Self-biasing transistor structure and sram cell - Google Patents
Self-biasing transistor structure and sram cellInfo
- Publication number
- WO2006022915A1 WO2006022915A1 PCT/US2005/015294 US2005015294W WO2006022915A1 WO 2006022915 A1 WO2006022915 A1 WO 2006022915A1 US 2005015294 W US2005015294 W US 2005015294W WO 2006022915 A1 WO2006022915 A1 WO 2006022915A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- region
- channel
- gate electrode
- transistor
- channel region
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 58
- 239000000463 material Substances 0.000 claims description 33
- 239000002019 doping agent Substances 0.000 claims description 25
- 230000003068 static effect Effects 0.000 claims description 22
- 238000003860 storage Methods 0.000 claims description 18
- 230000008859 change Effects 0.000 claims description 10
- 238000009413 insulation Methods 0.000 claims description 8
- 230000005669 field effect Effects 0.000 abstract description 9
- 230000015572 biosynthetic process Effects 0.000 abstract description 7
- 210000004027 cell Anatomy 0.000 description 70
- 238000000034 method Methods 0.000 description 33
- 230000008569 process Effects 0.000 description 21
- 239000000758 substrate Substances 0.000 description 18
- 230000001965 increasing effect Effects 0.000 description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 230000006399 behavior Effects 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 239000002800 charge carrier Substances 0.000 description 10
- 238000013461 design Methods 0.000 description 9
- 238000002513 implantation Methods 0.000 description 9
- 238000005468 ion implantation Methods 0.000 description 9
- 230000003213 activating effect Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 8
- 239000003990 capacitor Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 230000015654 memory Effects 0.000 description 5
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 230000003247 decreasing effect Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- 230000035882 stress Effects 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 206010010144 Completed suicide Diseases 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000009877 rendering Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 241000288140 Gruiformes Species 0.000 description 1
- 208000037656 Respiratory Sounds Diseases 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000005465 channeling Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 230000006355 external stress Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 206010037833 rales Diseases 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 241000894007 species Species 0.000 description 1
- 210000000352 storage cell Anatomy 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 230000003936 working memory Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/105—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with vertical doping variation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
Definitions
- the present invention generally relates to the fabrication of integrated circuits, and, more particularly, to transistor architectures that enable an extended functionality of transistor devices, thereby providing the potential for simplifying the configuration of circuit elements, such as registers, static RAM cells, and the like.
- FETs field effect transistors
- a gate electrode which may influence, upon application of an appropriate control voltage, the conductivity of a channel region formed between a drain terminal and a source terminal.
- FIG. 1 schematically shows a cross-sectional view of a typical field effect transistor element as may be used in modern MOS-based logic circuitry.
- a transistor element 100 comprises a substrate 101, for instance a silicon substrate having formed thereon or therein a crystalline region 102 on and in which further components of the transistor element 100 are formed.
- the substrate 101 may also represent an insulating substrate having formed thereon a crystalline semiconductor layer of specified thickness that accommodates further components of the transistor 100.
- the crystalline region 102 comprises two or more different dopant materials in a varying concentration to obtain the desired transistor function.
- drain and source regions 104 defining a first conductivity type, for instance, an N-conductivity, are formed within the crystalline region 102 and have a specified lateral and vertical dopant profile.
- the crystalline region 102 between the drain and source regions 104 may be doped with a material providing the opposite conductivity type, that is, as in the example shown, a P-conductivity, to produce a PN junction with each of the drain and source regions 104.
- a relatively thin channel region 103 may be established between the drain and source regions 104 and it may be doped with a P-type material when the transistor 100 is to represent an N-channel enhancement transistor, or which may be slightly doped with an N-type material when the transistor 100 is to represent an N- channel depletion transistor.
- a gate electrode 105 Formed above the channel region 103 is a gate electrode 105, which is separated and thus electrically insulated from the channel region 103 by a thin gate insulation layer 106.
- sidewall spacers 107 may be provided at sidewalls at the gate electrode 105, which may be used during the formation of the drain and source regions 104 by ion implantation and/or in subsequent processes for enhancing the conductivity of the gate electrode 105, which is typically comprised of doped polysilicoii in silicon-based transistor elements.
- the gate electrode 105 which is typically comprised of doped polysilicoii in silicon-based transistor elements.
- any further components such as metal suicides and the like are not shown in Figure Ia.
- one essential dimension of the transistor 100 is the channel length, i.e., in Figure Ia, the horizontal extension of the channel region 103, wherein the channel length is substantially determined by the dimension of the gate electrode 105 since the gate electrode 105, possibly in combination with any sidewall spacers, such as the spacers 107, is used as an implantation mask during the formation of the drain and source regions 104.
- the basic operations scheme is as follows.
- the drain and source regions 104 are connected to respective voltages, such as ground and supply voltage VDD, wherein it is now assumed that the channel region 103 is slightly P- doped to provide the functionality of an N-channel enhancement transistor. It is further assumed that the left region 104 is connected to ground and will thus be referred to as the source region, even though, in principle, the transistor architecture shown in Figure Ia is symmetric with respect to the regions 104.
- the region 104 on the right-hand side, connected to VDD, will be referred to as the drain region.
- the crystalline region 102 is also connected to a specified potential, which may be ground potential and any voltages referred to in the following are considered as voltages with respect to the ground potential supplied to the crystalline region 102 and the source region 104.
- a voltage supplied to the gate electrode 105 or with a negative voltage the conductivity of the channel region 103 remains extremely low, since at least the PN junction from the channel region 103 to the drain region 104 is inversely biased and only a negligible number of minority charge carriers is present in the channel region 103.
- the number of minority charge carriers, i.e., electrons, in the channel region 103 may be increased due the capacitive coupling of the gate potential to the channel region 103, but without significantly increasing the total conductivity of the channel region 103, as the P.N junction is still not sufficiently forward-biased.
- the channel conductivity abruptly increases, as the number of minority charge carriers is increased to remove the space charge area in the PN junction, thereby forward-biasing the PN junction so that electrons may flow from the source region to the drain region.
- the gate voltage at which the abrupt conductivity change of the channel region 103 occurs is referred to as threshold voltage VT.
- Figure Ib qualitatively illustrates the behavior of the device 100 when representing an N-channel enhancement transistor.
- the gate voltage VG is plotted on the horizontal axis, while the vertical axis represents the current, that is the electrons, flowing from the source region to the drain region via the channel region 103.
- the drain current depends on the applied voltage VDD and the specifics of the transistor 100.
- the drain current may represent the behavior of the channel conductivity, which may be controlled by gate voltage VG.
- a high impedance state and a high conductivity state are defined by the threshold voltage VT.
- Figure Ic schematically shows the behavior of the transistor element 100 when provided in the form of an N-channel depletion transistor, i. e. , when the channel region 103 is slightly N-doped.
- the majority charge carriers (electrons) provide for conductivity of the channel region 103 for a zero gate voltage, and even for a negative gate voltage, unless the negative gate voltage is sufficiently high to create sufficient minority charge carriers to establish an inversely biased PN junction, thereby abruptly decreasing the channel conductivity.
- the threshold voltage VT is shifted to negative gate voltages in the N-channel depletion transistor when compared with the behavior of the N-channel enhancement transistor. It should be noted that a similar behavior is obtained for P-channel enhancement and depletion transistors, wherein, however, the channel conductivity is high for negative gate voltages and abruptly decreases at the respective threshold voltages with a further increasing gate voltage.
- registers In the form of registers, static RAM (random access memory), and dynamic RAM represent an important component of complex logic circuitries. For example, during the operation of complex CPU cores, a large amount of data has to be temporarily stored and retrieved, wherein the operating speed and the capacity of the storage elements significantly influence the overall performance of the CPU.
- memory elements Depending on the memory hierarchy used in a complex integrated circuit, different types of memory elements are used. For instance, registers and static RAM cells are typically used in the CPU core due to their superior access time, while dynamic RAM elements are preferably used as working memory due to the increased bit density compared to registers or static RAM cells.
- a dynamic RAM cell comprises a storage capacitor and a single transistor, wherein, however, a complex memory management system is required to periodically refresh the charge stored in the storage capacitors, which may otherwise be lost due to unavoidable leakage currents.
- a charge has to be transferred from and to storage capacitors in combination with periodic refresh pulses, thereby rendering these devices less efficient in terms of speed and power consumption when compared to static RAM cells.
- static RAM cells require a plurality of transistor elements to allow the storage of an information bit.
- Figure Id schematically shows a sketch of a static RAM cell 150 in a configuration as may typically be used in modern integrated circuits.
- the cell 150 comprises a bit cell 110 including, for instance, two inversely coupled inverters 111.
- the bit cell 110 may be connectable to a bit line 112 and to an inverse bit line 113 (not shown in Figure Id) by respective select transistor elements 114, 115.
- the bit cell 110 that is, the inverters 111, as well as the select transistor elements 114, 115, may be formed of transistor elements, such as the transistor 100 shown in Figure Ia.
- the inverters 111 may each comprise a complementary pair of transistors 100, that is, one P-channel enhancement transistor and one N-channel enhancement transistor coupled as shown in Figure Id.
- the select transistor elements 114, 115 may be comprised of N-channel enhancement transistors 100.
- the bit cell 110 may be "programmed" by pre-charging the bit lines 112, 113, for example with logic high and logic zero, respectively, and by activating the select line 116, thereby connecting the bit cell 110 with the bit lines 112, 113. After deactivating the select line 116, the state of the bit cell 110 is maintained as long as the supply voltage is connected to the cell 150 or as long as a new write cycle is performed. The state of the bit cell 110 may be retrieved by, for example, bringing the bit lines 112, 113 in a high impedance state and activating the select line 116.
- the present invention is directed to a technique that enables the formation of circuit components including transistor elements in a more space-efficient manner, especially in static memory devices, in that the functionality of a transistor element is extended so that a self-biasing conductive state may be obtained.
- a semiconductor device comprises a drain region formed in a substantially crystalline semiconductor material and doped with a first type of dopant material to provide a first conductivity type.
- the device further comprises a source region formed in the substantially crystalline semiconductor material, which is doped with the first type of dopant material to provide the first conductivity type.
- a first channel region is located between the drain region and the source region and is doped with the first type of dopant material to provide the first conductivity type.
- a second channel region is located between the drain region and the source region and adjacent to the first channel region and is doped with a second type of dopant material to provide a second conductivity type that differs from the first conductivity type.
- a gate electrode is located to enable control of the first and second channel regions.
- a transistor element comprises a drain region, a source region, and a channel region, which is formed between the drain region and the source region and which is configured to define at least a first threshold of a first abrupt conductivity change and a second threshold of a second abrupt conductivity change of the channel region.
- the transistor element further comprises a gate electrode that is located to enable control of the channel region by capacitive coupling.
- a static RAM cell comprises a select transistor and an information storage element coupled to the select transistor, wherein the information storage element includes less than four transistor elements.
- a static RAM cell comprises a transistor element having a gate electrode, a dram region, a source region, and a channel region that is electrically connected with the gate electrode. Moreover, the transistor element is configured to self-bias the gate electrode to maintain the channel region in a stationary conductive state.
- a static RAM cell comprises two or less transistor elements.
- Figure Ia schematically shows a cross-sectional view of a typical conventional field effect transistor
- Figure Ib and Figure Ic schematically show plots of the progression of the drain current, i.e., the progression of the channel conductivity, versus the applied gate voltage for an N-channel enhancement transistor and for an N-channel depletion transistor, respectively;
- Figure Id schematically shows a circuit diagram of a typical conventional static RAM cell including at least six individual transistor elements
- Figure 2a schematically shows a circuit diagram of a storage element including a self-biasing semiconductor device in accordance with illustrative embodiments of the present invention
- Figure 2b schematically shows a qualitative plot of the progression of a channel conductivity versus an applied control voltage to obtain a self-biased stationary conductivity state according to an illustrative embodiment of the present invention
- Figures 3a and 3b schematically show cross-sectional views of transistor elements, each having two inversely doped channel regions for an N-type double channel transistor and a P-type double channel transistor, respectively, according to particular embodiments of the present invention
- Figure 3 c schematically illustrates a circuit diagram for a simplified model of a double-channel field effect transistor in accordance with illustrative embodiments of the present invention
- Figure 3d schematically illustrates a plot of a channel conductivity for each of the two channels in the double channel transistor in a simplified fashion
- Figure 3e schematically shows a plot qualitatively illustrating the drain currents, i.e., the channel conductivity of the double channel transistor with respect to a variation of the gate voltage according to illustrative embodiments;
- Figure 4a schematically shows a circuit diagram of a static RAM cell, including a double channel transistor in accordance with a particular embodiment of the present invention, wherein the RAM cell comprises only two transistor elements;
- Figure 4b schematically shows a circuit diagram of a RAM cell including less than six transistor elements in accordance with a further illustrative embodiment
- Figure 5 schematically shows a cross-sectional view of an SOI transistor element having two inversely doped channel regions according to one illustrative embodiment
- Figure 6 schematically shows a cross-sectional view of a transistor element having inversely doped channel regions, which also differ in at least one of material composition and internal strain. While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims. MODE(S) FOR CARRYING OUT THE INVENTION
- the present invention is based on the concept that the circuit architecture of a plurality of logic circuit portions, especially of registers, static memory cells, and the like, may be significantly simplified in that one or more characteristics of a semiconductor switch element may be modified to obtain extended functionality.
- the inventors contemplated to provide a self-biasing semiconductor switch which may be based in particular embodiments of the present invention on a field effect transistor design with a modified channel region, wherein a conductive state, once initiated, is maintained as long as the supply voltage is applied, unless a change of conductivity state is externally initiated.
- the number count of individual switch elements in a static RAM cell may be drastically reduced compared to conventional RAM cell designs and may be less than six, thereby enabling the fabrication of fast storage devices with a bit density that is comparable with that of dynamic RAM devices.
- Figure 2a schematically shows a circuit diagram of a basic static RAM cell 250 comprising a bit cell 210 for storing an information bit.
- the bit cell 210 is coupled to a select transistor 214, which in turn is connected to a bit line 212 and a select line 216.
- the bit cell 210 is comprised of a semiconductor element including a channel region 203 that is configured to provide a controllable conductivity, wherein a gate electrode 205 is provided, which enables the control of the channel region 203 via capacitive coupling.
- a feedback section 208 is provided, for instance in the form of an electrically conductive region having a specified resistivity or the like, to connect the channel region 203 via an output terminal 204s with the gate electrode 205.
- the channel region 203 may be connected to a specified voltage source, such as the source supplying the supply voltage VDD, by a respective output terminal 204d.
- the bit cell 210 is configured such that, upon application of a specified control voltage to the gate electrode 205, the conductivity of the channel region 203 changes from a moderately high impedance state into a state of moderately high conductivity, which may be maintained, even after interrupting the initial control voltage, via the feedback section 208.
- the semiconductor device 210 exhibits a specified behavior with respect to the conductivity of the channel region 203 in relation to the applied control voltage VG once the device 210 is in the conductive state, as will be explained with reference to Figure 2b.
- Figure 2b qualitatively describes the behavior of the bit cell 210 that is obtained by the above-described configuration.
- the conductivity of the channel region 203 is plotted along the vertical axis in arbitrary units and the control voltage VG supplied to the gate electrode 205 is shown on the horizontal axis.
- the semiconductor device 210 is configured such that at a specified threshold voltage VT, which may be set by structural measures as will be described in more detail with reference to Figures 3 a, 3b, 5 and 6, the conductivity of the channel region 203 shows a pronounced abrupt change or, in particular embodiments, a local maximum in such a way that with a further increase of the control voltage VG at the gate electrode 205 a significant drop in conductivity is obtained.
- VT specified threshold voltage
- the channel region 203 is in a highly conductive state so that the supply voltage VDD is more or less also present at the output 204s and, via the feedback section 208, at the gate electrode 205.
- a corresponding voltage is supplied via the conductive channel region 203, the feedback section 208 to the gate electrode 205, wherein a self-stabilizing condition is established, since the channel conductivity increases as the voltage at the gate electrode 205 tends to decrease during discontinuing the initially supplied control voltage pulse owing to, for example, charge carrier leakage and the like.
- the bit cell 210 may be written to by pre-charging the bit line 212 with a voltage above or at the threshold voltage VT, for instance VDD, and by activating the select line 216, thereby switching the select transistor 214 from its off-state into its on-state.
- the selector transistor 214 is in its on-state, the voltage at the bit line 212 is supplied via the feedback section 208 to the gate electrode 205, which is correspondingly charged to generate a conductivity of the channel region 203, as is qualitatively shown in Figure 2b, at or above the threshold voltage VT.
- the select transistor 214 may be disabled and the bit line 212 may be brought into a high impedance state so that it is prepared for a read operation. Due to the self-biasing mechanism of the bit cell 210, the conductivity of the channel region 203 is maintained at a moderately high value, even though the initial control voltage pulse supplied via the select transistor 214 is discontinued. As previously explained, this low impedance state of the bit cell 210 is stationary and remains as long as the supply voltage VDD is present or a new write cycle is initiated. During reading of the bit cell 210, the bit line 212 may be in a high impedance state and the select transistor 214 may be switched into its on-state by activating the select line 216.
- bit cell 210 Due to the self-biased high conductivity state of the bit cell 210, charge may be supplied from the supply voltage source VDD to the bit line 212 to establish the voltage VDD at the bit line 212, which may be sensed by a corresponding sense amplifier (not shown). Thus, a logic state corresponding to the self-biased state of the bit cell 210 may be identified and read out. Similarly, a high impedance state may be written into the bit cell 210 by, for instance, pre-charging the bit line 212 with ground potential and activating the select line 216.
- the ground potential is supplied to the gate electrode 205 via the feedback section 208 - the inherent resistance of the bit line 212 is assumed to be significantly lower than the resistance of the channel region 203 in its high conductivity state - and hence the channel region 203 is brought into its high impedance state, which is maintained even if the bit line 212 is decoupled from the output 204s by deactivating the select line 216.
- the semiconductor bit cell 210 a significantly simplified architecture for a static RAM cell is obtained, wherein particularly the number of individual semiconductor elements may be less than in the conventional RAM cell described with reference to Figure Id.
- FIG 3a schematically shows a cross-sectional view of a transistor element 300 that may be used in forming a self-biasing semiconductor device, such as the self-biasing bit cell 210 in Figure 2a.
- the transistor element 300 comprises a substrate 301, which may be any appropriate substrate, such as a bulk semiconductor substrate, an insulating substrate having formed thereon a crystalline semiconductor layer, and the like.
- the substrate 301 may represent a bulk silicon substrate or a silicon-on-insulator (SOI) substrate, since presently and in the near future the vast majority of complex integrated circuits is and will be fabricated on the basis of silicon.
- SOI silicon-on-insulator
- a substantially crystalline semiconductor region 302 which may comprise a specified dopant material to provide a specified conductivity type for the region 302.
- the semiconductor region 302 is doped to provide a P-conductivity.
- drain and source regions 304 Adjacent to the region 302 are formed drain and source regions 304 including a dopant material that imparts an opposite conductivity type to the semiconductor region 302.
- the drain and source regions 304 are heavily doped so that corre ⁇ sponding PN junctions are formed along interfaces between the drain and source regions 304 and the semiconductor region 302. Moreover, a channel region 303 is formed between the drain and source regions 304, wherein, contrary to the conventional transistor design as is explained with reference to Figure Ia, the channel region 303 is modified in that it defines a specified threshold voltage at which an abrupt conductivity change occurs yet still providing a moderately high conductivity at both sides of the specified threshold voltage.
- the channel region 303 may comprise a first channel sub-region 303a that is inversely doped with respect to the drain and source regions 304.
- the first channel sub-region 303a may be considered as a "conventional" channel region of a conventional enhancement transistor, such as, for instance, the transistor 100 in Figure Ia.
- the channel region 303 may further comprise a second channel sub-region 303b that is inversely doped to the first channel sub-region 303a, and may therefore be considered as a "depletion" channel.
- the transistor element 300 further comprises a gate electrode 305 located to enable the control of the first and second channel sub-regions 303a and 303b by capacitive coupling.
- the gate electrode 305 is separated from the channel region 303 by a gate insulation layer 306 comprised of silicon dioxide and/or silicon nitride and/or silicon oxynitride and/or high-k dielectric materials and the like.
- the transistor element 300 may comprise sidewall spacers 307 formed on sidewalls of the gate electrode 305.
- any contact portions that typically provide an electrical connection to the drain and source regions 304 and the gate electrode 305 are not shown.
- a connection may be provided that connects one of the drain and source regions 304 with the gate electrode 305, as is schematically shown in Figure 2a in the form of the feedback section 208.
- a corresponding connection may be established in the form of a so- called local interconnect.
- Figure 3b schematically shows the transistor element 300 when configured as a P-type transistor.
- the transistor element 300 of Figure 3b comprises the same components as previously described with reference to Figure 3a with the exception that the drain and source regions 304, the channel sub-regions 303a and 303b, and the semiconductor region 302 are inversely doped compared to the device of Figure 3a.
- a typical process flow for forming the semiconductor device 300 as shown in Figure 3a or Figure 3b may comprise the following processes.
- the vertical dopant profile of the semiconductor region 302 may be created by well-established ion implantation cycles. During this ion implantation sequence, also the vertical dopant profile of the channel region 303 may be established.
- an N-doped region corresponding to the second channel sub-region 303b ( Figure 3a) may be created.
- a surface portion of the semiconductor region 302 may be pre-amorphized to reduce any channeling effects during the ion implantation of the N-type dopant material for defining the second channel sub-region 303b.
- a further ion implantation sequence may be performed to create the P-doped first channel sub-region 303a, wherein, in both implantation cycles, the dose and implantation energy may be appropriately selected to achieve a desired concentration and a specified depth within the semiconductor region 302.
- the dose and implantation energy may be appropriately selected to achieve a desired concentration and a specified depth within the semiconductor region 302.
- Corresponding process parameters may readily be obtained by performing simulation calculations and/or test runs.
- one or two semiconductor layers may be epitaxially grown in a deposition atmosphere containing the required type of dopant. For instance, an N-type semiconductor layer may be grown on the semiconductor region 302, followed by the epitaxial growth of a P-type semiconductor layer with a desired thickness.
- the semiconductor region 302 may be implanted to create the second channel sub-region 303b and subsequently a layer for the first channel sub-region 303a may be formed by epitaxial growth in a dopant-containing atmosphere.
- additional threshold voltage implantations may be performed to correspondingly adjust the finally obtained thresholds for the controllability of the channel region 303 by means of the gate electrode 305.
- the gate insulation layer 306 and the gate electrode 305 may be formed in conformity with conventionally established processes, followed by advanced implantation cycles for forming the drain and source regions 304.
- N-type transistor of Figure 3 a wherein corresponding explanations with inverse voltages also apply to the device 300 of Figure 3b.
- the region 304 on the left-hand side of Figure 3a represents the source region and is connected to ground potential.
- the semiconductor region 302 is connected to ground potential while the region 304 on the right-hand side is connected to the supply voltage VDD to act as a dram region.
- the gate electrode 305 is connected to a voltage source that may provide a control voltage VG. Any values for applied voltages are given with respect to the ground potential, to which the semiconductor region 302, as well as the source region 304, are connected in the example shown.
- Applying a zero voltage VG may lead to a relatively low conductivity of the channel regions 303, that is, it may represent a substantially high impedance state of the transistor 300, since the first channel sub-region 303a may be operated below its threshold voltage for providing sufficient minority charge carriers to establish a conductive channel, as is previously explained with reference to the enhancement transistor of Figure Ib.
- the second channel sub-region 303b forming a PN- junction with the overlying region 303a may donate some of its majority charge carriers to the region 303a, which in turn may provide some of its majority charge carriers to the region 303b until a corresponding space charge area is established.
- the second channel sub-region 303b may also form a space charge area with respect to the neighboring drain region 304, wherein this area is inversely biased by VDD and ground potential to significantly reduce the conductivity of the second channel sub-region 303b. Consequently, the overall conductance of the channel region 303 is moderately low.
- the control voltage VG Upon increasing the control voltage VG, electrons are increasingly redistributed to the second channel region 303b, thereby increasing the overall conductivity, while the first channel sub-region 303 a is still below its threshold value.
- the control voltage VG reaches the threshold voltage for the first channel sub-region 303a, which will be referred to as VTl, the conductivity thereof abruptly increases, and hence the overall conductivity of the channel region 303 also abruptly increases.
- the second channel sub-region 303b has a second threshold value, referred to in the following as VT2, at which the channel is completely depleted, wherein the corresponding threshold voltage is adjusted to be significantly higher than the first threshold voltage VTl, determining the behavior of the first channel sub-region 303a.
- VT2 second threshold value
- both channels are conductive, thereby imparting a relatively high conductivity to the entire channel region 303.
- the overall conductivity abruptly decreased since the current flow is now restricted to the first channel sub-region 303a.
- the overall conductivity again increases since the conductivity of the first channel region 303 a continuously increases while the second channel sub-region 303b is still in a high impedance state.
- Figure 3c schematically shows a simplified electrical model of the transistor element 300 shown in Figure 3a or 3b.
- the first channel sub-region 303a is represented by a first resistor Rl
- the second channel sub-region 303b is represented by a resistor R2.
- the resistors Rl and R2 may have a resistance value on the order of magnitude of 1000 ohms.
- the resistance value of Rl may take on a high value below the first threshold voltage VTl, which is substantially determined by the structural specifics of the transistor element 300.
- the resistor R2 is assumed to take on a high impedance state when the device 300 is operated with a gate voltage at or above the second threshold voltage VT2, since then the second channel sub-region 303b is substantially completely depleted.
- Figure 3d illustrates the above-explained behavior in a qualitative fashion, wherein the vertical axis represents the resistance values of the resistors Rl and R2, while the horizontal axis indicates the applied gate voltage VG.
- the second channel sub-region 303b exhibits a substantially constant ohm-resistance of approximately 1200 ohms at gate voltages below the second threshold voltage VT2, which is approximately 0.45 volts in the present example.
- the first channel sub-region 303a exhibits a high resistance value for gate voltages below the first threshold voltage VTl, which is here selected to be approximately 0.15 volts, and abruptly changes to approximately 800 ohm for gate voltages above the first threshold voltage VTl . It should be appreciated that actually the channel conductivity in the low-impedance state varies with the gate voltage, wherein, however, this variation is negligible compared to the abrupt change at the respective threshold voltages VTl and VT2 and is therefore not shown in Figure 3d.
- Figure 3e schematically shows a graph representing the current flow through the channel region 303, which may also be considered as representing the conductivity of the channel region 303, with a varying gate voltage.
- the resistor Rl is in its high impedance state, while the resistor R2 is in its low ohmic state, wherein a slight reduction in the conductivity may be observed due to the typical dependence of the drain current from the gate voltage, i.e., the number of free charge carriers is determined by the gate potential and thus leads to a typical variation of the channel conductivity and hence of the channel resistance, which is not taken into consideration in the model shown in Figure 3d since the variation of the resistance in the on-state is significantly less compared to the difference between the high impedance state and the high conductivity state.
- the total conductivity has a minimum, as previously explained, and slightly increases for positive gate voltages until the threshold VTl is reached, which causes an abrupt change in conductivity. Thereafter, both resistances Rl and R2 are in their low-ohmic state and the drain current, and thus the conductivity, increases with increasing gate voltage mainly due to the variation of the first channel resistance.
- the second threshold voltage VT2 the second channel is depleted and hence the total drain current, and thus the total conductivity of the channel region 303, is abruptly decreased and starts increasing from a lower level with increasing gate voltage due to the ongoing increase in conductivity of the first channel region 303 a.
- the transistor elements 300 exhibit a behavior of the channel conductivity as is explained with reference to Figure 2b, thereby enabling the formation of a semiconductor device, such as the bit cell 210 of Figure 2a, on the basis of conventional transistor technologies with a modification of the channel region, as is described, for instance, with reference to the channel region 303.
- Figure 4a schematically shows a circuit diagram of an SRAM cell 450 including a transistor element having a modified channel region to store a bit of information.
- the cell 450 comprises a transistor element 400 having a modified channel region 403 that may include a first channel region and a second channel region, as is shown, for instance, in Figures 3a and 3b.
- the transistor element 400 comprises a gate electrode 405 and a drain terminal 404d and a source terminal 404s.
- Figure 4a also illustrates a circuit symbol for a field effect transistor having a modified channel configuration that provides the above-described characteristic and which may, in particular embodiments, provide a double channel configuration.
- the gate electrode 405 and the source terminal 404s are electrically connected and are both connected to a select transistor 414, the gate 414g of which is connected to a select line 416 while a source/drain terminal 414s is connected to a bit line 412.
- the SRAM cell 450 merely includes the transistor elements 414 and 400 as the only transistor elements and does not require any further active components. In other embodiments, further transistor elements may be provided to enhance the functionality and/or the reliability of the cell 450 as will be described later on. It is to be noted, however, that the total number of transistor elements may still be less than six transistor elements, as in the conventional design shown in Figure Id.
- the transistor elements 400 and 414 may be readily formed in accordance with the process flow as previously described with reference to Figures 3a and 3b, wherein any additional process steps for forming the modified channel region 403 may be performed, for instance by ion implantation, while the transistor 414 is masked so that a high degree of compatibility is still maintained for the entire process flow for forming the cell 450.
- the operation of the cell 450 is substantially the same as is previously described with reference to Figures 2a and 2b. That is, when -writing a logic 1 state into the cell 450, that is, into the transistor element 400, the bit line 412 may be pre-charged and the select transistor 414 may be turned on by activating the select line 416.
- the gate 405 is set to the potential of the bit line 412, which is assumed to be VDD that, in turn, is higher than the specified threshold voltage, at which the conductivity of the channel region 403 has a local maximum.
- the specified threshold voltage may be referred to as VT2, as shown in Figures 3e and 3d.
- the high conductivity state is maintained since now the transistor element 400 is in a self-biased stationary state, which leads to an increase of conductivity whenever the gate voltage tends to drop.
- the source terminal 404s is maintained at a voltage at or above the threshold voltage VT2, thereby indicating a logic high state.
- This state may be read out in the same way as is described with reference to Figure 2a.
- a high impedance state may be written into the cell 450 by correspondingly pre-charging the bit line 412 and activating the select line 416. In this case, the conductivity of the channel region 403 is low and remains low unless a new state is written into the cell 450.
- Figure 4b schematically shows a circuit diagram describing the SRAM cell 450 containing more than two transistor elements, but less than six transistor elements.
- a first double channel transistor element 400a and a second double channel transistor element 400b are provided, which may differ from each other by a different threshold voltage VT2a and VT2b.
- a corresponding arrangement may be advantageous in operating the cell 450 with two different supply voltages VDD, wherein a first operating mode may be considered as a low current mode with a reduced supply voltage and possibly reduced operating speed, while a high current mode may allow the operation with an increased supply voltage, thereby possibly improving the total operating speed and/or the signal-to-noise ratio for storing information in the cell 450.
- the transistor element 400a may have threshold voltage VT2a being less compared to threshold voltage VT2b of the transistor element 400b.
- the generation of different threshold voltages VT2 may readily be achieved during the fabrication of the cell 450 in that, for example, a first implantation sequence is performed to form the channel region of the device 400a while the device 400b is masked, and performing a second implantation sequence with the device 400a masked and the device 400b exposed.
- Other approaches for the generation of different threshold voltages will also be described with reference to Figure 6.
- the write and read cycles may be performed as previously described, wherein, when operated at a higher VDD, the transistor element 400b is operated in the self-biasing mode and thus maintains its gate voltage and the gate voltage of the transistor element 400a at the high threshold voltage VT2b when remaining in the high conductivity state.
- the device 400a when being operated with a low VDD that may range between the threshold VT2b and VT2a of the transistor 400b and the transistor 400a, the device 400a remains in the high conductivity state and thus keeps the gate voltages of the devices 400a and 400b at the lower threshold voltage VT2a.
- the device 450 may be used to store three different states, one state representing a high impedance state, one state representing a high conductivity state with a gate voltage at the lower threshold voltage VT2a, and one state representing a high conductivity state at the higher threshold voltage VT2b of the device 400b.
- the bit line When writing corresponding states into the cell 450, the bit line has to be pre-charged with respective voltages.
- a corresponding number of different states maybe stored in the cell 450, wherein a single select line 416 and a single bit line 412 is sufficient to address the cell 450 having stored therein a plurality of different states.
- the lower threshold VT2a may be considered as a stand-by threshold, to ensure data integrity when the supply voltage VDD decreases below the normal operating voltage due to a sleep mode, during which the supply voltage may be delivered by a storage capacitor or the like.
- Figure 5 schematically shows a cross-sectional view of a double channel transistor element 500 in the form of an N-type transistor configured as an SOI device.
- the transistor element 500 comprises drain and source regions 504 formed in a semiconductor layer 502 located above an insulation layer 520.
- the insulation layer 520 may represent a thin dielectric layer formed on any appropriate substrate 501, which is typically a bulk semiconductor substrate such as a silicon substrate.
- the device 500 comprises a first channel region 503a and a second channel region 503b, which are inversely doped to provide the required channel characteristics as previously described.
- a gate electrode 505 is formed above the channel regions 503a, 503b, and is separated therefrom by a gate insulation layer 506.
- the transistor element 500 may be manufactured in accordance with conventional process techniques, wherein the channel regions 503a, 503b may be formed by ion implantation and/or epitaxial growth techniques, as is previously described with reference to Figures 3a and 3b.
- the SOI device 500 may be advantageously incorporated into complex microprocessors, which are increasingly fabricated as SOI devices.
- Figure 6 schematically shows a double channel transistor element 600 comprising a substrate 601 with a crystalline semiconductor region 602 formed thereon or therein.
- Drain and source regions 604 having a first conductivity type are formed within the regions 602 to form a PN-junction with the remainder of the semiconductor regions 602, which is doped to exhibit a second conductivity type.
- a first channel region 603a and a second channel region 603b are formed such that the first channel region 603a is located more closely to a gate electrode 605, which is separated from the channel region 603a by a gate insulation layer 606.
- the first channel region 603a may be doped to exhibit the second conductivity type, whereas the second channel region 603b may exhibit the first conductivity type.
- first and second channel regions 603a, 603b differ from each other in at least one of material composition and internal strain. That is, the characteristics of the respective channel regions may not only be determined by dopant concentration, but also by other parameters such as material composition, internal strain, and the like.
- the second channel region 603b may be comprised of a silicon/germanium composition, which may be formed by epitaxial growth with a subsequent growth of a silicon layer for the first channel region 603 a, wherein, depending on process requirements, the layer 603b may be relaxed or not to have specified internal strain or to impart a specified stress to the layer 603a.
- the channel region 603a may be provided as a strained silicon/germanium layer.
- other materials such as silicon/carbon may be used with appropriate composition in one or both of the channel regions 603 a and 603b.
- the various thresholds VTl and VT2 for the channel regions 603a and 603b may effectively be adjusted by correspondingly selecting a specified material composition and/or a specified internal strain. Since strain engineering becomes more and more important in advanced MOS devices, corresponding process schemes may also be advantageously employed in designing the double channel transistor characteristics. For instance, different threshold voltages may be created at different die regions for the same transistor configuration by locally modifying the strain.
- a specific internal strain in the channel region 603 a and/or 603b may be created by applying external stress, for instance by means of a specifically stress-containing capping layer enclosing the transistor element 600.
- stress may be created additionally or alternatively by a corresponding implantation of specific ion species, such as hydrogen, helium, oxygen, and the like, in or in the vicinity of the first and second channel regions 603a, 603b, thereby specifically adjusting the respective threshold voltages.
- specific ion species such as hydrogen, helium, oxygen, and the like
- the present invention provides a self-biasing semiconductor device that may mostly be advantageously used in combination with static storage cells, such as RAM cells, to significantly reduce the number of transistor elements required. Since already well-established process techniques may be used in forming a corresponding self-biasing transistor element, for instance in the form of a double channel transistor, a significant improvement in bit density and/or performance may be achieved for a given technology node. Moreover, since SRAM devices may now be fabricated in a highly efficient manner with a bit density comparable to dynamic RAM devices, the dynamic devices, usually employed as external operating memory for CPUs, may be readily replaced, thereby providing immense cost and performance advantages. Moreover, the simplified SRAM design of the present invention in combination with a low-cost power supply enables a cost-effective utilization of SRAM devices in a wide variety of applications, which may currently employ magnetic storage devices or EEPROMs.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Memories (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020077002765A KR101125825B1 (en) | 2004-07-30 | 2005-04-29 | Self-biasing transistor structure and sram cell |
JP2007523549A JP2008508715A (en) | 2004-07-30 | 2005-04-29 | Self-biased transistor structure and SRAM cell |
GB0702553A GB2431774B (en) | 2004-07-30 | 2005-04-29 | Self-biasing transistor structure and SRAM cell |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102004037087A DE102004037087A1 (en) | 2004-07-30 | 2004-07-30 | Self-biasing transistor structure and SRAM cells with fewer than six transistors |
DE102004037087.7 | 2004-07-30 | ||
US11/045,177 | 2005-01-28 | ||
US11/045,177 US7442971B2 (en) | 2004-07-30 | 2005-01-28 | Self-biasing transistor structure and an SRAM cell having less than six transistors |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2006022915A1 true WO2006022915A1 (en) | 2006-03-02 |
Family
ID=34968873
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2005/015294 WO2006022915A1 (en) | 2004-07-30 | 2005-04-29 | Self-biasing transistor structure and sram cell |
Country Status (4)
Country | Link |
---|---|
JP (1) | JP2008508715A (en) |
KR (1) | KR101125825B1 (en) |
GB (1) | GB2431774B (en) |
WO (1) | WO2006022915A1 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102008045037B4 (en) * | 2008-08-29 | 2010-12-30 | Advanced Micro Devices, Inc., Sunnyvale | Static RAM cell structure and multiple contact scheme for connecting dual-channel transistors |
FR2958779B1 (en) * | 2010-04-07 | 2015-07-17 | Centre Nat Rech Scient | MEMORY POINT RAM HAS A TRANSISTOR |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4021835A (en) * | 1974-01-25 | 1977-05-03 | Hitachi, Ltd. | Semiconductor device and a method for fabricating the same |
US4145233A (en) * | 1978-05-26 | 1979-03-20 | Ncr Corporation | Method for making narrow channel FET by masking and ion-implantation |
US4276095A (en) * | 1977-08-31 | 1981-06-30 | International Business Machines Corporation | Method of making a MOSFET device with reduced sensitivity of threshold voltage to source to substrate voltage variations |
US4350991A (en) * | 1978-01-06 | 1982-09-21 | International Business Machines Corp. | Narrow channel length MOS field effect transistor with field protection region for reduced source-to-substrate capacitance |
US4819043A (en) * | 1985-11-29 | 1989-04-04 | Hitachi, Ltd. | MOSFET with reduced short channel effect |
US5672536A (en) * | 1995-06-21 | 1997-09-30 | Micron Technology, Inc. | Method of manufacturing a novel static memory cell having a tunnel diode |
US6245607B1 (en) * | 1998-12-28 | 2001-06-12 | Industrial Technology Research Institute | Buried channel quasi-unipolar transistor |
US20030048657A1 (en) * | 2001-08-28 | 2003-03-13 | Leonard Forbes | Four terminal memory cell, a two-transistor SRAM cell, a SRAM array, a computer system, a process for forming a SRAM cell, a process for turning a SRAM cell off, a process for writing a SRAM cell and a process for reading data from a SRAM cell |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6019152B2 (en) * | 1977-08-31 | 1985-05-14 | インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン | field effect transistor |
US6282137B1 (en) * | 1999-09-14 | 2001-08-28 | Agere Systems Guardian Corp. | SRAM method and apparatus |
-
2005
- 2005-04-29 JP JP2007523549A patent/JP2008508715A/en active Pending
- 2005-04-29 GB GB0702553A patent/GB2431774B/en active Active
- 2005-04-29 WO PCT/US2005/015294 patent/WO2006022915A1/en active Application Filing
- 2005-04-29 KR KR1020077002765A patent/KR101125825B1/en active IP Right Grant
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4021835A (en) * | 1974-01-25 | 1977-05-03 | Hitachi, Ltd. | Semiconductor device and a method for fabricating the same |
US4276095A (en) * | 1977-08-31 | 1981-06-30 | International Business Machines Corporation | Method of making a MOSFET device with reduced sensitivity of threshold voltage to source to substrate voltage variations |
US4350991A (en) * | 1978-01-06 | 1982-09-21 | International Business Machines Corp. | Narrow channel length MOS field effect transistor with field protection region for reduced source-to-substrate capacitance |
US4145233A (en) * | 1978-05-26 | 1979-03-20 | Ncr Corporation | Method for making narrow channel FET by masking and ion-implantation |
US4819043A (en) * | 1985-11-29 | 1989-04-04 | Hitachi, Ltd. | MOSFET with reduced short channel effect |
US5672536A (en) * | 1995-06-21 | 1997-09-30 | Micron Technology, Inc. | Method of manufacturing a novel static memory cell having a tunnel diode |
US6245607B1 (en) * | 1998-12-28 | 2001-06-12 | Industrial Technology Research Institute | Buried channel quasi-unipolar transistor |
US20030048657A1 (en) * | 2001-08-28 | 2003-03-13 | Leonard Forbes | Four terminal memory cell, a two-transistor SRAM cell, a SRAM array, a computer system, a process for forming a SRAM cell, a process for turning a SRAM cell off, a process for writing a SRAM cell and a process for reading data from a SRAM cell |
Also Published As
Publication number | Publication date |
---|---|
KR101125825B1 (en) | 2012-03-27 |
KR20070046840A (en) | 2007-05-03 |
GB0702553D0 (en) | 2007-03-21 |
JP2008508715A (en) | 2008-03-21 |
GB2431774B (en) | 2009-04-01 |
GB2431774A (en) | 2007-05-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7442971B2 (en) | Self-biasing transistor structure and an SRAM cell having less than six transistors | |
US7880239B2 (en) | Body controlled double channel transistor and circuits comprising the same | |
US6421269B1 (en) | Low-leakage MOS planar capacitors for use within DRAM storage cells | |
US7257043B2 (en) | Isolation device over field in a memory device | |
US7209384B1 (en) | Planar capacitor memory cell and its applications | |
US8164145B2 (en) | Three-dimensional transistor with double channel configuration | |
US10176859B2 (en) | Non-volatile transistor element including a buried ferroelectric material based storage mechanism | |
US20090310431A1 (en) | Semiconductor device including capacitorless ram | |
KR101689409B1 (en) | Low power memory device with jfet device structures | |
US9178062B2 (en) | MOS transistor, fabrication method thereof, and SRAM memory cell circuit | |
WO2004001801A2 (en) | Insulated-gate semiconductor device and approach involving junction-induced intermediate region | |
US20080084731A1 (en) | DRAM devices including fin transistors and methods of operating the DRAM devices | |
KR20110094213A (en) | Jfet device structures and methods for fabricating the same | |
James et al. | Dopingless 1T DRAM: Proposal, design, and analysis | |
US20070176246A1 (en) | SRAM cells including self-stabilizing transistor structures | |
KR20110044331A (en) | Drive current adjustment for transistors formed in the same active region by locally providing embedded strain inducing semiconductor material in the active region | |
WO2006022915A1 (en) | Self-biasing transistor structure and sram cell | |
US8525248B2 (en) | Memory cell comprising a floating body, a channel region, and a diode | |
KR101804197B1 (en) | Ram memory cell comprising a transistor | |
WO2023212887A1 (en) | Memory peripheral circuit having recessed channel transistors with elevated sources/drains and method for forming thereof | |
Wang et al. | Access Transistor Design and Optimization for 65/45nm High Performance SOI eDRAM |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KM KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SM SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LT LU MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
DPE1 | Request for preliminary examination filed after expiration of 19th month from priority date (pct application filed from 20040101) | ||
WWE | Wipo information: entry into national phase |
Ref document number: 200580025910.4 Country of ref document: CN Ref document number: 2007523549 Country of ref document: JP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1020077002765 Country of ref document: KR |
|
ENP | Entry into the national phase |
Ref document number: 0702553 Country of ref document: GB Kind code of ref document: A Free format text: PCT FILING DATE = 20050429 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 0702553.9 Country of ref document: GB |
|
122 | Ep: pct application non-entry in european phase |