Nothing Special   »   [go: up one dir, main page]

WO2006091826A3 - Low noise divider - Google Patents

Low noise divider Download PDF

Info

Publication number
WO2006091826A3
WO2006091826A3 PCT/US2006/006619 US2006006619W WO2006091826A3 WO 2006091826 A3 WO2006091826 A3 WO 2006091826A3 US 2006006619 W US2006006619 W US 2006006619W WO 2006091826 A3 WO2006091826 A3 WO 2006091826A3
Authority
WO
WIPO (PCT)
Prior art keywords
transition
phase
clock
determines
true
Prior art date
Application number
PCT/US2006/006619
Other languages
French (fr)
Other versions
WO2006091826A2 (en
Inventor
John Wood
Original Assignee
Multigig Inc
John Wood
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Multigig Inc, John Wood filed Critical Multigig Inc
Priority to EP06736045A priority Critical patent/EP1856804A4/en
Publication of WO2006091826A2 publication Critical patent/WO2006091826A2/en
Publication of WO2006091826A3 publication Critical patent/WO2006091826A3/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/18—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising distributed inductance and capacitance
    • H03B5/1841—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising distributed inductance and capacitance the frequency-determining element being a strip line resonator
    • H03B5/1847—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising distributed inductance and capacitance the frequency-determining element being a strip line resonator the active element in the amplifier being a semiconductor device
    • H03B5/1852—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising distributed inductance and capacitance the frequency-determining element being a strip line resonator the active element in the amplifier being a semiconductor device the semiconductor device being a field-effect device

Landscapes

  • Manipulation Of Pulses (AREA)

Abstract

A system and method for dividing a clock in a way that achieves low phase noise. In one embodiment, a multi-phase oscillator (20) such as a rotary traveling wave oscillator operates a state machine (26) which determines times at which a transition coupled phase signal of the multi-phase oscillator should be suppressed. Suppression of the transition is performed by a transition structure that holds the phase signal at a high or low so that the transition does not occur at the output. Fewer transitions in the ph signal create a divided clock. In another embodiment, a decoder (24) determines times for suppressing transitions in a true and complement clock and a polarity flip-flop determines the correct polarity for suppressing edges on both clocks. In yet another embodiment, a multiplexer is used to selectively pass either a true or complement clock to an output load.
PCT/US2006/006619 2005-02-23 2006-02-23 Low noise divider WO2006091826A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP06736045A EP1856804A4 (en) 2005-02-23 2006-02-23 Low noise divider

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US65606505P 2005-02-23 2005-02-23
US60/656,065 2005-02-23

Publications (2)

Publication Number Publication Date
WO2006091826A2 WO2006091826A2 (en) 2006-08-31
WO2006091826A3 true WO2006091826A3 (en) 2006-12-21

Family

ID=36928048

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/006619 WO2006091826A2 (en) 2005-02-23 2006-02-23 Low noise divider

Country Status (3)

Country Link
EP (1) EP1856804A4 (en)
CN (1) CN101199120A (en)
WO (1) WO2006091826A2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8742857B2 (en) * 2008-05-15 2014-06-03 Analog Devices, Inc. Inductance enhanced rotary traveling wave oscillator circuit and method
US8487710B2 (en) * 2011-12-12 2013-07-16 Analog Devices, Inc. RTWO-based pulse width modulator
US10303200B2 (en) * 2017-02-24 2019-05-28 Advanced Micro Devices, Inc. Clock divider device and methods thereof
US11264949B2 (en) 2020-06-10 2022-03-01 Analog Devices International Unlimited Company Apparatus and methods for rotary traveling wave oscillators

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6114914A (en) * 1999-05-19 2000-09-05 Cypress Semiconductor Corp. Fractional synthesis scheme for generating periodic signals

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2666706B1 (en) * 1990-09-12 1993-08-06 Sgs Thomson Microelectronics FAST COUNTER / DIVIDER AND APPLICATION TO A SWALLOW COUNTER.

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6114914A (en) * 1999-05-19 2000-09-05 Cypress Semiconductor Corp. Fractional synthesis scheme for generating periodic signals

Also Published As

Publication number Publication date
WO2006091826A2 (en) 2006-08-31
EP1856804A4 (en) 2008-10-15
CN101199120A (en) 2008-06-11
EP1856804A2 (en) 2007-11-21

Similar Documents

Publication Publication Date Title
US7576584B2 (en) Clock generators for generation of in-phase and quadrature clock signals
GB0724002D0 (en) Noise tolerant voltage controlled oscillator
WO2006067716A3 (en) Interface circuit as well as method for receiving and/or for decoding data signals
TW200610277A (en) Circuits and methods for recovering a clock signal
WO2006119171A3 (en) Digital frequency synthesizer
TW200518469A (en) Delay locked loop and its control method
TW200515710A (en) Delay locked loop and its control method
DE60134835D1 (en) Method and circuit arrangement for data transmission between pseudo-synchronized channels
TWI340546B (en) A glitch-free clock signal multiplexer circuit and method of operation
EP1903712A3 (en) Signal interleaving for serial clock and data recovery
WO2006091826A3 (en) Low noise divider
WO2003032137A3 (en) Deskewing global clock skew using localized adjustable delay circuits
CA2874459C (en) Differential clock signal generator
WO2006044111A3 (en) Circuit and method for interpolative delay
US8558589B2 (en) Fully digital method for generating sub clock division and clock waves
WO2004073175A3 (en) Adaptive input logic for phase adjustments
TW200620833A (en) Local oscillator and mixer for a transceiver
GB2330966A (en) Phase detection apparatus and method
CN108540128B (en) Clock frequency dividing circuit and frequency dividing method thereof
US9647824B2 (en) System and apparatus for clock retiming with catch-up mode and associated methods
US20130335125A1 (en) Input signal processing device
CN101989857B (en) Device for generating clock in semiconductor integrated circuit
TW200510987A (en) Method and related apparatus for outputting clock through data path
US8928369B1 (en) Low power local oscillator quadrature generator
WO2004068706A3 (en) Programmable dual-edge triggered counter

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 200680005606.8

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application
DPE1 Request for preliminary examination filed after expiration of 19th month from priority date (pct application filed from 20040101)
WWE Wipo information: entry into national phase

Ref document number: 1280/MUMNP/2007

Country of ref document: IN

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 2006736045

Country of ref document: EP

DPE1 Request for preliminary examination filed after expiration of 19th month from priority date (pct application filed from 20040101)