WO2005020419A1 - 電力変換器の制御装置 - Google Patents
電力変換器の制御装置 Download PDFInfo
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- WO2005020419A1 WO2005020419A1 PCT/JP2003/010711 JP0310711W WO2005020419A1 WO 2005020419 A1 WO2005020419 A1 WO 2005020419A1 JP 0310711 W JP0310711 W JP 0310711W WO 2005020419 A1 WO2005020419 A1 WO 2005020419A1
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- 238000000034 method Methods 0.000 description 29
- 238000010586 diagram Methods 0.000 description 27
- 230000008859 change Effects 0.000 description 23
- 230000001629 suppression Effects 0.000 description 18
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
- H02M7/42—Conversion of DC power input into AC power output without possibility of reversal
- H02M7/44—Conversion of DC power input into AC power output without possibility of reversal by static converters
- H02M7/48—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/5387—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
- H02M7/53871—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
- H02M7/53873—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current with digital control
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
- H02M7/42—Conversion of DC power input into AC power output without possibility of reversal
- H02M7/44—Conversion of DC power input into AC power output without possibility of reversal by static converters
- H02M7/48—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/5387—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
- H02M7/53871—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
- H02M7/53875—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current with analogue control of three-phase output
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
- H02M7/42—Conversion of DC power input into AC power output without possibility of reversal
- H02M7/44—Conversion of DC power input into AC power output without possibility of reversal by static converters
- H02M7/48—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/5387—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
- H02M7/53871—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
- H02M7/53875—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current with analogue control of three-phase output
- H02M7/53876—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current with analogue control of three-phase output based on synthesising a desired voltage vector via the selection of appropriate fundamental voltage vectors, and corresponding dwelling times
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P21/00—Arrangements or methods for the control of electric machines by vector control, e.g. by control of field orientation
Definitions
- the present invention relates to a control device for a power converter driven by PWM (pulse width modulation) control, and particularly to an abnormally high voltage generated at a cable connection end of a load when a connection cable between the power converter and the load becomes long. It relates to a control device that suppresses voltage (hereinafter referred to as “surge voltage”).
- surge voltage suppresses voltage
- FIG. 1 is a diagram illustrating a connection cable between an inverter, which is a power converter driven by PWM control, and a motor.
- a motor 2 is connected to an inverter 1 as a power converter via a connection cable 3.
- the inverter 1 controls the switching operation of the constituent semiconductor switch elements (for example, IGBT elements) by PWM control by a control device (not shown), and generates a three-phase voltage (uvw) that changes stepwise from a DC power supply of a voltage Vdc. Generate and output to motor 2 via connection cable 3.
- connection cable 3 when the connection cable 3 between the inverter 1 and the motor 2 becomes long, a surge voltage exceeding twice the DC bus voltage V dc may be generated at the cable connection end of the motor 2.
- the connection cable 3 can be considered as a resonance circuit composed of the wiring inductance and the stray capacitance, but if the connection cape rail 3 becomes longer, both the wiring inductance and the stray capacitance increase, so that the resonance frequency of the resonance circuit increases. descend.
- FIGS. 2 and 3 are diagrams showing line voltage waveforms at both ends of the connection cable 3 shown in FIG.
- FIG. 2 (1) shows a case where the voltage VuV ⁇ inV between the impeller end lines changes stepwise from Vdc ⁇ 0 ⁇ Vdc. At this time, if the pulse width of the voltage change coincides with the resonance period of 1Z2, as shown in Fig. 2 (2), the motor end-to-end voltage VuV—m0tor is a DC The voltage becomes three times higher than the bus voltage Vdc.
- FIG. 3 (1) shows a case where the inverter end-to-end line voltage VuV—inV force changes from 0 ⁇ Vdc ⁇ —Vdc ⁇ 0.
- the motor end-to-end line voltage VuV-motor becomes a high voltage that is at most four times the DC bus voltage Vdc.
- Patent Documents 1 and 2 In order to solve the problem of the surge voltage, for example, in Patent Documents 1 and 2, the firing pulse width of each IGBT element, which is the basis of the line voltage pulse width of the inverter, is monitored, and the maximum firing pulse width is monitored. A technique is disclosed in which the value is limited to a certain value or less, and the minimum value of the firing pulse width is limited to a certain value or more.
- Patent Document 1 U.S. Pat. No. 5,716,130 publication
- Patent Document 2 U.S. Pat. No. 5,990,658 publication.
- Patent Documents 3 and 4 each phase voltage command value input to a PWM controller that generates a firing pulse for each IGBT element is monitored, and the maximum value of each phase voltage command value is kept constant.
- a technique is disclosed in which the minimum value of each phase voltage command value is limited to a certain value or more by limiting the value to a value equal to or less than the value.
- Patent Document 3 U.S. Pat. No. 5,912,813,
- Patent Document 4 U.S. Pat. No. 6,144,977.
- the present invention has been made in view of the above, and has an object to obtain a power converter control device capable of treating all phases collectively and optimally suppressing a surge voltage exceeding twice the DC bus voltage. With the goal. Disclosure of the invention
- a voltage vector output by the power converter within one control cycle of the pulse width modulation control and the voltage vector Voltage vector control means for determining the output time of the voltage vector based on the voltage command value for the power conversion, and voltage vector adjustment means for adjusting the output time of the voltage vector input from the voltage vector control means
- a voltage vector adjusting means for adjusting the zero voltage vector output time to be equal to or more than a predetermined value, and the voltage vector output time adjusted by the voltage vector adjusting means.
- a firing pulse generating means for generating a signal for turning on and off the semiconductor switch element constituting the power converter.
- the zero voltage vector output time is always constant ⁇ ! : Since the above is ensured, it is possible to attenuate the resonance phenomenon accompanying the switching of the semiconductor switch element during the output of the zero voltage vector, and to effectively suppress the surge voltage which is higher than twice the DC bus voltage. Can be.
- the following invention relates to a control device for a power converter in which an output voltage is controlled by pulse width modulation control, wherein a voltage vector output by the power converter within one control cycle of the pulse width modulation control and a voltage vector thereof are provided.
- Voltage vector control means for determining the time for outputting the vector based on the voltage command value for the power conversion, and voltage vector adjustment for adjusting the output time of the voltage vector input from the voltage vector control means.
- Voltage vector adjusting means for setting the time to zero; and a semiconductor switch element constituting the power converter based on the output time of the voltage vector adjusted by the voltage vector adjusting means. Characterized in that a firing pulse generating means that generates a signal off. ⁇
- a force for providing a zero-voltage vector output time equal to or more than a certain value is selected by rounding off whether the zero-voltage vector output time is zero. Can be suppressed.
- the next invention is a control device for a power converter in which an output voltage is controlled by pulse width modulation control, wherein a voltage vector output by the power converter in two or more control cycles of the pulse width modulation control is provided.
- Voltage vector control means for determining the voltage and the time for outputting the voltage vector based on the voltage command value for the power conversion, and the pulse width modulation control input from the voltage vector control means.
- a voltage vector adjusting means for adjusting an output time of a voltage vector in the plurality of control cycles, wherein a total of output times of all zero voltage vectors in the two or more control cycles is a predetermined value. If it is shorter, the output voltage of the zero-voltage vector in the middle of two adjacent cycles is set to zero, and the voltage is adjusted so that the output time is distributed to the output time of the zero-voltage vector at both ends of the two cycles.
- Bek Torque adjusting means, and ignition pulse generating means for generating a signal for turning on and off the semiconductor switch element constituting the power conversion based on the output time of the voltage vector adjusted by the voltage vector adjusting means. It is characterized by having.
- the present invention when two or more control cycles of pulse width modulation control are set as a control target as one unit, the remaining zero voltage vector in the middle of two adjacent cycles is eliminated, and the remaining The output time of the zero voltage vector can be doubled.
- the force for providing a zero-voltage vector output time that is equal to or more than a certain value ⁇ the zero-voltage vector output time is set to zero or a deviation, so the DC bus voltage is the same as in the above invention. It is possible to suppress surge voltage, which is a high voltage that is more than twice as large.
- the next invention is a control device for a power converter in which an output voltage is controlled by pulse width modulation control, wherein a voltage vector output by the power converter in two or more control cycles of the pulse width modulation control is provided.
- Voltage vector control means for determining the time and the time for outputting the voltage vector based on the voltage command value to the power converter; and the pulse width modulation control input from the voltage vector control means.
- Voltage vector adjusting means for adjusting an output time of a voltage vector in a plurality of control cycles, wherein a total of output times of all zero voltage vectors in said two or more control cycles is greater than a predetermined value.
- the voltage vector adjusting means for adjusting the output time of the same voltage vector in the two or more control cycles so as to be integrated into one, and the voltage vector adjusting means adjusts the output time.
- Sa On the semiconductor Suitsuchi elements constituting the power variable i was based on the output time of the voltage base vector, and wherein the obtaining Bei a firing pulse generating means that generates a signal off.
- the output time of the same voltage vector within the two or more control cycles is reduced by one.
- the output time of each voltage vector including the zero voltage vector can be doubled.
- a zero-voltage vector output time that is always equal to or greater than a certain value is always ensured, so that a surge voltage that is a high voltage exceeding twice the DC bus voltage can be suppressed as in the above invention.
- the following invention relates to a control device for a power converter in which an output voltage is controlled by pulse width modulation control, wherein a voltage vector output by the power converter within one control cycle of the pulse width modulation control and a voltage vector thereof are provided.
- Voltage vector control means for determining a time for outputting a vector based on a voltage command value to the power converter, and voltage vector adjustment for adjusting an output time of the voltage vector inputted from the voltage vector control means.
- the vector output at the end of the previous cycle receives the voltage vector used in the adjustment one control cycle before, and the zero-vector Voltage vector adjustment means for adjusting one output time of both zero voltage vectors in the present cycle to zero according to whether the current time is equal to or not and distributing the output time to the other output time;
- a delay unit that delays the voltage vector output by the voltage vector adjustment unit by the one control cycle and outputs the voltage vector to the voltage vector adjustment unit; and a delay unit that outputs the voltage vector adjusted by the voltage vector adjustment unit.
- a firing pulse generating means for generating a signal for turning on and off the semiconductor switch element constituting the power converter based on the signal.
- the output time of the zero voltage vector is doubled. be able to.
- either the force for providing a zero-voltage vector output time equal to or more than a certain value or the zero-voltage vector output time is zero, so that the DC bus voltage It is possible to suppress a surge voltage which is a high voltage more than twice.
- the next invention is a control device for a power converter in which an output voltage is controlled by pulse width modulation control, wherein the power converter outputs the power within one control cycle of the pulse width modulation control.
- Voltage vector control means for determining a voltage vector to be changed and a time for outputting the voltage vector based on a voltage command value for the power conversion, and a voltage vector input from the voltage vector control means.
- Voltage vector adjusting means for adjusting the output time
- the output time of the zero voltage vector adjusted and output at the end of the previous cycle and the output time of the voltage vector control If the sum of the output time of the zero-voltage vector and the output time of the zero-voltage vector is shorter than the fixed value, the output time of the zero-voltage vector that is output first in this cycle is adjusted from the fixed value to Voltage vector adjustment means for adjusting the output time of the zero voltage vector obtained by subtracting the output time, and the voltage vector output by the voltage vector adjustment means and the adjusted output time are set to the one control cycle.
- Delay means for delaying the output of the voltage vector to the voltage vector adjusting means; and a semiconductor switch constituting the power converter based on the output time of the voltage vector adjusted by the voltage vector adjusting means.
- a semiconductor switch constituting the power converter based on the output time of the voltage vector adjusted by the voltage vector adjusting means.
- On the switch elements characterized in that example Bei a firing pulse generating means that generates a signal off.
- the following invention relates to a control device for a power converter in which an output voltage is controlled by pulse width modulation control, wherein a voltage vector output by the power converter within one control cycle of the pulse width modulation control and a voltage vector thereof are provided.
- Voltage vector control means for determining a time for outputting a vector based on a voltage command value to the power converter, and voltage vector adjustment for adjusting an output time of the voltage vector inputted from the voltage vector control means.
- a voltage vector adjusting means for reducing the zero voltage vector output time to zero, and an error caused by adjusting the output time of the voltage vector outputted by the voltage vector adjusting means, by delaying the control cycle by one control cycle, and A signal for turning on and off the semiconductor switch element constituting the power conversion based on a delay means for outputting to the vector adjusting means and an output time of the voltage vector adjusted by the voltage vector adjusting means.
- a firing pulse generating means for reducing the zero voltage vector output time to zero, and an error caused by adjusting the output time of the voltage vector outputted by the voltage vector adjusting means, by delaying the control cycle by one control cycle, and A signal for turning on and off the semiconductor switch element constituting the power conversion based on a delay means for outputting to the vector adjusting means and an output time of the voltage vector adjusted by the voltage vector adjusting means.
- a surge voltage which is a high voltage exceeding twice the DC bus voltage can be suppressed in the same manner as in the above invention, but this time, the adjustment error in the previous pulse width modulation control cycle is used.
- the output time of the voltage vector that is output at the cycle of is corrected to eliminate the influence of the previous adjustment, so that the end point of the current flux vector locus can be made to coincide with the desired point, and the surge voltage can be suppressed.
- the accompanying disturbance of the magnetic flux vector locus can be minimized.
- the voltage vector adjusting means sets the output time of the zero voltage vector to a constant value without changing the relative ratio of the output time of the voltage vector other than the zero voltage vector. It is characterized in that it is adjusted so as to secure the above.
- the disturbance of the magnetic flux vector locus due to the suppression of the surge voltage can be minimized by devising the voltage vector adjustment.
- the voltage vector adjusting means when the voltage vector adjusting means adjusts the output time of the zero voltage vector to zero, the output time of the voltage vector other than the zero voltage vector is also equal to or more than a predetermined value. It is characterized in that it is adjusted to be zero.
- a surge voltage may occur depending on the output time of the non-zero voltage vector other than the zero voltage vector. Since the voltage can be limited, surge voltage, which is higher than twice the DC bus voltage, can be reliably suppressed.
- the voltage vector adjusting means adjusts the output time of the zero voltage vector to zero, and sets the voltage vector output at the end of the previous cycle to the first in the current cycle. If the voltage vector that is output is different from the voltage vector that is output first, the voltage vector that is output first in this cycle is changed to the voltage vector that was output last in the previous cycle.
- a surge voltage may occur depending on the output time of the non-zero voltage vector other than the zero voltage vector. Since the voltage can be limited, surge voltage, which is higher than twice the DC bus voltage, can be reliably suppressed.
- the adjustment of the voltage vector output time is performed for the output time of the voltage vector which is a parameter common to the three phases generated based on the three-phase voltage command.
- FIG. 1 is a diagram explaining the connection cable between the inverter, which is a power converter driven by PWM control, and the motor.
- Fig. 2 shows the line voltage waveform at both ends of the connection cable shown in Fig. 1.
- FIG. 3 is a diagram (part 1)
- FIG. 3 is a diagram (line 2) showing a line voltage waveform at both ends of the connection cable shown in FIG. 1
- FIG. 4 is an embodiment of the present invention.
- FIG. 5 is a block diagram showing a configuration of a control device of the power converter which is 1;
- FIG. 5 is a basic diagram of a three-phase voltage inverter used in this embodiment as a power converter driven by PWM control;
- FIG. 6 is a circuit diagram showing the configuration.
- FIG. 6 is a diagram for explaining the relationship between the IGBT element that is turned on and the voltage vector in the eight control states of the inverter shown in FIG. 5, and FIG. FIG. 8 is a diagram for explaining a voltage vector, and FIG. 8 shows a relationship between a phase and a voltage vector.
- FIG. 9 is a flowchart illustrating the operation of the voltage vector adjustment unit shown in FIG. 4, and FIG. 10 is a trajectory of the magnetic flux vector when the voltage vector is adjusted.
- Fig. 11 Fig. 12 is a time chart for explaining the operation of the firing pulse generator shown in Fig. 4;
- Fig. 12 is a diagram for explaining the relationship between the transition of the voltage vector and the line voltage; Fig. 13 Fig.
- FIG. 14 shows the line voltage pattern extracted by focusing on the pulse polarity, zero-voltage vector output time, and vector output time other than zero voltage.
- FIG. 14 shows the line voltage pattern shown in Fig. 13.
- FIG. 15 is a flow chart for explaining an operation of a voltage vector adjusting unit provided in the control device for the power converter according to the second embodiment of the present invention.
- FIG. 6 is a block diagram showing a configuration of a power converter control device according to Embodiment 3 of the present invention.
- FIG. 17 is a flowchart for explaining the operation of the voltage vector adjusting unit shown in FIG.
- FIG. 18 shows a power converter according to the fourth embodiment of the present invention.
- FIG. 19 is a flowchart illustrating the operation of a voltage vector adjustment unit included in the control device of FIG. 19;
- FIG. 19 is a flowchart illustrating the operation of a voltage vector adjustment unit included in the control device of FIG. 19; FIG.
- FIG. 20 is a flowchart for explaining the operation of the voltage vector adjusting unit shown in FIG. 19, and FIG. 21 is a voltage vector included in the control device of the power converter according to the sixth embodiment of the present invention.
- FIG. 22 is a flowchart for explaining the operation of the adjustment unit.
- FIG. 22 is a block diagram showing the configuration of the control device of the power converter according to the seventh embodiment of the present invention.
- FIG. 23 is a block diagram of FIG.
- FIG. 24 is a flowchart for explaining the operation of the voltage vector adjustment unit shown in FIG. 24.
- FIG. 24 is a diagram for explaining the operation of error calculation performed by the voltage vector adjustment unit shown in FIG. 22.
- Embodiment 8 A power conversion control apparatus according to Embodiment 8 of the present invention A flow chart for explaining the operation of the voltage base vector adjustment part comprises, second 6 Figure the embodiment of the present invention
- FIG. 9 is a flowchart illustrating the operation of a voltage vector adjuster included in the power converter control device of No. 9.
- FIG. 4 is a block diagram showing a configuration of a control device for a power converter according to Embodiment 1 of the present invention.
- the control device shown in FIG. 4 includes a voltage vector control unit 11, a voltage vector adjustment unit 12, and a firing pulse generation unit 13.
- the voltage vector control unit 11 selects a voltage vector that the power converter outputs within one control cycle of the PWM control from the voltage command values Vu, Vv, Vw of each phase of the power converter (in the illustrated example, V0, VI, V2, V7) and their output times (t0, tl, t2, t7) are calculated.
- the voltage vector adjustment unit 12 outputs the voltage vectors (V0, VI, V2, V7 in the illustrated example) input from the voltage vector control unit 11 as they are, and outputs the output time of the voltage vector (t 0, tl, t2, t7) are adjusted and output so that the zero-voltage vector output time is a fixed value or more (t0 ', tl', t2 ', t7').
- the firing pulse generator 13 is configured to configure each power converter based on the voltage vector input from the voltage vector adjuster 12 and the output time of the voltage vector adjusted by the voltage vector adjuster 12. Generates ON / OFF signals “PQ1, PQ2, PQ3, PQ4, PQ5, PQ6, PQ7” of the semiconductor switch element.
- FIG. 5 is a circuit diagram showing a basic configuration of a three-phase voltage-type inverter used in this embodiment as a power converter driven by PWM control.
- FIG. 6 is a diagram for explaining the relationship between the IGBT element that is turned on and the voltage vector in the eight control states of the inverter shown in FIG.
- FIG. 7 is a diagram illustrating a voltage vector.
- FIG. 8 is a diagram for explaining a relationship between a phase and a voltage vector.
- the three-phase voltage-source inverter has three sets of semiconductor switch elements (Qi, Q4) and (Q3, Q6) (Q5, Q2) connected in series connected to the DC power supply 15 in parallel. It is the structure connected to.
- Each semiconductor switch element has a built-in or mounted flywheel diode.
- Each semiconductor switch element is, for example, an IGBT element, and is hereinafter referred to as an IGBT element.
- the IGBT elements (Q 1, Q4) is the u-phase
- the IGBT elements (Q3, Q6) are the v-phase
- the IGBT elements (Q5, Q2) are the W-phase.
- the three-phase voltage UVW is extracted from each connection terminal.
- the on / off control state of the IGBT element is determined in each phase by the force at which the upper arm IGBT element (Q1, Q3, Q5) connected to the positive side of the DC power supply 115 turns on, and the state connected to the negative side.
- There are two states of whether the lower arm IGBT element (Q4, Q6, Q2) is turned on, and there are 2 X 2 X 2 8 states in three phases.
- Fig. 6 shows the relationship between these eight states, the ON state of the IGBT element, and the voltage vector output by the three-phase voltage inverter.
- the voltage vector V0 is the vector when the IGBT elements (Q4, Q6, Q2) are on.
- the voltage vector V1 is a vector when the IGBT elements (Q1, Q6, Q2) are on.
- the voltage vector V2 is the vector when the IGBT elements (Q1, Q3, Q2) are on.
- Voltage vector V3 is the vector when the IGBT elements (Q4, Q3, Q2) are on.
- Voltage vector V4 is a vector when the IGBT elements (Q4, Q3, Q5) are on.
- the voltage vector V5 is the vector when the IGBT elements (Q4, Q6, Q5) are on.
- the voltage vector V6 is the vector when the IGBT elements (Q1, Q6, Q5) are on.
- the voltage vector V7 is the vector when the IGBT elements (Q1, Q3, Q5) are on.
- voltage vectors V1 to V6 are vectors having a phase difference every ⁇ / 3 [rad] and having the same magnitude as voltage Vdc of DC power supply 15.
- the voltage vectors V0 and V7 are zero-sized vectors, and are called zero-voltage vectors.
- the phase of voltage vector VI matches the u phase
- the phase of voltage vector V 3 matches the V phase
- the phase of voltage vector V 5 matches the w phase.
- the three-phase voltage type impeller can output a voltage of any size and phase on average by changing the combination type and output time of the voltage vectors V0 to V7 output during the PWM control cycle T. is there.
- the voltage vector control unit 11 T each phase voltage command Vu for performing a combination selection of the type of vector V0 ⁇ V7 and the determination of the output time, Vv, Vw is to be given by equation (1) (
- phase ⁇ ⁇ ⁇ ⁇ in this equation (1) increases with time, but can be considered constant during the short PWM control cycle ⁇ .
- the range of phase 0 is 0 ⁇ ⁇ ⁇ ⁇ 3, ⁇ / 3 ⁇ ⁇ ⁇ 2 ⁇ / 3, 2 ⁇ / 3 ⁇ ⁇ ⁇ , ⁇ ⁇ ⁇ 4 ⁇ / 3, 4 ⁇ / 3 ⁇ ⁇ 5 ⁇ / 3 and 5 ⁇ / 3 ⁇ ⁇ 2 ⁇ .
- the number of voltage vectors to select is four out of eight, but the combination is different for each range of phase ⁇ . However, zero voltage vector t0, t7 is included in all combinations.
- the selected combination of voltage vectors is VI, V2, VO, and V7.
- the times t1, t2, t0, and t7 for outputting the selected voltage vectors VI, V2, V0, and V7 are given by Equation (2), respectively.
- the time to output the selected voltage vector is expressed by the remainder obtained by dividing 0 by ⁇ / 3 instead of ⁇ ⁇ ⁇ ⁇ in equation (2). Required by using.
- FIG. 9 is a flowchart illustrating the operation of the voltage vector adjusting unit shown in FIG.
- FIG. 10 is a diagram for explaining the trajectory of the magnetic flux vector when the voltage vector is adjusted.
- step ST10 the voltage vector adjustment unit 12 will adjust the voltage vector output by the voltage vector control unit 11
- the output times tl, t2, t0, and t7 are read (step ST10), and whether the total output time t0 + t7 of the zero-voltage vector is longer than the minimum zero-voltage vector output time Tz or not. Is determined (step ST11).
- step ST11 Yes
- the read output times tl, t The output times 1 ′, t 2 t 0 ′, and t 7 ′ are obtained by adjusting 2, t 0 and t 7 as they are (step ST 12).
- step ST14 the output time t O ,, t 1 t 2 ', t 7' of the voltage vector VO, VI, V2, V7 adjusted in step ST12 or ST13 is output to the firing pulse generator 13. Yes (step ST14).
- the voltage vectors V0, VI, V2, and V7 selected by the voltage vector control unit 11 are used as they are and output to the firing pulse generation unit 13.
- FIG. 10 is obtained by drawing the vector trajectory of the magnetic flux obtained by integrating the voltage.
- Figure 10 (1) shows the trajectory A of the magnetic flux vector for one PWM control cycle before the adjustment of the voltage vector.
- Figure 10 (2) shows the track A 'of the magnetic flux vector after the adjustment of the voltage vector.
- the trajectory A of the previous magnetic flux vector has become the trajectory A 'as a result of securing the minimum zero-voltage vector output time, and the trajectory has become shorter.
- Fig. 10 (3) shows (1) and (2) in Fig. 10 in an overlapping manner.
- the magnetic flux vectors ⁇ 0 and ⁇ 7 are the magnetic flux vectors corresponding to the zero-voltage vectors VO and V7, respectively. Since the zero-voltage vectors V0 and V7 have no magnitude, the magnetic flux vectors ⁇ 0 and ⁇ 7 remain at one point over time.
- the magnetic flux vector ⁇ 1 is a magnetic flux vector corresponding to the voltage vector V 1.
- the magnitude of the magnetic flux vector ⁇ 1 is the product of the magnitude of the voltage vector V 1 and the output time.
- the magnetic flux vector ⁇ 2 is a magnetic flux vector corresponding to the voltage vector V2.
- the magnitude of the magnetic flux vector ⁇ 2 is the product of the magnitude of the voltage vector V 2 and the output time.
- the flux vectors ⁇ 1 and ⁇ 2 have a phase difference of ⁇ / 3 [rad], similar to the voltage vectors VI and V2.
- the trajectories A, A, of the magnetic flux vector are in the order of ⁇ 0 ⁇ ⁇ 1 ⁇ ⁇ 2 ⁇ ⁇ 7.
- the magnetic flux vector corresponds to the stator magnetic flux, so the locus ⁇ ⁇ of the magnetic flux vector before the voltage vector is adjusted by the voltage vector adjustment unit 12 changes smoothly along an arc.
- the type and output time of the voltage vector are selected, and it is required that the trajectory A 'of the magnetic flux vector transition smoothly along the arc even after the voltage vector is adjusted by the voltage vector adjustment unit 12.
- the locus A of the magnetic flux vector before adjustment (Fig. 10) (1)) changes to locus A '(Fig. 10 (2)) after the adjustment, but as shown in Fig. 5 (3), connects the start point and end point of the locus A' in the PWM control cycle T.
- the triangle is similar to the triangle connecting the start and end points of trajectory A. Therefore, in a state where the period T is sufficiently short and the arc can be regarded as a straight line, the end point of the trajectory A 'also exists on the arc like the trajectory A. Therefore, if the voltage vector is adjusted so as not to change the relative ratio of the output times of the voltage vectors VI and V2, the trajectory A 'of the adjusted magnetic flux vector can also smoothly change along the arc. it can.
- FIG. 11 is a time chart for explaining the operation of the firing pulse generator shown in FIG.
- the firing pulse generator 13 includes voltage vectors VI, V2, VO, and V7 output from the voltage vector adjuster 12 and output times tl, t2 ', tO', of the adjusted voltage vector. Based on t 7 ′, the on / off signals PQ 1 to PQ 6 of each IGBT element are generated. That is, the relationship between the voltage vector and the IGBT element to be turned on is shown in FIG. As shown in Fig.
- FIG. 12 is a diagram for explaining the relationship between the transition of the voltage vector and the line voltage.
- FIG. 13 is a diagram showing a line voltage pattern extracted by focusing on the pulse polarity, the zero-voltage vector output time, and the vector output time other than the zero voltage.
- Fig. 12 shows the transition of the four types of voltage vectors shown in (1) to (4) above together with the line voltage waveform. From FIG. 12, it can be understood that the pulse of the line voltage changes in the same polarity across the zero-voltage vector, and changes in the opposite polarity across the zero-voltage vector.
- Fig. 13 shows the line voltage pattern extracted from Fig. 12 by focusing on the pulse polarity, the output time of the zero voltage vector, and the output time of the voltage vector other than the zero voltage vector. ing. Figure 13 shows that the combination of the length of the output time of the zero-voltage vector and the length of the output time of the voltage vectors other than the zero-voltage vector has the same polarity across the zero-voltage vector.
- FIG. 14 shows the magnitude of the surge voltage generated in each of the line voltage changes shown in FIG.
- FIG. 14 shows the magnitude of the surge voltage generated in each of the line voltage changes shown in FIG.
- the two zero-voltage vector if the sum of the two zero-voltage vector output times is shorter than the minimum zero-voltage vector output time, the two zero-voltage vector The four voltage vector output times are adjusted so that the total of the two zero voltage vector output times is equal to the minimum zero voltage vector output time without changing the relative ratio of the output time. .
- the first embodiment it is possible to always obtain a zero-voltage vector output time that is equal to or greater than a certain value, so that the resonance phenomenon accompanying the switching of the IGBT element can be attenuated during the zero-voltage vector output. It is possible to effectively suppress a surge voltage exceeding twice the DC bus voltage Vdc.
- the adjustment of the output time of the voltage vector covers the output time of the voltage vector, which is a parameter common to the three phases, generated based on the three-phase voltage command.
- the effect of suppressing the voltage can be obtained.
- FIG. 15 is a flowchart illustrating an operation of a voltage vector adjusting unit included in the power converter control device according to Embodiment 2 of the present invention.
- the voltage vector adjustment unit 12 according to Embodiment 2 adjusts the output time of the voltage vector output by the voltage vector control unit 11 according to the procedure shown in Fig. 15, and secures the zero voltage vector output time exceeding a certain value.
- the adjustment operation is performed both when the adjustment is made and when it is set to zero.
- the operation of the voltage vector adjustment unit 12 according to the second embodiment will be described with reference to FIG. Note that, in FIG. 15, the same reference numerals are given to the processing procedures that are the same as the processing procedures shown in FIG. Here, a description will be given focusing on a portion related to the second embodiment.
- step ST11 if the total output time t0 + t7 of the zero-voltage vector is shorter than the minimum zero-voltage vector output time Tz (step ST11: No), this embodiment 2 Then, it is further determined whether or not the total output time t 0 + t 7 of the zero voltage vector is longer than 1/2 of the minimum zero voltage vector output time Tz (step ST 20).
- step ST14 the output times t0 ', tl', t2 'of the voltage vectors V0, VI, V2, V7 adjusted in any of steps ST12, ST13, and step ST21. , t 7 ′ to the firing pulse generator 13.
- the voltage vectors V 0, VI, V 2, and V 7 selected by the voltage vector control unit 11 are used as they are and output to the ignition pulse generation unit 13 as in the first embodiment.
- the total value of the output time of the zero voltage vector is set to the minimum zero voltage vector output time Tz at / 2, or is set to zero. Therefore, in the second embodiment, the concept of rounding can be applied, and even if the voltage vector is adjusted, the average error of the zero-voltage vector output time can be reduced.
- the power for providing the zero voltage vector output time that is equal to or greater than a certain value is selected by rounding off whether the zero voltage vector output time is set to zero. Surge voltage more than twice Vdc can be suppressed.
- the voltage vector output time is adjusted for the output time of the voltage vector, which is a parameter common to three phases generated based on the three-phase voltage command, the surge voltage can be adjusted for all phases with one adjustment. Can be obtained.
- the boundary between whether the total output time of the zero-voltage vector, t0 + t7, is the minimum zero-voltage vector output time, Tz, and the force, zero is Tz / 2.
- Tz / 2 the boundary between whether the total output time of the zero-voltage vector, t0 + t7, is the minimum zero-voltage vector output time, Tz, and the force, zero, is Tz / 2.
- the boundary is set to zero and the total value of the output time of the zero voltage vector is set to the minimum zero voltage. This can be considered as an example of rounding up to the vector output time Tz.
- FIG. 16 is a block diagram showing a configuration of a power converter control device according to Embodiment 3 of the present invention.
- the components are the same as those in the first embodiment, but an example of a configuration in which control is performed with one PWM control cycle, for example, two control cycles as one unit.
- the concept of the control phase ⁇ ⁇ ⁇ ⁇ in each cycle is the same as in the first embodiment, and here, the range of 0 ⁇ 0 ⁇ 3 is considered.
- the voltage vector control unit 21 uses the method described in the first embodiment to perform the PWM control based on the voltage command values Vu, Vv, and Vw of each phase of the power converter.
- the voltage vector to be output in the control cycle is selected ((V0-1, Vl_l, V2_l, V7_l) (V0_2, V1-2, V2-2, V7_2) in the example shown), and the output time (t0 1, tl— 1, t 2_1, t 7_1) (t 0_2, t 1— 2, t 2_2, t 7-1 2)
- the voltage vector adjustment unit 22 converts the voltage vector input from the voltage vector control unit 21 ((V0-1, VI-1, V2-1, V7-1) in the method described later (FIG. 17). ) (V0_2, VI—2, V2_2, V7_2)) and output time of the voltage vector (t 0—1, tl—1, t 2_1, t 7—l) (t O ⁇ 1, t 1 ⁇ 2, t 2_2, t 7_2) are adjusted and output so that the zero-voltage vector output time becomes a certain value or more (t 0 ⁇ 1 ′, tl ⁇ 1 ′, t 2_1 t 7 ⁇ 1,) ( tO-1 2 ', tl-2, t2_2', t7-2,).
- the firing pulse generating unit 23 outputs the voltage vector input from the voltage vector adjusting unit 22 and the output of the voltage vector adjusted by the voltage vector adjusting unit 22 in the method described in the first embodiment. Based on time, on / off signals “PQ1, PQ2, PQ3, PQ4, PQ5, PQ6, PQ7” of each semiconductor switch element constituting the power converter are generated.
- the voltage vector control unit 21 and the firing pulse generation unit 23 respectively correspond to the voltage vector control unit 11 and the firing pulse generation unit 13 in the first embodiment (FIG. 4) for two PWM control periods. Therefore, detailed description is omitted.
- FIG. 17 is a flow chart for explaining the operation of the voltage vector adjustment unit 22 shown in FIG. In FIG.
- the voltage vector adjuster 22 outputs the output time (t 0—1) of the voltage vector output from the voltage vector controller 21.
- tl—1, t2_1, t7_1) (t0_2, t1-2, t2-1-2, t7-2) are read (step ST31), and the total output time of the zero-voltage vector in each cycle is read. It is determined whether one or both of (t 0—1 + t 7—1) and (t 0—2 + t 7—2) is longer than the minimum zero-voltage vector output time T z (step ST 32). .
- the read output time t1—1, t2—1, t0—1, t7_1, t1_2, t2—2, tO—2, t7—2 are set as output times t 1—1 ′, t 2_1 t 0_1 t 7_1 ′, t 1_2 ′, t 2__ 2 ′, t 0—2 ′, and t 7 ⁇ 12 (step ST33).
- one or both of the total output time of the zero-voltage vector in each cycle (t 0 — 1 + t 7 — 1) (t 0 — 2 + t 7 — 2) is the minimum zero-voltage vector output time T If it is shorter than z (Step ST32: No), the total output time of the zero-voltage vector over two cycles (t0—1 + t7—1 + t0—2 + t7—2) Is longer than the minimum zero voltage vector output time Tz (step ST34).
- Step ST 34 Yes
- tl— 1 ' (T -T z / 2) ⁇ t (t 1-l + t 2— 1) ⁇
- t 2_1' (TT z / 2) ⁇ t 2_1 / (tl— l + t 2—1) ⁇
- t 1—2 (TT z / 2) ⁇ tl-1 2 / (tl-1 2+ t 2—2) ⁇
- t 2—2 ' (TT z / 2) ⁇ t 2_2 / (tl— 2+ t 2— 2) ⁇ .
- the voltage vector for two cycles selected by the voltage vector control unit 21 V 0-1, VI-1, V2-1, V7-1, V0-2, VI-2, V2-2, V7- 2 is used as it is and output to the firing pulse generator 23.
- the voltage vector is adjusted with two PWM control periods as one unit, so that the output time of the zero voltage vector at the end of each period is set to zero. By doing so, the output time of the remaining zero voltage vector can be doubled.
- the output time of the zero-voltage vector is a force that is equal to or less than the force that is ensured to be equal to or more than a fixed value of the minimum zero-voltage vector output time. Surge voltage more than doubled can be suppressed.
- the adjustment of the output time of the voltage vector covers the output time of the voltage vector which is a parameter common to the three phases generated based on the three-phase voltage command. Can be obtained.
- the voltage vector it is possible to minimize the disturbance of the magnetic flux vector locus due to the suppression of the surge voltage.
- the target period is particularly limited to two periods. It is needless to say that it is not limited, and can be freely set within a range of two or more cycles.
- FIG. 18 is a flowchart illustrating an operation of a voltage vector adjustment unit provided in a power converter control device according to Embodiment 4 of the present invention.
- the voltage vector adjustment unit 22 according to the fourth embodiment determines the output time of the voltage vector output by the voltage vector control unit 21 in two control cycles of PWM control according to the procedure shown in FIG. Adjustment is performed, and adjustment operations such as combining the output time of the same voltage vector within two cycles in a fixed case are performed.
- FIG. 16 The operation of the voltage vector adjustment unit 22 according to the fourth embodiment will be described. Note that, in FIG.
- Step ST34 the same reference numerals are given to processing procedures that are the same as the processing procedures shown in FIG. Here, a description will be given mainly of a portion related to the fourth embodiment.
- the total of the output time of the zero-voltage vector over two cycles (t0-1 + t7-1 + t0_2 + t7-2) is the minimum zero-voltage value. If it is longer than the vector output time Tz (Step ST34: Yes), in Step ST41, the time during which the same voltage vector is output within two cycles is combined.
- tl- 1 ' t l_l + tl- 2
- t 2_1' t 2-l + t 2-2
- the voltage vectors V0_1, V V2-1, V7_1, V0—2, VI—2, V2_2, and V7—2 for the two cycles selected by the voltage vector control unit 21 are used as they are. Output to arc pulse generator 23.
- the fourth embodiment when adjusting the voltage vector with two PWM control periods as one unit, the time for outputting the same voltage vector in two periods is reduced to one.
- the output time of each voltage vector including the zero voltage vector can be doubled.
- the minimum zero voltage vector time is always maintained, surge voltage exceeding twice the DC bus voltage Vdc can be suppressed.
- the surge voltage of all phases can be adjusted by one adjustment.
- the suppression effect can be obtained.
- the voltage vector it is possible to minimize the disturbance of the magnetic flux vector locus due to the suppression of the surge voltage.
- the number of cycles is not particularly limited to two, and can be freely set within a range of two or more.
- FIG. 19 is a block diagram showing a configuration of a power converter control device according to Embodiment 5 of the present invention. Note that in FIG. 19, the configuration shown in FIG. Equivalent components are denoted by the same reference numerals. Here, the part related to the fifth embodiment will be mainly described.
- a voltage vector adjustment unit 31 is provided instead of voltage vector adjustment unit 12, and a delay unit 32 is added. ing.
- the delay unit 32 delays each voltage vector that is adjusted and output by the voltage vector adjustment unit 31 and its output time by one cycle, and provides the output to the voltage vector adjustment unit 31.
- the delay unit 32 includes a voltage vector V0__p, V1-P, V2_p, V7-p delayed by one cycle, and an output time t0-p, tl-p, t2-p, t delayed by one cycle. 7—p is supplied to the voltage vector adjustment unit 31.
- voltage vector adjustment section 31 adjusts the output time of the voltage vector output from voltage vector control section 11 so that the zero-voltage vector output time becomes a certain value or more.
- the output is adjusted and adjusted using the adjustment time one cycle before the PWM control cycle obtained via the delay unit 32 at that time.
- FIG. 20 is a flowchart for explaining the operation of the voltage vector adjusting unit 31 shown in FIG.
- the same reference numerals are given to processing procedures that are the same as or equivalent to the processing procedures shown in FIG.
- the voltage vector adjustment unit 31 includes output time t 1, t 2, t 0, and t 7 of the voltage vector input / output from the voltage vector control unit 11 1, and PWM control input from the delay unit 32.
- the voltage vector VI-p, V2_p, V0_p, V7-p, which is the adjustment output one cycle before the cycle, and its output time tl-p, t2_p, t0__p, t7-p are read (step ST 51) Since the output time of the zero-voltage vector may be zero, it is determined whether or not the last output vector (one cycle before the PWM control cycle) is the zero-voltage vector (step ST52).
- step ST52 Yes
- step ST11 If the total output time t0 + t7 of the zero-voltage vector is longer than the minimum zero-voltage vector output time Tz (step ST11: Yes), the current output times t1, t2 , t 0, and t 7 are output times t 1 ′, t 2 ′, t 0 ′, and t 7 ′ that are directly adjusted (step ST 12).
- step ST11 if the total output time t0 + t7 of the zero-voltage vector is shorter than the minimum zero-voltage vector output time Tz (step ST11: Yes), the zero-voltage vector It is determined whether or not the total output time t 0 + t 7 of the vector is longer than 1Z2 of the minimum zero voltage vector output time T z (step ST53). As a result, if the total output time t0 + t7 of the zero-voltage vector is longer than the minimum zero-voltage vector output time Tz of 1Z2 (step ST53: Yes), the signal is output at the beginning of the cycle.
- the output time t 0 ′ of the zero voltage vector V 0 is adjusted to the total output time t 0 + t 7 of the zero voltage vector (t O ′ two t 0 + t 7), and the zero output at the end of the cycle is adjusted.
- the output times t1 and t2 of the non-zero voltage vector are output times t1 'and t2' adjusted as they are (step ST54).
- the output times t 1 and t 2 of the non-zero voltage vectors V 1 and V 2 are adjusted according to Equation 3 so that the relative ratio of the output times of the voltage vectors VI and V 2 does not change.
- step 52 If the last output vector is not a zero vector (step 52: No), the process branches to a sequence starting from a non-zero voltage vector this time. In step ST56, the output time of the zero voltage vector is determined.
- the output times of the non-zero voltage vectors V1 and V2 are the output times tl, and t2 'obtained by directly adjusting the current output times t1 and t2 (step ST57).
- step ST14 the output times t 0 ′, t 1 t 2 ′, t 7 of the voltage vectors V0, VI, V2, V7 adjusted in any of steps ST12, ST54, ST55, ST57, ST58. 'Is output to the firing pulse generator 13 (step ST14).
- the voltage vectors V0, VI, V2, and V7 selected by the voltage vector control unit 11 are used as they are and output to the firing pulse generation unit 13.
- the output time of the voltage vector is adjusted so that the zero voltage vector existing at the beginning and end of the PWM control cycle is combined into one.
- the output time of the zero voltage vector can be doubled.
- the output time of the zero-voltage vector is either a force that is secured to a certain value or more of the minimum zero-voltage vector time or zero, so that the DC bus voltage Vdc is 2 Surge voltage more than doubled can be suppressed.
- the surge voltage of all phases can be adjusted by one adjustment.
- the suppression effect can be obtained.
- the voltage vector it is possible to minimize the disturbance of the magnetic flux vector locus due to the suppression of the surge voltage.
- FIG. 21 is a flowchart illustrating an operation of a voltage vector adjustment unit provided in a control device for a power converter according to Embodiment 6 of the present invention.
- the voltage vector adjustment unit 31 is slightly added to the function. . That is, the voltage vector adjustment unit 31 according to the sixth embodiment uses the output time of the zero voltage vector output at the end of the previous PWM control cycle to generate the zero output at the beginning of the current PWM control cycle. An adjustment operation for determining the output time of the voltage vector is performed.
- FIG. 21 the same reference numerals are given to the same processing procedures as those shown in FIG. Here, a description will be given mainly of a portion relating to the sixth embodiment.
- the voltage vector adjustment unit 31 includes an output time t 1, t 2, t 0, 1: 7 of the voltage vector input from the voltage vector control unit 11 1, and an input from the delay unit 32.
- Voltage vector VI—p, V2—P, V0_p, V7—p which is the adjustment output one cycle before the PWM control cycle to be output, and its output time t1—p, t2—p, tO — P, t 7—
- the last time (one cycle before the PWM control cycle) Determine whether the total time of the output time t0_p of the zero voltage vector output later and the output time t0 of the zero voltage vector output first this time is longer than the minimum zero voltage vector output time Tz (Step ST61).
- step ST61: Yes the current output time tl, t The output times t1, t2 ', t0', and tT obtained by adjusting 2, t0 and t7 as they are (step ST12).
- step ST61: No the zero-voltage vector output time It is determined whether or not the total t0_p + t0 + t7 is longer than the minimum zero voltage vector output time Tz (step ST62).
- Step ST62 If the total output time of the zero-voltage vector, t0—p + t0 + t7, is longer than the minimum zero-voltage vector output time Tz (Step ST62: Yes), the signal is output at the beginning of the cycle.
- the output times t 1 and t 2 of the non-zero voltage vector are the output times t l 'and t 2' adjusted as they are (step ST 63).
- step ST62 No
- Step ST14 the output times t 0 ′, t 1 t 2, and t 7 ′ of the voltage vectors V 0, VI, V 2, and V 7 adjusted in any one of steps ST 12, ST 63, and ST 64 are used as the ignition pulse generator 13.
- the voltage vectors V 0, VI, V 2, and V 7 selected by the voltage vector control unit 11 are used as they are and output to the firing pulse generation unit 13.
- the output time of the zero-voltage vector output at the end of the previous PWM control cycle is used to calculate the zero-voltage vector output at the beginning of the current PWM control cycle. Since the output time is determined, the minimum zero-voltage vector time can be ensured even when the zero-voltage vector straddles the PWM control cycle. Therefore, it is possible to reliably suppress a surge voltage exceeding twice the DC bus voltage Vdc.
- the surge voltage of all phases can be adjusted by one adjustment.
- the suppression effect can be obtained.
- the voltage vector it is possible to minimize the disturbance of the magnetic flux vector locus due to the suppression of the surge voltage.
- FIG. 22 is a block diagram showing a configuration of a power converter control device according to Embodiment 7 of the present invention.
- components that are the same as or equivalent to the configuration shown in FIG. 4 are given the same reference numerals.
- the part related to the seventh embodiment will be mainly described.
- a voltage vector adjustment unit 41 is provided instead of voltage vector adjustment unit 12, and a delay unit 42 is added. ing.
- voltage vector adjustment section 41 adjusts the output time of the voltage vector output from voltage vector control section 11 so that the zero-voltage vector output time becomes a certain value or more.
- the output is adjusted, but in the seventh embodiment, the error It has a function of outputting the difference E rr, and uses the error E rr-1 p one cycle before the PWM control cycle input via the delay unit 42 for voltage vector adjustment one cycle after.
- FIG. 23 is a flowchart illustrating the operation of voltage vector adjusting section 41 shown in FIG.
- FIG. 24 is a diagram for explaining an error calculation operation performed by the voltage vector adjustment unit shown in FIG.
- the voltage vector adjustment unit 41 together with the output times t1, t2, t0, and t7 of the voltage vector output by the voltage vector control unit 11
- the calculated error E rr—p is read (one cycle before the control cycle) (step ST71), and the output time t1, t2, t0, Correct t7 (step ST72).
- step ST72 the output time t1 is corrected to t1 (1 + Err-p). Correct the output time t 2 to t 2 (1 + E rr — p). Then, the output times t0 and t7 are corrected to (T_t1-t2) / 2 using the new output times tl and t2. Then, the minimum zero-voltage vector output time Tz is secured or the zero-voltage vector output time is deleted according to the procedure described in the second embodiment (FIG. 15) (steps ST11 to ST11). twenty one).
- the output times t 1 ′, t 2 ′ of the obtained adjusted voltage vectors VI, V 2 and the output times tl, t 2 of the voltage vectors VI, V 2 corrected in the previous step ST 72 are obtained.
- Calculate the error E rr of. That is, the calculation of Err (tl + t'2—tl'—t2) / (t1 + t2) is performed (step ST73).
- the output times t 1 ′, t 2 ⁇ t 0 t 7 ′ of the obtained adjusted voltage vectors VI, V 2, V 0, V 7 and the error E rr are output (step ST 74).
- FIG. Fig. 24 (1) shows the trajectories A and B of the magnetic flux vector for two PWM control cycles before the adjustment of the voltage vector.
- the trajectory A is for the previous cycle
- the trajectory B is for the current cycle.
- Figure 24 (2) shows the trajectories A 'and B' of the magnetic flux vector after the adjustment of the voltage vector.
- the trajectory A of the previous magnetic flux vector secured the minimum zero voltage vector output time, and as a result, the trajectory A 'becomes short, and the trajectory becomes short.
- Fig. 24 (1) shows the trajectories A and B of the magnetic flux vector for two PWM control cycles before the adjustment of the voltage vector.
- the trajectory A is for the previous cycle
- the trajectory B is for the current cycle.
- Figure 24 (2) shows the trajectories A 'and B' of the magnetic flux vector after the adjustment of the voltage vector.
- the trajectory A of the previous magnetic flux vector secured the minimum zero voltage vector output time, and as a result, the trajectory A 'becomes
- the arc can be regarded as a straight line. Therefore, the difference between the trajectories A and B and the trajectories A and B ' It can be considered that only the ratios are different. Since the division ratio between the trajectory A and the trajectory B before the adjustment is 1: 1, when adding the shorter part of the trajectory A 'to the trajectory B' to make the total value equal, the trajectory A and the trajectory A ' It is only necessary to know the ratio. Therefore, the error E rr obtained by any of the following equations (7) to (9) is used.
- the adjustment of the voltage vector output time covers the output time of the voltage vector, which is a parameter common to the three phases generated based on the three-phase voltage command. The effect of suppressing the surge voltage can be obtained.
- FIG. 25 is a flowchart illustrating an operation of a voltage vector adjustment unit included in the power converter control device according to Embodiment 8 of the present invention.
- steps that are the same as or equivalent to the processing steps shown in FIG. 9 are given the same reference numerals.
- the description will focus on the parts related to the eighth embodiment.
- the output time of the zero voltage vector described in the second embodiment is set to zero. Examples of countermeasures for items (faults) that were not considered as exceptions when adjusting to (steps ST81 to ST84) are shown.
- step ST81 if the adjusted output time t1 'of the voltage vector VI is longer than the minimum zero-voltage vector output time Tz of 1Z2 (step ST81: No), the adjusted output time t of the voltage vector V2 It is determined whether or not 2 ′ is shorter than 1 ⁇ 2 of the minimum zero voltage vector output time T Z (step ST83).
- Step 83 If the adjusted output time t2 'of the voltage vector V2 is longer than 1/2 of the minimum zero-voltage vector output time Tz (Step 83: No), the adjustment is performed in Steps ST11 to ST21.
- the read output times t l ', t 2', t ⁇ ', and t 7' are not readjusted (step ST85).
- the surge voltage related to the voltage vector output time other than the zero voltage vector which may occur when the output time of the zero voltage vector is adjusted to zero, is limited.
- a surge voltage exceeding twice the DC bus voltage Vdc can be reliably suppressed.
- the suppression of the surge voltage can obtain the effect over all phases only by adjusting the voltage vector output time which is a parameter common to the three phases.
- by adjusting the voltage vector it is possible to minimize the disturbance of the magnetic flux betattle locus due to the suppression of the surge voltage.
- FIG. 26 is a flowchart illustrating an operation of a voltage vector adjustment unit provided in a power converter control device according to Embodiment 9 of the present invention.
- the same reference numerals are given to the same or similar procedures as the processing procedures shown in FIG. 20 (Embodiment 5).
- a description will be given focusing on a portion related to the ninth embodiment.
- V0 ⁇ V1 ⁇ V2 ⁇ (V7) ⁇ V2 ⁇ V3 ⁇ V0
- step 90 in step 90 instead of the first step ST51 shown in FIG. 20, the voltage vectors VI, V2, VO, V7 input from the voltage vector control unit 11 and the output thereof are output.
- the time vectors t1, t2, t0, t7 and the voltage vector VI—p, V2.p which is the adjustment output one cycle before the PWM control cycle input from the delay unit 32, Read VO-p, V7-p, and their output times t1-p, t2_p, tO-p, t7_p. If the output time of the zero voltage vector is adjusted to zero in step ST57 or step ST58, it is determined whether the last output voltage vector is the same as the first output voltage vector this time.
- Judge (Step ST9 1) 0
- step ST91 if the last output voltage vector is the same as the first output voltage vector this time (step ST91: Yes), since it is the case of the above (3), no operation is performed and step ST91 is performed. Proceed to 93.
- step ST91 if the last output voltage vector is different from the first output voltage vector this time (step ST91: No), since it is the case of (4) 'above, the first output voltage vector is Change to the last output voltage vector (step ST92) and proceed to step ST93.
- step ST93 output times t1, t2 ', t0', t7 'of the adjusted voltage vector and voltage vectors Vl, V2', VO ', V7' are output.
- step ST12, ST54, ST55 to step 93 the voltage vectors V 0, VI, V2, V 7 selected by the voltage vector control unit 11 are directly converted to the voltage vector V0.
- the individual methods for suppressing the generation of the surge voltage exceeding twice the DC bus voltage V dc have been described, but the two methods of the first to ninth embodiments have been described. It is also possible to use a combination of the above.
- the surge voltage can be adjusted for all phases by one adjustment. The effect of suppressing the above can be obtained.
- by adjusting the voltage vector it is possible to minimize the disturbance of the magnetic flux vector path caused by surge voltage suppression.
- the relative ratio of the output time of the voltage vectors other than the zero voltage vector should not be changed. Although adjustment is performed, the relative ratio may be changed if the only purpose is to suppress surge voltage. This is clear from the description of the first embodiment relating to the suppression of the surge voltage.
- a surge voltage exceeding twice the DC bus voltage V dc can be suppressed by using a force that secures the output time of the zero-voltage vector to a certain value or more, or by using a cross section.
- the adjustment of the voltage vector output time covers the output time of the voltage vector, which is a parameter common to the three phases generated based on the three-phase voltage command, the surge voltage can be adjusted for all phases by one adjustment. Can be obtained.
- This invention is suitable as a control device of a power converter when the connection cable between a power converter and a load becomes long.
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Abstract
Description
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Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005508195A JP4312760B2 (ja) | 2003-08-25 | 2003-08-25 | 電力変換装置の制御装置 |
EP03818300.0A EP1659680B1 (en) | 2003-08-25 | 2003-08-25 | Controller for power converter |
PCT/JP2003/010711 WO2005020419A1 (ja) | 2003-08-25 | 2003-08-25 | 電力変換器の制御装置 |
US10/530,720 US7426122B2 (en) | 2003-08-25 | 2003-08-25 | Power-converter control apparatus employing pulse width modulation and adjusting duration of a zero-voltage vector |
CNB038253593A CN100527586C (zh) | 2003-08-25 | 2003-08-25 | 电力变换器的控制装置 |
TW92123535A TWI230498B (en) | 2003-08-25 | 2003-08-27 | Controller for power inverter |
Applications Claiming Priority (1)
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PCT/JP2003/010711 WO2005020419A1 (ja) | 2003-08-25 | 2003-08-25 | 電力変換器の制御装置 |
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WO2005020419A1 true WO2005020419A1 (ja) | 2005-03-03 |
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PCT/JP2003/010711 WO2005020419A1 (ja) | 2003-08-25 | 2003-08-25 | 電力変換器の制御装置 |
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Country | Link |
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US (1) | US7426122B2 (ja) |
EP (1) | EP1659680B1 (ja) |
JP (1) | JP4312760B2 (ja) |
CN (1) | CN100527586C (ja) |
TW (1) | TWI230498B (ja) |
WO (1) | WO2005020419A1 (ja) |
Cited By (3)
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JP2006333671A (ja) * | 2005-05-30 | 2006-12-07 | Hitachi Industrial Equipment Systems Co Ltd | 電力変換装置 |
JP2017032323A (ja) * | 2015-07-29 | 2017-02-09 | 新電元工業株式会社 | 半導体試験装置及び半導体試験方法 |
WO2023136340A1 (ja) * | 2022-01-17 | 2023-07-20 | サンデン株式会社 | 電力変換装置 |
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CN100525050C (zh) * | 2004-08-27 | 2009-08-05 | 三菱电机株式会社 | 3相pwm信号发生装置 |
US8648561B2 (en) * | 2007-03-27 | 2014-02-11 | Danfoss Drives A/S | Method for driving a pulse width modulated controller |
WO2011135696A1 (ja) * | 2010-04-28 | 2011-11-03 | 株式会社 日立製作所 | 電力変換装置 |
FR2975843B1 (fr) * | 2011-05-23 | 2013-05-17 | Renault Sa | Procede de commande des interrupteurs d'un redresseur de courant connecte a un chargeur embarque. |
JP2015033204A (ja) * | 2013-08-01 | 2015-02-16 | 株式会社デンソー | モータ制御装置 |
JP6272077B2 (ja) * | 2014-02-25 | 2018-01-31 | 三菱重工業株式会社 | 過給機及び船舶 |
US9431951B2 (en) * | 2014-07-16 | 2016-08-30 | Atieva, Inc. | Direct torque control motor controller with transient current limiter |
US9444384B2 (en) * | 2014-07-16 | 2016-09-13 | Atieva, Inc. | Direct torque control motor controller with transient current limiter |
JP6176495B2 (ja) * | 2014-08-19 | 2017-08-09 | 富士電機株式会社 | 3レベルインバータの制御方法及び制御装置 |
CN104779830B (zh) * | 2015-04-29 | 2017-10-20 | 厦门大学 | 一种死区时间可变的逆变控制方法 |
US9602041B1 (en) * | 2016-01-08 | 2017-03-21 | Newfrey Llc | Software-controlled electronic circuit for switching power to a three-phase motor |
KR101898815B1 (ko) * | 2017-09-14 | 2018-09-13 | 한국전력공사 | 3상 전압 비율을 이용한 싸이리스터 점호 제어 장치 및 그 제어 방법 |
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Also Published As
Publication number | Publication date |
---|---|
EP1659680A1 (en) | 2006-05-24 |
JP4312760B2 (ja) | 2009-08-12 |
EP1659680A4 (en) | 2008-12-17 |
JPWO2005020419A1 (ja) | 2006-10-19 |
TW200509512A (en) | 2005-03-01 |
TWI230498B (en) | 2005-04-01 |
CN100527586C (zh) | 2009-08-12 |
US7426122B2 (en) | 2008-09-16 |
US20060062033A1 (en) | 2006-03-23 |
EP1659680B1 (en) | 2017-04-19 |
CN1701501A (zh) | 2005-11-23 |
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