WO2004008118A1

WO2004008118A1 - Detection method and apparatus

Info

Publication number: WO2004008118A1
Application number: PCT/GB2003/003030
Authority: WO
Inventors: Victor Higgs
Original assignee: Aoti Operating Company, Inc.
Priority date: 2002-07-12
Filing date: 2003-07-14
Publication date: 2004-01-22
Also published as: GB0216184D0; AU2003281074A1; TW200427977A

Abstract

A method of detecting impurities in a semiconductor structure, in particular during thermal processing as part of device fabrication, comprises exposing the surface of the semiconductor structure to at least one high-intensity beam of light from a suitable light source, preferably a laser, and in particular a high-intensity laser, and collecting photoluminescence produced by excitation of the semiconductor structure by the light beam; numerically analysing the photoluminescence emitted across the area of the structure; comparing the result with a predetermined acceptable specification range of photoluminescence; making a quality classification of the semiconductor structure based thereon, and in particular rejecting or selecting for remedial action semiconductor structures exhibiting a photoluminescence response outside the said predetermined acceptable specification range. In a refinement of the method a spatially resolved PL map is also collected. An apparatus for performing the method is also described.

Description

DETECTION METHOD AND APPARATUS

The invention relates to a non-destructive method and apparatus for detecting surface layer metal contamination in semiconductors such as silicon, for detecting surface layer metal contamination introduced by heat treatment processes, and in particular rapid thermal treatment (RTP) processes during device fabrication, both as a quality control metric and as a diagnostic method to identify processing problems during device fabrication.

Advances in silicon technology in the last 50 years have produced dramatic improvements in chip performance. Rapidly shrinking device geometry and technological demand for high-performance circuits have led us to a point where the number of transistors which can be included on a single chip has increased to five million. This means that, with 200 chips being possible on a single 200 mm wafer a total of 1 billion transistors may be included per wafer.

As the chip size approaches 0.1 μm the device yield has become more sensitive to defects and impurities. Such defects and impurities can be unintentionally introduced in the manufacturing line. An ability to monitor the presence of these impurities, particularly those arising from metal contamination during processing, and an understanding of their degrading impact on IC performance and yield, is essential, both as a means of quality control, and as a means of process control and to develop methodologies for improved and cleaner processing techniques.

There is an important requirement to control defects and contamination in the furnace area, because of the high diffusivity and solubility of metal impurities at elevated temperatures, which can lead to the activation of these metal impurities and their complexes. These impurities once activated can lead to degradation of the junction device performance, and increased leakage and device reliability. Also in the furnace area high temperature treatment can lead to thermal slip, which is well know to cause degradation of device performance.

Now with the on-going improvements to reduce manufacturing cost and improve productivity fast feedback is requires enabling tight processes control; uncertainties about defects in the process can cause loss of time and money. There have been many detailed studies have which have shown how Fe can lead to the degradation of the gate oxide in a MOS (metal oxide semiconductor) device. International standards (see for example International Semiconductor Roadmap for Semiconductor Materials 2001, SEMATECH, 3101 Industrial Terrace Suite 106, Austin TX 78758) suggest that the bulk Fe concentration must be below 1 x 10 cm^" to avoid yield loss.

Conventional methods used for monitoring contamination are based on bulk lifetime and diffusion measurements. These methods are slow and rely on the impurities being distributed in the bulk of the wafer. This is not necessarily the case for some specific thermal processing steps rapid thermal processing (RTP) is used which provide high wafer throughput by using short annealing times and elevated temperatures. This means any impurities or defects that are formed during RTP will have not have time to diffuse into the bulk, but will nevertheless reach surface concentrations high enough to be significantly detrimental to yield. For contamination testing using bulk lifetime analysis the wafers would have further annealed to drive the metals into the bulk. This slows down the process, and it might in any case not be desirable to subject the wafer to further heat treatments.

It is an object of the present invention to provide a method and apparatus for detecting surface layer metal contamination in semiconductors such as silicon which mitigates some or all of the above disadvantages. It is a particular object of the present invention to provide a method and apparatus which provides for a more rapid assessment of contamination introduced by heat treatment processes than prior art methods.

It is a particular object of the present invention to provide a method and apparatus applicable to an improved quality control metric.

It is a further object of the present invention to provide a method and apparatus for detecting surface layer metal contamination in semiconductors such as silicon which offers potential additional functionality as a diagnostic method to identify processing problems during device fabrication.

Thus, in accordance with the present invention in its first aspect a method of detecting impurities in a semiconductor structure, in particular during thermal processing as part of device fabrication, comprises the steps of: exposing the surface of the semiconductor structure to at least one high- intensity beam of light from a suitable light source, preferably a laser, and in particular a high-intensity laser, and collecting photoluminescence produced by excitation of the semiconductor structure by the light beam; making an analysis of the collected photoluminescence signal and using that analysis as the basis for a quality classification of the suitability of the semiconductor for further device fabrication processing.

The quality classification step comprises performing a numerical analysis of the collected photoluminescence signal, comparing the result of that numerical analysis with a predetermined acceptable photoluminescence specification such as a predetermined range of photoluminescence known to be associated with satisfactory quality, and making a quality classification of the semiconductor structure based thereon. In one simple alternative the method comprises determining an average photoluminescence intensity, comparing the average with a predetermined acceptable specification range of photoluminescence, and making a quality classification of the semiconductor structure as above based thereon.

The average may be a whole area average based on mean photoluminescence intensity emitted across the area of the structure, or local area average wherein the area of the structure is divided into a two dimensional array of subregions, a mean photoluminescence intensity is determined for each subregion, the mean for each subregion is compared with a predetermined acceptable photoluminescence specification, and a quality classification as above is based thereon. This can be advantageous since the response attributable to an isolated defect could be swamped in a whole area average even though that defect was sufficiently serious to justify a quality rejection. At an appropriate subregion size it is possible to ensure that such a response can still be detected.

Use of a predetermined photoluminescence specification based on the mean is an example only. In the alternative, especially if the subregion approach is followed, other numerical parameters could be applied to the analysis of the photoluminescence signal, such as standard deviation, local maxima and/or minima, deviation from a predetermined baseline, or other numerical analysis method to determine, either on a local or whole area basis, a deviation of the photoluminescence response from predetermined parameters known to be associated with a semiconductor structure of satisfactory quality. Where reference is made below to numerical analysis based on average luminescence it will be appreciated that this is for exemplification only and that the precise numerical parameters chosen for the comparison between observed and predetermined acceptable response is not critical to the invention. The photoluminescence technique produces a spatially resolved PL map at a resolution determined by the characteristics of the high-intensity beam of light. This can be exploited by further preferred features of the present method, but for the fundamental objective of the invention as a simple and rapid quality test for a whole wafer during processing an average PL intensity result over the whole wafer area is obtained. This can be related to a predetermined acceptable specification range developed in association with studies using slower analysis methods (e.g. bulk carrier lifetime methods or electrical yield test methods). It has been surprisingly found, as described in detail below, that a close and apparently linear correlation can be demonstrated between impurity data obtained from the near-surface-based PL technique of the present invention and the bulk carrier lifetime methods conventionally used.

The light beam is so controlled, and in particular beam power and/or wavelength and/or spot size so controlled, as to identify defects at a selective depth in said semiconductor structure, so as to collect PL information from a suitable near-surface depth, for example from the upper 12 μm of the semiconductor structure. For certain materials and devices, smaller depths may be appropriate, down to for example 5 μm or even 1 μm.

Thus the present invention is a defect-monitoring tool that can be used to monitor surface contamination and edge slip. Because this technique measures the surface region it will detect near-surface defects and contamination that would be missed using conventional methods (e.g. because they have not yet diffused into the bulk) but which are most determinative in their impact on device quality and performance. The method is thus particularly suited to modern rapid thermal processing techniques, where it is an acknowledged draw back of bulk methods that impurities introduced during processing might not have diffused fully into the bulk. For bulk methods to be effective it is likely to be necessary to subject the wafer to an additional annealing step. By contrast, the method of the present invention made as impurity levels specifically in the surface, in the region where the device is to be, without the need to anneal to drive these impurities into the bulk prior to analysis.

In accordance with the invention, a predetermined acceptable specification range of average photoluminescence is first determined and then used as a reference for the results for any given wafer for quality control purposes. The predetermined specification range will include a minimum and or maximum photoluminescence value. In particular, it is known that the photoluminescence signal can be affected in different ways depending upon the particular chemical species comprised in the impurity. Accordingly, the specification range will preferably comprise a minimum and a maximum photoluminescence value.

A quality control decision is taken depending upon whether the measured result lies within the predetermined specification range. For example, the decision may be "pass" for within the range, and "fail" for outside the range. "Failed" items may be discarded, subjected to remedial action such as additional cleaning etc. The predetermined acceptable PL range will vary in accordance with the particular material and process involved. It will be determined by relating the PL responses when a wafer is subjected to the method of the present invention with existing quality control specification ranges developed in accordance with existing prior art measuring techniques. An example is given below.

Once a relationship has been established between an existing process specification for an existing process and a specification PL range for that process, the present invention provides very high throughput relative to prior art methods. For example, for a 12 inch (300 mm) wafer equivalent results can be obtained in around five minutes which would take around an hour with existing bulk processing methods. Accordingly, the technique of the present invention, in addition to being particularly suited to wafers which have been subjected to rapid thermal processing, where the slow diffusion rates of impurities over processing time scales would leave prior art bulk methods ineffective without an annealing step, the method of the present invention also offers speed of throughput advantages over bulk methods regardless of the specific thermal processing technique used for the wafer.

Photoluminescence (PL) spectroscopy is a very sensitive technique for investigating both intrinsic and extrinsic electronic transitions at impurities and defects in semiconductors. When silicon is excited at low temperatures with laser irradiation above the band-gap of the material, electron hole pairs are produced. These carriers can recombine in various different ways, some of which give rise to luminescence. The electron hole pairs formed at low temperature can be trapped at impurities in silicon and they emit photons characteristic of this interaction, thereby giving impurity specific information in the photoluminescence spectra. There are a significant number of applications of PL spectroscopy to silicon including characterisation of silicon after different processing steps, characteristic of device fabrication for example implantation, oxidation, plasma etching, the detection of point defect complexes and the presence of dislocations. One of the most important applications includes the non-destructive measurement of shallow donors and acceptors such as arsenic, boron and phosphorous. Notably, this technique enables the measurement of the concentration of these shallow donors and acceptors. However, in conventional applications in order to obtain this spectral information and unambiguous chemical identification of the optical centres, measurements need to be carried out at liquid helium temperatures. It is known throughout the industry that at room temperature the PL signal is significantly weakened and very little useful spectral information can be obtained.

A room temperature technique is accordingly preferred, such as in particular that described by International patent application W098/11425, which describes a non-destructive technique which makes practical the detection of electrically active defects in semiconductor structures based on room temperature PL. The patent application discloses a PL technique which has industrial application in that it enables the image to be produced within minutes and which has a further added advantage in producing micro imaging of small individual defects particularly near to the surface of the wafer, where the device is fabricated.

The technique provides information concerning defects in a semiconductor or silicon structure at a rate appropriate to industrial use and in particular enables us to visualise defects in the upper regions of the semiconductor or silicon structure and in particular near to the surface of same. The technique exploits enhanced non-radiative recombination of electron hole pairs at defects in a semiconductor or silicon structure with a view to enhancing contrast in a PL image of said semiconductor or silicon structure so as to enhance the viewing of defects in same. The preferred PL technique is therefore that in W098/11425 incorporated herein by reference.

The success of the room temperature PL method disclosed therein is, in part, due to the probing volume probed by the laser being small, spatial resolution preferably 0.1 to 20 μm, ideally 2 to 5 μm, and with a peak or average power density of between 10 to 10⁹ watts/cm², so that localised defects have much greater effect on the measured PL intensity and is also believed, in part, because since the excitation is focused the injected carrier density is high. This greatly increases the probability of non-radiated recombination at the defect and hence physical location of the defect. The present invention in certain preferred embodiments exploits this by preparing a spatial map, and more preferably still a spatial image, of the defects of which the PL response is representative.

Reference herein to a high-intensity laser is meant to include, without limitation, a high power density laser i.e. regardless of where the power of the laser the emittance is focused.

In a preferred method of the invention a pulsed laser excitation source is used and ideally luminescence data is measured and/or the luminescence images collected as a function of time. This means that both depth and spatial resolution are improved and can be used to obtain information on the carrier capture cross sections of the defects. Time resolved measurements can also be used to measure the effective carrier lifetime and obtain lifetime maps.

The PL technique of the present invention generates a spatially resolved PL map across the area of the wafer. In the primary method of the invention, this data map is then processed to provide an average PL level across the whole wafer, which is compared with the reference to make the quality control decision. If the method is to be used for such a go-no go quality control decision then only the averaged PL level is of concern, and the resolution of the map produced by the method is immaterial. Resolutions of the order of 7mm are adequate. At this level of resolution, processing times are reduced, and test throughput rates maximised. For example it can take just five minutes to obtain a result from a 12 inch (300 mm) wafer.

Nevertheless, it is a particular advantage of the technique of the present invention that it can additionally be used to generate a spatially resolved map of PL signals across the surface of the semiconductor under test, and in particular to generate a spatially resolved image of those signals. Accordingly, in a preferred embodiment, the method further comprises the step of generating such a map and/or such an image. In these circumstances, it can be appropriate to work to mapping/imaging resolutions of 0.5mm or less.

Preferably, the method further comprises storing the spatially resolved PL map on suitable data storage means and/or transmitting digitised data derived from the spatially resolved map through suitable processing means for onward processing. In particular, successive digitised maps relating to results produced by successive stages of thermal treatment can be stored and/or processed in this way, to identify which particular stage during treatment a problem might arise.

Preferably, the method further comprises the step of displaying any generated PL image on suitable display means.

In the preferred embodiment, taking full advantage of the ability of the technique to produce spatially resolved data on the PL response of a semiconductor structure under test, it might be appropriate, as indicated, to work at higher resolutions. Accordingly, throughput will be slower than where the technique is used as a basis for basic (eg "go - no go") quality control decisions only. A preferred more developed quality control strategy might therefore be to process each unit using the more rapid, basic technique, and to sample process batches using the additional functionality offered by the collection of spatially resolved data.

The feature of the invention is exploited further in a further aspect of the invention, comprising a diagnostic method to identify processing problems during device fabrication, which comprises performing the detection method in accordance with the first aspect of the invention on at least one semiconductor structure successively at the end of a plurality of processing steps during device fabrication, and in particular at the end of a plurality of thermal processing steps; additionally collecting and storing data relating to a spatially resolved map of PL response across the surface of the semiconductor structure; on completion of the processing stages, electrically testing the finished product, for example by producing a yield map; relating data from the electrical test indicative of areas of unsatisfactory operation in the finished product, to data from the spatially resolved PL maps from the various process stages to identify which process stages are likely to be responsible for problems arising in the areas in question.

For example, the PL map for a particular stage in thermal processing might illustrate that a particular region appears to have a level of impurity after that processing stage. The resultant electrical test might indicate that chips in this particular region are performing sub-specification. The method in accordance with this aspect of the invention thus enables identification of the processing stage in question as a likely candidate for further investigation. Accordingly, this aspect of the invention can serve as a diagnostic method for the whole fabrication process.

In extreme cases, it has even been found that a spatially resolved PL map, or an image produced therefrom, from a single thermal processing stage can show a contamination pattern produced by the furnace structure. This can present clear evidence that a particular contamination problem is associated with the particular furnace.

The method is suitable for any basic semiconductor structure on which devices are fabricated by thermal processing in the manner above described. In particular, the method is suitable for structures based on wafers of silicon and silicon alloys. The devices may be fabricated from simple single layer wafers or from multilayer wafers, for example formed in an epitaxial layer on a basic silicon wafer.

In accordance with a further aspect of the invention an apparatus for detecting impurities in a semiconductor structure, in particular during thermal processing as part of device fabrication, comprises a high intensity light source, preferably a laser, and in particular a high-intensity laser; means to focus a high intensity beam of light from the light source onto a surface of a semiconductor structure under test; collection means to collect photoluminescence data from across the surface of the semiconductor structure under test produced by excitation of the semiconductor structure by the light beam; analysis means to process and numerically analyse the collected data; a comparator to compare the results of the analysis with predetermined acceptable specification parameters.

The apparatus to perform the basic method generates data based on a numerical analysis of the PL response, for example an average PL signal across the whole area or a set of local area data as described. This is compared with predetermined acceptable specification parameters.

However, to perform the refined alternatives of the method described above, the apparatus preferably further comprises means to resolve the collected PL data into a spatially resolved PL map across the area of the semiconductor structure, and optionally further comprises means to convert the resolved data into a PL image and/or image/data storage means to store the map/image, and in particular to store successive map/images for future comparison, and/or means to transmit the map/image to a suitable remote data processor and/or image display means such as a visual display screen to display an image and/or related data to a user. In a further aspect of the invention, there is provided a computer program and/or a suitably programmed computer for performing some or all of the steps of the method as hereinbefore described, and in particular for performing data processing steps on collected PL data, for example to determine average PL across the wafer area and/or to spatially resolve a PL map from collected PL data and/or to compare the average with a predetermined acceptable specification range and/or to compare successive spatially resolved PL maps to facilitate the identification of problem processing stages as part of a process diagnostic.

The invention will now be described by way of example only with reference to Figures 1 to 8 of the accompanying drawings in which:

Figure 1 is an illustration of a suitable apparatus for obtaining the PL data;

Figure 2 is a schematic illustration of how data is processed;

Figure 3 illustrates correlation of a PL map to impurity levels determined by conventional methods;

Figure 4 illustrates the use of PL measurement as a determinant of material specification;

Figure 5 illustrates a spatially resolved map of in and out of specification areas on a wafer;

Figure 6 illustrates PL images of the front and back of a wafer; Figures 7 and 8 illustrate a possible numerical analysis technique in accordance with the invention.

The apparatus illustrated in Figure 1 essentially comprises a PL imaging microscope which which: towards the right hand side, comprises a bank of lasers (3-8); towards the bottom comprises a sample stage such as an X-Y table or R-table; towards the left hand side comprises a microprocessor (40) and a display screen (39) and in the centre of the Figure there are shown various optical components for directing light through the system.

In the embodiment shown in Figure 1, six lasers are provided with a view to probing different depths in the sample. However, it is within the scope of the invention to use only one laser, or indeed to use a greater number of lasers. In any event, at least one of the lasers is a high intensity laser and ideally has a spot size of between 0.1 mm and 0.5 micron and a power density of between 10⁴ to 10⁹ watts/cm². A laser selector (16) coupled with said bank of lasers is provided so as to select one or more lasers for use and further also to select the frequency and wavelength of the lasers.

Conventional optics, such as optical fibres (9) are used to direct light towards the collimator to (10) and laser beam expander (11). An apodization plate (12) is positioned between laser beam expander (11) and beam splitter (31). Beam splitter (31) directs a fraction of light from the aforementioned lasers towards sample (2) via objective (34).

An automatic focus controller (30) is provided and coupled to a piezo driven focusing stage (33). The microscope is equipped with a conventional rotating turret (36) which is provided with at least one high numerical aperture objective for micro examination and one low numerical aperture objective for macro examination (34, 35) respectively. In addition, also coupled to turret (36) there is provided an optical displacement measuring system (38).

Cabling is provided so as to connect the automatic focusing controller (30) to microprocessor (40) and also a microscope objective indexing arrangement (32) to microprocessor (40).

Downstream of beam splitter (31) there is provided as filter wheel (13) for laser notch filters, down stream thereof there is provided a swing-aside folding mirror (14) whose function will be described hereinafter. Aligned with said mirror (14) there is provided a filter wheel (27) for wavelength selection, and rearward thereof there is provided a zoom lenses attached to a suitable CCD 2- D array detector (29).

Infinity system compensating lens (37) is provided in the optical path foremost of cold mirror (17) which reflects light towards a further filter wheel (23) for wavelength selection and a focusing lenses (24) which is foremost of a detector (25) for UV and visible light. Detector (25) is coupled to lock-in amplifier (26). This is used to obtain a reflected image of the surfaces.

Rearmost of cold mirror (17) is provided a further filter wheel (18) again for wavelength selection, and rearmost thereof a focusing lens (22) and a further aperture wheel (19) for pinhole selection which is provided foremost of a detector (21) for detecting the luminescence.

Both the UV and visible region detector (25) and infrared detector (21) are coupled to lock-in amplifier (26).

Operation of the system is explained having regard to the following. A range of wavelengths to probe different planes in the sample is provided by several lasers (3-8). The lasers can be modulated by a frequency generator (16) so that the signal emitted from the sample (2) can be isolated from background radiation by means of the detectors being synchronised to the laser modulation frequency by the lock-in amplifier (26). In a further embodiment, the range of wavelengths could be produced by using a tuneable laser and/or an Optical Parametric Oscillator. Each laser is connected to, and aligned with, a Multi-branch optical fibre (9) so that any or all of the lasers can illuminate the sample (2). The common end of the Multi-branch optical fibre terminates in an optical system (10) which collimates the emerging light. This optical system is aligned with a beam expander (11) which matches the laser beam's diameter to that required by the microscope objectives (34, 35) above the sample (2). The expanded beam then passes through an apodization plate (12) which distributes the optical energy evenly over the beam area.

The expanded and apodized beam is reflected by a beamsplitter (31) and passes to the microscope objectives (34 and 35). The beam is focused by a microscope objective (34 or 35) on to the sample. In the micro mode this objective is selected to focus the beam to a diffraction limited spot size. A rotating turret (36), operated by an indexing mechanism (32), permits the objective to be changed for the macro mode where a larger area of the sample can be illuminated. In a further embodiment the apodization plate (12) can be removed so that the spot for the micro mode can be made smaller to allow higher injection levels.

An optical displacement sensor (38) measures the distance to the sample and, by means of a feedback loop through the antifocus controller (30), maintains the correct spacing by means of the piezo actuated focusing stage (33). The Photoluminescence signal from the sample is collected by the microscope objective (34) (in the micro mode) and transported back through the beamsplitter (31) and a notch filter in the filter wheel (13) which contains notch filters matched to the range of laser wavelengths. The notch filter removes any reflected laser light, passing only the Photoluminescence signal.

The folding mirror (14) is swung out of the beam allowing the signal to pass to the tube lens (37), which may be incorporated to compensate for any infinity microscope objectives which may be used, and on to the cold mirror (17). This component reflects those wavelengths below a selected cut off point (approximately 700 nm) to the focusing lens (24) which focuses the signal into the detector (25). A filter wheel (23) in front of the detector focusing lens (24) contains filters to isolate selected wavelength bands.

The portion of the Photoluminescence signal lying in the wavelength range above the cut-off point passes through the cold mirror (17) and is similarly focused by the lens (22) into the detector (21). This signal also passes through a filter wheel (18) containing filters to isolate selected wavelength bands.

A series of pinholes of different diameters are contained in an aperture wheel (19) positioned in front of the detector (21). This aperture wheel can be moved axially by the piezo actuator (20) so that the pinholes can be positioned confocally with the desired image plane. By this means, planes at different depths in the sample (2) can be imaged to provide accurate depths information.

The electrical signal from the detectors (21, 25) is fed to the lock-in amplifier

(26) where it is synchronised with the modulation frequency of the laser (3-8) by means of a reference signal from the frequency generator (15). The electric signal is then fed to the central processor (40) for analysis. The PL image is obtained by raster scanning the stage. Alternatively optical scanning using galvo mirrors may be employed.

In an alternative micro mode of operation, the folding mirror (14) is swung into the beam of the Photoluminescence signal. The diverted signal passes through a filter wheel (27), which contains filters to isolate selected wavelength bands, and into the zoom lens (28). The zoom lens allows different magnifications to be used in imaging the illuminated spot on the sample (2) on to the CCD two dimensional array (29). This allows the illuminated area of the sample (2) to be imaged at different resolutions. The electrical signal from the CCD array is fed to the central processor (40) for analysis.

The processing of data is illustrated schematically in Figure 2. PL data is collected by the collection apparatus of Figure 1 (shown in simplified schematic form as the device 102) from a sample (101). In a first processing path, in accordance with the main aspect of the invention, the PL map data is passed to a processor (103) which processes the data to determine an average PL intensity across the whole area of the sample (101).

The resulting average is passed to a comparator (104) which relates the average PL intensity data to a predetermined stored specification range within the data store (105), and based on that comparison passes a quality control decision onto the control unit (106). Depending upon the preferred mode of operation, the control unit (106) could for example be a display means giving an indication to an operator, or could be a control unit for an automatic processing system, which on the basis of the decision sent to the control unit (106) could then act upon an automatic processing line, for example to make an acceptable/reject choice, to divert the sample under test (101) for remedial processing etc. A secondary processing route, shown by the broken line, reflects the optional second aspect of the invention. In this optional aspect, data corresponding to the PL intensity map across the surface of the sample (101) is also passed to a processing unit (110) which is able to resolve the data into a digitised spatially resolved map of intensity across the surface of the sample (101). The resulting map is passed to a data store (111) and to a visual display screen (112). The data store (111) is capable of storing and comparing data from sequential results, for example produced from a plurality of samples and/or from the same sample after a plurality of processing steps. This data could be used, for example in association with device testing, for example electrical testing, for example yield testing of the final produced device, to determine where flaws in manufacturing might have arisen.

To establish if the average PL signal could be used to measure contamination during furnace treatment, a selection of 300 mm oxidized wafers, which contained different levels of metal contamination, were measured using the bulk lifetime standard method. A map of each wafer was recorded and then measured on the system illustrated in Figure 1. By direct comparison of the wafer maps from each system is was possible to create a calibration graph of contamination level versus average PL signal.

A typical example is shown in Figure 3. On inspection of this graph it can be seem quite clearly that there is a direct linear correlation between the average PL signal and the metal contamination concentration. Therefore the average PL signal obtained from a wafer map could be used as a metric of wafer quality. The PL map would be recorded and then compared against a predetermined value. This specified range would used to determine the wafer quality and therefore a go-no go process control procedure created. An example of this procedure can be seen in Figure 4. Examples of spatially resolved maps such as might be used to identify the location of defects, for example in association with the preferred second aspect of the invention, wherein the invention is used not only as a quality control method but as a means of process control, are illustrated in Figures 5 and 6.

After setting up the specified range in the procedure described in association with Figures 3 and 4 it is possible then to associate this range to any colour or grey scale system and generate an image illustrative of wafer quality. Figure 5 is an example, wherein lighter areas (are in specification) and darker areas are out of specification). This simple colour-coding or grey-coding can be used to see the variation in the wafer quality across the sample, with the darker areas in the wafer map shows areas outside the specified range.

This approach could be used to qualify wafer quality in other furnace processes such as RTP and anywhere were thermal treatments can be used.

After the wafer quality has been investigated using the average PL signal level, further measurements can be recorded with higher resolution. Also wafer maps can be recorded on the wafer backside. This helps to identify the source of the contamination, and in particular whether it came from the wafer back surface. Figure 6 shows the wafer maps obtained from a wafer after furnace treatment. In this example the backside of the wafer was contaminated, from the wafer support. During thermal treatment this contamination has diffused to the wafer front surface. This can be seen by the clear delineation of impurities corresponding to the furnace structure in Figure 6a (back of wafer) which is apparent in Figure 6b (front).

The example in figure demonstrates that higher resolution wafer maps can be used to deteπnine the "fingerprint" of the tool when it is contaminated. At the final part of testing fully processed chips electrically, if there was an area exhibiting demonstrable yield problems, the wafer maps could be used for diagnostic purposes to identify the likely culprit furnace or processing stage which might have introduced the contamination causing the problem.

An differential interference contrast imaging (DIG) module may be added to the tool illustrated in Figure 1 to enable the detection of slip lines. Therefore the system can be used to detect metal contamination using the PL wafer maps and slip (generally also generated in the furnace area) using the DIG system on one tool rather than using two separate machines.

Thus in accordance with the invention the photoluminescence tool is used as a rapid process control tool to determine wafer quality. Wafer maps are obtained and the measured PL response numerically analysed to provide a quality metric, in that a deviation of the photoluminescence response from predetermined parameters known to be associated with a semiconductor structure of satisfactory quality is used as the basis of a quality control decision.

In the basic example given this can simply be a comparison of mean response over the whole area. However in general contamination can be a very localised and the average PL signal (averaged over all measured pixels in the wafer map) may not a reliable indication of such contamination. If wafer map is sub-divided using a 2D grid, then analysed using average PL, very localised signals could be detected.

After a wafer map has been recorded a virtual grid may be applied and displayed on top of the wafer map using suitable software. This can be used to perform the analysis. A local area analysis also allows better location of problem sites in the structure. For example the grid elements that have failed may be indicated, a micro scan can be launched at the same location as the grid element to allows the area of interest to be inspected in more detail, and a report of the failed elements in the wafer map analysis can be exported in suitable format.

The local grid method is not restricted to a numerical analysis based on mean values. Any suitable pre-defined parameters, including average intensity, PL min, Max, Standard deviation and baseline) can be used to determine regions of contamination. The PL signal baseline method can be a more useful parameter to use because the variation in signal across is not uniform wafer. This technique is explained below.

A typical wafer map is shown in figure 7a with an associated histogram of PL intensity in Figure 7b.

Contamination is detected in the wafer map by the deviation from the baseline value and limits can be set. However, the PL average value in this wafer map is modified by the contamination. Whereas the value to be used should represent the signal level for an uncontaminated wafer. The peak value shown in Figure 8 represents the true PL value of a non-contaminated wafer. Modifying the baseline function to have a peak value would allow the customer to accurately track the contamination and with more sensitivity.

A suitable algorithm involves the following steps: 1. To define peak value as maximum value in histogram and use this for baseline

2. Search data for peak value.

3. Then calculate ±70% of maximum value (user defined) then re-define the peak maximum as the center position of these points. 4. Then calculate precise value of peak maximum and then define PL level.

5. Also allow user to input typical baseline value form uncontaminated wafer, this will help if there are two peaks of equal intensity.

The baseline of the wafer is the PL value that corresponds to the maximum number of points.

The baseline variation is defined by the following relationship: Baseline variation = PL value - baseline

The PL value is the AVG PL of each element of the grid. The baseline variation must be measured for each element.

Claims

1. A method of detecting impurities in a semiconductor structure, in particular during thermal processing as part of device fabrication, comprising the steps of: exposing the surface of the semiconductor structure to at least one high- intensity beam of light from a suitable light source, and collecting photoluminescence produced by excitation of the semiconductor structure by the light beam; making an analysis of the collected photoluminescence signal and using that analysis as the basis for a quality classification of the suitability of the semiconductor for further device fabrication processing.

2. A method in accordance with claim 1 wherein the quality classification step comprises: determining an average photoluminescence intensity emitted across the area of the structure or subregions thereof; comparing the average with a predetermined acceptable specification range of photoluminescence; making a quality classification of the semiconductor structure based thereon.

3. A method in accordance with claim 1 or claim 2 wherein the quality classification step comprises rejecting or selecting for remedial action semiconductor structures exhibiting a photoluminescence response outside a predetermined acceptable specification range.

4. A method in accordance with any preceding claim wherein the beam power and/or wavelength and/or spot size of the light beam is so controlled as to collect near-surface PL information from the upper 12 μm of the semiconductor structure.

5. A method in accordance with claim 4 wherein the light beam is so controlled as to collect near-surface PL information from the upper 1 μm of the semiconductor structure.

6. A method in accordance with any preceding claim wherein the PL response is obtained at around room temperature.

7. A method in accordance with any preceding claim wherein the light source is a high-intensity laser.

8. A method in accordance with claim 7 wherein the laser has a small probing volume with spot size 0.1 to 20 μm, ideally 2 to 5μm, and with a peak or average power density of between 10⁴ to 10⁹ watts/cm².

9. A method in accordance with claim 7 or 8 wherein a pulsed laser excitation source is used and luminescence data is measured and/or the luminescence images collected as a function of time.

10. A method in accordance with any preceding claim further comprising the step of using the collected PL signals to generate a spatially resolved map of PL signals across the surface of the semiconductor under test, and in particular to generate a spatially resolved image of those signals.

11. A method in accordance with claim 10 further comprising the step of storing the spatially resolved PL map on suitable data storage means and/or transmitting digitised data derived from the spatially resolved map through suitable processing means for onward processing.

12. A method in accordance with claim 10 or 11 further comprising the step of displaying any generated PL image on suitable display means.

13. A diagnostic method to identify processing problems during device fabrication, comprising performing the detection method in accordance with any preceding claim on at least one semiconductor structure successively at the end of a plurality of processing steps during device fabrication, and in particular at the end of a plurality of thermal processing steps; additionally collecting and storing data relating to a spatially resolved map of PL response across the surface of the semiconductor structure; on completion of the processing stages, electrically testing the finished product, for example by producing a yield map; relating data from the electrical test indicative of areas of unsatisfactory operation in the finished product, to data from the spatially resolved PL maps from the various process stages to identify which process stages are likely to be responsible for problems arising in the areas in question.

14. An apparatus for detecting impurities in a semiconductor structure, in particular during thermal processing as part of device fabrication, comprising a high intensity light source; means to focus a high intensity beam of light from the light source onto a surface of a semiconductor structure under test; collection means to collect photoluminescence data from across the surface of the semiconductor structure under test produced by excitation of the semiconductor structure by the light beam; analysis means to process and numerically analyse the collected data; a comparator to compare the results of the analysis with predetermined acceptable specification parameters.

15. An apparatus in accordance with claim 14 wherein the beam power and/or wavelength and or spot size of the light beam is so controlled that the apparatus is adapted to generate and collect near-surface PL information from the upper 12 μm of the semiconductor structure.

16. An apparatus in accordance claim 14 or 15 wherein the light source is a high-intensity laser.

17. An apparatus in accordance with claim 16 wherein the laser has a small probing volume with spot size 0.1 to 20μm, ideally 2 to 5μm, and with a peak or average power density of between 10⁴ to 10⁹ watts/cm².

18. An apparatus in accordance with one of claims 14 to 17 further comprising means to resolve the collected PL data into a spatially resolved PL map across the area of the semiconductor structure.

19. An apparatus in accordance with claim 18 further comprising means to convert the resolved data into a PL image and/or image/data storage means to store the map/image, and in particular to store successive map/images for future comparison, and/or means to transmit the map/image to a suitable remote data processor and/or image display means such as a visual display screen to display an image and/or related data to a user.