WO2004088621A1

WO2004088621A1 - Method and circuit arrangement for simulating pixel and sub-pixel defects that occur in matrix-addressed displays

Info

Publication number: WO2004088621A1
Application number: PCT/EP2004/003097
Authority: WO
Inventors: Udo Fischbeck; Markus Friebe; Johannes Spindler
Original assignee: Grundig Multimedia B.V.
Priority date: 2003-03-29
Filing date: 2004-03-24
Publication date: 2004-10-14
Also published as: CN1795482A; DE10314268B3; JP2006523854A; CN100466031C; EP1636777A1

Abstract

The invention relates to a method for simulating pixel and sub-pixel defects that occur in matrix-addressed displays, in addition to a circuit arrangement for carrying out said method. According to said method, an R-G-B signal (10), a horizontal synchronisation signal (9) and a vertical synchronisation signal (8) are generated from a video data stream that represents the video images that are to be reproduced, said signals controlling a screen (7) by means of a screen control circuit (6). A programmable pixel-defect simulation unit (3) controls the substitution of the R-G-B-Signal (10) by an R'-G'-B'-Signal (11), which simulates the pixel or sub-pixel defect. The time and duration of the substitution are calculated in such a way that the pixel or sub-pixel defect that has been simulated by the R'-G'-B' signal (11) is reproduced in a preselectable location on the screen (7).

Description

Method and circuit arrangement for the simulation of Posell and occurring in πnatrixadressißr displays

sub pixel

The invention relates to a method and a circuit arrangement for simulating pixel and sub-pixel defects occurring in matrix-addressed displays.

In the past, television signals were predominantly reproduced via cathode ray tubes. For some time now, playback systems have increasingly been used which have a flat screen and in which each pixel can be controlled directly via a mat-shaped addressing. The like reproduction concepts have become known under the term plasma screen or LCD screen.

The plasma screens are a matrix of small gas discharge areas, three of which each represent a picture element. Such a picture element is called a pixel, the three associated gas discharge areas represent the subpixels.

The above-mentioned LCD screens are matrix-shaped liquid crystal display devices. Here, too, an image point or pixel is formed by three liquid crystal cells lying next to one another, which represent the colors red, green and blue and are also referred to as subpixels. Of course, the category of matrix-addressed displays also includes projection display devices that use a matrix of picture elements located in the beam path of a light source, such as, for. B. rear projection screens or video projectors. The matrix of picture elements works on the reflection principle such as LCOSs (Liquid Crystal On Silicon) or DiVIDs (Digital Micromirror Device) or on the transmitted light principle such as e.g. B. LCDs (Liquid Crystal Display).

In principle, all of these display devices mentioned by way of example have in common that, as already mentioned above, a matrix of picture elements is provided which can be controlled as a function of the video signal by means of a control circuit which is adapted to the type of display.

Due to the complex structure of such matrix-type display devices, it is unavoidable that some of the many pixels or subpixels are defective with reasonable manufacturing effort. Very different error images occur, both with regard to the subpixels themselves and with regard to the occurrence of such errors in different areas of the screen area (edge area, center) and with regard to the effect of the errors occurring in connection with the displayed video image (brightness, color). , So a subpixel z. B. always on or always off or it may flicker uncontrollably. Depending on the type of error and the basic color of which the defective subpixel belongs, a different error pattern will occur depending on the color and brightness of the neighboring pixels. Under these circumstances, it is now very difficult to assess which error groups can still be considered qualitatively acceptable in the sense described above, because appropriate displays from the manufacturing process have to be selected by hand for an assessment. The targeted generation of certain error patterns in the manufacturing process is very difficult due to the complexity. To remedy this problem, it is an object of the invention to provide a method which allows the above-mentioned pixel and / or sub-pixel defects and their accumulation to be simulated on a screen and in this way to create assessment criteria as to which error images for the practical use are still tolerable.

It is also part of the task to specify a circuit arrangement for simulating pixel and sub-pixel defects occurring in matrix-addressed displays.

The object is achieved by a method according to patent claim 1 and by a circuit arrangement according to the features of patent claim 3.

The method according to the invention has the advantage that the error images already in the data stream with which the

Display control is applied, are mixed in, which enables a very simple change of the error images on the one hand and a display of the error images independent of the display type.

Advantageous embodiments of the invention are specified in the subclaims.

The method according to the invention and the circuit arrangement for carrying out the method are described and explained in more detail below in conjunction with the drawings.

Show it:

Fig. 1 shows a circuit arrangement for generating pixel and / or sub-pixel defects in a control signal for a screen.

FIG. 2 shows a detail of the circuit arrangement according to FIG. 1 According to the illustration in FIG. 1, a video data signal 1 is fed to a video data processing unit 2. In this video data processing unit 2, on the one hand, an RGB signal 10 is generated from the video data signal 1 and, on the other hand, e in a horizontal synchronization signal 9 and a vertical synchronization signal 8. The RGB signal 10 generated in the video data processing unit 2 is applied to a screen control circuit via a switching array 5 6 switched through, which is also supplied with the horizontal synchronization signal 9 and the vertical synchronization signal 8 from the video data processing unit 2. The screen control circuit 6 in turn controls the screen 7, so that an image that corresponds to the video data signal 1 normally appears on the screen 7.

In order to now simulate pixel and / or sub-pixel defects, a programmable pixel defect simulation unit 3 is used, which is acted upon on the one hand by the horizontal synchronization signal 9 and the vertical synchronization signal 8 from the video data processing unit 2 and on the other hand has a connection to a programming device 4. Pixel error data or sub-pixel error data are transferred to the programmable pixel defect simulation unit 3 via the programming device 4, these error data defining on the one hand the type of error and on the other hand the location of the error on the screen surface.

From the addressed pixel error data, the programmable pixel defect simulation unit 3 on the one hand generates an R'-G ^' -B ^' signal 11, which represents the respective pixel or sub-pixel error, on the other hand, the programmable pixel defect simulation unit 3 generates the horizontal synchronization signal 9 and the like Vertical synchronization signal 8 and the data parts that define the location of the respective error on the screen, a switching signal 18 with which the switching array 5 is acted upon such that the R ^' -G ^' -B ^' signal 11, which the programmable pixel defect simulation unit has also briefly applied to the inputs of the screen control circuit 6 becomes. After the time defined by the pixel error data has elapsed, the programmable pixel data simulation unit 3 switches the switching array 5 back to its initial state, so that the normal RGB signal 10 is switched through again to the screen control circuit 6.

Due to this brief application of the R ^' -G ^' -B ^' signal 11 to the screen control circuit 6, the corresponding pixel error is shown at the desired location on the screen 7.

At this point it should also be emphasized that, of course, a large number of pixel or sub-pixel defect error data are entered into the programmable pixel defect simulation unit 3 via the programming device 4, so that a large number of pixel or sub-pixel defects within a video image are described in the manner described can be represented.

An example of the functioning of the programmable pixel defect simulation unit 3 is explained in more detail below in connection with FIG. 2.

Pixel defects or sub-pixel defects are defined via the programming device 4 and are then transferred in the form of binary data into a memory 12 of the programmable pixel defect simulation unit 3. The binary data contained in the memory 12 contain, on the one hand, information about how the R ^' -G ^' -B ^' signal should look in order to represent the respective pixel defects and, on the other hand, information about where the respective errors should appear on the screen. In the exemplary embodiment, the last-mentioned information, that is to say that which relate to the location of the display on the screen, are count values with which a comparator 13 is applied. The comparator 13 is also supplied with the counter reading of a counter 14, the counter 14 being set to a defined counter value as a function of the horizontal synchronization signal 9 or the vertical synchronization signal 8. From this defined counter value, the counter 14 counts the clock signals on the horizontal synchronization signal 9 or the vertical synchronization signal 8 synchronized clock generator 15 and offers the counter reading to the comparator 13 for comparison. If the comparator 13 determines the equality between the counter reading of the counter 14 and the count value taken over from the memory 12, the comparator 13 generates at its output a signal which is sent via the switching signal generator 17 to the switching array 5, which is already in connection with FIG 1 is described.

At this point in time, R'-G ^' -B ^' data 19 are already present on the pixel defect generator, from which the pixel defect generator 16 generates an R ^' -G ^' -B ^' signal 11. As already shown in connection with the example according to FIG. 1, this R ^' -G'-B' signal 1 is briefly applied to the screen control circuit 6 by means of the switching array 5, which is acted upon by the switching signal generator 17 with a switching signal 18, which generates a corresponding representation on the screen 7.

The arrangement shown in FIG. 2 is of course only exemplary, in particular the arrangement shown in the example according to FIG. 2 can contain a large number of comparators 13 counters 14 and switching signal generators 17 in order to also easily display pixel or sub-pixel defects that are close together can. In addition, it is of course possible to achieve the conversion of a location on the screen specified by binary information into the real location on the screen using a wide variety of procedures which are familiar to the person skilled in the art; he will do so in connection with the example according to FIG. 2 specified basic functions operate synchronization, clock generation, counting and comparing in different ways.

Furthermore, it is of course conceivable to implement the programmable pixel defect simulation unit 3 by means of a microprocessor which simulates the functioning of the circuit parts described. However, this does not change the principle of operation. After the simulation of the pixel or sub-pixel defects by manipulation of the RGB signal applied to the screen control circuit 6 is achieved, as explained above with reference to FIGS. 1 and 2, the method and the arrangement for the simulation of the pixel or sub-pixel defects regardless of the type of screen used. The method and arrangement can be used equally for plasma screens, LCD screens, LCOS and DMD projectors and their respective subspecies, in short all matrix-addressable display types. The prerequisite here is that a screen 7 is used to display the pixel or sub-pixel defects, which itself has as few such pixel or sub-pixel defects as possible, since otherwise the image impression to be simulated would be distorted.

Furthermore, the described arrangement and the described method can also be used in connection with cathode ray picture tubes, so that it is possible to display on a cathode ray picture tube the picture impression that a plasma screen or LCD screen with pixel or sub-pixel defects would provide ,

Claims

claims

1. A method for simulating pixel or sub-pixel defects occurring in matrix-addressed displays, wherein

- An R-G-B signal (10), a horizontal synchronization signal (9) and a vertical synchronization signal (8) are generated from a video data stream representing the video images to be displayed, by means of which a screen control circuit is used

(6) the control of a screen (7) takes place,

controlled by a programmable pixel defect simulation unit (3), the RGB signal (10) is exchanged for an R ^' -G ^' -B ^' signal (11) which simulates the pixel or sub-pixel defect,

- The exchange with regard to the time and duration takes place in such a way that the pixel or sub-pixel defect simulated by the R ^' -G ^' -B ^' signal (11) occurs at a preselectable position on the screen

(7) is shown.

2. The method of claim 1, wherein

- An RGB signal (10), a horizontal synchronization signal (9) and a vertical synchronization signal (8) is generated from a video data stream representing the video images to be represented by means of a video data processing unit (2), the RGB signal (10) being generated via a switching array (5) is applied to a screen control circuit (6) which is a function of time controls the screen (7) from the horizontal synchronization signal (9) and the vertical synchronization signal (8),

an R ^' -G ^' -B ^' signal (11) is generated from the pixel or sub-pixel defect data supplied by a programming device (4) by means of a programmable pixel defect simulation unit (3), which represents the pixel or sub-pixel defect,

- Using the programmable pixel defect simulation unit (3), a switching signal (18) from the pixel or sub-pixel defect data supplied by the programming device (4) in dependence on the time of the horizontal synchronization signal (9) generated by the video data processing unit (2) and the vertical synchronization signal (8) is produced,

the switching array (5), when activated with the switching signal (18), switches its inputs to the R ^' -G ^' -B ^' signal (1) generated by the programmable pixel defect simulation unit (3),

- The time for the generation of the switching signal (18) and

Duration for which the switching signal (18) is applied to the switching array (5), by means of which the pixel or sub-pixel defect data supplied by the programming device (4) is predetermined such that the image of the pixel or sub-pixel defect is dependent on the horizontal synchronization signal (9) and vertical synchronization signal (8) appears at a predetermined position on the screen (7).

3. Circuit arrangement for the simulation of pixel or sub-pixel defects occurring in matπxaddressed displays consisting of - A video data processing unit (2) which generates a RGB signal (10), a horizontal synchronization signal (9) and a vertical synchronization signal (8) from a video data stream representing the video images to be displayed, the R-GB signal (10) via a switching array (5 ) is applied to a screen control circuit (6) which controls the screen (7) as a function of the horizontal synchronization signal (9) and the vertical synchronization signal (8),

- A programmable pixel defect simulation unit (3), which generates an R ^' -G ^' -B ^' signal (1 1) from the pixel or sub-pixel defect data supplied by a programming device (4), which represents the pixel or sub-pixel defect, the programmable Pixel defect simulation unit (3) generates a switching signal (18) from the pixel or sub-pixel defect data supplied by the programming device (4) as a function of time on the horizontal synchronization signal (9) generated by the video data processing unit (2) and the vertical synchronization signal (8) so that the switching array (5) controls, such that the switching array (5) switches its inputs to the R ^' - G'-B ^' signal (1) generated by the programmable pixel defect simulation unit (3) and the time for Generation of the switching signal (18) and the duration for which the switching signal (18) is applied to the switching array (5) by the one supplied by the programming device (4) Pixel or sub-pixel defect data is specified in such a way that the image of the pixel or sub-pixel defect appears as a function of time from the horizontal synchronization signal (9) and vertical synchronization signal (8) at a predetermined point on the screen (7). Circuit arrangement according to claim 3, wherein the programmable pixel defect simulation unit (3) is connected to a programming device (4) and at least one memory (12) at least one comparator (13) at least one counter (14) at least one clock generator (15) at least one pixel defect Generator (16) and at least one switching signal generator (17), wherein

the programming device (4) generates pixel or sub-pixel defect data and transfers it to the memory (12),

the pixel or sub-pixel defect data contain a first part which represents the pixel or sub-pixel defect and a second part which represents the location on the screen (7) at which the pixel or sub-pixel defect is displayed,

- The memory areas that contain the first part of the pixel or sub-pixel defect data with the pixel defect generator (16) and the memory areas that contain the second part of the pixel or

Contain sub-pixel defect data, are connected to a comparator (13),

- The pixel defect generator (16) generates an R ^' -G ^' -B ^' signal (1 1) at its output - the comparator (13) the counter value of the counter (14), which the

Counts clock signals of the clock generator (15) synchronized to the horizontal synchronization signal (9), compares them with the second part of the pixel or sub-pixel defect data and, if they match, controls the switching signal generator 17, which then outputs a switching signal 18,

- The counter (14) in synchronization with the horizontal synchronization signal (9) and vertical synchronization signal (8) is set to a predetermined value at the beginning of the display of a video image. Circuit arrangement according to claim 4, characterized in that the at least one memory (12), the at least one comparator (13), the at least one counter (14), the at least one clock generator (15), the at least one pixel defect generator (16) and the function of the at least one switching signal generator (17) is simulated in its function by a microcomputer.