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WO2002039683A3 - Apparatus and method for sending and receiving data signals over a clock signal line by pulse with modulation - Google Patents

Apparatus and method for sending and receiving data signals over a clock signal line by pulse with modulation Download PDF

Info

Publication number
WO2002039683A3
WO2002039683A3 PCT/US2001/045364 US0145364W WO0239683A3 WO 2002039683 A3 WO2002039683 A3 WO 2002039683A3 US 0145364 W US0145364 W US 0145364W WO 0239683 A3 WO0239683 A3 WO 0239683A3
Authority
WO
WIPO (PCT)
Prior art keywords
clock
transmission line
data
signal
clock signal
Prior art date
Application number
PCT/US2001/045364
Other languages
French (fr)
Other versions
WO2002039683A2 (en
Inventor
Gyudong Kim
Min-Kyu Kim
Seung Ho Hwang
Original Assignee
Silicon Image Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Silicon Image Inc filed Critical Silicon Image Inc
Priority to AU2002228699A priority Critical patent/AU2002228699A1/en
Priority to JP2002541879A priority patent/JP2004514325A/en
Priority to EP01989823A priority patent/EP1334594A2/en
Priority to KR1020027008940A priority patent/KR20020081248A/en
Priority to CA002396948A priority patent/CA2396948A1/en
Publication of WO2002039683A2 publication Critical patent/WO2002039683A2/en
Publication of WO2002039683A3 publication Critical patent/WO2002039683A3/en

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264Arrangements for coupling to transmission lines
    • H04L25/0292Arrangements specific to the receiver end
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264Arrangements for coupling to transmission lines
    • H04L25/0272Arrangements for coupling to multiple lines, e.g. for differential transmission
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264Arrangements for coupling to transmission lines
    • H04L25/028Arrangements specific to the transmitter end
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/0008Synchronisation information channels, e.g. clock distribution lines
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00Arrangements for detecting or preventing errors in the information received
    • H04L1/12Arrangements for detecting or preventing errors in the information received by using return channel

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Information Transfer Systems (AREA)
  • Dc Digital Transmission (AREA)

Abstract

The system preferably includes a unique transmitter that sends both clock and data signals over the same transmission line. The receiver uses the same transmission line to send data signals back to the transmitter. The transmitter comprises a clock generator, a decoder and a line interface. The clock generator produces a clock signal that includes a variable position falling edge (T0, T1, T3, T4) for pulse with modulation by the data (00, 01, 10, 11). The falling edge position is decoded by the receiver to extract data from the clock signal. The receiver comprises a clock re-generator, a data decoder and a returm channel encoder. The clock re-generator monitors the transmission line, receives signals, filters them and generates a clock signal at the receiver from the signal on the transmission line. The return channel encoder generates signals and asserts them on the transmission line. The signal is asserted or superimposed over the clock & data signal provided by the transmitter.
PCT/US2001/045364 2000-11-10 2001-10-30 Apparatus and method for sending and receiving data signals over a clock signal line by pulse with modulation WO2002039683A2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
AU2002228699A AU2002228699A1 (en) 2000-11-10 2001-10-30 Apparatus and method for sending and receiving data signals over a clock signal line by pulse with modulation
JP2002541879A JP2004514325A (en) 2000-11-10 2001-10-30 System and method for transmitting and receiving data signals over a clock signal line
EP01989823A EP1334594A2 (en) 2000-11-10 2001-10-30 Apparatus and method for sending and receiving data signals over a clock signal line by pulse width modulation
KR1020027008940A KR20020081248A (en) 2000-11-10 2001-10-30 A system and method for sending and receiving data signals over a clock signal line
CA002396948A CA2396948A1 (en) 2000-11-10 2001-10-30 A system and method for sending and receiving data signals over a clock signal line

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US70981600A 2000-11-10 2000-11-10
US09/709,816 2000-11-10

Publications (2)

Publication Number Publication Date
WO2002039683A2 WO2002039683A2 (en) 2002-05-16
WO2002039683A3 true WO2002039683A3 (en) 2002-10-17

Family

ID=24851401

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/045364 WO2002039683A2 (en) 2000-11-10 2001-10-30 Apparatus and method for sending and receiving data signals over a clock signal line by pulse with modulation

Country Status (6)

Country Link
EP (1) EP1334594A2 (en)
JP (1) JP2004514325A (en)
KR (1) KR20020081248A (en)
AU (1) AU2002228699A1 (en)
CA (1) CA2396948A1 (en)
WO (1) WO2002039683A2 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7792152B1 (en) 2004-06-08 2010-09-07 Owlink Technology, Inc. Scheme for transmitting video and audio data of variable formats over a serial link of a fixed data rate
KR100924704B1 (en) * 2009-01-30 2009-11-03 주식회사 아나패스 Display and method for transmitting clock signal in blank period
JP4315462B1 (en) 2008-04-23 2009-08-19 シリコンライブラリ株式会社 Receiving device capable of generating audio reference clock
US8958497B2 (en) * 2012-06-12 2015-02-17 Silicon Image, Inc. Simultaneous transmission of clock and bidirectional data over a communication channel
JP6534720B2 (en) * 2017-11-10 2019-06-26 マクセル株式会社 Display device
JP6534757B2 (en) * 2018-02-20 2019-06-26 マクセル株式会社 Display device
CN109188444B (en) * 2018-10-10 2023-04-11 中国船舶重工集团公司七五0试验场 Submarine underwater acoustic response type positioning method and system based on synchronous signal system
CN112463701B (en) * 2020-11-17 2024-02-23 江苏科大亨芯半导体技术有限公司 I2C slave circuit based on SCL real-time high-level pulse width
CN114513293B (en) * 2022-02-24 2022-10-14 中国水利水电科学研究院 Pulse-per-second delay compensation system and method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000016525A1 (en) * 1998-09-10 2000-03-23 Silicon Image, Inc. A system and method for sending and receiving data signals over a clock signal line

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000016525A1 (en) * 1998-09-10 2000-03-23 Silicon Image, Inc. A system and method for sending and receiving data signals over a clock signal line

Also Published As

Publication number Publication date
AU2002228699A1 (en) 2002-05-21
JP2004514325A (en) 2004-05-13
EP1334594A2 (en) 2003-08-13
WO2002039683A2 (en) 2002-05-16
CA2396948A1 (en) 2002-05-16
KR20020081248A (en) 2002-10-26

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